WO2018036029A1 - 像素结构及其制作方法 - Google Patents

像素结构及其制作方法 Download PDF

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Publication number
WO2018036029A1
WO2018036029A1 PCT/CN2016/110083 CN2016110083W WO2018036029A1 WO 2018036029 A1 WO2018036029 A1 WO 2018036029A1 CN 2016110083 W CN2016110083 W CN 2016110083W WO 2018036029 A1 WO2018036029 A1 WO 2018036029A1
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Prior art keywords
electrode
drain
pixel electrode
pixel
horizontal
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PCT/CN2016/110083
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English (en)
French (fr)
Inventor
郝思坤
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深圳市华星光电技术有限公司
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Priority to US15/328,496 priority Critical patent/US10114254B2/en
Publication of WO2018036029A1 publication Critical patent/WO2018036029A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel structure and a method of fabricating the same.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • a liquid crystal display panel comprises a CF (Color Filter) substrate, a thin film transistor (TFT) substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame ( Sealant) composition.
  • CF Color Filter
  • TFT thin film transistor
  • LC liquid crystal
  • Sealant sealant frame
  • TFT-LCDs thin film transistor liquid crystal displays
  • LCD wide viewing angle technology currently mainly includes Multi-domain Vertical Alignment (MVA) technology and In Plane Switching (IPS) technology.
  • MVA Multi-domain Vertical Alignment
  • IPS In Plane Switching
  • the advantage of MVA technology is that the front contrast is high, usually can reach 4000:1 and above; IPS technology makes the liquid crystal molecules rotate under the action of horizontal electric field by forming parallel and repeatedly distributed pixel electrodes and common electrodes on the thin film transistor array substrate. Thereby a wide viewing angle is formed, but the contrast is relatively low, typically below 2000:1.
  • the pixel structure of a conventional vertical alignment type liquid crystal display includes a thin film transistor 100 and a pixel electrode 200 electrically connected to the thin film transistor 100.
  • the pixel electrode 200 is composed of four.
  • the region 210 is configured to have the same polar angle (liquid crystal molecules) corresponding to the liquid crystal molecules in one region 210 of the pixel electrode 200 under the driving of the pixel electrode 200.
  • the angle between the long axis direction and the display screen when viewing the display screen from different viewing angles, due to the birefringence effect of the liquid crystal molecules, the refractive index of the same liquid crystal molecule is different at different viewing angles, so it is received
  • the intensity of the light is also different. Specifically, the larger the viewing angle is, the lower the brightness of the screen is seen, so that the viewing angle characteristics of the liquid crystal display using the pixel structure are poor.
  • the present invention firstly provides a pixel structure including a substrate substrate, a first metal layer disposed on the substrate substrate, and a first insulation disposed on the first metal layer and the substrate a semiconductor layer disposed on the first insulating layer, a second metal layer disposed on the semiconductor layer and the first insulating layer, and the second metal layer, the semiconductor layer, and the first insulating layer a second insulating layer thereon, and a transparent conductive layer disposed on the second insulating layer;
  • the first metal layer includes a scan line
  • the semiconductor layer includes a first active layer and a second active layer disposed at intervals, and the first active layer and the second active layer are respectively disposed above the scan line;
  • the second metal layer includes a first data line, a first source connected to one side of the first data line, a first drain and a second data line spaced apart from the first source, and connected to a second source on one side of the second data line, and a second drain spaced apart from the second source;
  • the first data line and the second data line respectively intersect perpendicularly with the scan line; the first source and the first drain are respectively in contact with two sides of the first active layer; The two sources and the second drain are respectively in contact with both sides of the second active layer;
  • the transparent conductive layer includes a first pixel electrode and a second pixel electrode that are not connected;
  • the second insulating layer is provided with a first through hole corresponding to the first drain and a second through hole corresponding to the second drain, and the first pixel electrode passes the first
  • the via hole is in contact with the first drain; the second pixel electrode is in contact with the second drain through the second via hole.
  • the first pixel electrode includes vertically intersecting vertical stem electrodes and horizontal stem electrodes, and four pixel electrode regions divided by the horizontal stem electrodes and the vertical stem electrodes perpendicularly intersecting, each pixel electrode region a plurality of first strip-shaped branch electrodes including an angle of ⁇ 45° or ⁇ 135° with the horizontal stem electrode or the vertical stem electrode, and a plurality of first strips of the four pixel electrode regions Branch electrodes along the horizontal stem electrode and the vertical stem respectively
  • the electrodes are symmetrical above and below, forming a "m"-shaped pixel electrode structure.
  • the second pixel electrode includes a bezel electrode located at a periphery of the first pixel electrode, and a plurality of second strip-shaped branch electrodes respectively connected to the bezel electrode, wherein the plurality of second strip-shaped branch electrodes are distributed in the The four pixel electrode regions of the first pixel electrode are parallel and interleaved with the first strip electrode electrodes of each pixel electrode region.
  • the bezel electrode includes a first horizontal electrode and a second horizontal electrode parallel to the horizontal main electrode, and a first vertical electrode and a second vertical electrode parallel to the vertical main electrode; the first level An electrode, a first vertical electrode, a second horizontal electrode, and a second vertical electrode are sequentially connected; the first horizontal electrode is disposed adjacent to the first drain and the second drain; the first horizontal electrode An opening is disposed, and the vertical trunk electrode of the first pixel electrode passes through the opening and is not connected to the first horizontal electrode and the second horizontal electrode on both sides of the opening, respectively.
  • the first pixel electrode includes a first connection electrode connected to the vertical trunk electrode, and the first connection electrode is in contact with the first drain through the first via hole such that the first pixel electrode and the first pixel electrode The first drain is electrically connected;
  • the second pixel electrode includes a second connection electrode connected to the bezel electrode, and the second connection electrode is in contact with the second drain through the second via hole, such that the second pixel electrode and the The second drain is electrically connected.
  • the invention also provides a method for fabricating a pixel structure, comprising the following steps:
  • Step 1 providing a substrate, forming a first metal layer on the substrate, the first metal layer comprising a scan line;
  • Step 2 forming a first insulating layer on the first metal layer and the substrate;
  • Step 3 forming a semiconductor layer on the first insulating layer, the semiconductor layer comprising a first active layer and a second active layer disposed at intervals, the first active layer and the second active layer respectively corresponding to Set above the scan line;
  • Step 4 forming a second metal layer on the semiconductor layer and the first insulating layer;
  • the second metal layer includes a first data line, a first source connected to one side of the first data line, a first drain and a second data line spaced apart from the first source, and connected to a second source on one side of the second data line, and a second drain spaced apart from the second source;
  • the first data line and the second data line respectively intersect perpendicularly with the scan line; the first source and the first drain are respectively in contact with two sides of the first active layer; The two sources and the second drain are respectively in contact with both sides of the second active layer;
  • Step 5 forming a second insulating layer on the second metal layer, the semiconductor layer, and the first insulating layer;
  • Step 6 forming a transparent conductive layer on the second insulating layer, the transparent conductive layer comprising a first pixel electrode and a second pixel electrode that are not connected;
  • the first pixel electrode is in contact with the first drain through the first via hole; and the second pixel electrode is in contact with the second drain through the second via hole.
  • the first pixel electrode includes vertically intersecting vertical stem electrodes and horizontal stem electrodes, and four pixel electrode regions divided by the horizontal stem electrodes and the vertical stem electrodes perpendicularly intersecting, each pixel electrode region a plurality of first strip-shaped branch electrodes including an angle of ⁇ 45° or ⁇ 135° with the horizontal stem electrode or the vertical stem electrode, and a plurality of first strips of the four pixel electrode regions
  • the branch electrodes are vertically symmetrical with the vertical stem electrodes along the horizontal stem electrodes, respectively, to form a "meter"-shaped pixel electrode structure.
  • the second pixel electrode includes a bezel electrode located at a periphery of the first pixel electrode, and a plurality of second strip-shaped branch electrodes respectively connected to the bezel electrode, wherein the plurality of second strip-shaped branch electrodes are distributed in the The four pixel electrode regions of the first pixel electrode are parallel and interleaved with the first strip electrode electrodes of each pixel electrode region.
  • the bezel electrode includes a first horizontal electrode and a second horizontal electrode parallel to the horizontal main electrode, and a first vertical electrode and a second vertical electrode parallel to the vertical main electrode; the first level An electrode, a first vertical electrode, a second horizontal electrode, and a second vertical electrode are sequentially connected; the first horizontal electrode is disposed adjacent to the first drain and the second drain; the first horizontal electrode An opening is disposed, and the vertical trunk electrode of the first pixel electrode passes through the opening and is not connected to the first horizontal electrode and the second horizontal electrode on both sides of the opening, respectively.
  • the first pixel electrode includes a first connection electrode connected to the vertical trunk electrode, and the first connection electrode is in contact with the first drain through the first via hole such that the first pixel electrode and the first pixel electrode The first drain is electrically connected;
  • the second pixel electrode includes a second connection electrode connected to the bezel electrode, and the second connection electrode is in contact with the second drain through the second via hole, such that the second pixel electrode and the The second drain is electrically connected.
  • the present invention also provides a pixel structure including a base substrate, a first metal layer disposed on the base substrate, a first insulating layer disposed on the first metal layer and the base substrate, and disposed at the a semiconductor layer on the first insulating layer, a second metal layer disposed on the semiconductor layer and the first insulating layer, and a second insulating layer disposed on the second metal layer, the semiconductor layer, and the first insulating layer a layer, and a transparent conductive layer disposed on the second insulating layer;
  • the first metal layer includes a scan line
  • the semiconductor layer includes a first active layer and a second active layer disposed at intervals, the first having The source layer and the second active layer are both disposed above the scan line;
  • the second metal layer includes a first data line, a first source connected to one side of the first data line, a first drain and a second data line spaced apart from the first source, and connected to a second source on one side of the second data line, and a second drain spaced apart from the second source;
  • the first data line and the second data line respectively intersect perpendicularly with the scan line; the first source and the first drain are respectively in contact with two sides of the first active layer; The two sources and the second drain are respectively in contact with both sides of the second active layer;
  • the transparent conductive layer includes a first pixel electrode and a second pixel electrode that are not connected;
  • the second insulating layer is provided with a first through hole corresponding to the first drain and a second through hole corresponding to the second drain, and the first pixel electrode passes the first a via hole is in contact with the first drain; the second pixel electrode is in contact with the second drain through the second via hole;
  • the first pixel electrode includes vertically intersecting vertical stem electrodes and horizontal stem electrodes, and four pixel electrode regions divided by the horizontal stem electrodes and the vertical stem electrodes perpendicularly intersecting, each pixel electrode
  • the regions each include a plurality of first strip-shaped branch electrodes connected at an angle of ⁇ 45° or ⁇ 135° to the horizontal stem electrode or the vertical stem electrode, and the first of the four pixel electrode regions
  • the strip-shaped branch electrodes are respectively vertically and horizontally symmetrically arranged along the horizontal stem electrode and the vertical stem electrode to form a pixel structure of a "meter" shape;
  • the second pixel electrode includes a bezel electrode located at a periphery of the first pixel electrode, and a plurality of second strip-shaped branch electrodes respectively connected to the bezel electrode, and the plurality of second strip-shaped branch electrodes are distributed.
  • a bezel electrode located at a periphery of the first pixel electrode, and a plurality of second strip-shaped branch electrodes respectively connected to the bezel electrode, and the plurality of second strip-shaped branch electrodes are distributed.
  • the bezel electrode comprises a first horizontal electrode and a second horizontal electrode parallel to the horizontal main electrode, and a first vertical electrode and a second vertical electrode parallel to the vertical main electrode; a horizontal electrode, a first vertical electrode, a second horizontal electrode, and a second vertical electrode are sequentially connected; the first horizontal electrode is disposed adjacent to the first drain and the second drain; the first An opening is disposed on the horizontal electrode, and the vertical trunk electrode of the first pixel electrode passes through the opening and is not connected to the first horizontal electrode and the second horizontal electrode on both sides of the opening;
  • the first pixel electrode includes a first connection electrode connected to the vertical trunk electrode, and the first connection electrode is in contact with the first drain through the first via hole, such that the first pixel An electrode is electrically connected to the first drain;
  • the second pixel electrode includes a second connection electrode connected to the bezel electrode, and the second connection electrode is in contact with the second drain through the second via hole, so that the second pixel electrode Electrically connected to the second drain.
  • the present invention provides a pixel structure in which two pixel electrodes that are not connected are disposed in a pixel structure, and the two pixel electrodes are respectively connected to two data lines through respective thin film transistors, and are normally When displayed, different voltages are applied to the two data lines, so that the potentials on the two pixel electrodes are different, and different potentials on the two pixel electrodes cause liquid crystal molecules close to different pixel electrodes to form different polar angles, thereby forming in the liquid crystal.
  • the distribution and presence of various polar angles reduces the difference in phase difference of the liquid crystals in different directions, thereby improving the viewing angle and color shift of the vertical alignment type liquid crystal display.
  • the invention provides a method for fabricating a pixel structure, the process is simple and easy to operate, and the obtained pixel structure can form a plurality of polar angle distributions and presences in the liquid crystal during normal display, and reduce the phase difference of the liquid crystals in different directions. The difference is to improve the viewing angle and color shift of the vertical alignment type liquid crystal display.
  • FIG. 1 is a top plan view showing a pixel structure of a conventional vertical alignment type liquid crystal display
  • FIG. 2 is a top plan view of a pixel structure of the present invention.
  • Figure 3 is a cross-sectional view taken along line A-A of Figure 2;
  • Figure 4 is a cross-sectional view taken along line B-B of Figure 2;
  • FIG. 5 is a top plan view of a first metal layer of a pixel structure of the present invention.
  • FIG. 6 is a top plan view of a first insulating layer of a pixel structure of the present invention.
  • FIG. 7 is a top plan view of a semiconductor layer of a pixel structure of the present invention.
  • FIG. 8 is a top plan view of a second metal layer of a pixel structure of the present invention.
  • FIG. 9 is a top plan view of a second insulating layer of a pixel structure of the present invention.
  • FIG. 10 is a top plan view of a transparent conductive layer of a pixel structure of the present invention.
  • FIG. 11 is a flow chart of a method of fabricating a pixel structure of the present invention.
  • the present invention provides a pixel structure including a substrate substrate 10, a first metal layer 20 disposed on the substrate substrate 10, and a first metal layer 20 and a substrate. a first insulating layer 30 on the first insulating layer 30, a semiconductor layer 40 disposed on the first insulating layer 30, and a second metal layer 50 disposed on the semiconductor layer 40 and the first insulating layer 30. a second metal layer 50, a semiconductor layer 40, and a second insulating layer 60 on the first insulating layer 30, and a transparent conductive layer 70 disposed on the second insulating layer 60;
  • the first metal layer 20 includes a scan line 21;
  • the semiconductor layer 40 includes a first active layer 41 and a second active layer 42 which are spaced apart, and the first active layer 41 and the second active layer 42 both correspond to the scan.
  • the second metal layer 50 includes a first data line 51 , a first source 52 connected to one side of the first data line 51 , and a first interval spaced apart from the first source 52 .
  • the first data line 51 and the second data line 54 respectively intersect the scan line 21 vertically; the first source 52 and the first drain 53 are respectively opposite to both sides of the first active layer 41 Contacting; the second source 55 and the second drain 56 are respectively in contact with both sides of the second active layer 42;
  • the transparent conductive layer 70 includes a first pixel electrode 71 and a second pixel electrode 72 that are not connected;
  • the second insulating layer 60 is provided with a first via hole 61 corresponding to the first drain electrode 53 and a corresponding upper portion of the second drain electrode 56.
  • a second via hole 62 the first pixel electrode 71 is in contact with the first drain electrode 53 through the first via hole 61; the second pixel electrode 72 passes through the second via hole 62 and the first via hole The two drains 56 are in contact.
  • the first pixel electrode 71 includes vertically intersecting vertical trunk electrodes 711 and horizontal trunk electrodes 712, and four pixel electrodes divided by the horizontal trunk electrodes 712 and the vertical stem electrodes 711 perpendicularly intersecting a region 713, each of the pixel electrode regions 713 includes a plurality of first strip-shaped branch electrodes 715 connected at an angle of ⁇ 45° or ⁇ 135° to the horizontal stem electrode 712 or the vertical stem electrode 711, A plurality of first strip-shaped branch electrodes 715 of the four pixel electrode regions 713 are vertically symmetrical with respect to the vertical stem electrode 711 along the horizontal stem electrode 711, respectively, to form a "m"-shaped pixel electrode structure.
  • the second pixel electrode 72 includes a frame electrode 80 located at a periphery of the first pixel electrode 71, and a plurality of second strip-shaped branch electrodes 725 respectively connected to the frame electrode 80, and the plurality of Two strip-shaped branch electrodes 725 are distributed over the four first pixel electrodes 71
  • the pixel electrode region 713 is disposed in parallel with and alternately with the first strip-shaped branch electrode 715 of each pixel electrode region 713.
  • the bezel electrode 80 includes a first horizontal electrode 81 and a second horizontal electrode 82 parallel to the horizontal main electrode 712, and a first vertical electrode 83 and a second parallel to the vertical main electrode 711.
  • a vertical electrode 84; the first horizontal electrode 81, the first vertical electrode 83, the second horizontal electrode 82, and the second vertical electrode 84 are sequentially connected; the first horizontal electrode 81 is adjacent to the first drain
  • the first horizontal electrode 81 is disposed with an opening 815.
  • the vertical main electrode 711 of the first pixel electrode 71 passes through the opening 815 and is respectively associated with the opening.
  • the first horizontal electrode 81 and the second horizontal electrode 82 on both sides of the 815 are not connected.
  • the first pixel electrode 71 includes a first connection electrode 710 connected to the vertical stem electrode 711, and the first connection electrode 710 passes through the first via hole 61 and the first drain electrode 53.
  • the first pixel electrode 71 is electrically connected to the first drain electrode 53 in contact with each other.
  • the second pixel electrode 72 includes a second connection electrode 720 connected to the frame electrode 80, and the second connection electrode 720 is in contact with the second drain 56 through the second through hole 62.
  • the second pixel electrode 72 is electrically connected to the second drain 56.
  • the second connection electrode 720 is connected to the first horizontal electrode 81.
  • the base substrate 10 is a transparent substrate; preferably, the base substrate 10 is a glass substrate.
  • the material of the first metal layer 20 and the second metal layer 50 includes at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).
  • the material of the semiconductor layer 40 includes at least one of amorphous silicon, polycrystalline silicon, and a metal oxide semiconductor material; and the metal oxide semiconductor material may be indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the materials of the first insulating layer 30 and the second insulating layer 60 respectively include at least one of silicon oxide (SiOx) and silicon nitride (SiNx).
  • the materials of the first pixel electrode 71 and the second pixel electrode 72 are both transparent conductive metal oxides, and the transparent conductive metal oxide is preferably indium tin oxide (ITO).
  • ITO indium tin oxide
  • two pixel electrodes that are not connected are disposed in one pixel structure, and the two pixel electrodes are respectively connected to two data lines through respective thin film transistors, and when the normal display is performed, the two data lines are respectively applied differently.
  • the voltage causes the potentials on the two pixel electrodes to be different, and the different potentials on the two pixel electrodes cause liquid crystal molecules close to different pixel electrodes to form different polar angles, thereby forming a distribution and existence of various polar angles in the liquid crystal, thereby reducing The difference in phase difference of the liquid crystals in different directions, thereby improving the viewing angle and color shift of the vertical alignment type liquid crystal display.
  • the present invention further provides a method for fabricating the above pixel structure, including the following steps:
  • Step 1 As shown in FIG. 5, a base substrate 10 is provided on which a first metal layer 20 is formed, the first metal layer 20 including a scan line 21.
  • the base substrate 10 is a transparent substrate; preferably, the base substrate 10 is a glass substrate.
  • the material of the first metal layer 20 includes at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).
  • Step 2 As shown in FIG. 6, a first insulating layer 30 is formed on the first metal layer 20 and the base substrate 10.
  • the material of the first insulating layer 30 includes at least one of silicon oxide and silicon nitride.
  • Step 3 as shown in FIG. 7, a semiconductor layer 40 is formed on the first insulating layer 30, and the semiconductor layer 40 includes a first active layer 41 and a second active layer 42 disposed at intervals, as shown in FIG.
  • the first active layer 41 and the second active layer 42 are both disposed above the scan line 21 .
  • the material of the semiconductor layer 40 includes at least one of amorphous silicon, polycrystalline silicon, and a metal oxide semiconductor material; and the metal oxide semiconductor material may be indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • Step 4 as shown in Figure 8, forming a second metal layer 50 on the semiconductor layer 40 and the first insulating layer 30;
  • the second metal layer 50 includes a first data line 51, a first source 52 connected to one side of the first data line 51, and a first drain 53 spaced apart from the first source 52. a second data line 54, a second source 55 connected to the second data line 54 side, and a second drain 56 spaced apart from the second source 55;
  • the first data line 51 and the second data line 54 respectively intersect the scan line 21 vertically; the first source 52 and the first drain 53 are respectively opposite to both sides of the first active layer 41 The second source 55 and the second drain 56 are in contact with both sides of the second active layer 42 respectively.
  • the material of the second metal layer 50 includes at least one of molybdenum, aluminum, copper, and titanium.
  • Step 5 as shown in Figure 9, forming a second insulating layer 60 on the second metal layer 50, the semiconductor layer 40, and the first insulating layer 30;
  • a first via hole 61 corresponding to the first drain electrode 53 and a second via hole corresponding to the second drain hole 56 are formed on the second insulating layer 60. 62.
  • the material of the second insulating layer 60 includes at least one of silicon oxide and silicon nitride.
  • a transparent conductive layer 70 is formed on the second insulating layer 60, the transparent conductive layer 70 includes a first pixel electrode 71 and a second pixel electrode 72 that are not connected;
  • the first pixel electrode 71 is in contact with the first drain electrode 53 through the first via hole 61; the second pixel electrode 72 is in phase with the second drain electrode 56 through the second via hole 62 contact.
  • the first pixel electrode 71 includes vertically intersecting vertical trunk electrodes 711 and horizontal trunk electrodes 712, and four pixel electrodes divided by the horizontal trunk electrodes 712 and the vertical stem electrodes 711 perpendicularly intersecting a region 713, each of the pixel electrode regions 713 includes a plurality of first strip-shaped branch electrodes 715 connected at an angle of ⁇ 45° or ⁇ 135° to the horizontal stem electrode 712 or the vertical stem electrode 711, A plurality of first strip-shaped branch electrodes 715 of the four pixel electrode regions 713 are vertically symmetrical with respect to the vertical stem electrode 711 along the horizontal stem electrode 711, respectively, to form a "m"-shaped pixel electrode structure.
  • the second pixel electrode 72 includes a frame electrode 80 located at a periphery of the first pixel electrode 71, and a plurality of second strip-shaped branch electrodes 725 respectively connected to the frame electrode 80, and the plurality of The two strip-shaped branch electrodes 725 are distributed in the four pixel electrode regions 713 of the first pixel electrode 71, and are arranged in parallel with and alternately with the first strip-shaped branch electrodes 715 of each of the pixel electrode regions 713.
  • the bezel electrode 80 includes a first horizontal electrode 81 and a second horizontal electrode 82 parallel to the horizontal main electrode 712, and a first vertical electrode 83 and a second parallel to the vertical main electrode 711.
  • a vertical electrode 84; the first horizontal electrode 81, the first vertical electrode 83, the second horizontal electrode 82, and the second vertical electrode 84 are sequentially connected; the first horizontal electrode 81 is adjacent to the first drain
  • the first horizontal electrode 81 is disposed with an opening 815.
  • the vertical main electrode 711 of the first pixel electrode 71 passes through the opening 815 and is respectively associated with the opening.
  • the first horizontal electrode 81 and the second horizontal electrode 82 on both sides of the 815 are not connected.
  • the first pixel electrode 71 includes a first connection electrode 710 connected to the vertical stem electrode 711, and the first connection electrode 710 passes through the first via hole 61 and the first drain electrode 53.
  • the first pixel electrode 71 is electrically connected to the first drain electrode 53 in contact with each other.
  • the second pixel electrode 72 includes a second connection electrode 720 connected to the frame electrode 80, and the second connection electrode 720 is in contact with the second drain 56 through the second through hole 62.
  • the second pixel electrode 72 is electrically connected to the second drain 56.
  • the second connection electrode 720 is connected to the first horizontal electrode 81.
  • the manufacturing method of the above pixel structure is simple and easy to operate, and the obtained pixel structure can form a plurality of polar angle distributions and existences in the liquid crystal during normal display, and reduce the difference of the phase difference of the liquid crystals in different directions, thereby improving The viewing angle and color shift of the vertical alignment type liquid crystal display.
  • the present invention provides a pixel structure and a method of fabricating the same.
  • two pixel electrodes that are not connected are disposed in one pixel structure, and the two pixel electrodes are respectively connected to two data lines through respective thin film transistors.
  • the two data lines are respectively Different voltages are applied to make the potentials on the two pixel electrodes different, and different potentials on the two pixel electrodes cause liquid crystal molecules close to different pixel electrodes to form different polar angles, thereby forming a plurality of polar angle distributions and existence in the liquid crystal.
  • the difference in phase difference of the liquid crystals in different directions is reduced, thereby improving the viewing angle and color shift of the vertical alignment type liquid crystal display.
  • the method for fabricating the pixel structure of the invention has the advantages that the process is simple and easy to operate, and the obtained pixel structure can form a plurality of polar angle distributions and existences in the liquid crystal during normal display, and reduce the difference of the phase difference of the liquid crystals in different directions. Thereby improving the viewing angle and color shift of the vertical alignment type liquid crystal display.

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Abstract

一种像素结构及像素结构的制作方法。在像素结构中，设置有两个不相连接的像素电极（71，72），两个像素电极（71，72）分别通过各自的薄膜晶体管与两条数据线（51，54）相连。正常显示时，两条数据线（51，54）上分别施加不同电压，使两个像素电极（71，72）上的电位不同，两个像素电极（71，72）上不同的电位使靠近不同像素电极（71，72）的液晶分子形成不同的极角，从而在液晶中形成多种极角的分布和存在，减小液晶沿不同方向相位差的差值，从而改善垂直配向型液晶显示器的视角和色偏。

Description

像素结构及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种像素结构及其制作方法。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成。
然而，与阴极射线管显示器相比，薄膜晶体管液晶显示器(TFT-LCD)的视角相对较窄，这就为其在对视角要求严格的高端显示领域的应用带来了很大局限，如航空航天、医疗等领域。随着LCD领域广视角技术的迅速发展，目前很多产品的视角已经可以达到水平视角和垂直视角分别为85°/85°，甚至更大的视角。
LCD广视角技术目前主要包括多畴垂直取向(Multi-domain Vertical Alignment，MVA)技术和面内转换(In Plane Switching，IPS)技术。MVA技术的优点是正面对比度高，通常可以达到4000:1及以上；IPS技术通过在薄膜晶体管阵列基板上形成平行且重复分布的像素电极和公用电极，使液晶分子在水平电场的作用下转动，从而形成广视角，但是其对比度相对较低，通常在2000:1以下。
如图1所示，为现有的一种垂直配向型液晶显示器的像素结构，其包括一薄膜晶体管100、及与该薄膜晶体管100电性连接的一像素电极200，该像素电极200由四个区域210构成，在该像素电极200的驱动下，对应该像素电极200的一个区域210中的液晶分子具有相同的极角(液晶分子 的长轴方向与显示屏之间的夹角)，从不同的视角对显示屏进行观看时，由于液晶分子的双折射效应，在不同视角下看到同一液晶分子的折射率不同，因此接收到的光线的强度也不同，具体来讲，观察视角越大，看到的屏幕亮度越低，从而使得采用该像素结构的液晶显示器的视角特性较差。
发明内容
本发明的目的在于提供一种像素结构，能够改善垂直配向型液晶显示器的视角和色偏。
本发明的目的还在于提供一种像素结构的制作方法，能够改善垂直配向型液晶显示器的视角和色偏。
为实现上述目的，本发明首先提供一种像素结构，包括衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板上的第一绝缘层、设于所述第一绝缘层上的半导体层、设于所述半导体层及第一绝缘层上的第二金属层、设于所述第二金属层、半导体层、及第一绝缘层上的第二绝缘层、及设于所述第二绝缘层上的透明导电层；
所述第一金属层包括扫描线；
所述半导体层包括间隔设置的第一有源层与第二有源层，所述第一有源层与第二有源层均对应于所述扫描线上方设置；
所述第二金属层包括第一数据线、连接于所述第一数据线一侧的第一源极、与所述第一源极间隔设置的第一漏极、第二数据线、连接于所述第二数据线一侧的第二源极、以及与所述第二源极间隔设置的第二漏极；
所述第一数据线与第二数据线分别与所述扫描线垂直相交叉；所述第一源极与第一漏极分别与所述第一有源层的两侧相接触；所述第二源极与第二漏极分别与所述第二有源层的两侧相接触；
所述透明导电层包括不相连接的第一像素电极与第二像素电极；
所述第二绝缘层上设有对应于所述第一漏极上方的第一通孔以及对应于所述第二漏极上方的第二通孔，所述第一像素电极通过所述第一通孔与所述第一漏极相接触；所述第二像素电极通过所述第二通孔与所述第二漏极相接触。
所述第一像素电极包括垂直相交的竖直主干电极和水平主干电极、以及由所述水平主干电极与所述竖直主干电极垂直相交所分成的四个像素电极区域，每个像素电极区域均包括与所述水平主干电极或所述竖直主干电极呈±45°或±135°夹角连接的数个第一条状分支电极，所述四个像素电极区域中的数个第一条状分支电极分别沿所述水平主干电极与所述竖直主干 电极上下左右对称，形成“米”字型的像素电极结构。
所述第二像素电极包括位于所述第一像素电极外围的边框电极、以及分别连接于所述边框电极的数个第二条状分支电极，所述数个第二条状分支电极分布于所述第一像素电极的四个像素电极区域中，并且与每一像素电极区域的第一条状分支电极平行且交错设置。
所述边框电极包括平行于所述水平主干电极的第一水平电极与第二水平电极、以及平行于所述竖直主干电极的第一竖直电极与第二竖直电极；所述第一水平电极、第一竖直电极、第二水平电极、及第二竖直电极依次相连；所述第一水平电极靠近所述第一漏极与所述第二漏极设置；所述第一水平电极上设有一开口，所述第一像素电极的竖直主干电极从该开口中穿过，并分别与该开口两侧的第一水平电极及第二水平电极不相连接。
所述第一像素电极包括与所述竖直主干电极相连的第一连接电极，所述第一连接电极通过所述第一通孔与所述第一漏极相接触，使得第一像素电极与所述第一漏极电性连接；
所述第二像素电极包括与所述边框电极相连的第二连接电极，所述第二连接电极通过所述第二通孔与所述第二漏极相接触，使得第二像素电极与所述第二漏极电性连接。
本发明还提供一种像素结构的制作方法，包括如下步骤：
步骤1、提供衬底基板，在所述衬底基板上形成第一金属层，所述第一金属层包括扫描线；
步骤2、在所述第一金属层及衬底基板上形成第一绝缘层；
步骤3、在所述第一绝缘层上形成半导体层，所述半导体层包括间隔设置的第一有源层与第二有源层，所述第一有源层与第二有源层均对应于所述扫描线上方设置；
步骤4、在所述半导体层及第一绝缘层上形成第二金属层；
所述第二金属层包括第一数据线、连接于所述第一数据线一侧的第一源极、与所述第一源极间隔设置的第一漏极、第二数据线、连接于所述第二数据线一侧的第二源极、以及与所述第二源极间隔设置的第二漏极；
所述第一数据线与第二数据线分别与所述扫描线垂直相交叉；所述第一源极与第一漏极分别与所述第一有源层的两侧相接触；所述第二源极与第二漏极分别与所述第二有源层的两侧相接触；
步骤5、在所述第二金属层、半导体层、及第一绝缘层上形成第二绝缘层；
在所述第二绝缘层上形成对应于所述第一漏极上方的第一通孔以及对 应于所述第二漏极上方的第二通孔；
步骤6、在所述第二绝缘层上形成透明导电层，所述透明导电层包括不相连接的第一像素电极与第二像素电极；
所述第一像素电极通过所述第一通孔与所述第一漏极相接触；所述第二像素电极通过所述第二通孔与所述第二漏极相接触。
所述第一像素电极包括垂直相交的竖直主干电极和水平主干电极、以及由所述水平主干电极与所述竖直主干电极垂直相交所分成的四个像素电极区域，每个像素电极区域均包括与所述水平主干电极或所述竖直主干电极呈±45°或±135°夹角连接的数个第一条状分支电极，所述四个像素电极区域中的数个第一条状分支电极分别沿所述水平主干电极与所述竖直主干电极上下左右对称，形成“米”字型的像素电极结构。
所述第二像素电极包括位于所述第一像素电极外围的边框电极、以及分别连接于所述边框电极的数个第二条状分支电极，所述数个第二条状分支电极分布于所述第一像素电极的四个像素电极区域中，并且与每一像素电极区域的第一条状分支电极平行且交错设置。
所述边框电极包括平行于所述水平主干电极的第一水平电极与第二水平电极、以及平行于所述竖直主干电极的第一竖直电极与第二竖直电极；所述第一水平电极、第一竖直电极、第二水平电极、及第二竖直电极依次相连；所述第一水平电极靠近所述第一漏极与所述第二漏极设置；所述第一水平电极上设有一开口，所述第一像素电极的竖直主干电极从该开口中穿过，并分别与该开口两侧的第一水平电极及第二水平电极不相连接。
所述第一像素电极包括与所述竖直主干电极相连的第一连接电极，所述第一连接电极通过所述第一通孔与所述第一漏极相接触，使得第一像素电极与所述第一漏极电性连接；
所述第二像素电极包括与所述边框电极相连的第二连接电极，所述第二连接电极通过所述第二通孔与所述第二漏极相接触，使得第二像素电极与所述第二漏极电性连接。
本发明还提供一种像素结构，包括衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板上的第一绝缘层、设于所述第一绝缘层上的半导体层、设于所述半导体层及第一绝缘层上的第二金属层、设于所述第二金属层、半导体层、及第一绝缘层上的第二绝缘层、及设于所述第二绝缘层上的透明导电层；
所述第一金属层包括扫描线；
所述半导体层包括间隔设置的第一有源层与第二有源层，所述第一有 源层与第二有源层均对应于所述扫描线上方设置；
所述第二金属层包括第一数据线、连接于所述第一数据线一侧的第一源极、与所述第一源极间隔设置的第一漏极、第二数据线、连接于所述第二数据线一侧的第二源极、以及与所述第二源极间隔设置的第二漏极；
所述第一数据线与第二数据线分别与所述扫描线垂直相交叉；所述第一源极与第一漏极分别与所述第一有源层的两侧相接触；所述第二源极与第二漏极分别与所述第二有源层的两侧相接触；
所述透明导电层包括不相连接的第一像素电极与第二像素电极；
所述第二绝缘层上设有对应于所述第一漏极上方的第一通孔以及对应于所述第二漏极上方的第二通孔，所述第一像素电极通过所述第一通孔与所述第一漏极相接触；所述第二像素电极通过所述第二通孔与所述第二漏极相接触；
其中，所述第一像素电极包括垂直相交的竖直主干电极和水平主干电极、以及由所述水平主干电极与所述竖直主干电极垂直相交所分成的四个像素电极区域，每个像素电极区域均包括与所述水平主干电极或所述竖直主干电极呈±45°或±135°夹角连接的数个第一条状分支电极，所述四个像素电极区域中的数个第一条状分支电极分别沿所述水平主干电极与所述竖直主干电极上下左右对称，形成“米”字型的像素电极结构；
其中，所述第二像素电极包括位于所述第一像素电极外围的边框电极、以及分别连接于所述边框电极的数个第二条状分支电极，所述数个第二条状分支电极分布于所述第一像素电极的四个像素电极区域中，并且与每一像素电极区域的第一条状分支电极平行且交错设置；
其中，所述边框电极包括平行于所述水平主干电极的第一水平电极与第二水平电极、以及平行于所述竖直主干电极的第一竖直电极与第二竖直电极；所述第一水平电极、第一竖直电极、第二水平电极、及第二竖直电极依次相连；所述第一水平电极靠近所述第一漏极与所述第二漏极设置；所述第一水平电极上设有一开口，所述第一像素电极的竖直主干电极从该开口中穿过，并分别与该开口两侧的第一水平电极及第二水平电极不相连接；
其中，所述第一像素电极包括与所述竖直主干电极相连的第一连接电极，所述第一连接电极通过所述第一通孔与所述第一漏极相接触，使得第一像素电极与所述第一漏极电性连接；
所述第二像素电极包括与所述边框电极相连的第二连接电极，所述第二连接电极通过所述第二通孔与所述第二漏极相接触，使得第二像素电极 与所述第二漏极电性连接。
本发明的有益效果：本发明提供的一种像素结构，通过在一个像素结构中设置两个不相连接的像素电极，该两个像素电极分别通过各自的薄膜晶体管与两条数据线相连，正常显示时，两条数据线上分别施加不同电压，使两个像素电极上的电位不同，两个像素电极上不同的电位使靠近不同像素电极的液晶分子形成不同的极角，从而在液晶中形成多种极角的分布和存在，减小液晶沿不同方向相位差的差值，从而改善垂直配向型液晶显示器的视角和色偏。本发明提供的一种像素结构的制作方法，制程简单易操作，制得的像素结构在正常显示时，能够在液晶中形成多种极角的分布和存在，减小液晶沿不同方向相位差的差值，从而改善垂直配向型液晶显示器的视角和色偏。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的一种垂直配向型液晶显示器的像素结构的俯视示意图；
图2为本发明的像素结构的俯视示意图；
图3为图2沿A-A线的剖视示意图；
图4为图2沿B-B线的剖视示意图；
图5为本发明的像素结构的第一金属层的俯视示意图；
图6为本发明的像素结构的第一绝缘层的俯视示意图；
图7为本发明的像素结构的半导体层的俯视示意图；
图8为本发明的像素结构的第二金属层的俯视示意图；
图9为本发明的像素结构的第二绝缘层的俯视示意图；
图10为本发明的像素结构的透明导电层的俯视示意图；
图11为本发明的像素结构的制作方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2-10，本发明提供一种像素结构，包括衬底基板10、设于所述衬底基板10上的第一金属层20、设于所述第一金属层20及衬底基板10上的第一绝缘层30、设于所述第一绝缘层30上的半导体层40、设于所述半导体层40及第一绝缘层30上的第二金属层50、设于所述第二金属层50、半导体层40、及第一绝缘层30上的第二绝缘层60、及设于所述第二绝缘层60上的透明导电层70；
如图5所示，所述第一金属层20包括扫描线21；
如图7所示，所述半导体层40包括间隔设置的第一有源层41与第二有源层42，所述第一有源层41与第二有源层42均对应于所述扫描线21上方设置；
如图8所示，所述第二金属层50包括第一数据线51、连接于所述第一数据线51一侧的第一源极52、与所述第一源极52间隔设置的第一漏极53、第二数据线54、连接于所述第二数据线54一侧的第二源极55、以及与所述第二源极55间隔设置的第二漏极56；
所述第一数据线51与第二数据线54分别与所述扫描线21垂直相交叉；所述第一源极52与第一漏极53分别与所述第一有源层41的两侧相接触；所述第二源极55与第二漏极56分别与所述第二有源层42的两侧相接触；
如图10所示，所述透明导电层70包括不相连接的第一像素电极71与第二像素电极72；
如图10与图2-4所示，所述第二绝缘层60上设有对应于所述第一漏极53上方的第一通孔61以及对应于所述第二漏极56上方的第二通孔62，所述第一像素电极71通过所述第一通孔61与所述第一漏极53相接触；所述第二像素电极72通过所述第二通孔62与所述第二漏极56相接触。
具体的，所述第一像素电极71包括垂直相交的竖直主干电极711和水平主干电极712、以及由所述水平主干电极712与所述竖直主干电极711垂直相交所分成的四个像素电极区域713，每个像素电极区域713均包括与所述水平主干电极712或所述竖直主干电极711呈±45°或±135°夹角连接的数个第一条状分支电极715，所述四个像素电极区域713中的数个第一条状分支电极715分别沿所述水平主干电极712与所述竖直主干电极711上下左右对称，形成“米”字型的像素电极结构。
具体的，所述第二像素电极72包括位于所述第一像素电极71外围的边框电极80、以及分别连接于所述边框电极80的数个第二条状分支电极725，所述数个第二条状分支电极725分布于所述第一像素电极71的四个 像素电极区域713中，并且与每一像素电极区域713的第一条状分支电极715平行且交错设置。
具体的，所述边框电极80包括平行于所述水平主干电极712的第一水平电极81与第二水平电极82、以及平行于所述竖直主干电极711的第一竖直电极83与第二竖直电极84；所述第一水平电极81、第一竖直电极83、第二水平电极82、及第二竖直电极84依次相连；所述第一水平电极81靠近所述第一漏极53与所述第二漏极56设置；所述第一水平电极81上设有一开口815，所述第一像素电极71的竖直主干电极711从该开口815中穿过，并分别与该开口815两侧的第一水平电极81及第二水平电极82不相连接。
进一步的，所述第一像素电极71包括与所述竖直主干电极711相连的第一连接电极710，所述第一连接电极710通过所述第一通孔61与所述第一漏极53相接触，使得第一像素电极71与所述第一漏极53电性连接。
进一步的，所述第二像素电极72包括与所述边框电极80相连的第二连接电极720，所述第二连接电极720通过所述第二通孔62与所述第二漏极56相接触，使得第二像素电极72与所述第二漏极56电性连接。优选的，所述第二连接电极720连接至所述第一水平电极81。
具体的，所述衬底基板10为透明基板；优选的，所述衬底基板10为玻璃基板。
具体的，所述第一金属层20与所述第二金属层50的材料包括钼(Mo)、铝(Al)、铜(Cu)、及钛(Ti)中的至少一种。
具体的，所述半导体层40的材料包括非晶硅、多晶硅、及金属氧化物半导体材料中的至少一种；所述金属氧化物半导体材料可以为铟镓锌氧化物(IGZO)。
具体的，所述第一绝缘层30与第二绝缘层60的材料分别包括氧化硅(SiOx)与氮化硅(SiNx)中的至少一种。
具体的，所述第一像素电极71与第二像素电极72的材料均为透明导电金属氧化物，所述透明导电金属氧化物优选为氧化铟锡(ITO)。
上述像素结构，通过在一个像素结构中设置两个不相连接的像素电极，该两个像素电极分别通过各自的薄膜晶体管与两条数据线相连，正常显示时，两条数据线上分别施加不同电压，使两个像素电极上的电位不同，两个像素电极上不同的电位使靠近不同像素电极的液晶分子形成不同的极角，从而在液晶中形成多种极角的分布和存在，减小液晶沿不同方向相位差的差值，从而改善垂直配向型液晶显示器的视角和色偏。
请参阅图11，本发明还提供一种上述像素结构的制作方法，包括如下步骤：
步骤1、如图5所示，提供衬底基板10，在所述衬底基板10上形成第一金属层20，所述第一金属层20包括扫描线21。
具体的，所述衬底基板10为透明基板；优选的，所述衬底基板10为玻璃基板。
具体的，所述第一金属层20的材料包括钼(Mo)、铝(Al)、铜(Cu)、及钛(Ti)中的至少一种。
步骤2、如图6所示，在所述第一金属层20及衬底基板10上形成第一绝缘层30。
具体的，所述第一绝缘层30的材料包括氧化硅与氮化硅中的至少一种。
步骤3、如图7所示，在所述第一绝缘层30上形成半导体层40，所述半导体层40包括间隔设置的第一有源层41与第二有源层42，如图2所示，所述第一有源层41与第二有源层42均对应于所述扫描线21上方设置。
具体的，所述半导体层40的材料包括非晶硅、多晶硅、及金属氧化物半导体材料中的至少一种；所述金属氧化物半导体材料可以为铟镓锌氧化物(IGZO)。
步骤4、如图8所示，在所述半导体层40及第一绝缘层30上形成第二金属层50；
所述第二金属层50包括第一数据线51、连接于所述第一数据线51一侧的第一源极52、与所述第一源极52间隔设置的第一漏极53、第二数据线54、连接于所述第二数据线54一侧的第二源极55、以及与所述第二源极55间隔设置的第二漏极56；
所述第一数据线51与第二数据线54分别与所述扫描线21垂直相交叉；所述第一源极52与第一漏极53分别与所述第一有源层41的两侧相接触；所述第二源极55与第二漏极56分别与所述第二有源层42的两侧相接触。
具体的，所述第二金属层50的材料包括钼、铝、铜、及钛中的至少一种。
步骤5、如图9所示，在所述第二金属层50、半导体层40、及第一绝缘层30上形成第二绝缘层60；
如图3-4所示，在所述第二绝缘层60上形成对应于所述第一漏极53上方的第一通孔61以及对应于所述第二漏极56上方的第二通孔62。
具体的，所述第二绝缘层60的材料包括氧化硅与氮化硅中的至少一种。
步骤6、如图10所示，在所述第二绝缘层60上形成透明导电层70，所述透明导电层70包括不相连接的第一像素电极71与第二像素电极72；
所述第一像素电极71通过所述第一通孔61与所述第一漏极53相接触；所述第二像素电极72通过所述第二通孔62与所述第二漏极56相接触。
具体的，所述第一像素电极71包括垂直相交的竖直主干电极711和水平主干电极712、以及由所述水平主干电极712与所述竖直主干电极711垂直相交所分成的四个像素电极区域713，每个像素电极区域713均包括与所述水平主干电极712或所述竖直主干电极711呈±45°或±135°夹角连接的数个第一条状分支电极715，所述四个像素电极区域713中的数个第一条状分支电极715分别沿所述水平主干电极712与所述竖直主干电极711上下左右对称，形成“米”字型的像素电极结构。
具体的，所述第二像素电极72包括位于所述第一像素电极71外围的边框电极80、以及分别连接于所述边框电极80的数个第二条状分支电极725，所述数个第二条状分支电极725分布于所述第一像素电极71的四个像素电极区域713中，并且与每一像素电极区域713的第一条状分支电极715平行且交错设置。
具体的，所述边框电极80包括平行于所述水平主干电极712的第一水平电极81与第二水平电极82、以及平行于所述竖直主干电极711的第一竖直电极83与第二竖直电极84；所述第一水平电极81、第一竖直电极83、第二水平电极82、及第二竖直电极84依次相连；所述第一水平电极81靠近所述第一漏极53与所述第二漏极56设置；所述第一水平电极81上设有一开口815，所述第一像素电极71的竖直主干电极711从该开口815中穿过，并分别与该开口815两侧的第一水平电极81及第二水平电极82不相连接。
进一步的，所述第一像素电极71包括与所述竖直主干电极711相连的第一连接电极710，所述第一连接电极710通过所述第一通孔61与所述第一漏极53相接触，使得第一像素电极71与所述第一漏极53电性连接。
进一步的，所述第二像素电极72包括与所述边框电极80相连的第二连接电极720，所述第二连接电极720通过所述第二通孔62与所述第二漏极56相接触，使得第二像素电极72与所述第二漏极56电性连接。优选的，所述第二连接电极720连接至所述第一水平电极81。
上述像素结构的制作方法，制程简单易操作，制得的像素结构在正常显示时，能够在液晶中形成多种极角的分布和存在，减小液晶沿不同方向相位差的差值，从而改善垂直配向型液晶显示器的视角和色偏。
综上所述，本发明提供一种像素结构及其制作方法。本发明的像素结构，通过在一个像素结构中设置两个不相连接的像素电极，该两个像素电极分别通过各自的薄膜晶体管与两条数据线相连，正常显示时，两条数据线上分别施加不同电压，使两个像素电极上的电位不同，两个像素电极上不同的电位使靠近不同像素电极的液晶分子形成不同的极角，从而在液晶中形成多种极角的分布和存在，减小液晶沿不同方向相位差的差值，从而改善垂直配向型液晶显示器的视角和色偏。本发明的像素结构的制作方法，制程简单易操作，制得的像素结构在正常显示时，能够在液晶中形成多种极角的分布和存在，减小液晶沿不同方向相位差的差值，从而改善垂直配向型液晶显示器的视角和色偏。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种像素结构，包括衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板上的第一绝缘层、设于所述第一绝缘层上的半导体层、设于所述半导体层及第一绝缘层上的第二金属层、设于所述第二金属层、半导体层、及第一绝缘层上的第二绝缘层、及设于所述第二绝缘层上的透明导电层；
    所述第一金属层包括扫描线；
    所述半导体层包括间隔设置的第一有源层与第二有源层，所述第一有源层与第二有源层均对应于所述扫描线上方设置；
    所述第二金属层包括第一数据线、连接于所述第一数据线一侧的第一源极、与所述第一源极间隔设置的第一漏极、第二数据线、连接于所述第二数据线一侧的第二源极、以及与所述第二源极间隔设置的第二漏极；
    所述第一数据线与第二数据线分别与所述扫描线垂直相交叉；所述第一源极与第一漏极分别与所述第一有源层的两侧相接触；所述第二源极与第二漏极分别与所述第二有源层的两侧相接触；
    所述透明导电层包括不相连接的第一像素电极与第二像素电极；
    所述第二绝缘层上设有对应于所述第一漏极上方的第一通孔以及对应于所述第二漏极上方的第二通孔，所述第一像素电极通过所述第一通孔与所述第一漏极相接触；所述第二像素电极通过所述第二通孔与所述第二漏极相接触。
  2. 如权利要求1所述的像素结构，其中，所述第一像素电极包括垂直相交的竖直主干电极和水平主干电极、以及由所述水平主干电极与所述竖直主干电极垂直相交所分成的四个像素电极区域，每个像素电极区域均包括与所述水平主干电极或所述竖直主干电极呈±45°或±135°夹角连接的数个第一条状分支电极，所述四个像素电极区域中的数个第一条状分支电极分别沿所述水平主干电极与所述竖直主干电极上下左右对称，形成“米”字型的像素电极结构。
  3. 如权利要求2所述的像素结构，其中，所述第二像素电极包括位于所述第一像素电极外围的边框电极、以及分别连接于所述边框电极的数个第二条状分支电极，所述数个第二条状分支电极分布于所述第一像素电极的四个像素电极区域中，并且与每一像素电极区域的第一条状分支电极平行且交错设置。
  4. 如权利要求3所述的像素结构，其中，所述边框电极包括平行于所述水平主干电极的第一水平电极与第二水平电极、以及平行于所述竖直主干电极的第一竖直电极与第二竖直电极；所述第一水平电极、第一竖直电极、第二水平电极、及第二竖直电极依次相连；所述第一水平电极靠近所述第一漏极与所述第二漏极设置；所述第一水平电极上设有一开口，所述第一像素电极的竖直主干电极从该开口中穿过，并分别与该开口两侧的第一水平电极及第二水平电极不相连接。
  5. 如权利要求3所述的像素结构，其中，所述第一像素电极包括与所述竖直主干电极相连的第一连接电极，所述第一连接电极通过所述第一通孔与所述第一漏极相接触，使得第一像素电极与所述第一漏极电性连接；
    所述第二像素电极包括与所述边框电极相连的第二连接电极，所述第二连接电极通过所述第二通孔与所述第二漏极相接触，使得第二像素电极与所述第二漏极电性连接。
  6. 一种像素结构的制作方法，包括如下步骤：
    步骤1、提供衬底基板，在所述衬底基板上形成第一金属层，所述第一金属层包括扫描线；
    步骤2、在所述第一金属层及衬底基板上形成第一绝缘层；
    步骤3、在所述第一绝缘层上形成半导体层，所述半导体层包括间隔设置的第一有源层与第二有源层，所述第一有源层与第二有源层均对应于所述扫描线上方设置；
    步骤4、在所述半导体层及第一绝缘层上形成第二金属层；
    所述第二金属层包括第一数据线、连接于所述第一数据线一侧的第一源极、与所述第一源极间隔设置的第一漏极、第二数据线、连接于所述第二数据线一侧的第二源极、以及与所述第二源极间隔设置的第二漏极；
    所述第一数据线与第二数据线分别与所述扫描线垂直相交叉；所述第一源极与第一漏极分别与所述第一有源层的两侧相接触；所述第二源极与第二漏极分别与所述第二有源层的两侧相接触；
    步骤5、在所述第二金属层、半导体层、及第一绝缘层上形成第二绝缘层；
    在所述第二绝缘层上形成对应于所述第一漏极上方的第一通孔以及对应于所述第二漏极上方的第二通孔；
    步骤6、在所述第二绝缘层上形成透明导电层，所述透明导电层包括不相连接的第一像素电极与第二像素电极；
    所述第一像素电极通过所述第一通孔与所述第一漏极相接触；所述第 二像素电极通过所述第二通孔与所述第二漏极相接触。
  7. 如权利要求6所述的像素结构的制作方法，其中，所述第一像素电极包括垂直相交的竖直主干电极和水平主干电极、以及由所述水平主干电极与所述竖直主干电极垂直相交所分成的四个像素电极区域，每个像素电极区域均包括与所述水平主干电极或所述竖直主干电极呈±45°或±135°夹角连接的数个第一条状分支电极，所述四个像素电极区域中的数个第一条状分支电极分别沿所述水平主干电极与所述竖直主干电极上下左右对称，形成“米”字型的像素电极结构。
  8. 如权利要求7所述的像素结构的制作方法，其中，所述第二像素电极包括位于所述第一像素电极外围的边框电极、以及分别连接于所述边框电极的数个第二条状分支电极，所述数个第二条状分支电极分布于所述第一像素电极的四个像素电极区域中，并且与每一像素电极区域的第一条状分支电极平行且交错设置。
  9. 如权利要求8所述的像素结构的制作方法，其中，所述边框电极包括平行于所述水平主干电极的第一水平电极与第二水平电极、以及平行于所述竖直主干电极的第一竖直电极与第二竖直电极；所述第一水平电极、第一竖直电极、第二水平电极、及第二竖直电极依次相连；所述第一水平电极靠近所述第一漏极与所述第二漏极设置；所述第一水平电极上设有一开口，所述第一像素电极的竖直主干电极从该开口中穿过，并分别与该开口两侧的第一水平电极及第二水平电极不相连接。
  10. 如权利要求8所述的像素结构的制作方法，其中，所述第一像素电极包括与所述竖直主干电极相连的第一连接电极，所述第一连接电极通过所述第一通孔与所述第一漏极相接触，使得第一像素电极与所述第一漏极电性连接；
    所述第二像素电极包括与所述边框电极相连的第二连接电极，所述第二连接电极通过所述第二通孔与所述第二漏极相接触，使得第二像素电极与所述第二漏极电性连接。
  11. 一种像素结构，包括衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板上的第一绝缘层、设于所述第一绝缘层上的半导体层、设于所述半导体层及第一绝缘层上的第二金属层、设于所述第二金属层、半导体层、及第一绝缘层上的第二绝缘层、及设于所述第二绝缘层上的透明导电层；
    所述第一金属层包括扫描线；
    所述半导体层包括间隔设置的第一有源层与第二有源层，所述第一有 源层与第二有源层均对应于所述扫描线上方设置；
    所述第二金属层包括第一数据线、连接于所述第一数据线一侧的第一源极、与所述第一源极间隔设置的第一漏极、第二数据线、连接于所述第二数据线一侧的第二源极、以及与所述第二源极间隔设置的第二漏极；
    所述第一数据线与第二数据线分别与所述扫描线垂直相交叉；所述第一源极与第一漏极分别与所述第一有源层的两侧相接触；所述第二源极与第二漏极分别与所述第二有源层的两侧相接触；
    所述透明导电层包括不相连接的第一像素电极与第二像素电极；
    所述第二绝缘层上设有对应于所述第一漏极上方的第一通孔以及对应于所述第二漏极上方的第二通孔，所述第一像素电极通过所述第一通孔与所述第一漏极相接触；所述第二像素电极通过所述第二通孔与所述第二漏极相接触；
    其中，所述第一像素电极包括垂直相交的竖直主干电极和水平主干电极、以及由所述水平主干电极与所述竖直主干电极垂直相交所分成的四个像素电极区域，每个像素电极区域均包括与所述水平主干电极或所述竖直主干电极呈±45°或±135°夹角连接的数个第一条状分支电极，所述四个像素电极区域中的数个第一条状分支电极分别沿所述水平主干电极与所述竖直主干电极上下左右对称，形成“米”字型的像素电极结构；
    其中，所述第二像素电极包括位于所述第一像素电极外围的边框电极、以及分别连接于所述边框电极的数个第二条状分支电极，所述数个第二条状分支电极分布于所述第一像素电极的四个像素电极区域中，并且与每一像素电极区域的第一条状分支电极平行且交错设置；
    其中，所述边框电极包括平行于所述水平主干电极的第一水平电极与第二水平电极、以及平行于所述竖直主干电极的第一竖直电极与第二竖直电极；所述第一水平电极、第一竖直电极、第二水平电极、及第二竖直电极依次相连；所述第一水平电极靠近所述第一漏极与所述第二漏极设置；所述第一水平电极上设有一开口，所述第一像素电极的竖直主干电极从该开口中穿过，并分别与该开口两侧的第一水平电极及第二水平电极不相连接；
    其中，所述第一像素电极包括与所述竖直主干电极相连的第一连接电极，所述第一连接电极通过所述第一通孔与所述第一漏极相接触，使得第一像素电极与所述第一漏极电性连接；
    所述第二像素电极包括与所述边框电极相连的第二连接电极，所述第二连接电极通过所述第二通孔与所述第二漏极相接触，使得第二像素电极 与所述第二漏极电性连接。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10551708B2 (en) 2017-06-07 2020-02-04 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd Array substrates, manufacturing methods thereof and display panels
CN107121859B (zh) * 2017-06-07 2020-01-03 深圳市华星光电半导体显示技术有限公司 阵列基板及其制造方法、显示面板
CN107329334B (zh) * 2017-08-03 2019-03-12 深圳市华星光电半导体显示技术有限公司 像素电极及液晶显示面板
US10473993B2 (en) 2017-08-03 2019-11-12 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Pixel electrode and liquid crystal display panel
CN107505787A (zh) * 2017-09-15 2017-12-22 深圳市华星光电技术有限公司 一种阵列基板及其制程方法、液晶显示面板
CN110346993A (zh) * 2019-06-19 2019-10-18 深圳市华星光电半导体显示技术有限公司 液晶显示面板
CN110928067B (zh) * 2019-11-26 2023-11-28 深圳市华星光电半导体显示技术有限公司 一种像素电极结构及液晶显示面板
CN111025807A (zh) * 2019-12-16 2020-04-17 深圳市华星光电半导体显示技术有限公司 阵列基板及液晶显示装置
CN111142294B (zh) * 2020-02-21 2022-11-25 Tcl华星光电技术有限公司 像素电极结构及阵列基板
CN111338133A (zh) * 2020-03-12 2020-06-26 Tcl华星光电技术有限公司 一种液晶显示面板及显示装置
CN114488630B (zh) * 2022-01-18 2023-11-28 Tcl华星光电技术有限公司 像素电极、液晶显示面板及显示装置
CN114815408B (zh) * 2022-04-14 2023-09-26 Tcl华星光电技术有限公司 显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010048500A1 (en) * 2000-05-31 2001-12-06 Lim Kyu Hwan Fringe field switching mode liquid crystal display
CN101950549A (zh) * 2010-09-29 2011-01-19 友达光电股份有限公司 像素结构、液晶显示器以及液晶显示器像素驱动方法
CN102629607A (zh) * 2012-02-09 2012-08-08 京东方科技集团股份有限公司 阵列基板和双视场显示装置及其制造方法
CN102799035A (zh) * 2012-05-04 2012-11-28 京东方科技集团股份有限公司 一种阵列基板、液晶面板和显示装置
CN104024933A (zh) * 2011-10-31 2014-09-03 夏普株式会社 薄膜晶体管阵列基板和液晶显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103901684B (zh) * 2012-12-28 2018-02-09 上海中航光电子有限公司 一种ips模式的液晶显示器
KR102367968B1 (ko) * 2015-07-22 2022-02-25 삼성디스플레이 주식회사 액정 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010048500A1 (en) * 2000-05-31 2001-12-06 Lim Kyu Hwan Fringe field switching mode liquid crystal display
CN101950549A (zh) * 2010-09-29 2011-01-19 友达光电股份有限公司 像素结构、液晶显示器以及液晶显示器像素驱动方法
CN104024933A (zh) * 2011-10-31 2014-09-03 夏普株式会社 薄膜晶体管阵列基板和液晶显示装置
CN102629607A (zh) * 2012-02-09 2012-08-08 京东方科技集团股份有限公司 阵列基板和双视场显示装置及其制造方法
CN102799035A (zh) * 2012-05-04 2012-11-28 京东方科技集团股份有限公司 一种阵列基板、液晶面板和显示装置

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