CN111025807A - 阵列基板及液晶显示装置 - Google Patents

阵列基板及液晶显示装置 Download PDF

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CN111025807A
CN111025807A CN201911296682.4A CN201911296682A CN111025807A CN 111025807 A CN111025807 A CN 111025807A CN 201911296682 A CN201911296682 A CN 201911296682A CN 111025807 A CN111025807 A CN 111025807A
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pixel electrode
electrode
pixel
array substrate
thin film
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曹武
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/640,741 priority patent/US20220308403A1/en
Priority to PCT/CN2019/129206 priority patent/WO2021120306A1/zh
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Abstract

本发明公开了一种阵列基板与液晶显示装置，所述阵列基板包括：多条水平方向设置的扫描线、多条竖直方向设置的数据线以及阵列排布的多个像素单元，任意一所述的像素单元包括：像素电极：包括主区像素电极与次区像素电极；薄膜晶体管：包括控制所述主区像素电极的第一薄膜晶体管以及控制所述次区像素电极的第二薄膜晶体管，其中，所述主区像素电极与所述次区像素电极设置于所述第一薄膜晶体管与所述第二薄膜晶体管的同一侧。通过该设计，可有效提升像素区开口率。

Description

阵列基板及液晶显示装置
技术领域
本发明涉及显示技术领域，具体涉及一种阵列基板及液晶显示装置。
背景技术
VA LCD(Vertical Alignment Liquid Crystal Display，垂直配向型液晶显示器)以其宽视野角度、高对比度和无需配向摩擦等优势，成为大尺寸电视用TFT-LCD的常见显示模式。
在现有的VA型LCD显示技术中，为了更优的广视角体验，诸如色度与可视角，通常增加像素电极畴数的方式进行提升。例如，通过设置具有不同驱动电压差的主区和次区，所述主区和次区分别含4个轴对称的畴，通过空间和液晶取向差异化的特性，使得正视/侧视之差异减小，即改善侧视色偏等特性。但在这种八畴的像素架构中，一般会增加一个薄膜晶体管器件进行分压比调节，便会造成画素开口率/原生穿透率受限；另一方面，为了防止串扰风险，一般需要增加DBS电极等做电场屏蔽，将进一步限制开口率提升。
发明内容
本发明提供一种阵列基板与液晶显示装置，所述阵列基板的像素区有较大的开口率。
为解决上述问题，第一方面，本发明提供一种阵列基板，所述阵列基板包括：多条水平方向设置的扫描线、多条竖直方向设置的数据线以及阵列排布的多个像素单元，所述多个像素单元中的任一者包括：
像素电极：包括主区像素电极与次区像素电极；
薄膜晶体管：包括控制所述主区像素电极的第一薄膜晶体管以及控制所述次区像素电极的第二薄膜晶体管，
其中，所述主区像素电极与所述次区像素电极设置于所述第一薄膜晶体管与所述第二薄膜晶体管的同一侧。
进一步地，所述第一薄膜晶体管包括U型形状的第一源极与条状的第一漏极，所述第一漏极的一端插入所述第一源极的U型开口区；
所述第二薄膜晶体管包括U型形状的第二源极与条状的第二漏极，所述第二漏极的一端插入所述第二源极的U型开口区，
其中，所述第一源极的U型开口方向与所述第二源极的U型开口方向一致。
进一步地，所述第一源极与所述多条数据线中之一者电性连接，所述第一漏极与所述主区像素电极电性连接；所述第二源极与所述第一源极电性连接，所述第二漏极与所述次区像素电极电性连接。
进一步地，所述同一列的所述多个像素单元，由所述多条数据线中之一者给入信号。
进一步地，任意一列所述的像素单元中的像素电极呈现相同的极性，为第一极性，与所述任意一列像素单元相邻的另一列像素单元中的像素电极呈现第二极性，所述第一极性与所述第二极性为相反的极性。
进一步地，所述主区像素电极与所述次区像素电极均呈四畴设置，在所述四畴内分别设置了向四个不同方向延伸的多个分支电极。
进一步地，所述主区像素电极与所述次区像素电极间的最小距离大于等于2.5微米。
进一步地，所述主区像素电极与所述次区像素电极在列方向上相邻设置。
进一步地，所述次区像素电极的内部设置有空白区域，所述主区像素电极设置于所述空白区域。
另一方面，本发明还提供了一种液晶显示装置，包括前述的阵列基板。
本发明的有益效果：本发明提供了一种阵列基板，所述阵列基板中的像素电极为八畴设计，包括四畴的主区像素电极与四畴的次区像素电极，本发明通过将主区像素电极与次区像素电极放置于扫描线(薄膜晶体管开关)的同一侧，可有效提升像素区域的开口率。
具体地，在现有的八畴像素电极设计中，通常将主区像素电极与次区像素电极分别放置于扫描线的两侧，那么在列方向上，一个像素中的主区像素电极与另一个像素的次区像素电极相邻排布，而相邻的两个像素通常具有相反的极性，即一个像素中的主区像素电极与相邻的另一个像素的次区像素电极呈现相反的，因极性相反导致在该交界处会形成一个较宽的暗纹，从而导致开口率降低。而在本发明提供的八畴像素电极设计中，避免了相邻的像素间因极性相反导致的暗纹，同时在同一个像素内，主区像素电极与次区像素电极之间极性相同，同样避免了较宽暗纹的出现，故有效提升了像素区域的开口率。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种阵列基板的结构示意图；
图2是本发明实施例提供的一种像素单元极性排布规律的示意图；
图3是本发明实施例提供的一种主区像素电极的结构示意图；
图4是本发明实施例提供的一种主区像素电极与次区像素电极排布方式的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在现有的VA型LCD中，为了改善色偏等问题，通常将像素电极设计为八畴的架构，包括四畴结构的主区像素电极与四畴结构的次区像素电极，在现有的技术中，通常将主区像素电极与次区像素电极设置在薄膜晶体管的两侧，如此一来，在整体的像素排布中，对于同一列的像素单元，第N行像素的次区像素电极与第N+1行像素的主区像素电极相邻且极性相反，在该交界处会存在一个较宽的暗纹，导致像素单元的开口率降低。
发明人经光学仿真与实验测试均发现，当相邻的像素之间极性不同时，交界处会出现较宽暗纹，而极性相同时，交界处暗纹明显收窄，本发明基于此原理实现了开口率的提升，详见后述。
本发明实施例提供了一种阵列基板，所述阵列基板的结构请参见图1，具体包括：
多条水平方向设置的扫描线101(图中仅示出一条)，控制薄膜晶体管的开与关；
多条竖直方向设置的数据线201(图中仅示出两条)，向像素灌入信号，决定像素电极的电压值，从而控制像素的亮度；
以及阵列排布的多个像素单元，任意一所述的像素单元包括：
像素电极：包括主区像素电极301与次区像素电极302；
薄膜晶体管：控制所述主区像素电极301的第一薄膜晶体管T1以及控制所述次区像素电极302的第二薄膜晶体管T2，
其中，所述主区像素电极301与所述次区像素电极302设置于所述第一薄膜晶体管T1与所述第二薄膜晶体管T2的同一侧。
在本实施例提供的阵列基板中，对于同一列的像素单元，第N行的次区像素电极与第N+1行像素单元扫描线/薄膜晶体管相邻，而非像素电极与像素电极相邻，避免了较宽暗纹的产生，另一方面，在一个像素单元以内，主区像素电极与次区像素电极相邻，但由于为同一数据线灌入信号，所述主区像素电极与所述次区像素电极的极性相同，交界处暗纹较窄，故，可有效提升像素开口率。
进一步地，所述第一薄膜晶体管T1包括U型形状的第一源极2021与条状的第一漏极2031，所述第一漏极2031插入所述第一源极2021的U型开口区设置；
所述第二薄膜晶体管T2包括U型形状的第二源极2022与条状的第二漏极2032，所述第二漏极2032插入所述第二源极2022的U型开口区设置，
其中，所述第一源极2021的U型开口方向与所述第二源极2022的U型开口方向一致。
可以理解的是，将所述第一源极的U型开口方向与所述第二源极的U型开口方向设置为一致，是为了便于走线，以实现所述主区像素电极与所述次区像素电极放置于所述薄膜晶体管的同一侧，其他能实现所述主区像素电极与所述次区像素电极放置于所述薄膜晶体管的同一侧的设计亦可。
进一步的，所述任意一像素单元中还包括公共电极102，与所述扫描线101为同一成膜工艺与图案化工艺形成。其中，所述主区像素电极与所述次区像素电极在所述公共电极面上的正投影图形与所述公共电极存在重叠的区域，分别形成主区像素电极的存储电容与次区像素电极的存储电容。
进一步地，所述第一源极2021与一数据线201电性连接，所述第一漏极2031与所述主区像素电极301电性连接；所述第二源极2022与所述第一源极2021电性连接，所述第二漏极2032与所述次区像素电极302电性连接。
其中所述第二源极与所述第一源极电性相连，接受到同样的Data信号，故主区像素电极与次区像素电极极性相同。
进一步地，所述同一列的像素单元，由同一条数据线给入信号，即同一列的像素单元中像素电极呈现相同的极性。
进一步地，所述任意相邻的两条数据线给入不同的电压信号，相邻的两列像素单元中极性相异，具体地，任意一列所述的像素单元中的像素电极呈现相同的极性，为第一极性，与所述任意一列像素单元相邻的另一列像素单元中的像素电极呈现第二极性，所述第一极性与所述第二极性为相反的极性，所述阵列排布的像素单元中像素电极呈现如图2所示的规律。
进一步地，所述主区像素电极与所述次区像素电极均呈四畴设置，在所述四畴内分别设置了向四个不同方向延伸的多个分支电极。
示例性地，以所述主区像素电极为例，如下进行了具体的描述。
请参照图3，所述主区像素电极301包括：
主干电极3011：为十字型构造，将像素单元划分为四个畴；
边框电极3016：矩形外框构造，分别于所述主干电极3011的四个端点电性连接；
多个分支电极：包括分别位于四个畴中的第一分支电极3012、第二分支电极3013、第三分支电极3014以及第四分支电极3015，四个畴内的分支电极分别向四个不同方向延伸，一端与所述主干电极3011电性连接，另一端与所述边框电极3016电性连接，
在一种优选的实施方式中，所述第一分支电极3012与水平方向的夹角为45°，所述第二分支电极3013与水平方向的夹角为135°、所述第三分支电极3014与水平方向的夹角为-135°，以及所述第四分支电极3015与水平方向的夹角为-45°。
在本实施例中，所述主区像素电极301与所述次区像素电极302间的最小距离大于等于2.5微米，通过设置一定的安全距离，防止主区像素电极与次区像素电极之间发生干扰，以防制程过程中产生的particle导致两者发生短接。
在本实施例中，所述主区像素电极301与所述次区像素电极302在列方向上相邻设置。
需要说明的是，所述主区像素电极与所述次区像素电极的排布方式不仅限定于上述的相邻设置，也可为如图4所示的排布方式，即将所述次区像素电极302内部设置一个空白区域，将所述主区像素电极301设置于该空白区域，如此，所述主区像素电极与所述次区像素电极通过共享区域的设置，优化显示效果。
需要说明的是，本申请中所提及的像素电极的正负极性由相对与彩膜基板公共电极的电位而定义，一般情况下彩膜基板中公共电极的点位为6～7V，当像素电极的点位小于彩膜基板公共电极点位时，称之为负极性；相反的，当像素电极的点位大于彩膜基板公共电极点位时，称之为正极性。
本发明的另一实施例还提供了一种液晶显示装置，包括前述的阵列基板。
需要说明的是，上述阵列基板实施例中仅描述了上述结构，可以理解的是，除了上述结构之外，本发明实施例显示面板中，还可以根据需要包括任何其他的必要结构，例如共享薄膜晶体管(通过分压以实现主区像素电极与次区像素电极间的电压差)，以及DBS电极(在阵列基板侧的ITO Com电极)等，具体此处不作限定。
以上对本发明实施例所提供的一种阵列基板进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (10)

1.一种阵列基板，其特征在于，所述阵列基板包括：多条水平方向设置的扫描线、多条竖直方向设置的数据线以及阵列排布的多个像素单元，所述多个像素单元中的任一者包括：
像素电极：包括主区像素电极与次区像素电极；
薄膜晶体管：包括控制所述主区像素电极的第一薄膜晶体管以及控制所述次区像素电极的第二薄膜晶体管，
其中，所述主区像素电极与所述次区像素电极设置于所述第一薄膜晶体管与所述第二薄膜晶体管的同一侧。
2.如权利要求1所述的阵列基板，其特征在于，所述第一薄膜晶体管包括U型形状的第一源极与条状的第一漏极，所述第一漏极的一端插入所述第一源极的U型开口区；
所述第二薄膜晶体管包括U型形状的第二源极与条状的第二漏极，所述第二漏极的一端插入所述第二源极的U型开口区，
其中，所述第一源极的U型开口方向与所述第二源极的U型开口方向一致。
3.如权利要求2所述的阵列基板，其特征在于，所述第一源极与所述多条数据线中之一者电性连接，所述第一漏极与所述主区像素电极电性连接；所述第二源极与所述第一源极电性连接，所述第二漏极与所述次区像素电极电性连接。
4.如权利要求1所述的阵列基板，其特征在于，所述同一列的所述多个像素单元，由所述多条数据线中之一者给入信号。
5.如权利要求4所述的阵列基板，其特征在于，任意一列所述的像素单元中的像素电极呈现相同的极性，为第一极性，与所述任意一列像素单元相邻的另一列像素单元中的像素电极呈现第二极性，所述第一极性与所述第二极性为相反的极性。
6.如权利要求1所述的阵列基板，其特征在于，所述主区像素电极与所述次区像素电极均呈四畴设置，在所述四畴内分别设置了向四个不同方向延伸的多个分支电极。
7.如权利要求1所述的阵列基板，其特征在于，所述主区像素电极与所述次区像素电极间的最小距离大于等于2.5微米。
8.如权利要求7所述的阵列基板，其特征在于，所述主区像素电极与所述次区像素电极在列方向上相邻设置。
9.如权利要求7所述的阵列基板，其特征在于，所述次区像素电极的内部设置有空白区域，所述主区像素电极设置于所述空白区域。
10.一种液晶显示装置，其特征在于，包括权利要求1-9任意一项所述的阵列基板。
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