WO2019096083A1 - 栅极驱动子电路、驱动方法和栅极驱动电路 - Google Patents

栅极驱动子电路、驱动方法和栅极驱动电路 Download PDF

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Publication number
WO2019096083A1
WO2019096083A1 PCT/CN2018/114997 CN2018114997W WO2019096083A1 WO 2019096083 A1 WO2019096083 A1 WO 2019096083A1 CN 2018114997 W CN2018114997 W CN 2018114997W WO 2019096083 A1 WO2019096083 A1 WO 2019096083A1
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Prior art keywords
control
gate
signal
shift
circuit
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PCT/CN2018/114997
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English (en)
French (fr)
Inventor
付弋珊
樊君
李付强
王继国
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/622,756 priority Critical patent/US11100834B2/en
Publication of WO2019096083A1 publication Critical patent/WO2019096083A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display driving technologies, and in particular, to a gate driving sub-circuit, a driving method, and a gate driving circuit.
  • the integrated memory pixel unit in the related art includes two gate driving signal outputs, but the gate driving unit in the related art can only output one gate driving signal, cannot be used with the integrated memory pixel unit, and cannot be provided for driving integration. Two mutually independent outputs of the memory pixel unit, which do not interfere with each other.
  • the present disclosure provides a gate driving sub-circuit for driving an integrated memory pixel unit, wherein the gate driving sub-circuit includes an input signal terminal, a shift signal output terminal, a shift inverted signal output terminal, and a positive phase a shift clock signal input end, an inverted shift clock signal input end, a first control clock signal input end, a second control clock signal input end, a first gate drive signal output end, a second gate drive signal output end, a shift register circuit and a control output circuit; the control output circuit comprising a first control output sub-circuit and a second control output sub-circuit;
  • the shift register circuit is configured to be obtained according to the input signal input by the input signal terminal under the control of the positive phase clock signal input end, the inverted shift clock signal input end and the positive phase enable end Shifting the inverted signal and shifting the signal;
  • the first control output sub-circuit is configured to generate a first gate driving signal according to the shift signal and the shift inversion signal under control of the first control clock signal input end and the first enable end And outputting the first gate driving signal through the first gate driving signal output end;
  • the second control output sub-circuit is configured to generate a second gate driving signal according to the shift signal and the shift inverted signal under the control of the second control clock signal input end and the inversion enable end And outputting the second gate driving signal through the second gate driving signal output end.
  • the gate driving sub-circuit further includes a power voltage signal output terminal and a power voltage signal output circuit; the power voltage signal output circuit and the power voltage signal output terminal, the shift signal output terminal, and the second An enable terminal connection is configured to generate a power supply voltage signal according to the shift signal under the control of the second enable end, and output the power supply voltage signal through the power supply voltage signal output end.
  • the gate driving sub-circuit includes M control output circuits, M power voltage signal output circuits, M first control clock signal inputs, M second control clock signal inputs, and M first gates. a pole drive signal output end, M second gate drive signal output ends and M power supply voltage signal output ends; M is a positive integer;
  • a first control output sub-circuit included in the control output circuit is connected to a first control clock signal input end and a first gate drive signal output end;
  • a second control output sub-circuit included in the control output circuit is connected to a second control clock signal input end and a second gate drive signal output end;
  • the power voltage signal output circuit is connected to a power voltage signal output end.
  • the shift register circuit includes:
  • a positive phase control terminal is coupled to the inverting shift clock signal input terminal, an inverting control terminal is coupled to the positive phase shift clock signal input terminal, and an input terminal is coupled to the input signal terminal;
  • a shift control transistor a gate connected to the positive phase enable terminal, a first pole connected to an output end of the first tri-state gate, and a second pole connected to the first voltage input end;
  • a positive phase control terminal is coupled to the positive phase shift clock signal input terminal
  • an inverting control terminal is coupled to the inverted shift clock signal input terminal
  • the input terminal and the shift inverter are coupled The output end is connected, and the output end is connected to the output end of the first three-state gate
  • the first input terminal is coupled to the positive phase shift clock signal input terminal, and the second input terminal is coupled to the output terminal of the first shift inverter;
  • the first control output sub-circuit includes:
  • a positive phase control terminal is coupled to the shift signal output terminal, an inverting control terminal is coupled to the shift inversion signal output terminal, and an input terminal is coupled to the first control clock signal input terminal ;
  • the positive phase control end is connected to the shift inversion signal output end
  • the inverting control end is connected to the shift signal output end
  • the input end is connected to the first enable end
  • a first control output inverter the input being coupled to an output of the first control output transmission gate and an output of the second control output transmission gate;
  • the second control output sub-circuit includes:
  • the positive phase control terminal is connected to the shift signal output end
  • the inverting control terminal is connected to the shift inverted signal output end
  • the input end is connected to the second control clock signal input end ;
  • a fourth control output transmission gate the positive phase control end is connected to the shift inversion signal output end, the inverting control end is connected to the shift signal output end, and the input end is connected to the inversion enable end;
  • a third control output inverter the input end being connected to an output end of the third control output transmission gate and an output end of the fourth control output transmission gate;
  • the fourth control output inverter is connected to the output end of the third control output inverter, and the output end is connected to the second gate drive signal output end.
  • the power voltage signal output circuit includes:
  • a power supply voltage signal output transmission gate a positive phase control end connected to the shift signal output end, an inverting control end connected to the shift inversion signal output end, and an input end connected to the second enable end;
  • a first power voltage signal output transistor a gate connected to the shift signal output end, a first pole connected to an output end of the power voltage signal output transmission gate, and a second pole connected to the first voltage input end;
  • a power supply voltage signal output inverter the input end being connected to an output end of the power voltage signal output transmission gate
  • a second power voltage signal output transistor a gate connected to an output end of the power voltage signal output transmission gate, a first pole connected to the second voltage input terminal, and a second pole connected to the power voltage signal output end; as well as,
  • a third power voltage signal output transistor a gate connected to an output end of the power voltage signal output inverter, a first pole connected to the first voltage input terminal, and a second pole connected to the power voltage signal output end .
  • the gate driving sub-circuit further includes an input circuit; wherein the input circuit and the forward scan control terminal, the reverse scan control terminal, the positive phase shift signal terminal, and the inverted shift signal And connecting to the input signal end, configured to control the positive phase shift signal end or the reverse phase shift signal end under the control of the forward scan control end and the reverse scan control end The input signal terminal is connected.
  • the input circuit includes a forward scan transmission gate and a reverse scan transmission gate
  • a positive phase control end of the forward scan transmission gate is connected to the forward scan control end, and an inverting control end of the forward scan transmission gate is connected to the reverse scan control end, the forward scan transmission
  • An input end of the gate is connected to the positive phase shift signal end, and an output end of the forward scan transmission gate is connected to the input signal end;
  • a positive phase control end of the reverse scan transmission gate is connected to the reverse scan control end, and an inverting control end of the reverse scan transmission gate is connected to the forward scan control end, the reverse scan transmission
  • An input end of the gate is coupled to the inverted shift signal terminal, and an output end of the reverse scan transmission gate is coupled to the input signal terminal.
  • the present disclosure also provides a driving method of a gate driving sub-circuit, which is applied to the above-described gate driving sub-circuit, wherein the driving method of the gate driving sub-circuit includes:
  • the shift register circuit obtains a shift inversion signal and a shift signal according to an input signal input from the input signal terminal under control of the clock signal input end and the positive phase enable end; the shift inversion signal is opposite to the shift signal phase;
  • the first control output sub-circuit generates a first gate driving signal according to the shift signal and the shift inversion signal under the control of the first control clock signal input end and the first enable terminal, and passes through the first gate
  • the pole drive signal output end outputs the first gate drive signal
  • the second control output sub-circuit generates a second gate driving signal according to the shift signal and the shift inverted signal under the control of the second control clock signal input end and the inverting enable end, and passes through the second gate
  • the pole drive signal output terminal outputs the second gate drive signal.
  • the driving method of the gate driving sub-circuit further includes: the power voltage signal output circuit generates a power voltage signal according to the shift signal under the control of the second enabling end, and outputs the power voltage signal output terminal Power supply voltage signal.
  • the present disclosure also provides a gate driving circuit including a plurality of cascaded first gate driving modules disposed on a first side of the display panel and a second disposed on a second side of the display panel Gate drive module;
  • the first gate driving module includes a plurality of cascaded gate driving sub-circuits
  • the second gate driving module includes a plurality of cascaded gate driving sub-circuits
  • the first gate driving module includes a gate driving sub-circuit connected to an integrated memory pixel unit located in an odd row
  • the second gate driving module includes a gate driving sub-circuit and an integrated memory located in an even row Pixel unit connection.
  • the first side is a left side, and the second side is a right side; or the first side is a right side and the second side is a left side;
  • the shift register circuit in the first gate driving module includes a positive phase shift clock signal input end connected to the positive phase clock signal line, and the shift register circuit in the first gate drive module includes an inverted shift The clock signal input end is connected to the inverted clock signal line;
  • the shift register circuit in the second gate drive module includes a positive phase shift clock signal input end connected to the inverted clock signal line, and the second gate drive
  • the shift register circuit in the module includes an inverted shift clock signal input end connected to the positive phase clock signal line;
  • the gate driving sub-circuit further includes a positive phase shift signal terminal and an inverted shift signal terminal; the gate driving sub-circuit further includes an input circuit; the input circuit and the forward scan control terminal, and the reverse scan control And the positive phase shift signal end, the inverted shift signal end and the input signal end are connected, and are used to control the control under the control of the forward scan control end and the reverse scan control end
  • the positive phase shift signal terminal or the inverted shift signal terminal is connected to the input signal terminal;
  • the first-phase shift signal terminal of the gate driving sub-circuit Connected to a shift signal output end of the gate driving sub-circuit adjacent to the upper stage; in addition to the last stage gate driving sub-circuit, the inverted shift signal end of the first-level gate driving sub-circuit is The shift signal output terminals of the gate driving sub-circuits adjacent to the next stage are connected.
  • the gate drive sub-circuit includes M supply voltage signal output terminals; M is a positive integer.
  • M is equal to 1;
  • the nth stage gate driving subcircuit included in the first gate driving module includes a power voltage signal output terminal for supplying a power voltage signal to the integrated memory pixel unit located in the 2nth row;
  • the nth stage gate driving sub-circuit included in the second gate driving module includes a power voltage signal output terminal for supplying a power supply voltage signal to the integrated memory pixel unit located in the 2n-1th row; n is a positive integer.
  • M is equal to 2
  • the first gate driving sub-circuit included in the first gate driving module includes a first power voltage signal output terminal for supplying power to the integrated memory pixel unit located in the 4n-2 row. a voltage signal
  • the second gate driving sub-circuit included in the first gate driving module includes a second power voltage signal output terminal for supplying a power voltage signal to the integrated memory pixel unit located in the 4n row
  • the first gate driving sub-circuit included in the second gate driving module includes a power voltage signal output end for supplying a power voltage signal to the integrated memory pixel unit located in the 4n-3 row
  • the included second stage gate drive sub-circuit includes a supply voltage signal output for providing a supply voltage signal for the integrated memory pixel unit located in the 4n-1 row;
  • n is a positive integer.
  • FIG. 1 is a circuit diagram of a MIP pixel unit in the related art
  • FIG. 2 is a structural diagram of a gate driving sub-circuit according to some embodiments of the present disclosure
  • FIG. 3 is a structural diagram of a gate driving sub-circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a structural diagram of a gate driving sub-circuit according to some embodiments of the present disclosure.
  • FIG. 5 is a circuit diagram of a specific embodiment of a gate driving sub-circuit according to some embodiments of the present disclosure
  • FIG. 6 is a timing diagram of operation timing when a pixel signal is written in a first display mode according to an embodiment of the gate driving sub-circuit according to some embodiments of the present disclosure
  • FIG. 7 is a timing simulation diagram of operation of a pixel driving sub-circuit in a first display mode when a pixel signal is displayed in a first display mode according to some embodiments of the present disclosure
  • FIG. 8 is a circuit diagram of another embodiment of a gate driving sub-circuit according to some embodiments of the present disclosure.
  • FIG. 9 is a timing diagram of operation timing when a pixel signal is written in a first display mode according to another embodiment of the gate driving sub-circuit according to some embodiments of the present disclosure.
  • FIG. 10 is a structural diagram of a specific embodiment of a gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 11 is a block diagram of another embodiment of a gate drive circuit in accordance with some embodiments of the present disclosure.
  • the integrated memory pixel unit in the related art includes a signal writing module, a latch, and a display module.
  • reference numeral M1 represents a first n-type transistor
  • reference numeral M1' represents a first p-type transistor
  • reference numeral M2 represents a second n-type transistor
  • reference numeral M2' represents a second p-type transistor
  • reference numeral M3 represents a third transistor.
  • Reference numeral M4 denotes a fourth transistor
  • reference numeral M5 denotes a fifth transistor
  • reference numeral M6 denotes a sixth transistor
  • reference numeral M7 denotes a seventh transistor.
  • the signal writing module includes M5 and M7, and the gate of M5 and the gate of M7 are both connected to the first gate driving signal output terminal GateA.
  • the latches include M1, M2, M1' and M2'.
  • the display module includes M3, M4, and M6.
  • reference numeral P denotes a pixel electrode
  • reference numeral N denotes a first node
  • reference numeral Q denotes a positive phase node
  • reference numeral Q' denotes an inverting node
  • a gate of M6 is connected to a second gate driving signal output terminal GateB.
  • the integrated memory pixel unit shown in Figure 1 includes two gate drive signal outputs.
  • the pixel signal When the pixel signal is written, the pixel is not displayed; when the pixel is displayed, no pixel signal is written, that is, GateA and GateB are separately driven in time division.
  • the high voltage VDD and the low voltage VSS ensure the latch.
  • FRP is a normally black signal and Data is a data line.
  • M5 When the pixel signal is written, M5 is turned on, and the data voltage signal on the data line Data is written into the latch. If the data voltage signal is low level, the potential of Q is low level, and the potential of Q' is high.
  • the first node N accesses the normally black signal FRP, and after the GateB controls the M6 tube to be turned on, the potential of the pixel electrode P is the potential of the first node N.
  • the gate driving unit in the related art can only output one gate driving signal, cannot be used with the integrated memory pixel unit, and cannot provide two mutually independent outputs for driving the integrated memory pixel unit, and the gate driving signals do not interfere with each other.
  • the embodiments of the present disclosure provide a gate driving sub-circuit, a driving method, and a gate driving circuit, which can solve the related art that the gate driving unit can only output one gate driving signal, and cannot be used with the integrated memory pixel unit. It is not possible to provide a problem of driving two independent outputs of the integrated memory pixel unit, which do not interfere with each other.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the gate driving sub-circuit of the embodiment of the present disclosure is configured to drive an integrated memory pixel unit.
  • the gate driving sub-circuit includes an input signal terminal STV_IN, a shift signal output terminal STV_N, and a shift counter.
  • Phase signal output terminal STV_F positive phase shift clock signal input terminal VCK, inverted shift clock signal input terminal VCKB, first control clock signal input terminal CK1, second control clock signal input terminal CK2, first gate drive signal
  • the control output circuit includes a first control output sub-circuit 221 and a second control output sub-circuit 222.
  • the phase shift clock signal input terminal VCKB is connected to the positive phase enable terminal EN3.
  • the shift register circuit 21 is configured to be under the control of the positive phase clock signal input terminal VCK, the inverted shift clock signal input terminal VCKB, and the positive phase enable terminal EN3 according to the input signal terminal
  • the input signal input to the STV_IN is obtained by shifting the inverted signal and the shift signal, and the shift inverted signal is outputted through the shift inverted signal output terminal STV_F, and the shift is output through the shift signal output terminal STV_N signal.
  • the first gate drive signal output terminal GateA1 is connected.
  • the first control output sub-circuit 221 is configured to generate a first according to the shift signal and the shift inverted signal under the control of the first control clock signal input terminal CK1 and the first enable terminal EN1. a gate driving signal, and outputting the first gate driving signal through the first gate driving signal output terminal GateA1.
  • the second control output sub-circuit 222 and the shift signal output terminal STV_N, the shift inversion signal output terminal STV_F, the second control clock signal input terminal CK2, the inversion enable terminal EN3B, and the The second gate drive signal output terminal GateB1 is connected.
  • the second control output sub-circuit 222 is configured to generate a second according to the shift signal and the shift inverted signal under the control of the second control clock signal input terminal CK2 and the inversion enable terminal EN3B. a gate driving signal, and outputting the second gate driving signal through the second gate driving signal output terminal GateB1.
  • the shifted inverted signal and the shifted signal are inverted.
  • the shift signal may be delayed by a predetermined time compared to the input signal.
  • the gate driving sub-circuit of the embodiment of the present disclosure shifts the input signal input by the input signal terminal STV_IN by using the shift register circuit 21 to obtain a shift signal, and adopts a first control output sub-circuit 221 and a Controlling the output circuit of the output sub-circuit 222 to obtain the first gate driving signal and the second gate driving signal according to the shift signal, so that the first gate driving sub-circuit can be MIP (Memory Integrated Pixel, integrated)
  • MIP Memory Integrated Pixel, integrated
  • the gate driving sub-circuit of the embodiment of the present disclosure can be used in conjunction with the integrated memory pixel unit, and the two gate driving signal output terminals respectively connected to the two rows of gate lines connected to the integrated memory pixel unit can be independently output by adjusting the timing. There is no interference between signal writing and display in the integrated memory pixel unit.
  • the gate driving sub-circuit further includes a power voltage signal output terminal VDD_OUT and a power voltage signal output circuit 23.
  • the power supply voltage signal output circuit 23 is connected to the power supply voltage signal output terminal VDD_OUT, the shift signal output terminal STV_N, and the second enable terminal EN2.
  • the power voltage signal output circuit 23 is configured to generate a power voltage signal according to the shift signal under the control of the second enable terminal EN2, and output the power voltage signal through the power voltage signal output terminal VDD_OUT.
  • the gate driving sub-circuit of the embodiment of the present disclosure further includes a power voltage signal output terminal VDD_OUT and a power voltage signal output circuit 23 to provide a power voltage signal for the MIP pixel unit.
  • the gate driving sub-circuit of the embodiment of the present disclosure includes a shift register sub-circuit, a control output circuit, and a power supply voltage signal output circuit.
  • the gate circuit and the clock signal cooperate with each other to implement writing, displaying, and providing power for the MIP pixel.
  • the voltage signal avoids the competitive risk phenomenon when the pixel signal is written;
  • the clock signal ensures that the gate drive signals are independently outputted without affecting each other;
  • the setting of each enable terminal ensures the signal reset and fast power-down function of the gate drive sub-circuit, In the case of low frequency driving, without the start signal and the clock signal, the pixel can still ensure the pre-written signal information, thereby ensuring the effective implementation of the MIP pixel unit function.
  • the gate driving sub-circuit includes M control output circuits, M power voltage signal output circuits, M first control clock signal inputs, M second control clock signal inputs, and M first a gate drive signal output end, M second gate drive signal output ends, and M power supply voltage signal output ends; M is a positive integer;
  • a first control output sub-circuit included in the control output circuit is connected to a first control clock signal input end and a first gate drive signal output end;
  • a second control output sub-circuit included in the control output circuit is connected to a second control clock signal input end and a second gate drive signal output end;
  • the power voltage signal output circuit is connected to a power voltage signal output end.
  • the number of the control output circuit and the power supply voltage signal output circuit included in the gate driving sub-circuit of the embodiment of the present disclosure may be one or more than one, so that the embodiment of the present disclosure
  • the gate driving sub-circuit can be used to drive the number of MIP pixel units or more than one.
  • the waveform of the clock signal needs to be adjusted accordingly, and is driven by a gate driving sub-circuit below.
  • An embodiment of two MIP pixel units is illustrated.
  • the shift register circuit may include:
  • a positive phase control terminal is coupled to the inverting shift clock signal input terminal, an inverting control terminal is coupled to the positive phase shift clock signal input terminal, and an input terminal is coupled to the input signal terminal;
  • a shift control transistor a gate connected to the positive phase enable terminal, a first pole connected to an output end of the first tri-state gate, and a second pole connected to the first voltage input end;
  • a positive phase control terminal is coupled to the positive phase shift clock signal input terminal
  • an inverting control terminal is coupled to the inverted shift clock signal input terminal
  • the input terminal and the shift inverter are coupled The output end is connected, and the output end is connected to the output end of the first three-state gate
  • the first input terminal is coupled to the positive phase shift clock signal input terminal, and the second input terminal is coupled to the output terminal of the first shift inverter;
  • the gate driving sub-circuit may further include a positive phase shift signal terminal STV_N-1 and an inverted shift signal terminal STV_N+1;
  • the gate driving sub-circuit of the embodiment of the present disclosure may further include an input circuit 24;
  • the input circuit 24 is configured to control the positive phase shift signal terminal STV_N-1 or the inverted shift signal terminal under the control of the forward scan control terminal CN and the reverse scan control terminal CNB.
  • STV_N+1 is connected to the input signal terminal STV_IN.
  • the positive phase shift signal terminal STV_N-1 is connected to a shift signal output end included in an adjacent upper-stage gate driving sub-circuit.
  • the second inverted shift signal terminal STV_N+1 is connected to a shift signal output end included in an adjacent lower stage gate drive sub-circuit.
  • the input circuit may include:
  • the forward scan transmission gate is connected to the forward scan control end, the inverting control end is connected to the reverse scan control end, the input end is connected to the positive phase shift signal end, and the output end and the input signal are connected. End connection; and,
  • a reverse scan transmission gate a positive phase control terminal is connected to the reverse scan control terminal, an inverting control terminal is connected to the forward scan control terminal, an input terminal is connected to the inverted shift signal terminal, and an output terminal is connected The input signal ends are connected.
  • the forward scan control terminal In the forward scan, the forward scan control terminal outputs a high level, the reverse scan control terminal outputs a low level, the forward scan transmission gate is opened, the reverse scan transmission gate is closed, and the positive phase shift signal terminal is Connected to the input signal end, that is, the shift signal output end of the adjacent upper stage gate drive sub-circuit is connected to the input signal end;
  • the reverse scan control terminal In the reverse scan, the reverse scan control terminal outputs a high level, the forward scan control terminal outputs a low level, the reverse scan transmission gate is opened, the forward scan transmission gate is closed, and the reverse shift signal terminal is turned off. Connected to the input signal terminal, that is, the shift signal output terminal of the adjacent lower stage gate drive sub-circuit is connected to the input signal terminal.
  • the first control output sub-circuit may include:
  • a positive phase control terminal is coupled to the shift signal output terminal, an inverting control terminal is coupled to the shift inversion signal output terminal, and an input terminal is coupled to the first control clock signal input terminal ;
  • the positive phase control end is connected to the shift inversion signal output end
  • the inverting control end is connected to the shift signal output end
  • the input end is connected to the first enable end
  • a first control output inverter the input being coupled to an output of the first control output transmission gate and an output of the second control output transmission gate;
  • a second control output inverter the input end is connected to the output end of the first control output inverter, and the output end is connected to the first gate drive signal output end;
  • the second control output sub-circuit includes:
  • the positive phase control terminal is connected to the shift signal output end
  • the inverting control terminal is connected to the shift inverted signal output end
  • the input end is connected to the second control clock signal input end ;
  • a fourth control output transmission gate the positive phase control end is connected to the shift inversion signal output end, the inverting control end is connected to the shift signal output end, and the input end is connected to the inversion enable end;
  • a third control output inverter the input end being connected to an output end of the third control output transmission gate and an output end of the fourth control output transmission gate;
  • the fourth control output inverter is connected to the output end of the third control output inverter, and the output end is connected to the second gate drive signal output end.
  • the power voltage signal output circuit may include:
  • a power supply voltage signal output transmission gate a positive phase control end connected to the shift signal output end, an inverting control end connected to the shift inversion signal output end, and an input end connected to the second enable end;
  • a first power voltage signal output transistor a gate connected to the shift signal output end, a first pole connected to an output end of the power voltage signal output transmission gate, and a second pole connected to the first voltage input end;
  • a power supply voltage signal output inverter the input end being connected to an output end of the power voltage signal output transmission gate
  • a second power voltage signal output transistor a gate connected to an output end of the power voltage signal output transmission gate, a first pole connected to the second voltage input terminal, and a second pole connected to the power voltage signal output end; as well as,
  • a third power voltage signal output transistor a gate connected to an output end of the power voltage signal output inverter, a first pole connected to the first voltage input terminal, and a second pole connected to the power voltage signal output end .
  • the first voltage may be the first high voltage
  • the second voltage may be the second high voltage, but not limited thereto.
  • the gate driving sub-circuit of the present disclosure will be described below by way of specific embodiments.
  • a specific implementation of the gate driving sub-circuit of the present disclosure includes a first input signal terminal STV_N-1, a second input signal terminal STV_N+1, a shift signal output terminal STV_N, and a shift counter.
  • Phase signal output terminal STV_F first control clock signal input terminal CK1, second control clock signal input terminal CK2, first gate drive signal output terminal GateA1, second gate drive signal output terminal GateB1, shift register circuit, control An output circuit, a power supply voltage signal output terminal VDD_OUT, a power supply voltage signal output circuit, and an input circuit;
  • the control output circuit includes a first control output sub-circuit and a second control output sub-circuit.
  • the shift register circuit includes:
  • the first three-state gate G1 has an input terminal connected to the input signal terminal STV_IN, a positive phase control terminal connected to the inverted shift clock signal input terminal VCKB, and an inverting control terminal connected to the positive phase shift clock signal input terminal VCK;
  • a shift control transistor MS having a gate connected to the positive phase enable terminal EN3, a drain connected to an output terminal of the first tri-state gate G1, and a source and a first high voltage input inputting the first high voltage VGH End connection
  • a first shifting inverter FS1 the input end is connected to the output end of the first tri-state gate G1;
  • the positive phase control terminal is connected to the positive phase shift clock signal input terminal VCK
  • the inverting control terminal is connected to the inverted shift clock signal input terminal VCKB
  • the input terminal and the first An output end of the shifting inverter FS1 is connected, and an output end is connected to an output end of the first tri-state gate G1;
  • the first input terminal is coupled to the positive phase shift clock signal input terminal VCK, and the second input terminal is coupled to the output terminal of the first shift inverter FS1;
  • the second shifting inverter FS2 has an input terminal connected to the shift inversion signal output terminal STV_F and an output terminal of the NAND gate AF, and an output terminal connected to the shift signal output terminal STV_N.
  • the input circuit includes a forward scan transmission gate TGS and a reverse scan transmission gate TGB;
  • the positive phase control end of the forward scan transmission gate TGS is connected to the forward scan control terminal CN, the inverting control end of the forward scan transmission gate TGS is connected to the reverse scan control terminal CNB, and the forward scan transmission gate TGS The input end is connected to the first input signal terminal STV_N-1, and the output end of the forward scan transmission gate TGS is connected to the input signal terminal STV_IN;
  • a positive phase control terminal of the reverse scan transmission gate TGB is connected to the reverse scan control terminal CNB, and an inversion control terminal of the reverse scan transmission gate TGB is connected to the forward scan control terminal CN, and the input end Connected to the second input signal terminal STV_N+1, the output terminal is connected to the input signal terminal STV_IN.
  • the first control output sub-circuit includes:
  • a first control output transmission gate TGC1 a positive phase control terminal connected to the shift signal output terminal STV_N, an inverting control terminal connected to the shift inversion signal output terminal STV_F, an input terminal and the first control clock signal Input CK1 is connected;
  • the second control output transmission gate TGC2 the positive phase control terminal is connected to the shift inversion signal output terminal STV_F, the inverting control terminal is connected to the shift signal output terminal STV_N, and the input terminal is connected to the first enable terminal EN1. ;
  • a first control output inverter FC1 the input terminal being connected to an output end of the first control output transmission gate TGC1 and an output end of the second control output transmission gate TGC2;
  • the second control output inverter FC2 has an input terminal connected to the output end of the first control output inverter FC1, and an output terminal connected to the first gate drive signal output terminal GateA1.
  • the second control output sub-circuit includes:
  • the third control output transmission gate TGC3, the normal phase control terminal is connected to the shift signal output terminal STV_N, the inverting control terminal is connected to the shift inversion signal output terminal STV_F, and the input terminal and the second control clock signal are Input CK2 is connected;
  • the fourth control output transmission gate TGC4 the positive phase control terminal is connected to the shift inversion signal output terminal STV_F, the inverting control terminal is connected to the shift signal output terminal STV_N, the input terminal and the inversion enable end EN3B connection;
  • a third control output inverter FC3 the input terminal is connected to an output end of the third control output transmission gate TGC3 and an output end of the fourth control output transmission gate TGC4;
  • the fourth control output inverter FC4 has an input terminal connected to the output terminal of the third control output inverter FC3, and an output terminal connected to the second gate drive signal output terminal GateB1.
  • the power voltage signal output circuit includes:
  • the power supply voltage signal is outputting the transmission gate TGV, the positive phase control terminal is connected to the shift signal output terminal STV_N, and the inverting control terminal is connected to the shift inverted signal output terminal STV_F, and the input terminal and the second enable terminal are connected. EN2 connection;
  • a first power voltage signal output transistor MVO1 a gate connected to the shift signal output terminal STV_N, a source connected to a first high voltage input terminal inputting the first high voltage VGH, and a drain and the power source voltage signal output transmission The output of the gate TGV is connected;
  • the power supply voltage signal is outputted to the inverter FV, and the input end is connected to the output end of the power voltage signal output transmission gate TGV;
  • a second power voltage signal output transistor MVO2 a gate connected to an output end of the power voltage signal output transmission gate TGV, a source connected to a second high voltage input terminal inputting the second high voltage VDD, a drain and the power source
  • the voltage signal output terminal VDD_OUT is connected;
  • a third power voltage signal output transistor MVO3 a gate connected to an output end of the power voltage signal output inverter FV, a drain connected to the power voltage signal output terminal VDD_OUT, a source and the input first high voltage The first high voltage input of VGH is connected.
  • VGH is the power supply voltage
  • VDD is close to the maximum value of the data voltage on the data line
  • VDD is lower than VGH
  • the voltage signal outputted by VDD_OUT is used to supply the MIP pixel unit voltage signal.
  • all of the transistors are p-type transistors, but in actual operation, the above transistors may be replaced with n-type transistors, and the types of transistors are not limited herein.
  • the gate driving sub-circuit of the present disclosure can be divided into three parts: a shift register circuit, a control output circuit and a power voltage signal output circuit, and GateA1 and GateB1 provide two required gate drive signals for one row of MIP pixel units.
  • the GateA1 is connected to the gate of the write transistor included in the MIP pixel unit
  • the GateB1 is connected to the gate of the display transistor included in the MIP pixel unit
  • the VDD_OUT is connected to the power supply voltage signal input end of the MIP pixel unit.
  • a specific implementation of the gate driving sub-circuit as shown in FIG. 5 can be used to provide corresponding two gate driving signals for odd-line MIP pixel units, and in actual operation, for providing corresponding two-gates for even-line MIP pixel units.
  • the gate driving sub-circuit of the pole driving signal is different from the above-described embodiment in that the first input terminal of the NAND gate AF is connected to the inverted shift clock signal input terminal VCKB, and the first tri-state gate G1 is positive.
  • the phase control terminal is connected to the VCK.
  • the inverting control terminal of the first tri-state gate G1 is connected to the VCKB
  • the positive phase control terminal of the second tri-state gate G2 is connected to the VCKB
  • the inverting control terminal of the second tri-state gate G2 is connected to the VCK. connection.
  • the gate driving sub-circuit described in the embodiment of the present disclosure may be a single-sided gate driving sub-circuit, and the first-level gate driving sub-circuit may be used by one row of MIP pixel units.
  • the multi-level gate driving sub-circuit disposed on the left side of the display panel can be controlled to drive the odd-line MIP pixel unit, and the multi-level gate driving sub-circuit disposed on the right side of the display panel is used for driving.
  • Even line MIP pixel unit The start signal on both sides is the same as the phase of the shift clock signal.
  • the clock signal of the CLK1 input for output and the clock signal input by CLK2 are different in phase on the left and right sides.
  • There are four gate drive signals on the left and right sides to ensure the left and right sides. Independent output, undisturbed control output clock signal input.
  • the first display mode is the normal display mode
  • the data voltage on the data line Data is written to the pixel electrode under the control of GateB1, that is, the signal is written.
  • the first display mode of the normal display screen is entered, and at this time, according to the data voltage on the data in the display phase, when the pixel signal is written,
  • STV_N inputs a high level
  • the positive phase shift clock signal input terminal VCK inputs a low level
  • the inverted shift clock signal input terminal VCKB inputs a high level
  • the positive phase enable terminal EN3 inputs a high level.
  • the NAND gate AF outputs a high level such that the shift inverted signal output terminal STV_F outputs a high level; the second shift inverter FS2 outputs a low level to cause the shift The signal output terminal STV_N outputs a low level; the first enable terminal EN1 outputs a low level, the first control output transmission gate TGC1 is turned off, and the second control output transmission gate TGC2 outputs a low level, the first The fourth control output inverter FC4 outputs a low level to the first gate driving signal output terminal GateA1; the second enabling terminal EN2 outputs a low level, and the power supply voltage signal output transmission gate TGV is turned off, the first The power voltage signal output transistor MVO1 is turned on to control the power voltage signal output The input end of the phase converter FV is
  • the first gate driving signal output stage S12 STV_IN inputs a low level, the positive phase shift clock signal input terminal VCK inputs a high level, and the inverted shift clock signal input terminal VCKB inputs a low level.
  • the positive phase enable terminal EN3 inputs a high level to control the shift control transistor MS to be turned off; the potential of the input terminal of the first shift inverter FS1 is maintained at a low level, and the first shift is reversed
  • the phase switch FS1 outputs a high level, the first three-state gate G1 is turned off, the second three-state gate G2 outputs a low level, and the NAND gate AF outputs a low level to invert the shift.
  • the signal output terminal STV_F outputs a low level; the second shift inverter FS2 outputs a high level, so that the shift signal output terminal STV_N outputs a high level; the first enable terminal EN1 outputs a low level Ping, the first control clock signal input terminal CK1 inputs a high level, the second control output transmission gate TGC2 is turned off, the first control output transmission gate TGC1 outputs a high level; the power supply voltage signal output transmission gate The TGV outputs a low level, and the first power voltage signal output transistor MVO1 is turned off.
  • the power supply voltage signal output inverter FV outputs a high level, the third power supply voltage signal output transistor MVO3 is turned off; the second power supply voltage signal output transistor MVO2 is turned on to control the power supply voltage signal output terminal VDD_OUT and The second high voltage input terminal of the input second high voltage VDD is connected, so that the power voltage signal output terminal VDD_OUT outputs the second high voltage VDD;
  • the STV_IN inputs a low level
  • the positive phase shift clock signal input terminal VCK inputs a high level
  • the inverted shift clock signal input terminal VCKB inputs a low level
  • the positive The phase enable terminal EN3 inputs a high level to control the shift control transistor MS to be turned off; the potential of the input terminal of the first shift inverter FS1 is maintained at a low level, the first shift inverter FS1 outputs a high level, the first three-state gate G1 is turned off, the second three-state gate G2 outputs a low level, and the NAND gate AF outputs a low level, so that the shift inverted signal output
  • the terminal STV_F outputs a low level; the second shift inverter FS2 outputs a high level, so that the shift signal output terminal STV_N outputs a high level; the first enable terminal EN1 outputs a low level,
  • the first control clock signal input terminal CK1 inputs a low level
  • the positive output cut-off hold phase S14 STV_IN inputs a low level, the positive phase shift clock signal input terminal VCK inputs a low level, and the inverted shift clock signal input terminal VCKB inputs a high level, the positive The phase enable terminal EN3 inputs a high level to control the shift control transistor MS to be turned off; the second three-state gate G2 is turned off, the first three-state gate G1 outputs a high level, and the first shift The inverter FS1 outputs a low level, the NAND gate AF outputs a high level, so that the shift inverted signal output terminal STV_F outputs a high level; the second shift inverter FS2 outputs a low power Leveling, so that the shift signal output terminal STV_N outputs a low level; the first enable terminal EN1 outputs a low level, and the first control clock signal input terminal CK1 inputs a high level, the first control The output transfer gate TGC1 is turned off, the second control output transfer gate TGC2 outputs
  • VCK and VCKB are responsible for the shift of the upper and lower gate drive units, respectively.
  • the pulse width of the VCK input clock signal and the VCKB input clock signal pulse width are twice the pulse width of the CK1 input clock signal.
  • CK1 inputs a high level
  • CK2 inputs a low level
  • GateA outputs a pulse signal
  • the frame GateB is opened thereafter. (That is, GateB1 outputs a pulse signal), and displays the signal written by the data line when GateA is turned on (that is, GateA1 outputs a pulse signal).
  • the power supply voltage signal output circuit set at the far right of Figure 5 is a design highlight, where VGH and VDD are input signals, VGH is the power supply voltage, VDD is close to the maximum value of the data voltage on the data line, and VDD is lower than the power supply voltage VGH. .
  • the voltage value of the voltage signal outputted by VDD_OUT is close to the maximum value of the data voltage on the data line, lower than VGH;
  • the voltage supplied to the pixel by VDD_OUT is VGH.
  • the first display mode is the normal display mode
  • M4 in FIG. 1 is turned on, and the data voltage on the data line Data is written to the pixel electrode under the control of GateB1. That is, when the data voltage on the data is low when the signal is written, the first display mode of the normal display screen is entered, and at this time, the display voltage is displayed according to the data voltage on the data), when the pixel signal is displayed.
  • STV_IN inputs the first level
  • the positive phase shift clock signal input terminal VCK inputs a low level
  • the inverted shift clock signal input terminal VCKB inputs a high level
  • the positive phase enable terminal EN3 inputs a high level.
  • the second three-state gate G2 is turned off, the first three-state gate G1 outputs a low level, and the first shift inverter FS outputs a high voltage Flat, the NAND gate AF outputs a high level such that the shift inverted signal output terminal STV_F outputs a high level; the second shift inverter FS2 outputs a low level to cause the shift The bit signal output terminal STV_N outputs a low level; the first enable terminal EN1 outputs a low level, the first control output transmission gate TGC1 is turned off, and the second control output transmission gate TGC2 outputs a low level,
  • the fourth control output inverter FC4 outputs a low level to the second gate driving signal output terminal GateB1 to cause the GateB1 to output a low level; the power supply voltage signal output transmission gate TGV is turned off, the first power supply voltage The signal output transistor MVO1 is turned on to cause the power supply voltage signal to be output The input end of the phase device F
  • the second gate driving signal output stage S22 STV_IN inputs a low level
  • the positive phase shift clock signal input terminal VCK inputs a high level
  • the inverted shift clock signal input terminal VCKB inputs a low level.
  • the positive phase enable terminal EN3 inputs a high level to control the shift control transistor MS to be turned off; the potential of the input terminal of the first shift inverter FS is maintained at a low level, and the first shift is reversed
  • the phase switch FS1 outputs a high level, the first three-state gate G1 is turned off, the second three-state gate G2 outputs a low level, and the NAND gate AF outputs a low level to invert the shift.
  • the signal output terminal STV_F outputs a low level; the second shift inverter FS2 outputs a high level such that the shift signal output terminal STV_N outputs a high level; the shift inverted signal output terminal FS outputs a low level, the shift signal output terminal STV_N outputs a high level, the inverting enable terminal EN3B outputs a low level, and the second control clock signal input terminal CK2 inputs a high level, the fourth control The output transfer gate TGC4 is turned off, and the third control output transfer gate TGC3 outputs a high level to make GateB1 Outputting a high level; the first power supply voltage signal output transistor MVO1 is turned off, the second enable terminal EN2 outputs a high level, and the power supply voltage signal output transmission gate TGV outputs a high level, the second power supply voltage The signal output transistor MVO2 is turned off, the output terminal of the power supply voltage signal output inverter FV outputs a low level, and the third power supply voltage signal output transistor MVO3 is turned
  • Figure 7 shows the output waveform of the gate drive sub-circuit when the simulated pixel is displayed.
  • CK1 inputs a low level
  • CK2 inputs a high level
  • GateA outputs a low level
  • GateB1 outputs a pulse signal
  • the pixel displays a previous time when GateA is turned on.
  • the state of the latch. Therefore, this time does not involve signal writing
  • EN2 outputs a high level.
  • the voltage value of the power supply voltage signal outputted by VDD_OUT can be maintained at the first high voltage VGH, and it is not necessary to output a voltage similar to the data voltage.
  • the gate driving sub-circuit of the embodiment of the present disclosure can realize time-division output of the first gate driving signal and the second gate driving signal, are not interfered with each other, and each gate driving signal has its independent enable signal.
  • the enable signal has the following three functions: First, when the pixel is normally written or displayed, the enable signal acts as a reset to ensure that the potential of the gate drive signal is restored to low power in time after the gate drive sub-circuit of the current stage is turned off. In the case of rapid discharge, the enable signal can pull the potential of the gate drive signal high and fully discharge; third, when the MIP pixel unit needs to continuously display the high or low level written by GateA1, no IC is needed. (Integrated Circuit, integrated circuit) provides a pulse signal, and the GateB1 is turned on when the enable signal is maintained as a DC voltage signal only when displayed.
  • the second display mode ie. the low frequency display mode
  • the third control output transmission gate TGC3 is turned off, and the fourth control output transmission gate TGC4 outputs high power.
  • VCK, VCKB, CK1, and CK2 all input low level, GateA1 outputs low level, GateB1 outputs high level, and VDD_OUT outputs VGH. That is, GateA1 writes a certain state to the pixel at a previous moment, and then does not need the clock signal input by STV, VCK, the clock signal of VCKB input, the clock signal of CK1 input, and the clock signal of CK2 input, only the inversion of EN3B output is required. The potential of the signal can be kept high, GateB1 can still be turned on, and the pixel can still display the state written by GateA1 at the previous moment.
  • the IC does not need to output a pulse signal. It only needs to continuously supply the first high voltage VGH, the first low voltage VGL, the second high voltage VDD, the second low voltage VSS, and the inversion enable.
  • the DC signal such as signal can be normally displayed by the pixel drive sub-circuit, and the pixel display effect can still be unaffected when the refresh frequency is extremely low.
  • GateB1 When the pixel is quickly discharged, GateB1 is turned on, the shift register circuit is turned off, and the gate drive sub-circuit of the current stage no longer discharges the next-stage gate drive sub-circuit quickly, but realizes rapid discharge by the enable signal. When discharging quickly, ensure that GateB1 is turned on, and its input and output waveforms are exactly the same as those displayed at low frequencies.
  • the driving method of the gate driving sub-circuit described in the embodiment of the present disclosure is applied to the above-mentioned gate driving sub-circuit, and the driving method of the gate driving sub-circuit includes:
  • the shift register circuit obtains a shift inversion signal and a shift signal according to an input signal input from the input signal terminal under control of the clock signal input end and the positive phase enable end; the shift inversion signal is opposite to the shift signal phase;
  • the first control output sub-circuit generates a first gate driving signal according to the shift signal and the shift inversion signal under the control of the first control clock signal input end and the first enable terminal, and passes through the first gate
  • the pole drive signal output end outputs the first gate drive signal
  • the second control output sub-circuit generates a second gate driving signal according to the shift signal and the shift inverted signal under the control of the second control clock signal input end and the inverting enable end, and passes through the second gate
  • the pole drive signal output terminal outputs the second gate drive signal.
  • the shift signal may be delayed by a predetermined time compared to the input signal.
  • the driving method of the gate driving sub-circuit described in the embodiment of the present disclosure uses a shift register circuit to shift an input signal input from an input signal terminal to obtain a shift signal, and adopts a first control output sub-circuit and a first Controlling an output circuit of the output sub-circuit to obtain a first gate driving signal and a second gate driving signal according to the shift signal, so that two gates can be provided for the MIP pixel unit through the first-level gate driving sub-circuit Drive signals to enable writing and display of MIP pixel cells.
  • the driving method of the gate driving sub-circuit according to the embodiment of the present disclosure can be used in conjunction with the integrated memory pixel unit, and the two gate driving signal outputs respectively connected to the two rows of gate lines connected to the integrated memory pixel unit can be controlled by adjusting the timing. Independent output, so that there is no interference between signal writing and display in the integrated memory pixel unit.
  • the driving method of the gate driving sub-circuit of the embodiment of the present disclosure further includes: the power voltage signal output circuit generates a power voltage signal according to the shift signal under the control of the second enabling end, and passes the power voltage The signal output terminal outputs the power supply voltage signal.
  • the driving method of the gate driving sub-circuit further includes: supplying a power voltage signal to the MIP pixel unit through the power voltage signal output circuit.
  • the shift register circuit includes a first three-state gate, a shift control transistor, a first shift inverter, a second three-state gate, a NAND gate, and a second shift inverter ;
  • the shift register circuit obtains the shift inversion signal and the shift signal according to the input signal input from the input signal terminal under the control of the clock signal input end and the positive phase enable end, including:
  • the potential of the input signal is the first level, the positive phase shift clock signal input terminal inputs the second level, and the inverted shift clock signal input terminal inputs the first level, a phase enable terminal inputs a first level to control the shift control transistor to be turned off;
  • the second three-state gate is off, the first three-state gate outputs a second level, and the first shift is inverted Outputting a first level, the NAND gate outputting a first level such that the shifted inverted signal output terminal outputs a first level;
  • the second shifting inverter outputs a second level, Taking the shift signal output end to output a second level;
  • a potential of the input signal is a second level
  • the positive phase shifting clock signal is input Inputting a first level, the inverted shift clock signal input terminal inputs a second level, and the positive phase enable terminal inputs a first level to control the shift control transistor to be turned off;
  • the potential of the input of the shifting inverter is maintained at a second level, the first shifting inverter outputs a first level, the first three-state gate is closed, and the second three-state gate is outputting a second Level, the NAND gate outputs a second level such that the shifted inverted signal output terminal outputs a second level; the second shifting inverter outputs a first level such that The shift signal output end outputs a first level;
  • the potential of the input signal is a second level
  • the positive phase shift clock signal input terminal inputs a second level
  • the inverted shift clock The signal input terminal inputs a first level, the positive phase enable terminal inputs a first level to control the shift control transistor to be turned off;
  • the second three-state gate is closed, and the first three-state gate output is a level, the first shifting inverter outputs a second level, and the NAND gate outputs a first level, such that the shifted inverted signal output end outputs a first level;
  • the second shifting inverter outputs a second level such that the shifting signal output terminal outputs a second level;
  • the shift register circuit obtains the shift inversion signal and the shift signal according to the input signal input by the input signal terminal under the control of the clock signal input end and the positive phase enable end, including:
  • the potential of the input signal is a second level, the input of the positive phase shift clock signal is input to a second level, the input of the inverted shift clock signal is input to a second level, and the input of the positive phase is enabled.
  • a second level to control the shift control transistor to be turned on such that a potential of an input end of the first shift inverter is a first voltage;
  • the second tri-state gate is off, the first three-state
  • the gate outputs a first level, the first shifting inverter outputs a second level, and the NAND gate outputs a first level such that the shifted inverted signal output terminal outputs a first level;
  • the second shifting inverter outputs a second level such that the shifting signal output terminal outputs a second level.
  • the first display mode is a normal display picture mode
  • the first gate driving signal output end outputs a first level
  • the first electric The level may be a high level, but not limited thereto
  • the pixel signal writing is performed in the first gate driving signal output stage; in the first input stage, the first reset stage, and the first output cutoff holding stage, the first The gate driving signal output terminal outputs a second level (in a specific implementation, the second level may be a low level, but not limited thereto).
  • the first control output sub-circuit includes a first control output transmission gate, a second control output transmission gate, a first control output inverter, and a second control output inverter;
  • the control output sub-circuit includes a third control output transmission gate, a fourth control output transmission gate, a third control output inverter, and a fourth control output inverter; in the first display mode, the first control output sub-circuit And generating, by the first control clock signal input end and the first enable end, a first gate driving signal according to the shift signal and the shift inversion signal, and outputting through the first gate driving signal output end
  • the step of driving the first gate driving signal includes:
  • the shift inversion signal output end outputs a first level
  • the shift signal output end outputs a second level
  • the first enable end outputs a second level
  • the first control output transmission gate is closed, the second control output transmission gate outputs a second level, and the fourth control output inverter outputs a second level to the first gate driving signal output end;
  • the shift inversion signal output end outputs a second level, the shift signal output end outputs a first level, and the first enable end outputs a second level Level, the first control clock signal input terminal inputs a first level, the second control output transmission gate is closed, and the first control output transmission gate outputs a first level;
  • the shift inversion signal output end outputs a second level, the shift signal output end outputs a first level, and the first enable end outputs a second level,
  • the first control clock signal input terminal inputs a second level, the second control output transmission gate is closed, and the first control output transmission gate outputs a second level;
  • the shift inverted signal output terminal outputs a first level
  • the shift signal output terminal outputs a second level
  • the first enable terminal outputs a second level
  • the first control clock signal input terminal inputs a first level
  • the first control output transmission gate is closed
  • the second control output transmission gate outputs a second level
  • the second control output sub-circuit In the first display mode, the second control output sub-circuit generates a second gate according to the shift signal and the shift inverted signal under the control of the second control clock signal input end and the inverting enable end
  • the step of driving the signal and outputting the second gate driving signal through the second gate driving signal output terminal includes:
  • the shift inversion signal output end outputs a first level
  • the shift signal output end outputs a second level
  • the first enable end outputs a second level
  • the first control output transmission gate is closed, the second control output transmission gate outputs a second level, and the fourth control output inverter outputs a second level to the first gate driving signal output end;
  • the shift inversion signal output end outputs a second level
  • the shift signal output end outputs a first level
  • the inverting enable end outputs a second level Level
  • the second control clock signal input terminal inputs a first level
  • the fourth control output transmission gate is closed
  • the third control output transmission gate outputs a first level
  • the shift inversion signal output terminal outputs a second level
  • the shift signal output terminal outputs a first level
  • the inverting enable terminal outputs a second level.
  • the second control clock signal input terminal inputs a second level
  • the fourth control output transmission gate is closed
  • the third control output transmission gate outputs a second level;
  • the shift inversion signal output terminal outputs a first level
  • the shift signal output terminal outputs a second level
  • the inverting enable terminal outputs a second level
  • the second control clock signal input terminal inputs a first level
  • the third control output transmission gate is closed
  • the fourth control output transmission gate outputs a second level.
  • the first control output sub-circuit In the second display mode, the first control output sub-circuit generates a first gate according to the shift signal and the shift inverted signal under the control of the first control clock signal input end and the first enable end
  • the step of driving the signal and outputting the first gate driving signal through the first gate driving signal output terminal includes:
  • the shift inversion signal output end outputs a first level, the shift signal output end outputs a second level; the first enable end outputs a second level, and the first control output transmission gate is closed
  • the second control output transmission gate outputs a second level such that the first gate driving signal output terminal outputs a second level; the inverting enable terminal outputs a first level, the third The control output transmission gate is closed, and the fourth control output transmission gate outputs a first level such that the second gate driving signal output terminal outputs the first level.
  • the first display mode is a normal display picture mode
  • the second gate drive signal output end outputs a first level
  • the first The level may be a high level, but not limited thereto
  • the pixel signal display is performed at the second gate driving signal output stage; the second gate stage, the second reset stage, and the second output cutoff holding stage, the second gate
  • the pole drive signal output terminal outputs a second level (in a specific implementation, the second level may be a low level, but not limited thereto).
  • the second display mode is a low frequency display mode
  • the first gate driving signal output end outputs a second level
  • the second level may be Low level, but not limited thereto
  • the second gate driving signal output end outputs a first level (in a specific implementation, the first level may be a high level, but not limited thereto) That is, the normal black signal FRP in FIG. 1 is read when GateB1 is turned on (that is, the display time in the low frequency display mode).
  • the power voltage signal output circuit includes a power voltage signal output transmission gate, a first power voltage signal output transistor, a power voltage signal output inverter, a second power voltage signal output transistor, and a third power voltage.
  • the power voltage signal output circuit In the first display mode, the power voltage signal output circuit generates a power voltage signal according to the shift signal under the control of the second enable terminal, and the step of outputting the power voltage signal through the power voltage signal output terminal includes:
  • the second enable terminal outputs a second level
  • the shift inverted signal output terminal outputs a first level
  • the shift signal output end Outputting a second level
  • the power voltage signal output transmission gate is closed, and the first power voltage signal output transistor is turned on to control an input end of the power voltage signal output inverter to be connected to the first voltage
  • the power source The output of the voltage signal output inverter outputs a second voltage such that the second power voltage signal output transistor is turned off, and the third power voltage signal output transistor is turned on, so that the power voltage signal output terminal outputs the first Voltage;
  • the second enable terminal outputs a second level
  • the shift inversion signal output terminal outputs a second level
  • the shift signal The output terminal outputs a first level
  • the power supply voltage signal output transmission gate outputs a second level
  • the first power supply voltage signal output transistor is turned off
  • the power supply voltage signal output inverter outputs a first level
  • the third power voltage signal output transistor is turned off;
  • the second power voltage signal output transistor is turned on to control the power voltage signal output terminal to be connected to the second voltage input terminal, so that the power voltage signal output terminal outputs the second voltage ;
  • the shift inversion signal output terminal outputs a first level
  • the shift signal output terminal outputs a second level
  • the power supply voltage signal The output transmission gate is closed, the first power voltage signal output transistor is turned on, so that the input end of the power voltage signal output inverter is connected to the first voltage, and the power voltage signal output inverter outputs the second level Controlling the second power voltage signal output transistor to be turned off, the third power voltage signal output transistor being turned on, so that the power voltage signal output terminal outputs a first voltage;
  • the shift inversion signal output end outputs a second level, and the shift signal output end outputs a first level, the first a power supply voltage signal output transistor is turned off, the second enable terminal outputs a first level, the power supply voltage signal output transmission gate outputs a first level, and the second power supply voltage signal output transistor is turned off, the power supply voltage
  • the output end of the signal output inverter outputs a second level, and the third power voltage signal output transistor is turned on, so that the power voltage signal output terminal outputs the first voltage;
  • the power voltage signal output circuit In the second display mode, the power voltage signal output circuit generates a power voltage signal according to the shift signal under the control of the second enable terminal, and outputs the power voltage signal through the power voltage signal output terminal.
  • the shift inversion signal output end outputs a first level, the shift signal output end outputs a second level, the power supply voltage signal output transmission gate is closed, and the first power supply voltage signal output transistor is turned on to
  • the input end of the power voltage signal output inverter is connected to a first voltage, the second power voltage signal output transistor is turned off, and the power voltage signal output inverter outputs a second level to control the first
  • the three power voltage signal output transistors are turned on to cause the power voltage signal output terminal to output the first voltage.
  • the first voltage may be a first high voltage VGH
  • the second voltage may be a second high voltage VDD (VDD is close to a maximum value of a data voltage on a data line), but not limited thereto. .
  • the voltage value of the voltage signal outputted by the power voltage signal output terminal is close to the data line.
  • the maximum value of the upper data voltage, VDD is lower than VGH; during the remaining time period, the voltage supplied to the MIP pixel unit at the output of the power supply voltage signal is VGH.
  • the low-level signal should be written, but a high-level signal is written into the latch due to the opening of M5, and a disorder occurs.
  • the addition of the power supply voltage signal output circuit can effectively prevent the problem that the latching ring inside the pixel structure is turbulent in the write latch and the pixel state is uncontrollable due to the competitive risk phenomenon when the signal is written.
  • FIG. 8 another specific embodiment of the gate driving sub-circuit of the present disclosure adds a second to the specific implementation of the gate driving sub-circuit of the present disclosure as shown in FIG. 5 .
  • the output circuit and the second power voltage signal output circuit are controlled.
  • the second control output circuit includes the first control output sub-circuit and a second control output sub-circuit.
  • the first control output sub-circuit includes:
  • the fifth control output transmission gate TGC5 the normal phase control terminal is connected to the shift signal output terminal STV_N, the inverting control terminal is connected to the shift inversion signal output terminal STV_F, and the input terminal and the third control clock signal are Input CK3 connection;
  • the sixth control output transmission gate TGC6 the positive phase control terminal is connected to the shift inversion signal output terminal STV_F, the inverting control terminal is connected to the shift signal output terminal STV_N, and the input terminal is connected to the first enable terminal EN1. ;
  • a fifth control output inverter FC5 the input terminal is connected to an output end of the fifth control output transmission gate TGC5 and an output end of the sixth control output transmission gate TGC6;
  • the sixth control output inverter FC6 has an input terminal connected to an output end of the fifth control output inverter FC5, and an output terminal connected to the third gate drive signal output terminal GateA3.
  • the second control output sub-circuit includes:
  • a seventh control output transmission gate TGC7 the positive phase control terminal is connected to the shift signal output terminal STV_N, and the inverting control terminal is connected to the shift inversion signal output terminal STV_F, the input terminal and the fourth control clock signal Input CK4 is connected;
  • the eighth control output transmission gate TGC8 the positive phase control terminal is connected to the shift inversion signal output terminal STV_F, the inverting control terminal is connected to the shift signal output terminal STV_N, the input terminal and the inversion enable end EN3B connection;
  • a seventh control output inverter FC7 the input terminal being connected to an output end of the seventh control output transmission gate TGC7 and an output end of the eighth control output transmission gate TGC8;
  • the eighth control output inverter FC8 has an input terminal connected to an output end of the seventh control output inverter FC7, and an output terminal connected to the fourth gate drive signal output terminal GateB3.
  • the second power voltage signal output circuit includes:
  • the second power voltage signal is output to the transmission gate TGV2, the positive phase control terminal is connected to the shift signal output terminal STV_N, and the inverting control terminal is connected to the shift inversion signal output terminal STV_F, the input terminal and the second enabler
  • the end can be connected to EN2;
  • a fourth power voltage signal output transistor MVO4 a gate connected to the shift signal output terminal STV_N, a source connected to the first high voltage input terminal inputting the first high voltage VGH, and a drain and the second power voltage signal The output end of the output transmission gate TGV2 is connected;
  • the second power voltage signal is outputted to the inverter FV2, and the input end is connected to the output end of the second power voltage signal output transmission gate TGV2;
  • a fifth power voltage signal output transistor MVO5 a gate connected to an output end of the second power voltage signal output transmission gate TGV2, a source connected to a second high voltage input terminal inputting the second high voltage VDD, a drain and a Two power supply voltage signal output terminals VDD_OUT2 are connected;
  • a sixth power supply voltage signal output transistor MVO6 a gate connected to an output end of the second power voltage signal output inverter FV2, a drain connected to the second power voltage signal output terminal VDD_OUT2, a source and the input The first high voltage input of the first high voltage VGH is connected.
  • the specific implementation of the gate driving sub-circuit shown in FIG. 8 can be used to drive two rows of MIP pixel units.
  • the first gate drive sub-circuit corresponds to four rows of MIP pixel units, and even more rows of MIP pixel units.
  • the structure of the parity-level gate driving sub-circuit still differs, and the differences are as follows:
  • the structure of the gate driving sub-circuit for driving the odd-line MIP pixel unit is as shown in FIG. 8;
  • the structure of the gate driving sub-circuit for driving the even-line MIP pixel unit is different from the structure of the gate driving sub-circuit shown in FIG. 8 in that the positive-phase control terminal of the first three-state gate G1 is connected to the VCK, The inverting control terminal of a three-state gate G1 is connected to the VCKB, the positive phase control terminal of the second tri-state gate G2 is connected to the VCKB, and the inverting control terminal of the second tri-state gate G2 is connected to the VCK; An input is connected to the VCKB.
  • FIG. 9 is a simulation diagram of a gate driving sub-circuit according to the present disclosure for driving a four-row MIP pixel unit in a pixel writing state, that is, a GateA is turned on, and a GateB1 is turned off. As shown in FIG.
  • the pulse width of the output drive signal output terminal STV_N outputted by each stage of the gate drive sub-circuit to the next stage is the same as the pulse width of the positive phase shift clock signal of the VCK input, but the first of the CK1 input
  • the pulse width of the control clock signal and the pulse width of the second control clock signal of the CK2 input become 1/4 of the pulse width of the positive phase shift clock signal of the VCK input, which is different from the gate drive subcircuit of each stage for driving two
  • the pulse width of the first control clock signal input by CK1 and the pulse width of the second control clock signal of the CK2 input become 1/2 of the pulse width of the positive phase shift clock signal of the VCK input.
  • the gate driving sub-circuit of each stage drives four rows of MIP pixel units
  • the gate driving sub-circuit described in the embodiment of the present disclosure still maintains all functions when driving two rows of MIP pixel units with each stage of the gate driving sub-circuit.
  • a series of functions such as high-frequency picture display, low-frequency picture display, and fast discharge can also be realized.
  • the gate drive sub-circuit drives two rows from each stage and increases to four rows per stage. With the same resolution, the number of required gate drive sub-circuits is halved, which is more conducive to the realization of narrow frames.
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of cascaded first gate driving modules disposed on a first side of the display panel and a second gate disposed on a second side of the display panel Pole drive module;
  • the first gate driving module includes a plurality of cascaded gate driving sub-circuits
  • the second gate driving module includes a plurality of cascaded gate driving sub-circuits
  • the first gate driving module includes a gate driving sub-circuit connected to an integrated memory pixel unit located in an odd row
  • the second gate driving module includes a gate driving sub-circuit and an integrated memory located in an even row Pixel unit connection.
  • the first side edge may be a left side edge, and the second side edge may be a right side edge; or the first side edge may be a right side edge, and the second side edge may be Is the left side;
  • the shift register circuit in the first gate driving module includes a positive phase shift clock signal input end connected to the positive phase clock signal line, and the shift register circuit in the first gate drive module includes an inverted shift The clock signal input end is connected to the inverted clock signal line;
  • the shift register circuit in the second gate drive module includes a positive phase shift clock signal input end connected to the inverted clock signal line, and the second gate drive
  • the shift register circuit in the module includes an inverted shift clock signal input end connected to the positive phase clock signal line;
  • the input signal terminal in the gate driving sub-circuit includes a first input signal terminal and a second input signal terminal;
  • the shift register circuit in the gate driving sub-circuit includes a forward scan transmission gate and a reverse scan transmission gate ;
  • the first gate driving module in addition to the first-stage gate driving sub-circuit, the first input signal terminal of the first-level gate driving sub-circuit and the adjacent upper-level gate driving a shift signal output terminal of the sub-circuit is connected; except for the last-stage gate drive sub-circuit, the second input signal terminal of the first-level gate drive sub-circuit and the adjacent lower-level gate drive sub-circuit The shift signal output is connected;
  • the second gate driving module in addition to the first-stage gate driving sub-circuit, the first input signal terminal of the first-level gate driving sub-circuit and the adjacent upper-level gate driving a shift signal output terminal of the sub-circuit is connected; except for the last-stage gate drive sub-circuit, the second input signal terminal of the first-level gate drive sub-circuit and the adjacent lower-level gate drive sub-circuit The shift signal output is connected.
  • the gate driving sub-circuit may include M power voltage signal output terminals; M is a positive integer;
  • the nth stage gate driving subcircuit included in the first gate driving module includes a power voltage signal output terminal for supplying a power voltage signal to the integrated memory pixel unit located in the 2nth row;
  • the nth gate driving sub-circuit included in the second gate driving module includes a power voltage signal output terminal for supplying a power voltage signal to the integrated memory pixel unit located in the 2n-1th row;
  • the first gate driving sub-circuit included in the first gate driving module includes a first power voltage signal output terminal for supplying a power voltage signal to the integrated memory pixel unit located in the 4n-2 row;
  • the second gate driving sub-circuit included in the first gate driving module includes a second power voltage signal output terminal for supplying a power voltage signal to the integrated memory pixel unit located in the 4n row;
  • the second gate The first stage gate driving sub-circuit included in the driving module includes a power voltage signal output end for supplying a power voltage signal to the integrated memory pixel unit located in the 4n-3 row;
  • the second gate driving module includes a
  • the secondary gate drive sub-circuit includes a supply voltage signal output for providing a supply voltage signal for the integrated memory pixel unit located in the 4n-1 row;
  • n is a positive integer.
  • the gate driving sub-circuit includes M power voltage signal output ends
  • the gate driving sub-circuit includes M control output circuits, M power voltage signal output circuits, M first control clock signal input terminals, and M The second control clock signal input end, the M first gate drive signal output ends, and the M second gate drive signal output ends.
  • the gate drive circuit of the present disclosure will be described below by two specific embodiments.
  • the gate driving sub-circuit is driven unilaterally, and the first gate driving signal and the second output of the same-stage gate driving sub-circuit are output.
  • the gate driving signal is used to drive the same row of MIP pixel units, and the power voltage signal output end of the gate driving sub-circuit is output to the MIP pixel unit driven by the opposite gate driving sub-circuit;
  • the gate driving sub-circuit for driving the odd-line MIP pixel unit may be disposed on the left side of the display panel, and the gate driving sub-circuit for driving the even-numbered row MIP pixel unit may be disposed on the right side of the display panel.
  • the left gate drive sub-circuit and the right gate drive sub-circuit in the same row control two rows of MIP pixel units, respectively providing the gate drive signals and the power required for the latches for the two rows of MIP pixel units Voltage signal.
  • GOA1L indicates a gate driving sub-circuit of a first row located on the left side of the display panel for driving the first row of MIP pixel cells Pixel1; and GOA1R indicates a first row located at the right side of the display panel. a gate driving sub-circuit for driving a second row of MIP pixel units Pixel2;
  • the power supply voltage signal of the VDD_OUT output of the GOA1L is supplied to the second row of MIP pixel units Pixel2; the power supply voltage signal of the VDD_OUT output included by the GOA1R is supplied to the first row of MIP pixel units PPixel1;
  • GOA2L indicates the gate drive sub-circuit of the second row on the left side of the display panel for driving the third row of MIP pixel cells Pixel3
  • GOA2R indicates the gate drive subcircuit of the second row on the right side of the display panel For driving the fourth row of MIP pixel units Pixel4;
  • GOA2L includes a VDD_OUT output power supply voltage signal is supplied to the fourth row of MIP pixel units Pixel4;
  • GOA2R includes a VDD_OUT output power supply voltage signal is supplied to the third row of MIP pixel units Pixel3;
  • GOAN-1L indicates the gate drive sub-circuit of the N-1th row on the left side of the display panel for driving the 2N-3th row MIP pixel unit Pixel2N-3; the GOAN-1R mark is located on the right side of the display panel a gate drive sub-circuit of the N-1th row for driving the 2N-2 row MIP pixel unit Pixel2N-2;
  • the power supply voltage signal of the VDD_OUT output of the GOAN-1L is supplied to the 2N-2 line MIP pixel unit Pixel2N-2; the power supply voltage signal of the VDD_OUT output included by the GOAN-1R is supplied to the 2N-3th line MIP pixel unit Pixel2N-3;
  • GOANL indicates the gate driving sub-circuit of the Nth row located on the left side of the display panel for driving the 2N-1th row MIP pixel unit Pixel2N-1;
  • the GOANR indicates the gate of the Nth row located at the right side of the display panel a pole drive sub-circuit for driving the 2N-th row MIP pixel unit Pixel2N;
  • the power supply voltage signal of the VDD_OUT output included in the GOANL is supplied to the 2Nth row MIP pixel unit Pixel2N; the power supply voltage signal of the VDD_OUT output included in the GOANR is supplied to the power supply voltage signal input terminal Pixel2N-1 of the 2N-1th row MIP pixel unit.
  • GateA1 is the first gate driving signal output end included in GOA1L
  • GateB1 is the second gate driving signal output end included in GOA1L
  • GateA2 is the first gate driving signal output end included in GOA1R
  • GateB2 is GOA1R.
  • the second gate driving signal output end is included
  • GateA3 is a first gate driving signal output end included in GOA2L
  • GateB3 is a second gate driving signal output end included in GOA2L
  • GateA4 is a first gate driving signal included in GOA2R At the output end, GateB4 is a second gate drive signal output end included in the GOA2R;
  • GateA2N-3 is the first gate drive signal output end of GOAN-1L
  • GateB2N-3 is the second gate drive signal output end of GOAN-1L
  • GateA2N-2 is the first gate drive included in GOAN-1R
  • GateB2N-2 is a second gate drive signal output end included in GOAN-1R;
  • GateA2N-1 is the first gate driving signal output end of GOANL
  • GateB2N-1 is the second gate driving signal output end of GOANL
  • GateA2N is the first gate driving signal output end of GOANR
  • GateB2N is GOANR included. a second gate drive signal output terminal
  • N is an integer greater than 3.
  • the first control clock signal input terminal (connected to the gate drive sub-circuit located on the left side) labeled CK1 and the second control clock signal input terminal labeled CK2 (with the gate on the left side)
  • the pole drive sub-circuit is connected
  • the third control clock signal input terminal (connected to the gate drive sub-circuit located on the right side) labeled CK3
  • the fourth control clock signal input end (located on the right side with the label CK4)
  • the gate drive sub-circuit is connected)
  • the start signal is labeled STV
  • the positive phase shift clock signal input end is labeled VCK
  • the VCKB is the input terminal of the inverted shift clock signal, which is provided by the control signal.
  • the circuit 110 provides the above clock signal and the start signal STV, and the start signal STV is supplied to the input signal terminal of GOA1L and the input signal terminal of GOA1R.
  • the gate driving sub-circuit is driven unilaterally, and the first gate driving signal outputted by the same-stage gate driving sub-circuit is The second gate driving signal is used to drive one row of MIP pixel units, and the third gate driving signal and the fourth gate driving signal outputted by the same level gate driving sub-circuit are used to drive another row of MIP pixel units;
  • the two power voltage signal output ends of the circuit are output to two rows of MIP pixel units driven by the opposite side gate driving sub-circuit;
  • the gate driving sub-circuit for driving the odd-line MIP pixel unit may be disposed on the left side of the display panel, and the gate driving sub-circuit for driving the even-numbered row MIP pixel unit may be disposed on the right side of the display panel.
  • the left gate drive sub-circuit and the right gate drive sub-circuit in the same row control four rows of MIP pixel units, respectively providing the gate drive signals and the power required for the latches for the four rows of MIP pixel units Voltage signal.
  • GOA1L indicates a gate driving sub-circuit of a first row located on a left side of the display panel for driving a first row of MIP pixel cells Pixel1 and a third row of MIP pixel cells Pixel3;
  • the GOA1R is located on the display panel a gate driving sub-circuit of the first row of the right side for driving the second row of MIP pixel cells Pixel2 and the fourth row of MIP pixel cells Pixel4;
  • the first power supply voltage signal of the VDD_OUT1 output of the GOA1L is supplied to the second row of MIP pixel units Pixel2; the second power supply voltage signal of the VDD_OUT2 output of the GOA1L is supplied to the fourth row of MIP pixel units Pixel4;
  • the first power supply voltage signal of the VDD_OUT1 output of the GOA1R is supplied to the first row of MIP pixel units Pixel1; the second power supply voltage signal of the VDD_OUT2 output of the GOA1R is supplied to the third row of MIP pixel units Pixel3;
  • GOA2L indicates the gate driving sub-circuit of the second row located on the left side of the display panel for driving the fifth row of MIP pixel cells Pixel5 and the seventh row of MIP pixel cells Pixel7; the GOA2R designating the second of the right side of the display panel a gate drive sub-circuit for driving a sixth row of MIP pixel cells Pixel6 and an eighth row of MIP pixel cells Pixel8;
  • the first power supply voltage signal of the VDD_OUT1 output of the GOA2L is supplied to the sixth row of MIP pixel units Pixel6; the second power supply voltage signal of the VDD_OUT2 output of the GOA2L is supplied to the eighth row of MIP pixel units Pixel8;
  • the first power supply voltage signal of the VDD_OUT1 output of the GOA2R is supplied to the fifth row of MIP pixel units Pixel5; the second power supply voltage signal of the VDD_OUT2 output of the GOA2R is supplied to the seventh row of MIP pixel units Pixel7;
  • GOANL indicates the gate driving sub-circuit of the Nth row located on the left side of the display panel for driving the 4N-3th row MIP pixel unit Pixel4N-3 and the 4N-1th row MIP pixel unit Pixel4N-1;
  • the GOA2R mark is located a gate driving sub-circuit of the Nth row of the right side of the display panel, for driving the 4N-2th row MIP pixel unit Pixel4N-2 and the 4Nth row MIP pixel unit Pixel4N;
  • the first power supply voltage signal of the VDD_OUT1 output of the GOANL is supplied to the 4N-2th row MIP pixel unit Pixel4N-2;
  • the second power supply voltage signal of the VDD_OUT2 output of the GOA2L is supplied to the 4Nth row MIP pixel unit Pixel4N;
  • the first power supply voltage signal of the VDD_OUT1 output included by the GOANR is supplied to the 4N-3th row MIP pixel unit Pixel4N-3; the second power supply voltage signal of the VDD_OUT2 output included by the GOANR is supplied to the 4N-1th row MIP pixel unit Pixel4N-1.
  • the gate driving sub-circuits of one row on the left side and the gate driving sub-circuits of the row on the right side sequentially provide the first row of four rows of MIP pixel cells.
  • a gate drive signal, a second gate drive signal, and a power supply voltage signal are sequentially provide the first row of four rows of MIP pixel cells.
  • the first control clock signal input terminal (connected to the gate drive sub-circuit located on the left side) labeled CK1 and the second control clock signal input terminal labeled CK2 (with the gate on the left side) Pole drive sub-circuit connection), labeled CK3 is the third control clock signal input terminal (connected to the gate drive sub-circuit located on the left side), and labeled as CK4 is the fourth control clock signal input terminal (with the left side
  • the gate drive sub-circuit is connected), the fifth control clock signal input terminal (connected to the gate drive sub-circuit located on the right side) labeled CK5, and the sixth control clock signal input end (labeled as CK6)
  • the gate drive sub-circuit on the right side is connected
  • the CK7 is the seventh control clock signal input terminal (connected to the gate drive sub-circuit located on the right side)
  • the CK8 is the eighth control clock signal input terminal ( Connected to the gate drive sub-circuit located on the right side, the start signal is labeled STV

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Abstract

一种栅极驱动子电路、驱动方法和栅极驱动电路。栅极驱动子电路包括输入信号端（STV_IN）、移位信号输出端（STV_N）、移位反相信号输出端（STV_F）、正相移位时钟信号输入端（VCK）、反相移位时钟信号输入端（VCKB）、第一控制时钟信号输入端（CK1）、第二控制时钟信号输入端（CK2）、第一栅极驱动信号输出端（GateA1）、第二栅极驱动信号输出端（GateB1）、移位寄存器电路（21）和控制输出电路；控制输出电路包括第一控制输出子电路（221）和第二控制输出子电路（222）。

Description

栅极驱动子电路、驱动方法和栅极驱动电路
相关申请的交叉引用
本申请主张在2017年11月15日在中国提交的中国专利申请号No.201711132896.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种栅极驱动子电路、驱动方法和栅极驱动电路。
背景技术
相关技术中的集成存储器像素单元包括两个栅极驱动信号输出端，但相关技术中的栅极驱动单元只能输出一个栅极驱动信号，不能配合集成存储器像素单元使用，不能提供用于驱动集成存储器像素单元的两个相互独立输出，互不干扰的栅极驱动信号。
发明内容
本公开提供了一种栅极驱动子电路，用于驱动集成存储器像素单元，其中，所述栅极驱动子电路包括输入信号端、移位信号输出端、移位反相信号输出端、正相移位时钟信号输入端、反相移位时钟信号输入端、第一控制时钟信号输入端、第二控制时钟信号输入端、第一栅极驱动信号输出端、第二栅极驱动信号输出端、移位寄存器电路和控制输出电路；所述控制输出电路包括第一控制输出子电路和第二控制输出子电路；
所述移位寄存器电路用于在所述正相时钟信号输入端、所述反相移位时钟信号输入端和所述正相使能端的控制下，根据所述输入信号端输入的输入信号得到移位反相信号和移位信号；
所述第一控制输出子电路用于在所述第一控制时钟信号输入端和第一使能端的控制下，根据所述移位信号和所述移位反相信号生成第一栅极驱动信号，并通过所述第一栅极驱动信号输出端输出所述第一栅极驱动信号；以及，
所述第二控制输出子电路用于在所述第二控制时钟信号输入端和反相使能端的控制下，根据所述移位信号和所述移位反相信号生成第二栅极驱动信号，并通过所述第二栅极驱动信号输出端输出所述第二栅极驱动信号。
实施时，所述栅极驱动子电路还包括电源电压信号输出端和电源电压信号输出电路；所述电源电压信号输出电路与所述电源电压信号输出端、所述移位信号输出端和第二使能端连接，用于在所述第二使能端的控制下根据所述移位信号生成电源电压信号，并通过所述电源电压信号输出端输出所述电源电压信号。
实施时，所述栅极驱动子电路包括M个控制输出电路、M个电源电压信号输出电路、M个第一控制时钟信号输入端、M个第二控制时钟信号输入端、M个第一栅极驱动信号输出端、M个第二栅极驱动信号输出端和M个电源电压信号输出端；M为正整数；
一所述控制输出电路包括的第一控制输出子电路与一所述第一控制时钟信号输入端和一所述第一栅极驱动信号输出端对应连接；
一所述控制输出电路包括的第二控制输出子电路与一所述第二控制时钟信号输入端和一所述第二栅极驱动信号输出端对应连接；
一所述电源电压信号输出电路与一所述电源电压信号输出端对应连接。
实施时，所述移位寄存器电路包括：
第一三态门，正相控制端与所述反相移位时钟信号输入端连接，反相控制端与所述正相移位时钟信号输入端连接，输入端与所述输入信号端连接；
移位控制晶体管，栅极与所述正相使能端连接，第一极与所述第一三态门的输出端连接，第二极与第一电压输入端连接；
第一移位反相器，输入端与所述第一三态门的输出端连接；
第二三态门，正相控制端与所述正相移位时钟信号输入端连接，反相控制端与所述反相移位时钟信号输入端连接，输入端与所述移位反相器的输出端连接，输出端与所述第一三态门的输出端连接；
与非门，第一输入端与所述正相移位时钟信号输入端连接，第二输入端与所述第一移位反相器的输出端连接；以及，
第二移位反相器，输入端与所述移位反相端和所述与非门的输出端连接， 输出端与所述移位输出端连接。
实施时，所述第一控制输出子电路包括：
第一控制输出传输门，正相控制端与所述移位信号输出端连接，反相控制端与所述移位反相信号输出端连接，输入端与所述第一控制时钟信号输入端连接；
第二控制输出传输门，正相控制端与移位反相信号输出端连接，反相控制端与所述移位信号输出端连接，输入端与所述第一使能端连接；
第一控制输出反相器，输入端与所述第一控制输出传输门的输出端和所述第二控制输出传输门的输出端连接；以及，
第二控制输出反相器，输入端与所述第一控制输出反相器的输出端连接，输出端与所述第一栅极驱动信号输出端连接。
实施时，所述第二控制输出子电路包括：
第三控制输出传输门，正相控制端与所述移位信号输出端连接，反相控制端与所述移位反相信号输出端连接，输入端与所述第二控制时钟信号输入端连接；
第四控制输出传输门，正相控制端与所述移位反相信号输出端连接，反相控制端与所述移位信号输出端连接，输入端与所述反相使能端连接；
第三控制输出反相器，输入端与所述第三控制输出传输门的输出端和所述第四控制输出传输门的输出端连接；以及、
第四控制输出反相器，输入端与所述第三控制输出反相器的输出端连接，输出端与所述第二栅极驱动信号输出端连接。
实施时，所述电源电压信号输出电路包括：
电源电压信号输出传输门，正相控制端与所述移位信号输出端连接，反相控制端与所述移位反相信号输出端连接，输入端与所述第二使能端连接；
第一电源电压信号输出晶体管，栅极与所述移位信号输出端连接，第一极与所述电源电压信号输出传输门的输出端连接，第二极与所述第一电压输入端连接；
电源电压信号输出反相器，输入端与所述电源电压信号输出传输门的输出端连接；
第二电源电压信号输出晶体管，栅极与所述电源电压信号输出传输门的输出端连接，第一极与所述第二电压输入端连接，第二极与所述电源电压信号输出端连接；以及，
第三电源电压信号输出晶体管，栅极与所述电源电压信号输出反相器的输出端连接，第一极与所述第一电压输入端连接，第二极与所述电源电压信号输出端连接。
实施时，所述栅极驱动子电路还包括输入电路；其中，所述输入电路与正向扫描控制端、反向扫描控制端、所述正相移位信号端、所述反相移位信号端和所述输入信号端连接，用于在所述正向扫描控制端和所述反向扫描控制端的控制下，控制所述正相移位信号端或所述反相移位信号端与所述输入信号端连接。
实施时，所述输入电路包括正向扫描传输门和反向扫描传输门；
所述正向扫描传输门的正相控制端与所述正向扫描控制端连接，所述正向扫描传输门的反相控制端与所述反向扫描控制端连接，所述正向扫描传输门的输入端与所述正相移位信号端连接，所述正向扫描传输门的输出端与所述输入信号端连接；以及，
所述反向扫描传输门的正相控制端与所述反向扫描控制端连接，所述反向扫描传输门的反相控制端与所述正向扫描控制端连接，所述反向扫描传输门的输入端与所述反相移位信号端连接，所述反向扫描传输门的输出端与所述输入信号端连接。
本公开还提供了一种栅极驱动子电路的驱动方法，应用于上述栅极驱动子电路，其中，所述栅极驱动子电路的驱动方法包括：
移位寄存器电路在时钟信号输入端和正相使能端的控制下，根据输入信号端输入的输入信号得到移位反相信号和移位信号；所述移位反相信号与所述移位信号反相；
第一控制输出子电路在第一控制时钟信号输入端和第一使能端的控制下，根据所述移位信号和所述移位反相信号生成第一栅极驱动信号，并通过第一栅极驱动信号输出端输出所述第一栅极驱动信号；
第二控制输出子电路在第二控制时钟信号输入端和反相使能端的控制下， 根据所述移位信号和所述移位反相信号生成第二栅极驱动信号，并通过第二栅极驱动信号输出端输出所述第二栅极驱动信号。
实施时，所述栅极驱动子电路的驱动方法还包括：电源电压信号输出电路在第二使能端的控制下根据所述移位信号生成电源电压信号，并通过电源电压信号输出端输出所述电源电压信号。
本公开还提供了一种栅极驱动电路，包括多个级联的设置于显示面板的第一侧边的第一栅极驱动模组以及设置于所述显示面板的第二侧边的第二栅极驱动模组；
所述第一栅极驱动模组包括多个级联的上述栅极驱动子电路；
所述第二栅极驱动模组包括多个级联的上述栅极驱动子电路；
所述第一栅极驱动模组包括的栅极驱动子电路与位于奇数行的集成存储器像素单元连接，所述第二栅极驱动模组包括的栅极驱动子电路与位于偶数行的集成存储器像素单元连接。
实施时，所述第一侧边为左侧边，所述第二侧边为右侧边；或者，所述第一侧边为右侧边，所述第二侧边为左侧边；
第一栅极驱动模组中的移位寄存器电路包括的正相移位时钟信号输入端与正相时钟信号线连接，第一栅极驱动模组中的移位寄存器电路包括的反相移位时钟信号输入端与反相时钟信号线连接；第二栅极驱动模组中的移位寄存器电路包括的正相移位时钟信号输入端与所述反相时钟信号线连接，第二栅极驱动模组中的移位寄存器电路包括的反相移位时钟信号输入端与所述正相时钟信号线连接；
所述栅极驱动子电路还包括正相移位信号端和反相移位信号端；所述栅极驱动子电路还包括输入电路；所述输入电路与正向扫描控制端、反向扫描控制端、所述正相移位信号端、所述反相移位信号端和所述输入信号端连接，用于在所述正向扫描控制端和所述反向扫描控制端的控制下，控制所述正相移位信号端或所述反相移位信号端与所述输入信号端连接；
在所述第一栅极驱动模组和所述第二栅极驱动模组中，除了第一级栅极驱动子电路之外，一级所述栅极驱动子电路的正相移位信号端与相邻上一级所述栅极驱动子电路的移位信号输出端连接；除了最后一级栅极驱动子电路 之外，一级所述栅极驱动子电路的反相移位信号端与相邻下一级所述栅极驱动子电路的移位信号输出端连接。
实施时，所述栅极驱动子电路包括M个电源电压信号输出端；M为正整数。
实施时，M等于1；所述第一栅极驱动模组包括的第n级栅极驱动子电路包括的电源电压信号输出端用于为位于第2n行的集成存储器像素单元提供电源电压信号；所述第二栅极驱动模组包括的第n级栅极驱动子电路包括的电源电压信号输出端用于为位于第2n-1行的集成存储器像素单元提供电源电压信号；n为正整数。
实施时，M等于2，所述第一栅极驱动模组包括的第n级栅极驱动子电路包括的第一电源电压信号输出端用于为位于4n-2行的集成存储器像素单元提供电源电压信号；所述第一栅极驱动模组包括的第n级栅极驱动子电路包括的第二电源电压信号输出端用于为位于4n行的集成存储器像素单元提供电源电压信号；所述第二栅极驱动模组包括的第一级栅极驱动子电路包括的电源电压信号输出端用于为位于4n-3行的集成存储器像素单元提供电源电压信号；所述第二栅极驱动模组包括的第二级栅极驱动子电路包括的电源电压信号输出端用于为位于4n-1行的集成存储器像素单元提供电源电压信号；
n为正整数。
附图说明
图1是相关技术中的MIP像素单元的电路图；
图2是本公开一些实施例所述的栅极驱动子电路的结构图；
图3是本公开一些实施例所述的栅极驱动子电路的结构图；
图4是本公开一些实施例所述的栅极驱动子电路的结构图；
图5是本公开一些实施例所述的栅极驱动子电路的一具体实施方式的电路图；
图6是本公开一些实施例所述的栅极驱动子电路的一具体实施方式在第一显示模式下像素信号写入时的工作时序仿真图；
图7是本公开一些实施例所述的栅极驱动子电路的一具体实施方式在第 一显示模式下像素信号显示时的工作时序仿真图；
图8是本公开一些实施例所述的栅极驱动子电路的另一具体实施方式的电路图；
图9是本公开一些实施例所述的栅极驱动子电路的另一具体实施方式在第一显示模式下像素信号写入时的工作时序仿真图；
图10是本公开一些实施例所述的栅极驱动电路的一具体实施方式的结构图；
图11是本公开一些实施例所述的栅极驱动电路的另一具体实施方式的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，相关技术中的集成存储器像素单元包括信号写入模块、锁存器以及显示模块。在图1中，标号M1代表第一n型晶体管，标号M1’代表第一p型晶体管，标号M2代表第二n型晶体管，标号M2’代表第二p型晶体管，标号M3代表第三晶体管，标号M4代表第四晶体管，标号M5代表第五晶体管，标号M6代表第六晶体管，标号M7代表第七晶体管。所述信号写入模块包括M5和M7，M5的栅极和M7的栅极都与第一栅极驱动信号输出端GateA连接。所述锁存器包括M1、M2、M1’和M2’。所述显示模块包括M3、M4和M6。在图1中，标号P代表像素电极，标号N代表第一节点，标号Q代表正相节点，标号Q’代表反相节点；M6的栅极与第二栅极驱动信号输出端GateB连接。
如图1所示的集成存储器像素单元包括两个栅极驱动信号输出端。当像素信号写入时，像素不显示；当像素显示时，无像素信号写入，也即GateA和GateB分时单独驱动。高电压VDD和低电压VSS确保锁存器，在图1中，FRP为常黑信号，Data为数据线。在像素信号写入时，M5打开，将数据线 Data上的数据电压信号写入锁存器内，若数据电压信号为低电平，则Q的电位为低电平，Q’的电位为高电平，M4打开，N的电位即为所述数据电压信号的电位；若Data上的数据电压信号高电平，则Q的电位为高电平，Q’的电位为低电平，M3打开，第一节点N接入常黑信号FRP，GateB控制M6管打开后，像素电极P的电位即为第一节点N的电位。相关技术中的栅极驱动单元只能输出一个栅极驱动信号，不能配合集成存储器像素单元使用，不能提供用于驱动集成存储器像素单元的两个相互独立输出，互不干扰的栅极驱动信号。
有鉴于此，本公开实施例提供一种栅极驱动子电路、驱动方法和栅极驱动电路，解决相关技术中的栅极驱动单元只能输出一个栅极驱动信号，不能配合集成存储器像素单元使用，不能提供用于驱动集成存储器像素单元的两个相互独立输出，互不干扰的栅极驱动信号的问题。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的栅极驱动子电路，用于驱动集成存储器像素单元，如图2所示，所述栅极驱动子电路包括输入信号端STV_IN、移位信号输出端STV_N、移位反相信号输出端STV_F、正相移位时钟信号输入端VCK、反相移位时钟信号输入端VCKB、第一控制时钟信号输入端CK1、第二控制时钟信号输入端CK2、第一栅极驱动信号输出端GateA1、第二栅极驱动信号输出端GateB1、移位寄存器电路21和控制输出电路；所述控制输出电路包括第一控制输出子电路221和第二控制输出子电路222。
所述移位寄存器电路21与所述输入信号端STV_IN、所述移位信号输出端STV_N和所述移位反相信号输出端STV_F、所述正相移位时钟信号输入端VCK、所述反相移位时钟信号输入端VCKB和正相使能端EN3连接。所述移位寄存器电路21用于在所述正相时钟信号输入端VCK、所述反相移位时钟信号输入端VCKB和所述正相使能端EN3的控制下，根据所述输入信号 端STV_IN输入的输入信号得到移位反相信号和移位信号，通过所述移位反相信号输出端STV_F输出所述移位反相信号，通过所述移位信号输出端STV_N输出所述移位信号。
所述第一控制输出子电路221与所述移位信号输出端STV_N、所述移位反相信号输出端STV_F、所述第一控制时钟信号输入端CK1、第一使能端EN1、所述第一栅极驱动信号输出端GateA1连接。所述第一控制输出子电路221用于在所述第一控制时钟信号输入端CK1和第一使能端EN1的控制下，根据所述移位信号和所述移位反相信号生成第一栅极驱动信号，并通过所述第一栅极驱动信号输出端GateA1输出所述第一栅极驱动信号。
所述第二控制输出子电路222与所述移位信号输出端STV_N、所述移位反相信号输出端STV_F、所述第二控制时钟信号输入端CK2、反相使能端EN3B和所述第二栅极驱动信号输出端GateB1连接。所述第二控制输出子电路222用于在所述第二控制时钟信号输入端CK2和反相使能端EN3B的控制下，根据所述移位信号和所述移位反相信号生成第二栅极驱动信号，并通过所述第二栅极驱动信号输出端GateB1输出所述第二栅极驱动信号。
在实际操作时，所述移位反相信号和所述移位信号反相。
在具体实施时，所述移位信号可以比所述输入信号延迟预定时间。
本公开实施例所述的栅极驱动子电路通过采用移位寄存器电路21对由输入信号端STV_IN输入的输入信号进行移位，得到移位信号，并采用包括第一控制输出子电路221和第二控制输出子电路222的控制输出电路，以根据该移位信号得到第一栅极驱动信号和第二栅极驱动信号，从而可以通过一级栅极驱动子电路为MIP(Memory Integrated Pixel，集成存储器像素)像素单元提供两个栅极驱动信号，实现MIP像素单元的写入和显示。本公开实施例所述的栅极驱动子电路可以配合集成存储器像素单元使用，通过调整时序可以控制与集成存储器像素单元连接的两行栅线分别连接的两个栅极驱动信号输出端独立输出，使得集成存储器像素单元内信号写入与显示之间无干扰。
可选的，如图3所示，所述栅极驱动子电路还包括电源电压信号输出端VDD_OUT和电源电压信号输出电路23。
所述电源电压信号输出电路23与所述电源电压信号输出端VDD_OUT、 所述移位信号输出端STV_N和第二使能端EN2连接。所述电源电压信号输出电路23用于在所述第二使能端EN2的控制下根据所述移位信号生成电源电压信号，并通过所述电源电压信号输出端VDD_OUT输出所述电源电压信号。
在一些实施例中，本公开实施例所述的栅极驱动子电路还包括电源电压信号输出端VDD_OUT和电源电压信号输出电路23，以为MIP像素单元提供电源电压信号。
本公开实施例所述的栅极驱动子电路包括移位寄存器子电路、控制输出电路和电源电压信号输出电路，通过门电路和时钟信号相互配合，可以实现MIP像素的写入、显示、提供电源电压信号，避免在像素信号写入时发生竞争冒险现象；时钟信号保证各栅极驱动信号独立输出，互不影响；各使能端的设置保证栅极驱动子电路的信号复位和快速掉电功能，以及在低频驱动时，无起始信号和时钟信号的情况下，依然可以保证像素显示预写入的信号信息，从而保证MIP像素单元功能的有效实现。
可选的，所述栅极驱动子电路包括M个控制输出电路、M个电源电压信号输出电路、M个第一控制时钟信号输入端、M个第二控制时钟信号输入端、M个第一栅极驱动信号输出端、M个第二栅极驱动信号输出端和M个电源电压信号输出端；M为正整数；
一所述控制输出电路包括的第一控制输出子电路与一所述第一控制时钟信号输入端和一所述第一栅极驱动信号输出端对应连接；
一所述控制输出电路包括的第二控制输出子电路与一所述第二控制时钟信号输入端和一所述第二栅极驱动信号输出端对应连接；
一所述电源电压信号输出电路与一所述电源电压信号输出端对应连接。
在一些实施中，本公开实施例所述的栅极驱动子电路包括的控制输出电路和电源电压信号输出电路的个数不仅可以为1个，也可以为大于1个，这样的话本公开实施例所述的栅极驱动子电路既可以用于驱动的MIP像素单元的个数也可以为大于1个，在实际操作时需相应调节时钟信号的波形，在下面将通过一栅极驱动子电路驱动两个MIP像素单元的实施例来说明。
具体的，所述移位寄存器电路可以包括：
第一三态门，正相控制端与所述反相移位时钟信号输入端连接，反相控制端与所述正相移位时钟信号输入端连接，输入端与所述输入信号端连接；
移位控制晶体管，栅极与所述正相使能端连接，第一极与所述第一三态门的输出端连接，第二极与第一电压输入端连接；
第一移位反相器，输入端与所述第一三态门的输出端连接；
第二三态门，正相控制端与所述正相移位时钟信号输入端连接，反相控制端与所述反相移位时钟信号输入端连接，输入端与所述移位反相器的输出端连接，输出端与所述第一三态门的输出端连接；
与非门，第一输入端与所述正相移位时钟信号输入端连接，第二输入端与所述第一移位反相器的输出端连接；以及，
第二移位反相器，输入端与所述移位反相端和所述与非门的输出端连接，输出端与所述移位输出端连接。
具体的，如图4所示，所述栅极驱动子电路还可以包括正相移位信号端STV_N-1和反相移位信号端STV_N+1；
如图4所示，本公开实施例所述的栅极驱动子电路还可以包括输入电路24；
所述输入电路24与正向扫描控制端CN、反向扫描控制端CNB、所述正相移位信号端STV_N-1、所述反相移位信号端STV_N+1和所述输入信号端STV_IN连接。所述输入电路24用于在所述正向扫描控制端CN和所述反向扫描控制端CNB的控制下，控制所述正相移位信号端STV_N-1或所述反相移位信号端STV_N+1与所述输入信号端STV_IN连接。
在具体实施时，所述正相移位信号端STV_N-1与相邻上一级栅极驱动子电路包括的移位信号输出端连接。
所述第二反相移位信号端STV_N+1与相邻下一级栅极驱动子电路包括的移位信号输出端连接。
具体的，所述输入电路可以包括：
正向扫描传输门，正相控制端与正向扫描控制端连接，反相控制端与反向扫描控制端连接，输入端与所述正相移位信号端连接，输出端与所述输入信号端连接；以及，
反向扫描传输门，正相控制端与所述反向扫描控制端连接，反相控制端与所述正向扫描控制端连接，输入端与所述反相移位信号端连接，输出端与所述输入信号端连接。
在正向扫描时，所述正向扫描控制端输出高电平，所述反向扫描控制端输出低电平，正向扫描传输门打开，反向扫描传输门关闭，正相移位信号端与输入信号端连接，也即相邻上一级栅极驱动子电路的移位信号输出端与所述输入信号端连接；
在反向扫描时，所述反向扫描控制端输出高电平，所述正向扫描控制端输出低电平，反向扫描传输门打开，正向扫描传输门关闭，反相移位信号端与输入信号端连接，也即相邻下一级栅极驱动子电路的移位信号输出端与所述输入信号端连接。
具体的，所述第一控制输出子电路可以包括：
第一控制输出传输门，正相控制端与所述移位信号输出端连接，反相控制端与所述移位反相信号输出端连接，输入端与所述第一控制时钟信号输入端连接；
第二控制输出传输门，正相控制端与移位反相信号输出端连接，反相控制端与所述移位信号输出端连接，输入端与所述第一使能端连接；
第一控制输出反相器，输入端与所述第一控制输出传输门的输出端和所述第二控制输出传输门的输出端连接；以及，
第二控制输出反相器，输入端与所述第一控制输出反相器的输出端连接，输出端与所述第一栅极驱动信号输出端连接；
所述第二控制输出子电路包括：
第三控制输出传输门，正相控制端与所述移位信号输出端连接，反相控制端与所述移位反相信号输出端连接，输入端与所述第二控制时钟信号输入端连接；
第四控制输出传输门，正相控制端与所述移位反相信号输出端连接，反相控制端与所述移位信号输出端连接，输入端与所述反相使能端连接；
第三控制输出反相器，输入端与所述第三控制输出传输门的输出端和所述第四控制输出传输门的输出端连接；以及、
第四控制输出反相器，输入端与所述第三控制输出反相器的输出端连接，输出端与所述第二栅极驱动信号输出端连接。
具体的，所述电源电压信号输出电路可以包括：
电源电压信号输出传输门，正相控制端与所述移位信号输出端连接，反相控制端与所述移位反相信号输出端连接，输入端与所述第二使能端连接；
第一电源电压信号输出晶体管，栅极与所述移位信号输出端连接，第一极与所述电源电压信号输出传输门的输出端连接，第二极与所述第一电压输入端连接；
电源电压信号输出反相器，输入端与所述电源电压信号输出传输门的输出端连接；
第二电源电压信号输出晶体管，栅极与所述电源电压信号输出传输门的输出端连接，第一极与所述第二电压输入端连接，第二极与所述电源电压信号输出端连接；以及，
第三电源电压信号输出晶体管，栅极与所述电源电压信号输出反相器的输出端连接，第一极与所述第一电压输入端连接，第二极与所述电源电压信号输出端连接。
在实际操作时，第一电压可以为第一高电压，第二电压可以为第二高电压，但不以此为限。
下面通过具体实施例来说明本公开所述的栅极驱动子电路。
如图5所示，本公开所述的栅极驱动子电路的一具体实施方式包括第一输入信号端STV_N-1、第二输入信号端STV_N+1、移位信号输出端STV_N、移位反相信号输出端STV_F、第一控制时钟信号输入端CK1、第二控制时钟信号输入端CK2、第一栅极驱动信号输出端GateA1、第二栅极驱动信号输出端GateB1、移位寄存器电路、控制输出电路、电源电压信号输出端VDD_OUT、电源电压信号输出电路和输入电路；所述控制输出电路包括第一控制输出子电路和第二控制输出子电路。
所述移位寄存器电路包括：
第一三态门G1，输入端与输入信号端STV_IN连接，正相控制端与反相移位时钟信号输入端VCKB连接，反相控制端与所述正相移位时钟信号输入 端VCK连接；
移位控制晶体管MS，栅极与所述正相使能端EN3连接，漏极与所述第一三态门G1的输出端连接，源极与输入第一高电压VGH的第一高电压输入端连接；
第一移位反相器FS1，输入端与所述第一三态门G1的输出端连接；
第二三态门G2，正相控制端与所述正相移位时钟信号输入端VCK连接，反相控制端与所述反相移位时钟信号输入端VCKB连接，输入端与所述第一移位反相器FS1的输出端连接，输出端与所述第一三态门G1的输出端连接；
与非门AF，第一输入端与所述正相移位时钟信号输入端VCK连接，第二输入端与所述第一移位反相器FS1的输出端连接；以及，
第二移位反相器FS2，输入端与所述移位反相信号输出端STV_F和所述与非门AF的输出端连接，输出端与所述移位信号输出端STV_N连接。
所述输入电路包括正向扫描传输门TGS和反向扫描传输门TGB；
所述正向扫描传输门TGS的正相控制端与正向扫描控制端CN连接，所述正向扫描传输门TGS的反相控制端与反向扫描控制端CNB连接，正向扫描传输门TGS的输入端与第一输入信号端STV_N-1连接，正向扫描传输门TGS的输出端与所述输入信号端STV_IN连接；以及，
所述反向扫描传输门TGB的正相控制端与所述反向扫描控制端CNB连接，所述反向扫描传输门TGB的反相控制端与所述正向扫描控制端CN连接，输入端与第二输入信号端STV_N+1连接，输出端与所述输入信号端STV_IN连接。
所述第一控制输出子电路包括：
第一控制输出传输门TGC1，正相控制端与所述移位信号输出端STV_N连接，反相控制端与所述移位反相信号输出端STV_F连接，输入端与所述第一控制时钟信号输入端CK1连接；
第二控制输出传输门TGC2，正相控制端与移位反相信号输出端STV_F连接，反相控制端与所述移位信号输出端STV_N连接，输入端与所述第一使能端EN1连接；
第一控制输出反相器FC1，输入端与所述第一控制输出传输门TGC1的 输出端和所述第二控制输出传输门TGC2的输出端连接；以及，
第二控制输出反相器FC2，输入端与所述第一控制输出反相器FC1的输出端连接，输出端与所述第一栅极驱动信号输出端GateA1连接。
所述第二控制输出子电路包括：
第三控制输出传输门TGC3，正相控制端与所述移位信号输出端STV_N连接，反相控制端与所述移位反相信号输出端STV_F连接，输入端与所述第二控制时钟信号输入端CK2连接；
第四控制输出传输门TGC4，正相控制端与所述移位反相信号输出端STV_F连接，反相控制端与所述移位信号输出端STV_N连接，输入端与所述反相使能端EN3B连接；
第三控制输出反相器FC3，输入端与所述第三控制输出传输门TGC3的输出端和所述第四控制输出传输门TGC4的输出端连接；以及
第四控制输出反相器FC4，输入端与所述第三控制输出反相器FC3的输出端连接，输出端与所述第二栅极驱动信号输出端GateB1连接。
所述电源电压信号输出电路包括：
电源电压信号输出传输门TGV，正相控制端与所述移位信号输出端STV_N连接，反相控制端与所述移位反相信号输出端STV_F连接，输入端与所述第二使能端EN2连接；
第一电源电压信号输出晶体管MVO1，栅极与所述移位信号输出端STV_N连接，源极与输入第一高电压VGH的第一高电压输入端连接，漏极与所述电源电压信号输出传输门TGV的输出端连接；
电源电压信号输出反相器FV，输入端与所述电源电压信号输出传输门TGV的输出端连接；
第二电源电压信号输出晶体管MVO2，栅极与所述电源电压信号输出传输门TGV的输出端连接，源极与输入第二高电压VDD的第二高电压输入端连接，漏极与所述电源电压信号输出端VDD_OUT连接；以及，
第三电源电压信号输出晶体管MVO3，栅极与所述电源电压信号输出反相器FV的输出端连接，漏极与所述电源电压信号输出端VDD_OUT连接，源极与所述输入第一高电压VGH的第一高电压输入端连接。
在图5所示的具体实施方式中，VGH即为电源电压，VDD接近数据线上的数据电压的最大值，VDD低于VGH，VDD_OUT输出的电压信号用于供给MIP像素单元电压信号。
在图5所示的具体实施方式中，所有的晶体管都为p型晶体管，但是在实际操作时，以上晶体管也可以被替换为n型晶体管，在此对晶体管的类型不作限定。
本公开所述的栅极驱动子电路可以分为三个部分：移位寄存器电路、控制输出电路和电源电压信号输出电路，GateA1和GateB1为一行MIP像素单元提供所需的两个栅极驱动信号，GateA1与MIP像素单元包括的写入晶体管的栅极连接，GateB1与MIP像素单元包括的显示晶体管的栅极连接，VDD_OUT与MIP像素单元的电源电压信号输入端连接。
如图5所示的栅极驱动子电路的具体实施方式可用于为奇数行MIP像素单元提供相应的两栅极驱动信号，在实际操作时，用于为偶数行MIP像素单元提供相应的两栅极驱动信号的栅极驱动子电路与上述具体实施方式的区别在于：与非门AF的第一输入端与所述反相移位时钟信号输入端VCKB连接，并且第一三态门G1的正相控制端与VCK连接，第一三态门G1的反相控制端与VCKB连接，第二三态门G2的正相控制端与VCKB连接，第二三态门G2的反相控制端与VCK连接。
本公开实施例所述的栅极驱动子电路可以为单侧栅极驱动子电路，一级栅极驱动子电路可以供一行MIP像素单元使用。在实际操作时，可以控制设置于显示面板左侧边的多级栅极驱动子电路用于驱动奇数行MIP像素单元，而设置于显示面板右侧边的多级栅极驱动子电路用于驱动偶数行MIP像素单元。两侧的起始信号和移位时钟信号的相位相同，用于输出的CLK1输入的时钟信号和CLK2输入的时钟信号在左右两侧相位不同，左右侧共有四个保证左右两侧栅极驱动信号独立输出，不受干扰的控制输出时钟信号输入端。
如图6所示，本公开所述的栅极驱动子电路的具体实施方式在工作时，
在第一显示模式(所述第一显示模式即为正常显示模式，此时图1中的M4导通，数据线Data上的数据电压在GateB1的控制下写入像素电极，也即在信号写入时Data上的数据电压为低电平，则进入正常显示画面的第一显示 模式，此时在显示阶段根据Data上的数据电压进行显示)下，在像素信号写入时，
在第一输入阶段S11，STV_N输入高电平，正相移位时钟信号输入端VCK输入低电平，反相移位时钟信号输入端VCKB输入高电平，正相使能端EN3输入高电平，以控制所述移位控制晶体管MS关闭；所述第二三态门G2关闭，所述第一三态门G1输出低电平，所述第一移位反相器FS1输出高电平，所述与非门AF输出高电平，以使得所述移位反相信号输出端STV_F输出高电平；所述第二移位反相器FS2输出低电平，以使得所述移位信号输出端STV_N输出低电平；所述第一使能端EN1输出低电平，所述第一控制输出传输门TGC1关闭，所述第二控制输出传输门TGC2输出低电平，所述第四控制输出反相器FC4输出低电平至所述第一栅极驱动信号输出端GateA1；第二使能端EN2输出低电平，所述电源电压信号输出传输门TGV关闭，所述第一电源电压信号输出晶体管MVO1开启，以控制所述电源电压信号输出反相器FV的输入端接入第一高电压VGH，所述电源电压信号输出反相器FV的输出端输出低电压，以使得所述第二电源电压信号输出晶体管MVO2关闭，所述第三电源电压信号输出晶体管MVO3开启，以使得所述电源电压信号输出端VDD_OUT输出第一高电压VGH；
在第一栅极驱动信号输出阶段S12，STV_IN输入低电平，所述正相移位时钟信号输入端VCK输入高电平，所述反相移位时钟信号输入端VCKB输入低电平，所述正相使能端EN3输入高电平，以控制所述移位控制晶体管MS关闭；所述第一移位反相器FS1的输入端的电位维持为低电平，所述第一移位反相器FS1输出高电平，所述第一三态门G1关闭，所述第二三态门G2输出低电平，所述与非门AF输出低电平，以使得所述移位反相信号输出端STV_F输出低电平；所述第二移位反相器FS2输出高电平，以使得所述移位信号输出端STV_N输出高电平；所述第一使能端EN1输出低电平，所述第一控制时钟信号输入端CK1输入高电平，所述第二控制输出传输门TGC2关闭，所述第一控制输出传输门TGC1输出高电平；所述电源电压信号输出传输门TGV输出低电平，所述第一电源电压信号输出晶体管MVO1关闭，所述电源电压信号输出反相器FV输出高电平，所述第三电源电压信号输出 晶体管MVO3关闭；所述第二电源电压信号输出晶体管MVO2开启，以控制所述电源电压信号输出端VDD_OUT与输入第二高电压VDD的第二高电压输入端连接，从而使得所述电源电压信号输出端VDD_OUT输出第二高电压VDD；
在第一复位阶段S13，所述STV_IN输入低电平，所述正相移位时钟信号输入端VCK输入高电平，所述反相移位时钟信号输入端VCKB输入低电平，所述正相使能端EN3输入高电平，以控制所述移位控制晶体管MS关闭；所述第一移位反相器FS1的输入端的电位维持为低电平，所述第一移位反相器FS1输出高电平，所述第一三态门G1关闭，所述第二三态门G2输出低电平，所述与非门AF输出低电平，以使得所述移位反相信号输出端STV_F输出低电平；所述第二移位反相器FS2输出高电平，以使得所述移位信号输出端STV_N输出高电平；所述第一使能端EN1输出低电平，所述第一控制时钟信号输入端CK1输入低电平，所述第二控制输出传输门TGC2关闭，所述第一控制输出传输门TGC1输出低电平；所述电源电压信号输出传输门TGV输出低电平，所述第一电源电压信号输出晶体管MVO1关闭，所述电源电压信号输出反相器FV输出高电平，所述第三电源电压信号输出晶体管MVO3关闭；所述第二电源电压信号输出晶体管MVO2开启，以控制所述电源电压信号输出端VDD_OUT与输入第二高电压VDD的第二高电压输入端连接，从而使得所述电源电压信号输出端VDD_OUT输出第二高电压VDD；
在第一输出截止保持阶段S14，STV_IN输入低电平，所述正相移位时钟信号输入端VCK输入低电平，所述反相移位时钟信号输入端VCKB输入高电平，所述正相使能端EN3输入高电平，以控制所述移位控制晶体管MS关闭；所述第二三态门G2关闭，所述第一三态门G1输出高电平，所述第一移位反相器FS1输出低电平，所述与非门AF输出高电平，以使得所述移位反相信号输出端STV_F输出高电平；所述第二移位反相器FS2输出低电平，以使得所述移位信号输出端STV_N输出低电平；所述第一使能端EN1输出低电平，所述第一控制时钟信号输入端CK1输入高电平，所述第一控制输出传输门TGC1关闭，所述第二控制输出传输门TGC2输出低电平；所述电源电压信号输出传输门TGV关闭，所述第一电源电压信号输出晶体管MVO1开 启，以控制所述电源电压信号输出反相器FV的输入端接入第一高电压VGH，所述电源电压信号输出反相器FV的输出端输出低电压，以使得所述第二电源电压信号输出晶体管MVO2关闭，所述第三电源电压信号输出晶体管MVO3开启，以使得所述电源电压信号输出端VDD_OUT输出第一高电压VGH。
在实际操作时，VCK和VCKB分别负责上下两级栅极驱动单元的移位，VCK输入的时钟信号的脉冲宽度和VCKB输入的时钟信号的脉冲宽度为CK1输入的时钟信号的脉冲宽度的两倍，
如图6所示，在第一栅极驱动信号输出阶段S12，CK1输入高电平，CK2输入低电平，GateA输出脉冲信号，将数据电压信号写入锁存环，待其后帧GateB打开(也即GateB1输出脉冲信号)后，显示GateA开启(也即GateA1输出脉冲信号)时数据线写入的信号。
设置于图5的最右侧的电源电压信号输出电路是设计亮点，其中VGH和VDD为输入信号，VGH即为电源电压，VDD接近数据线上的数据电压的最大值、VDD低于电源电压VGH。
如图6所示，在第一栅极驱动信号输出阶段S12和第一复位阶段S13，VDD_OUT输出的电压信号的电压值接近数据线上的数据电压的最大值，低于VGH；在其余时间段，VDD_OUT提供给像素的电压均为VGH。此设计优点在于，在信号写入时，图1中的M2’的栅极和源极两端电压不会出现差异过大、导致图1所示的MIP像素单元中M5出现倒灌现象，即本该写入低电平信号，但由于M5打开造成高电平信号写入锁存器内，出现紊乱现象。此处电源电压信号输出电路的添加，可以有效防止像素结构内部的锁存环在信号写入时由于竞争冒险现象而造成写入锁存器信紊乱、像素状态不可控的问题发生。
如图7所示，在第一显示模式(所述第一显示模式即为正常显示模式，此时图1中的M4导通，数据线Data上的数据电压在GateB1的控制下写入像素电极，也即在信号写入时Data上的数据电压为低电平，则进入正常显示画面的第一显示模式，此时在显示阶段根据Data上的数据电压进行显示)下，在像素信号显示时，
在第二输入阶段S21，STV_IN输入第一电平，正相移位时钟信号输入端VCK输入低电平，反相移位时钟信号输入端VCKB输入高电平，正相使能端EN3输入高电平，以控制所述移位控制晶体管MS关闭；所述第二三态门G2关闭，所述第一三态门G1输出低电平，所述第一移位反相器FS输出高电平，所述与非门AF输出高电平，以使得所述移位反相信号输出端STV_F输出高电平；所述第二移位反相器FS2输出低电平，以使得所述移位信号输出端STV_N输出低电平；所述第一使能端EN1输出低电平，所述第一控制输出传输门TGC1关闭，所述第二控制输出传输门TGC2输出低电平，所述第四控制输出反相器FC4输出低电平至所述第二栅极驱动信号输出端GateB1，以使得GateB1输出低电平；所述电源电压信号输出传输门TGV关闭，所述第一电源电压信号输出晶体管MVO1开启，以使得所述电源电压信号输出反相器FV的输入端接入第一高电压VGH，所述电源电压信号输出反相器FV输出低电平，以控制所述第二电源电压信号输出晶体管MVO2关闭，所述第三电源电压信号输出晶体管MVO3开启，从而使得所述电源电压信号输出端VDD_OUT输出第一高电压VGH；
在第二栅极驱动信号输出阶段S22，STV_IN输入低电平，所述正相移位时钟信号输入端VCK输入高电平，所述反相移位时钟信号输入端VCKB输入低电平，所述正相使能端EN3输入高电平，以控制所述移位控制晶体管MS关闭；所述第一移位反相器FS的输入端的电位维持为低电平，所述第一移位反相器FS1输出高电平，所述第一三态门G1关闭，所述第二三态门G2输出低电平，所述与非门AF输出低电平，以使得所述移位反相信号输出端STV_F输出低电平；所述第二移位反相器FS2输出高电平，以使得所述移位信号输出端STV_N输出高电平；所述移位反相信号输出端FS输出低电平，所述移位信号输出端STV_N输出高电平，所述反相使能端EN3B输出低电平，所述第二控制时钟信号输入端CK2输入高电平，所述第四控制输出传输门TGC4关闭，所述第三控制输出传输门TGC3输出高电平，以使得GateB1输出高电平；所述第一电源电压信号输出晶体管MVO1关闭，所述第二使能端EN2输出高电平，所述电源电压信号输出传输门TGV输出高电平，所述第二电源电压信号输出晶体管MVO2关闭，所述电源电压信号输出反相器FV的 输出端输出低电平，所述第三电源电压信号输出晶体管MVO3开启，从而使得所述电源电压信号输出端VDD_OUT输出第一高电压VGH；
在第二复位阶段S23，STV_IN输入低电平，所述正相移位时钟信号输入端VCK输入高电平，所述反相移位时钟信号输入端VCKB输入低电平，所述正相使能端EN3输入高电平，以控制所述移位控制晶体管MS关闭；所述第一移位反相器FS的输入端的电位维持为低电平，所述第一移位反相器FS1输出高电平，所述第一三态门G1关闭，所述第二三态门G2输出低电平，所述与非门AF输出低电平，以使得所述移位反相信号输出端STV_F输出低电平；所述反相使能端EN3B输出低电平，所述第二控制时钟信号输入端CK2输入低电平，所述第四控制输出传输门TGC4关闭，所述第三控制输出传输门TGC3输出低电平，以使得GateB1输出低电平；所述第一电源电压信号输出晶体管MVO1关闭，所述第二使能端EN2输出高电平，所述电源电压信号输出传输门TGV输出高电平，所述第二电源电压信号输出晶体管MVO2关闭，所述电源电压信号输出反相器FV的输出端输出低电平，所述第三电源电压信号输出晶体管MVO3开启，从而使得所述电源电压信号输出端VDD_OUT输出第一高电压VGH；
在第二输出截止保持阶段S24，STV_IN输入第二电平，所述正相移位时钟信号输入端VCK输入低电平，所述反相移位时钟信号输入端VCKB输入高电平，所述正相使能端EN3输入高电平，以控制所述移位控制晶体管MS关闭；所述第二三态门G2关闭，所述第一三态门G1输出高电平，所述第一移位反相器FS1输出低电平，所述与非门AF输出高电平，以使得所述移位反相信号输出端STV_F输出高电平；所述第二移位反相器FS2输出低电平，以使得所述移位信号输出端STV_N输出低电平；所述反相使能端EN3B输出低电平，所述第二控制时钟信号输入端CK2输入高电平，所述第三控制输出传输门TGC3关闭，所述第四控制输出传输门TGC4输出低电平，以使得GateB1输出低电平；所述电源电压信号输出传输门TGV关闭，所述第一电源电压信号输出晶体管MVO1开启，以使得所述电源电压信号输出反相器FV的输入端接入第一高电压VH，所述电源电压信号输出反相器FV输出低电平，以控制所述第二电源电压信号输出晶体管MVO2关闭，所述第三电源电压信 号输出晶体管MVO3开启，从而使得所述电源电压信号输出端VDD_OUT输出第一高电压VGH。
图7示出了仿真得到的像素显示时栅极驱动子电路输出波形。如图7所示，在第二栅极驱动信号输出阶段S22，CK1输入低电平、CK2输入高电平，GateA输出低电平，GateB1输出脉冲信号，像素显示前一时刻GateA开启时写入锁存器的状态。因此，此时刻不涉及信号写入，EN2输出高电平，此时可以实现VDD_OUT输出的电源电压信号的电压值保持为第一高电压VGH，不需要再输出与数据电压相近的电压。
本公开实施例所述的栅极驱动子电路可以实现第一栅极驱动信号和第二栅极驱动信号分时输出、彼此不受干扰，且每个栅极驱动信号均有其独立的使能信号。使能信号有以下三种作用：其一，像素正常写入或显示时，使能信号起到复位作用，保证本级栅极驱动子电路关闭之后，栅极驱动信号的电位及时恢复至低电平；其二；在快速放电时，使能信号可以将栅极驱动信号的电位拉高，充分放电；其三，MIP像素单元需要持续显示GateA1写入的高电平或低电平时，无需IC(Integrated Circuit，集成电路)提供脉冲信号，只需显示时使能信号维持为直流电压信号，即可保证GateB1打开。
下面说明在第二显示模式(也即低频显示模式)下如图5所示的本公开所述的栅极驱动子电路的具体实施方式的工作过程。
在第二显示模式(也即低频显示模式)下，
STV_IN输入低电平，所述正相移位时钟信号输入端VCK输入低电平，所述反相移位时钟信号输入端VCKB输入低电平，正相使能端EN3输入低电平，以控制所述移位控制晶体管MS开启，从而使得所述第一移位反相器FS1的输入端的电位为第一高电压VGH；所述第二三态门G2关闭，所述第一三态门G1输出高电平，所述第一移位反相器FS1输出低电平，所述与非门AF输出高电平，以使得所述移位反相信号输出端STV_F输出高电平；所述第二移位反相器FS2输出低电平，以使得所述移位信号输出端STV_N输出第二电平；所述第一使能端EN1输出低电平，所述第一控制输出传输门TGV1关闭，所述第二控制输出传输门TGC2输出低电平，以使得所述第一栅极驱动信号输出端GateA1输出低电平；所述反相使能端EN3B输出高电平，所述第 三控制输出传输门TGC3关闭，所述第四控制输出传输门TGC4输出高电平，以使得GateB1输出高电平；所述电源电压信号输出传输门TGV关闭，所述第一电源电压信号输出晶体管MVO1开启，以使得所述电源电压信号输出反相器FV的输入端接入第一高电压VGH，所述第二电源电压信号输出晶体管MVO2关闭，所述电源电压信号输出反相器FV输出低电平，以控制所述第三电源电压信号输出晶体管MVO3开启，以使得所述电源电压信号输出端VDD_OUT输出第一高电压VGH。
在第二显示模式下，VCK、VCKB、CK1和CK2均输入低电平，GateA1输出低电平，GateB1输出高电平，VDD_OUT输出VGH。即GateA1前一时刻给像素写入某种状态，其后无需STV、VCK输入的时钟信号、VCKB输入的时钟信号、CK1输入的时钟信号以及CK2输入的时钟信号，只需EN3B输出的反相使能信号的电位保持高电平，GateB1依然可以打开，像素依然可以显示GateA1前一时刻为其写入的状态，直至下一时刻，GateA1再次打开，改变之前写入像素锁存环内的状态。此种显示方式最大的优点就是节省功耗，IC无需输出脉冲信号，只需持续提供第一高电压VGH、第一低电压VGL、第二高电压VDD、第二低电压VSS和反相使能信号等直流信号，通过栅极驱动子电路作用，像素端依然可以实现正常显示，在刷新频率极低的情况下，像素显示效果依然可以不受影响。
当像素快速放电时，GateB1打开，移位寄存器电路关闭，本级栅极驱动子电路不再给下一级栅极驱动子电路快速放电，而是通过使能信号实现快速放电。快速放电时，保证GateB1打开，其输入输出波形与低频率显示时完全相同。
本公开实施例所述的栅极驱动子电路的驱动方法，应用于上述的栅极驱动子电路，所述栅极驱动子电路的驱动方法包括：
移位寄存器电路在时钟信号输入端和正相使能端的控制下，根据输入信号端输入的输入信号得到移位反相信号和移位信号；所述移位反相信号与所述移位信号反相；
第一控制输出子电路在第一控制时钟信号输入端和第一使能端的控制下，根据所述移位信号和所述移位反相信号生成第一栅极驱动信号，并通过第一 栅极驱动信号输出端输出所述第一栅极驱动信号；
第二控制输出子电路在第二控制时钟信号输入端和反相使能端的控制下，根据所述移位信号和所述移位反相信号生成第二栅极驱动信号，并通过第二栅极驱动信号输出端输出所述第二栅极驱动信号。
在具体实施时，所述移位信号可以比所述输入信号延迟预定时间。
本公开实施例所述的栅极驱动子电路的驱动方法通过采用移位寄存器电路对由输入信号端输入的输入信号进行移位，得到移位信号，并采用包括第一控制输出子电路和第二控制输出子电路的控制输出电路，以根据该移位信号得到第一栅极驱动信号和第二栅极驱动信号，从而可以通过一级栅极驱动子电路为MIP像素单元提供两个栅极驱动信号，实现MIP像素单元的写入和显示。本公开实施例所述的栅极驱动子电路的驱动方法可以配合集成存储器像素单元使用，通过调整时序可以控制与集成存储器像素单元连接的两行栅线分别连接的两个栅极驱动信号输出端独立输出，使得集成存储器像素单元内信号写入与显示之间无干扰。
可选的，本公开实施例所述的栅极驱动子电路的驱动方法还包括：电源电压信号输出电路在第二使能端的控制下根据所述移位信号生成电源电压信号，并通过电源电压信号输出端输出所述电源电压信号。
在一些实施例中，所述栅极驱动子电路的驱动方法还包括：通过电源电压信号输出电路为MIP像素单元提供电源电压信号。
根据一种具体实施方式，所述移位寄存器电路包括第一三态门、移位控制晶体管、第一移位反相器、第二三态门、与非门和第二移位反相器；
在第一显示模式下，所述移位寄存器电路在时钟信号输入端和正相使能端的控制下，根据输入信号端输入的输入信号得到移位反相信号和移位信号包括：
在第一输入阶段和第二输入阶段，输入信号的电位为第一电平，正相移位时钟信号输入端输入第二电平，反相移位时钟信号输入端输入第一电平，正相使能端输入第一电平，以控制所述移位控制晶体管关闭；所述第二三态门关闭，所述第一三态门输出第二电平，所述第一移位反相器输出第一电平，所述与非门输出第一电平，以使得所述移位反相信号输出端输出第一电平； 所述第二移位反相器输出第二电平，以使得所述移位信号输出端输出第二电平；
在第一栅极驱动信号输出阶段、第一复位阶段、第二栅极驱动信号输出阶段和第二复位阶段，所述输入信号的电位为第二电平，所述正相移位时钟信号输入端输入第一电平，所述反相移位时钟信号输入端输入第二电平，所述正相使能端输入第一电平，以控制所述移位控制晶体管关闭；所述第一移位反相器的输入端的电位维持为第二电平，所述第一移位反相器输出第一电平，所述第一三态门关闭，所述第二三态门输出第二电平，所述与非门输出第二电平，以使得所述移位反相信号输出端输出第二电平；所述第二移位反相器输出第一电平，以使得所述移位信号输出端输出第一电平；
在第一输出截止保持阶段和第二输出截止保持阶段，所述输入信号的电位为第二电平，所述正相移位时钟信号输入端输入第二电平，所述反相移位时钟信号输入端输入第一电平，所述正相使能端输入第一电平，以控制所述移位控制晶体管关闭；所述第二三态门关闭，所述第一三态门输出第一电平，所述第一移位反相器输出第二电平，所述与非门输出第一电平，以使得所述移位反相信号输出端输出第一电平；所述第二移位反相器输出第二电平，以使得所述移位信号输出端输出第二电平；
在第二显示模式下，所述移位寄存器电路在时钟信号输入端和正相使能端的控制下，根据输入信号端输入的输入信号得到移位反相信号和移位信号包括：
所述输入信号的电位为第二电平，所述正相移位时钟信号输入端输入第二电平，所述反相移位时钟信号输入端输入第二电平，正相使能端输入第二电平，以控制所述移位控制晶体管开启，从而使得所述第一移位反相器的输入端的电位为第一电压；所述第二三态门关闭，所述第一三态门输出第一电平，所述第一移位反相器输出第二电平，所述与非门输出第一电平，以使得所述移位反相信号输出端输出第一电平；所述第二移位反相器输出第二电平，以使得所述移位信号输出端输出第二电平。
在实际操作时，所述第一显示模式为正常显示画面模式，在第一栅极驱动输出阶段，第一栅极驱动信号输出端输出第一电平(在具体实施时，所述 第一电平可以为高电平，但不以此为限)，在第一栅极驱动信号输出阶段进行像素信号写入；在第一输入阶段、第一复位阶段和第一输出截止保持阶段，第一栅极驱动信号输出端输出第二电平(在具体实施时，所述第二电平可以为低电平，但不以此为限)。
根据一种具体实施方式，所述第一控制输出子电路包括第一控制输出传输门、第二控制输出传输门、第一控制输出反相器和第二控制输出反相器；所述第二控制输出子电路包括第三控制输出传输门、第四控制输出传输门、第三控制输出反相器和第四控制输出反相器；在第一显示模式下，所述第一控制输出子电路在第一控制时钟信号输入端和第一使能端的控制下，根据所述移位信号和所述移位反相信号生成第一栅极驱动信号，并通过第一栅极驱动信号输出端输出所述第一栅极驱动信号步骤包括：
在所述第一输入阶段，所述移位反相信号输出端输出第一电平，所述移位信号输出端输出第二电平，所述第一使能端输出第二电平，所述第一控制输出传输门关闭，所述第二控制输出传输门输出第二电平，所述第四控制输出反相器输出第二电平至所述第一栅极驱动信号输出端；
在所述第一栅极驱动信号输出阶段，所述移位反相信号输出端输出第二电平，所述移位信号输出端输出第一电平，所述第一使能端输出第二电平，所述第一控制时钟信号输入端输入第一电平，所述第二控制输出传输门关闭，所述第一控制输出传输门输出第一电平；
在所述第一复位阶段，所述移位反相信号输出端输出第二电平，所述移位信号输出端输出第一电平，所述第一使能端输出第二电平，所述第一控制时钟信号输入端输入第二电平，所述第二控制输出传输门关闭，所述第一控制输出传输门输出第二电平；
在所述第一输出截止保持阶段，所述移位反相信号输出端输出第一电平，所述移位信号输出端输出第二电平，所述第一使能端输出第二电平，所述第一控制时钟信号输入端输入第一电平，所述第一控制输出传输门关闭，所述第二控制输出传输门输出第二电平；
在第一显示模式下，所述第二控制输出子电路在第二控制时钟信号输入端和反相使能端的控制下，根据所述移位信号和所述移位反相信号生成第二 栅极驱动信号，并通过第二栅极驱动信号输出端输出所述第二栅极驱动信号步骤包括：
在所述第二输入阶段，所述移位反相信号输出端输出第一电平，所述移位信号输出端输出第二电平，所述第一使能端输出第二电平，所述第一控制输出传输门关闭，所述第二控制输出传输门输出第二电平，所述第四控制输出反相器输出第二电平至所述第一栅极驱动信号输出端；
在所述第二栅极驱动信号输出阶段，所述移位反相信号输出端输出第二电平，所述移位信号输出端输出第一电平，所述反相使能端输出第二电平，所述第二控制时钟信号输入端输入第一电平，所述第四控制输出传输门关闭，所述第三控制输出传输门输出第一电平；
在所述第二复位阶段，所述移位反相信号输出端输出第二电平，所述移位信号输出端输出第一电平，所述反相使能端输出第二电平，所述第二控制时钟信号输入端输入第二电平，所述第四控制输出传输门关闭，所述第三控制输出传输门输出第二电平；
在所述第二输出截止保持阶段，所述移位反相信号输出端输出第一电平，所述移位信号输出端输出第二电平，所述反相使能端输出第二电平，所述第二控制时钟信号输入端输入第一电平，所述第三控制输出传输门关闭，所述第四控制输出传输门输出第二电平。
在第二显示模式下，所述第一控制输出子电路在第一控制时钟信号输入端和第一使能端的控制下，根据所述移位信号和所述移位反相信号生成第一栅极驱动信号，并通过第一栅极驱动信号输出端输出所述第一栅极驱动信号步骤包括：
所述移位反相信号输出端输出第一电平，所述移位信号输出端输出第二电平；所述第一使能端输出第二电平，所述第一控制输出传输门关闭，所述第二控制输出传输门输出第二电平，以使得所述第一栅极驱动信号输出端输出第二电平；所述反相使能端输出第一电平，所述第三控制输出传输门关闭，所述第四控制输出传输门输出第一电平，以使得所述第二栅极驱动信号输出端输出第一电平。
在实际操作时，所述第一显示模式为正常显示画面模式，在第二栅极驱 动输出阶段，第二栅极驱动信号输出端输出第一电平(在具体实施时，所述第一电平可以为高电平，但不以此为限)，在第二栅极驱动信号输出阶段进行像素信号显示；在第二输入阶段、第二复位阶段和第二输出截止保持阶段，第二栅极驱动信号输出端输出第二电平(在具体实施时，所述第二电平可以为低电平，但不以此为限)。
在实际操作时，所述第二显示模式为低频显示模式，在第二显示模式下，第一栅极驱动信号输出端输出第二电平(在具体实施时，所述第二电平可以为低电平，但不以此为限)，第二栅极驱动信号输出端输出第一电平(在具体实施时，所述第一电平可以为高电平，但不以此为限)，也即在GateB1打开(也即低频显示模式下的显示时刻)时读取图1中的常黑信号FRP。
根据一种具体实施方式，所述电源电压信号输出电路包括电源电压信号输出传输门、第一电源电压信号输出晶体管、电源电压信号输出反相器、第二电源电压信号输出晶体管和第三电源电压信号输出晶体管；
在第一显示模式下，所述电源电压信号输出电路在第二使能端的控制下根据所述移位信号生成电源电压信号，并通过电源电压信号输出端输出所述电源电压信号步骤包括：
在所述第一输入阶段和所述第一输出截止保持阶段，第二使能端输出第二电平，所述移位反相信号输出端输出第一电平，所述移位信号输出端输出第二电平，所述电源电压信号输出传输门关闭，所述第一电源电压信号输出晶体管开启，以控制所述电源电压信号输出反相器的输入端接入第一电压，所述电源电压信号输出反相器的输出端输出第二电压，以使得所述第二电源电压信号输出晶体管关闭，所述第三电源电压信号输出晶体管开启，以使得所述电源电压信号输出端输出第一电压；
在所述第一栅极驱动信号输出阶段和所述第一复位阶段，第二使能端输出第二电平，所述移位反相信号输出端输出第二电平，所述移位信号输出端输出第一电平，所述电源电压信号输出传输门输出第二电平，所述第一电源电压信号输出晶体管关闭，所述电源电压信号输出反相器输出第一电平，所述第三电源电压信号输出晶体管关闭；所述第二电源电压信号输出晶体管开启，以控制所述电源电压信号输出端与第二电压输入端连接，从而使得所述 电源电压信号输出端输出第二电压；
在所述第二输入阶段和所述第二输出截止保持阶段，所述移位反相信号输出端输出第一电平，所述移位信号输出端输出第二电平，所述电源电压信号输出传输门关闭，所述第一电源电压信号输出晶体管开启，以使得所述电源电压信号输出反相器的输入端接入第一电压，所述电源电压信号输出反相器输出第二电平，以控制所述第二电源电压信号输出晶体管关闭，所述第三电源电压信号输出晶体管开启，从而使得所述电源电压信号输出端输出第一电压；
在所述第二栅极驱动信号输出阶段和所述第二复位阶段，所述移位反相信号输出端输出第二电平，所述移位信号输出端输出第一电平，所述第一电源电压信号输出晶体管关闭，所述第二使能端输出第一电平，所述电源电压信号输出传输门输出第一电平，所述第二电源电压信号输出晶体管关闭，所述电源电压信号输出反相器的输出端输出第二电平，所述第三电源电压信号输出晶体管开启，从而使得所述电源电压信号输出端输出第一电压；
在所述第二显示模式下，所述电源电压信号输出电路在第二使能端的控制下根据所述移位信号生成电源电压信号，并通过电源电压信号输出端输出所述电源电压信号步骤包括：
所述移位反相信号输出端输出第一电平，所述移位信号输出端输出第二电平，所述电源电压信号输出传输门关闭，所述第一电源电压信号输出晶体管开启，以使得所述电源电压信号输出反相器的输入端接入第一电压，所述第二电源电压信号输出晶体管关闭，所述电源电压信号输出反相器输出第二电平，以控制所述第三电源电压信号输出晶体管开启，以使得所述电源电压信号输出端输出第一电压。
在实际操作时，所述第一电压可以为第一高电压VGH，所述第二电压可以为第二高电压VDD(VDD接近数据线上的数据电压的最大值)，但不以此为限。
在具体实施时，在第一显示模式下，在进行像素信号写入时，在第一栅极驱动信号输出阶段和第一复位阶段，电源电压信号输出端输出的电压信号的电压值接近数据线上的数据电压的最大值，VDD低于VGH；在其余时间 段，电源电压信号输出端提供给MIP像素单元的电压均为VGH。通过如上电压设计，在像素信号写入时，使得图1中的M2’的栅极和源极两端电压不会出现差异过大、导致图1所示的MIP像素单元中M5出现倒灌现象，即本该写入低电平信号，但由于M5打开造成高电平信号写入锁存器内，出现紊乱现象。此处电源电压信号输出电路的添加，可以有效防止像素结构内部的锁存环在信号写入时由于竞争冒险现象而造成写入锁存器的信号紊乱、像素状态不可控的问题发生。
如图8所示，本公开所述的栅极驱动子电路的另一具体实施方式在如图5所示的本公开所述的栅极驱动子电路的具体实施方式的基础上增加了第二控制输出电路和第二电源电压信号输出电路。
如图8所示，所述第二控制输出电路包括所述第一控制输出子电路和第二控制输出子电路。
其中，所述第一控制输出子电路包括：
第五控制输出传输门TGC5，正相控制端与所述移位信号输出端STV_N连接，反相控制端与所述移位反相信号输出端STV_F连接，输入端与所述第三控制时钟信号输入端CK3连接；
第六控制输出传输门TGC6，正相控制端与移位反相信号输出端STV_F连接，反相控制端与所述移位信号输出端STV_N连接，输入端与所述第一使能端EN1连接；
第五控制输出反相器FC5，输入端与所述第五控制输出传输门TGC5的输出端和所述第六控制输出传输门TGC6的输出端连接；以及，
第六控制输出反相器FC6，输入端与所述第五控制输出反相器FC5的输出端连接，输出端与所述第三栅极驱动信号输出端GateA3连接。
所述第二控制输出子电路包括：
第七控制输出传输门TGC7，正相控制端与所述移位信号输出端STV_N连接，反相控制端与所述移位反相信号输出端STV_F连接，输入端与所述第四控制时钟信号输入端CK4连接；
第八控制输出传输门TGC8，正相控制端与所述移位反相信号输出端STV_F连接，反相控制端与所述移位信号输出端STV_N连接，输入端与所 述反相使能端EN3B连接；
第七控制输出反相器FC7，输入端与所述第七控制输出传输门TGC7的输出端和所述第八控制输出传输门TGC8的输出端连接；以及
第八控制输出反相器FC8，输入端与所述第七控制输出反相器FC7的输出端连接，输出端与所述第四栅极驱动信号输出端GateB3连接。
所述第二电源电压信号输出电路包括：
第二电源电压信号输出传输门TGV2，正相控制端与所述移位信号输出端STV_N连接，反相控制端与所述移位反相信号输出端STV_F连接，输入端与所述第二使能端EN2连接；
第四电源电压信号输出晶体管MVO4，栅极与所述移位信号输出端STV_N连接，源极与输入第一高电压VGH的第一高电压输入端连接，漏极与所述第二电源电压信号输出传输门TGV2的输出端连接；
第二电源电压信号输出反相器FV2，输入端与所述第二电源电压信号输出传输门TGV2的输出端连接；
第五电源电压信号输出晶体管MVO5，栅极与所述第二电源电压信号输出传输门TGV2的输出端连接，源极与输入第二高电压VDD的第二高电压输入端连接，漏极与第二电源电压信号输出端VDD_OUT2连接；以及，
第六电源电压信号输出晶体管MVO6，栅极与所述第二电源电压信号输出反相器FV2的输出端连接，漏极与所述第二电源电压信号输出端VDD_OUT2连接，源极与所述输入第一高电压VGH的第一高电压输入端连接。
本公开如图8所示的栅极驱动子电路的具体实施方式可以用于驱动两行MIP像素单元，在实际操作时，当采用更多的控制输出电路和电源电压信号输出电路时，也可以做到一级栅极驱动子电路对应四行MIP像素单元，甚至更多行MIP像素单元。当一级栅极驱动子电路对应四行MIP像素单元时，奇偶级栅极驱动子电路的结构依然存在差别，差别如下：
用于驱动奇数行MIP像素单元的栅极驱动子电路的结构如图8所示；
而用于驱动偶数行MIP像素单元的栅极驱动子电路的结构与图8所示的栅极驱动子电路的结构的区别在于：第一三态门G1的正相控制端与VCK连 接，第一三态门G1的反相控制端与VCKB连接，第二三态门G2的正相控制端与VCKB连接，第二三态门G2的反相控制端与VCK连接；与非门AF的第一输入端与VCKB连接。
如图9所示，本公开如图8所示的栅极驱动子电路的具体实施方式在工作时，在第一显示模式下，在进行多行驱动像素写入时，
在输入阶段S0，STV_IN输入高电平；
在第一输出阶段S1，STV_IN输入低电平，GateA1输出高电平，GateB1、GateA3和GateB3都输出低电平；
在第一复位阶段S2，STV_IN输入低电平，GateA1、GateB1、GateA3和GateB3都输出低电平；
在第二输出阶段S3，STV_IN输入低电平，GateA3输出高电平，GateA1、GateB1和GateB3都输出低电平；
在第二复位阶段S4，STV_IN输入低电平，GateA1、GateB1、GateA3和GateB3都输出低电平；
在所述第一输出阶段S1、所述第一复位阶段S2、第二输出阶段S3和所述第二复位阶段S4，STV_N输出高电平；
在所述第一输出阶段S1、所述第一复位阶段S2、第二输出阶段S3和所述第二复位阶段S4，VDD_OUT和VDD_OUT2都输出VDD；在其他阶段,VDD_OUT和VDD_OUT2都输出VGH。
图9为本公开所述的栅极驱动子电路的具体实施方式用于驱动四行MIP像素单元时，在像素写入状态下，即GateA开启，GateB1关闭时刻的仿真形。如图9所示，每级栅极驱动子电路输出给下一级的输移位信号输出端STV_N的脉冲宽度与VCK输入的正相移位时钟信号的脉冲宽度相同，但CK1输入的第一控制时钟信号的脉冲宽度和CK2输入的第二控制时钟信号的脉冲宽度变为VCK输入的正相移位时钟信号的脉冲宽度的1/4，区别于每级栅极驱动子电路用于驱动两行MIP像素单元时，CK1输入的第一控制时钟信号的脉冲宽度和CK2输入的第二控制时钟信号的脉冲宽度变为VCK输入的正相移位时钟信号的脉冲宽度的1/2。
在每级栅极驱动子电路驱动四行MIP像素单元时，本公开实施例所述的 栅极驱动子电路依然保持着与每级栅极驱动子电路驱动两行MIP像素单元时的全部功能，也可以实现高频率画面显示、低频率画面显示以及快速放电等一系列功能。栅极驱动子电路从每级驱动两行，增加至每级驱动四行，面对同样的分辨率，将所需栅极驱动子电路的数量减半，这样更有利于窄边框的实现。
本公开实施例所述的栅极驱动电路包括多个级联的设置于显示面板的第一侧边的第一栅极驱动模组以及设置于所述显示面板的第二侧边的第二栅极驱动模组；
所述第一栅极驱动模组包括多个级联的上述的栅极驱动子电路；
所述第二栅极驱动模组包括多个级联的上述的栅极驱动子电路；
所述第一栅极驱动模组包括的栅极驱动子电路与位于奇数行的集成存储器像素单元连接，所述第二栅极驱动模组包括的栅极驱动子电路与位于偶数行的集成存储器像素单元连接。
在实际操作时，所述第一侧边可以为左侧边，所述第二侧边可以为右侧边；或者，所述第一侧边可以为右侧边，所述第二侧边可以为左侧边；
第一栅极驱动模组中的移位寄存器电路包括的正相移位时钟信号输入端与正相时钟信号线连接，第一栅极驱动模组中的移位寄存器电路包括的反相移位时钟信号输入端与反相时钟信号线连接；第二栅极驱动模组中的移位寄存器电路包括的正相移位时钟信号输入端与所述反相时钟信号线连接，第二栅极驱动模组中的移位寄存器电路包括的反相移位时钟信号输入端与所述正相时钟信号线连接；
所述栅极驱动子电路中的输入信号端包括第一输入信号端和第二输入信号端；所述栅极驱动子电路中的移位寄存器电路包括正向扫描传输门和反向扫描传输门；
在所述第一栅极驱动模组中，除了第一级栅极驱动子电路之外，一级所述栅极驱动子电路的第一输入信号端与相邻上一级所述栅极驱动子电路的移位信号输出端连接；除了最后一级栅极驱动子电路之外，一级所述栅极驱动子电路的第二输入信号端与相邻下一级所述栅极驱动子电路的移位信号输出端连接；
在所述第二栅极驱动模组中，除了第一级栅极驱动子电路之外，一级所述栅极驱动子电路的第一输入信号端与相邻上一级所述栅极驱动子电路的移位信号输出端连接；除了最后一级栅极驱动子电路之外，一级所述栅极驱动子电路的第二输入信号端与相邻下一级所述栅极驱动子电路的移位信号输出端连接。
具体的，所述栅极驱动子电路可以包括M个电源电压信号输出端；M为正整数；
M等于1；所述第一栅极驱动模组包括的第n级栅极驱动子电路包括的电源电压信号输出端用于为位于第2n行的集成存储器像素单元提供电源电压信号；所述第二栅极驱动模组包括的第n级栅极驱动子电路包括的电源电压信号输出端用于为位于第2n-1行的集成存储器像素单元提供电源电压信号；
M等于2，所述第一栅极驱动模组包括的第n级栅极驱动子电路包括的第一电源电压信号输出端用于为位于4n-2行的集成存储器像素单元提供电源电压信号；所述第一栅极驱动模组包括的第n级栅极驱动子电路包括的第二电源电压信号输出端用于为位于4n行的集成存储器像素单元提供电源电压信号；所述第二栅极驱动模组包括的第一级栅极驱动子电路包括的电源电压信号输出端用于为位于4n-3行的集成存储器像素单元提供电源电压信号；所述第二栅极驱动模组包括的第二级栅极驱动子电路包括的电源电压信号输出端用于为位于4n-1行的集成存储器像素单元提供电源电压信号；
n为正整数。
当所述栅极驱动子电路包括M个电源电压信号输出端时，该栅驱动子电路包括M个控制输出电路、M个电源电压信号输出电路、M个第一控制时钟信号输入端、M个第二控制时钟信号输入端、M个第一栅极驱动信号输出端和M个第二栅极驱动信号输出端。
下面通过两个具体实施方式来说明本公开所述的栅极驱动电路。
如图10所示，在本公开所述的栅极驱动电路的一具体实施方式中，栅极驱动子电路单边驱动，同一级栅极驱动子电路输出的第一栅极驱动信号和第二栅极驱动信号用于驱动同一行MIP像素单元，该级栅极驱动子电路的电源电压信号输出端输出至对侧栅极驱动子电路驱动的MIP像素单元；
在实际操作时，可以将用于驱动奇数行MIP像素单元的栅极驱动子电路设置于显示面板的左侧边，将驱动偶数行MIP像素单元的栅极驱动子电路设置于显示面板的右侧边；即位于同一行的左侧栅极驱动子电路和右侧栅极驱动子电路控制两行MIP像素单元，分别为这两行MIP像素单元提供栅极驱动信号和锁存器所需的电源电压信号。
在图10中，GOA1L标示位于显示面板的左侧边的第一行的栅极驱动子电路，用于驱动第一行MIP像素单元Pixel1；GOA1R标示位于显示面板的右侧边的第一行的栅极驱动子电路，用于驱动第二行MIP像素单元Pixel2；
GOA1L包括的VDD_OUT输出的电源电压信号提供给第二行MIP像素单元Pixel2；GOA1R包括的VDD_OUT输出的电源电压信号提供给第一行MIP像素单元PPixel1；
GOA2L标示位于显示面板的左侧边的第二行的栅极驱动子电路，用于驱动第三行MIP像素单元Pixel3；GOA2R标示位于显示面板的右侧边的第二行的栅极驱动子电路，用于驱动第四行MIP像素单元Pixel4；
GOA2L包括的VDD_OUT输出的电源电压信号提供给第四行MIP像素单元Pixel4；GOA2R包括的VDD_OUT输出的电源电压信号提供给位于第三行MIP像素单元Pixel3；
GOAN-1L标示位于显示面板的左侧边的第N-1行的栅极驱动子电路，用于驱动第2N-3行MIP像素单元Pixel2N-3；GOAN-1R标示位于显示面板的右侧边的第N-1行的栅极驱动子电路，用于驱动第2N-2行MIP像素单元Pixel2N-2；
GOAN-1L包括的VDD_OUT输出的电源电压信号提供给第2N-2行MIP像素单元Pixel2N-2；GOAN-1R包括的VDD_OUT输出的电源电压信号提供给第2N-3行MIP像素单元Pixel2N-3；
GOANL标示位于显示面板的左侧边的第N行的栅极驱动子电路，用于驱动第2N-1行MIP像素单元Pixel2N-1；GOANR标示位于显示面板的右侧边的第N行的栅极驱动子电路，用于驱动第2N行MIP像素单元Pixel2N；
GOANL包括的VDD_OUT输出的电源电压信号提供给第2N行MIP像素单元Pixel2N；GOANR包括的VDD_OUT输出的电源电压信号提供给第 2N-1行MIP像素单元的电源电压信号输入端Pixel2N-1。
在图10中，GateA1为GOA1L包括的第一栅极驱动信号输出端，GateB1为GOA1L包括的第二栅极驱动信号输出端；GateA2为GOA1R包括的第一栅极驱动信号输出端，GateB2为GOA1R包括的第二栅极驱动信号输出端；GateA3为GOA2L包括的第一栅极驱动信号输出端，GateB3为GOA2L包括的第二栅极驱动信号输出端；GateA4为GOA2R包括的第一栅极驱动信号输出端，GateB4为GOA2R包括的第二栅极驱动信号输出端；
GateA2N-3为GOAN-1L包括的第一栅极驱动信号输出端，GateB2N-3为GOAN-1L包括的第二栅极驱动信号输出端；GateA2N-2为GOAN-1R包括的第一栅极驱动信号输出端，GateB2N-2为GOAN-1R包括的第二栅极驱动信号输出端；
GateA2N-1为GOANL包括的第一栅极驱动信号输出端，GateB2N-1为GOANL包括的第二栅极驱动信号输出端；GateA2N为GOANR包括的第一栅极驱动信号输出端，GateB2N为GOANR包括的第二栅极驱动信号输出端；
N为大于3的整数。
在图10中，标号为CK1的为第一控制时钟信号输入端(与位于左侧的栅极驱动子电路连接)，标号为CK2的为第二控制时钟信号输入端(与位于左侧的栅极驱动子电路连接)，标号为CK3的为第三控制时钟信号输入端(与位于右侧的栅极驱动子电路连接)，标号为CK4的为第四控制时钟信号输入端(与位于右侧的栅极驱动子电路连接)，标号为STV的为起始信号，标号为VCK的为正相移位时钟信号输入端，标号为VCKB的为反相移位时钟信号输入端，由控制信号提供电路110提供如上时钟信号和起始信号STV，起始信号STV提供至GOA1L的输入信号端和GOA1R的输入信号端。
如图11所示，在本公开所述的栅极驱动电路的另一具体实施方式中，栅极驱动子电路单边驱动，同一级栅极驱动子电路输出的第一栅极驱动信号、第二栅极驱动信号用于驱动一行MIP像素单元，同一级栅极驱动子电路输出的第三栅极驱动信号、第四栅极驱动信号用于驱动另一行MIP像素单元；该级栅极驱动子电路的两个电源电压信号输出端输出至对侧栅极驱动子电路驱动的两行MIP像素单元；
在实际操作时，可以将用于驱动奇数行MIP像素单元的栅极驱动子电路设置于显示面板的左侧边，将驱动偶数行MIP像素单元的栅极驱动子电路设置于显示面板的右侧边；即位于同一行的左侧栅极驱动子电路和右侧栅极驱动子电路控制四行MIP像素单元，分别为这四行MIP像素单元提供栅极驱动信号和锁存器所需的电源电压信号。
在图11中，GOA1L标示位于显示面板的左侧边的第一行的栅极驱动子电路，用于驱动第一行MIP像素单元Pixel1和第三行MIP像素单元Pixel3；GOA1R标示位于显示面板的右侧边的第一行的栅极驱动子电路，用于驱动第二行MIP像素单元Pixel2和第四行MIP像素单元Pixel4；
GOA1L包括的VDD_OUT1输出的第一电源电压信号提供给第二行MIP像素单元Pixel2；GOA1L包括的VDD_OUT2输出的第二电源电压信号提供给第四行MIP像素单元Pixel4；
GOA1R包括的VDD_OUT1输出的第一电源电压信号提供给第一行MIP像素单元Pixel1；GOA1R包括的VDD_OUT2输出的第二电源电压信号提供给第三行MIP像素单元Pixel3；
GOA2L标示位于显示面板的左侧边的第二行的栅极驱动子电路，用于驱动第五行MIP像素单元Pixel5和第七行MIP像素单元Pixel7；GOA2R标示位于显示面板的右侧边的第二行的栅极驱动子电路，用于驱动第六行MIP像素单元Pixel6和第八行MIP像素单元Pixel8；
GOA2L包括的VDD_OUT1输出的第一电源电压信号提供给第六行MIP像素单元Pixel6；GOA2L包括的VDD_OUT2输出的第二电源电压信号提供给第八行MIP像素单元Pixel8；
GOA2R包括的VDD_OUT1输出的第一电源电压信号提供给第五行MIP像素单元Pixel5；GOA2R包括的VDD_OUT2输出的第二电源电压信号提供给第七行MIP像素单元Pixel7；
GOANL标示位于显示面板的左侧边的第N行的栅极驱动子电路，用于驱动第4N-3行MIP像素单元Pixel4N-3和第4N-1行MIP像素单元Pixel4N-1；GOA2R标示位于显示面板的右侧边的第N行的栅极驱动子电路，用于驱动第4N-2行MIP像素单元Pixel4N-2和第4N行MIP像素单元Pixel4N；
GOANL包括的VDD_OUT1输出的第一电源电压信号提供给第4N-2行MIP像素单元Pixel4N-2；GOA2L包括的VDD_OUT2输出的第二电源电压信号提供给第4N行MIP像素单元Pixel4N；
GOANR包括的VDD_OUT1输出的第一电源电压信号提供给第4N-3行MIP像素单元Pixel4N-3；GOANR包括的VDD_OUT2输出的第二电源电压信号提供给第4N-1行MIP像素单元Pixel4N-1。
在图11所示的栅极驱动电路的具体实施方式中，位于左侧的一行的栅极驱动子电路和位于右侧的该行的栅极驱动子电路依次为四行MIP像素单元提供第一栅极驱动信号、第二栅极驱动信号和电源电压信号。
在图11中，标号为CK1的为第一控制时钟信号输入端(与位于左侧的栅极驱动子电路连接)，标号为CK2的为第二控制时钟信号输入端(与位于左侧的栅极驱动子电路连接)，标号为CK3的为第三控制时钟信号输入端(与位于左侧的栅极驱动子电路连接)，标号为CK4的为第四控制时钟信号输入端(与位于左侧的栅极驱动子电路连接)，标号为CK5的为第五控制时钟信号输入端(与位于右侧的栅极驱动子电路连接)，标号为CK6的为第六控制时钟信号输入端(与位于右侧的栅极驱动子电路连接)，标号为CK7的为第七控制时钟信号输入端(与位于右侧的栅极驱动子电路连接)，标号为CK8的为第八控制时钟信号输入端(与位于右侧的栅极驱动子电路连接)，标号为STV的为起始信号，标号为VCK的为正相移位时钟信号输入端，标号为VCKB的为反相移位时钟信号输入端，由控制信号提供电路110提供如上时钟信号和起始信号STV，起始信号STV提供至GOA1L的输入信号端和GOA1R的输入信号端。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (16)

  1. 一种栅极驱动子电路，用于驱动集成存储器像素单元，其中，所述栅极驱动子电路包括输入信号端、移位信号输出端、移位反相信号输出端、正相移位时钟信号输入端、反相移位时钟信号输入端、第一控制时钟信号输入端、第二控制时钟信号输入端、第一栅极驱动信号输出端、第二栅极驱动信号输出端、移位寄存器电路和控制输出电路；所述控制输出电路包括第一控制输出子电路和第二控制输出子电路；
    所述移位寄存器电路用于在所述正相时钟信号输入端、所述反相移位时钟信号输入端和所述正相使能端的控制下，根据所述输入信号端输入的输入信号得到移位反相信号和移位信号；
    所述第一控制输出子电路用于在所述第一控制时钟信号输入端和第一使能端的控制下，根据所述移位信号和所述移位反相信号生成第一栅极驱动信号，并通过所述第一栅极驱动信号输出端输出所述第一栅极驱动信号；以及，
    所述第二控制输出子电路用于在所述第二控制时钟信号输入端和反相使能端的控制下，根据所述移位信号和所述移位反相信号生成第二栅极驱动信号，并通过所述第二栅极驱动信号输出端输出所述第二栅极驱动信号。
  2. 如权利要求1所述的栅极驱动子电路，其中，所述栅极驱动子电路还包括电源电压信号输出端和电源电压信号输出电路；
    所述电源电压信号输出电路与所述电源电压信号输出端、所述移位信号输出端和第二使能端连接，用于在所述第二使能端的控制下根据所述移位信号生成电源电压信号，并通过所述电源电压信号输出端输出所述电源电压信号。
  3. 如权利要求2所述的栅极驱动子电路，其中，所述栅极驱动子电路包括M个控制输出电路、M个电源电压信号输出电路、M个第一控制时钟信号输入端、M个第二控制时钟信号输入端、M个第一栅极驱动信号输出端、M个第二栅极驱动信号输出端和M个电源电压信号输出端；M为正整数；
    一所述控制输出电路包括的第一控制输出子电路与一所述第一控制时钟信号输入端和一所述第一栅极驱动信号输出端对应连接；
    一所述控制输出电路包括的第二控制输出子电路与一所述第二控制时钟信号输入端和一所述第二栅极驱动信号输出端对应连接；
    一所述电源电压信号输出电路与一所述电源电压信号输出端对应连接。
  4. 如权利要求1至3中任一权利要求所述的栅极驱动子电路，其中，所述移位寄存器电路包括：
    第一三态门，正相控制端与所述反相移位时钟信号输入端连接，反相控制端与所述正相移位时钟信号输入端连接，输入端与所述输入信号端连接；
    移位控制晶体管，栅极与所述正相使能端连接，第一极与所述第一三态门的输出端连接，第二极与第一电压输入端连接；
    第一移位反相器，输入端与所述第一三态门的输出端连接；
    第二三态门，正相控制端与所述正相移位时钟信号输入端连接，反相控制端与所述反相移位时钟信号输入端连接，输入端与所述移位反相器的输出端连接，输出端与所述第一三态门的输出端连接；
    与非门，第一输入端与所述正相移位时钟信号输入端连接，第二输入端与所述第一移位反相器的输出端连接；以及，
    第二移位反相器，输入端与所述移位反相端和所述与非门的输出端连接，输出端与所述移位输出端连接。
  5. 如权利要求4所述的栅极驱动子电路，其中，所述第一控制输出子电路包括：
    第一控制输出传输门，正相控制端与所述移位信号输出端连接，反相控制端与所述移位反相信号输出端连接，输入端与所述第一控制时钟信号输入端连接；
    第二控制输出传输门，正相控制端与移位反相信号输出端连接，反相控制端与所述移位信号输出端连接，输入端与所述第一使能端连接；
    第一控制输出反相器，输入端与所述第一控制输出传输门的输出端和所述第二控制输出传输门的输出端连接；以及，
    第二控制输出反相器，输入端与所述第一控制输出反相器的输出端连接，输出端与所述第一栅极驱动信号输出端连接。
  6. 如权利要求5所述的栅极驱动子电路，其中，所述第二控制输出子电 路包括：
    第三控制输出传输门，正相控制端与所述移位信号输出端连接，反相控制端与所述移位反相信号输出端连接，输入端与所述第二控制时钟信号输入端连接；
    第四控制输出传输门，正相控制端与所述移位反相信号输出端连接，反相控制端与所述移位信号输出端连接，输入端与所述反相使能端连接；
    第三控制输出反相器，输入端与所述第三控制输出传输门的输出端和所述第四控制输出传输门的输出端连接；以及、
    第四控制输出反相器，输入端与所述第三控制输出反相器的输出端连接，输出端与所述第二栅极驱动信号输出端连接。
  7. 如权利要求2或3所述的栅极驱动子电路，其中，所述电源电压信号输出电路包括：
    电源电压信号输出传输门，正相控制端与所述移位信号输出端连接，反相控制端与所述移位反相信号输出端连接，输入端与所述第二使能端连接；
    第一电源电压信号输出晶体管，栅极与所述移位信号输出端连接，第一极与所述电源电压信号输出传输门的输出端连接，第二极与所述第一电压输入端连接；
    电源电压信号输出反相器，输入端与所述电源电压信号输出传输门的输出端连接；
    第二电源电压信号输出晶体管，栅极与所述电源电压信号输出传输门的输出端连接，第一极与所述第二电压输入端连接，第二极与所述电源电压信号输出端连接；以及，
    第三电源电压信号输出晶体管，栅极与所述电源电压信号输出反相器的输出端连接，第一极与所述第一电压输入端连接，第二极与所述电源电压信号输出端连接。
  8. 如权利要求1所述的栅极驱动子电路，其中，所述栅极驱动子电路还包括输入电路；其中，所述输入电路与正向扫描控制端、反向扫描控制端、所述正相移位信号端、所述反相移位信号端和所述输入信号端连接，用于在所述正向扫描控制端和所述反向扫描控制端的控制下，控制所述正相移位信 号端或所述反相移位信号端与所述输入信号端连接。
  9. 如权利要求8所述的栅极驱动子电路，其中，所述输入电路包括正向扫描传输门和反向扫描传输门；
    所述正向扫描传输门的正相控制端与所述正向扫描控制端连接，所述正向扫描传输门的反相控制端与所述反向扫描控制端连接，所述正向扫描传输门的输入端与所述正相移位信号端连接，所述正向扫描传输门的输出端与所述输入信号端连接；以及，
    所述反向扫描传输门的正相控制端与所述反向扫描控制端连接，所述反向扫描传输门的反相控制端与所述正向扫描控制端连接，所述反向扫描传输门的输入端与所述反相移位信号端连接，所述反向扫描传输门的输出端与所述输入信号端连接。
  10. 一种栅极驱动子电路的驱动方法，应用于如权利要求1至9中任一权利要求所述的栅极驱动子电路，其中，所述栅极驱动子电路的驱动方法包括：
    移位寄存器电路在时钟信号输入端和正相使能端的控制下，根据输入信号端输入的输入信号得到移位反相信号和移位信号；所述移位反相信号与所述移位信号反相；
    第一控制输出子电路在第一控制时钟信号输入端和第一使能端的控制下，根据所述移位信号和所述移位反相信号生成第一栅极驱动信号，并通过第一栅极驱动信号输出端输出所述第一栅极驱动信号；
    第二控制输出子电路在第二控制时钟信号输入端和反相使能端的控制下，根据所述移位信号和所述移位反相信号生成第二栅极驱动信号，并通过第二栅极驱动信号输出端输出所述第二栅极驱动信号。
  11. 如权利要求10所述的栅极驱动子电路的驱动方法，还包括：电源电压信号输出电路在第二使能端的控制下根据所述移位信号生成电源电压信号，并通过电源电压信号输出端输出所述电源电压信号。
  12. 一种栅极驱动电路，包括多个级联的设置于显示面板的第一侧边的第一栅极驱动模组以及设置于所述显示面板的第二侧边的第二栅极驱动模组；
    所述第一栅极驱动模组包括多个级联的如权利要求1至9中任一权利要 求所述的栅极驱动子电路；
    所述第二栅极驱动模组包括多个级联的如权利要求1至9中任一权利要求所述的栅极驱动子电路；
    所述第一栅极驱动模组包括的栅极驱动子电路与位于奇数行的集成存储器像素单元连接，所述第二栅极驱动模组包括的栅极驱动子电路与位于偶数行的集成存储器像素单元连接。
  13. 如权利要求12所述的栅极驱动电路，其中，所述第一侧边为左侧边，所述第二侧边为右侧边；或者，所述第一侧边为右侧边，所述第二侧边为左侧边；
    第一栅极驱动模组中的移位寄存器电路包括的正相移位时钟信号输入端与正相时钟信号线连接，第一栅极驱动模组中的移位寄存器电路包括的反相移位时钟信号输入端与反相时钟信号线连接；第二栅极驱动模组中的移位寄存器电路包括的正相移位时钟信号输入端与所述反相时钟信号线连接，第二栅极驱动模组中的移位寄存器电路包括的反相移位时钟信号输入端与所述正相时钟信号线连接；
    所述栅极驱动子电路还包括正相移位信号端和反相移位信号端；所述栅极驱动子电路还包括输入电路；所述输入电路与正向扫描控制端、反向扫描控制端、所述正相移位信号端、所述反相移位信号端和所述输入信号端连接，用于在所述正向扫描控制端和所述反向扫描控制端的控制下，控制所述正相移位信号端或所述反相移位信号端与所述输入信号端连接；
    在所述第一栅极驱动模组和所述第二栅极驱动模组中，除了第一级栅极驱动子电路之外，一级所述栅极驱动子电路的正相移位信号端与相邻上一级所述栅极驱动子电路的移位信号输出端连接；除了最后一级栅极驱动子电路之外，一级所述栅极驱动子电路的反相移位信号端与相邻下一级所述栅极驱动子电路的移位信号输出端连接。
  14. 如权利要求12或13所述的栅极驱动电路，其中，所述栅极驱动子电路包括M个电源电压信号输出端；M为正整数。
  15. 如权利要求14所述的栅极驱动电路，其中，M等于1；所述第一栅极驱动模组包括的第n级栅极驱动子电路包括的电源电压信号输出端用于为 位于第2n行的集成存储器像素单元提供电源电压信号；所述第二栅极驱动模组包括的第n级栅极驱动子电路包括的电源电压信号输出端用于为位于第2n-1行的集成存储器像素单元提供电源电压信号；n为正整数。
  16. 如权利要求14所述的栅极驱动电路，其中，M等于2，所述第一栅极驱动模组包括的第n级栅极驱动子电路包括的第一电源电压信号输出端用于为位于4n-2行的集成存储器像素单元提供电源电压信号；所述第一栅极驱动模组包括的第n级栅极驱动子电路包括的第二电源电压信号输出端用于为位于4n行的集成存储器像素单元提供电源电压信号；所述第二栅极驱动模组包括的第一级栅极驱动子电路包括的电源电压信号输出端用于为位于4n-3行的集成存储器像素单元提供电源电压信号；所述第二栅极驱动模组包括的第二级栅极驱动子电路包括的电源电压信号输出端用于为位于4n-1行的集成存储器像素单元提供电源电压信号；
    n为正整数。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112927644A (zh) * 2021-02-02 2021-06-08 合肥维信诺科技有限公司 栅极驱动电路和显示面板

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107767809B (zh) * 2017-11-15 2019-11-26 鄂尔多斯市源盛光电有限责任公司 栅极驱动单元、驱动方法和栅极驱动电路
CN108109667B (zh) 2017-12-15 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示装置、驱动方法
WO2020199124A1 (zh) * 2019-04-02 2020-10-08 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法以及栅极驱动电路、显示装置
CN110751929B (zh) * 2019-11-29 2022-12-02 厦门天马微电子有限公司 一种显示面板及显示装置
CN110930927A (zh) * 2019-12-09 2020-03-27 厦门天马微电子有限公司 显示面板和显示装置
CN110930928B (zh) 2019-12-13 2021-09-21 京东方科技集团股份有限公司 像素电路、显示面板、显示装置及驱动方法
CN111276177B (zh) * 2020-02-21 2022-05-03 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN111627372B (zh) * 2020-06-30 2022-07-26 武汉天马微电子有限公司 一种移位寄存器及其电路、显示面板和电子设备
CN112071252B (zh) * 2020-09-15 2022-11-04 昆山龙腾光电股份有限公司 源极驱动电路与显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101093649A (zh) * 2006-06-22 2007-12-26 三星电子株式会社 液晶显示装置及其驱动方法
CN101295481A (zh) * 2007-04-27 2008-10-29 三星电子株式会社 栅极驱动电路和具有该栅极驱动电路的液晶显示器
US20110273408A1 (en) * 2010-05-07 2011-11-10 Ra Dong-Gyun Gate driving circuit and organic electroluminescent display apparatus using the same
JP2012083599A (ja) * 2010-10-13 2012-04-26 Funai Electric Co Ltd 液晶表示装置
CN105741732A (zh) * 2014-12-31 2016-07-06 乐金显示有限公司 栅极驱动器、具有栅极驱动器的显示装置及其驱动方法
CN107767809A (zh) * 2017-11-15 2018-03-06 鄂尔多斯市源盛光电有限责任公司 栅极驱动单元、驱动方法和栅极驱动电路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137081B (zh) * 2011-11-22 2014-12-10 上海天马微电子有限公司 一种显示面板栅驱动电路及显示屏
CN104966480B (zh) * 2015-07-21 2017-08-25 京东方科技集团股份有限公司 阵列基板行驱动电路单元、驱动电路和显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101093649A (zh) * 2006-06-22 2007-12-26 三星电子株式会社 液晶显示装置及其驱动方法
CN101295481A (zh) * 2007-04-27 2008-10-29 三星电子株式会社 栅极驱动电路和具有该栅极驱动电路的液晶显示器
US20110273408A1 (en) * 2010-05-07 2011-11-10 Ra Dong-Gyun Gate driving circuit and organic electroluminescent display apparatus using the same
JP2012083599A (ja) * 2010-10-13 2012-04-26 Funai Electric Co Ltd 液晶表示装置
CN105741732A (zh) * 2014-12-31 2016-07-06 乐金显示有限公司 栅极驱动器、具有栅极驱动器的显示装置及其驱动方法
CN107767809A (zh) * 2017-11-15 2018-03-06 鄂尔多斯市源盛光电有限责任公司 栅极驱动单元、驱动方法和栅极驱动电路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112927644A (zh) * 2021-02-02 2021-06-08 合肥维信诺科技有限公司 栅极驱动电路和显示面板

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