WO2019095731A1 - 异质结太阳能电池及其制备方法 - Google Patents

异质结太阳能电池及其制备方法 Download PDF

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WO2019095731A1
WO2019095731A1 PCT/CN2018/099038 CN2018099038W WO2019095731A1 WO 2019095731 A1 WO2019095731 A1 WO 2019095731A1 CN 2018099038 W CN2018099038 W CN 2018099038W WO 2019095731 A1 WO2019095731 A1 WO 2019095731A1
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layer
conductive film
transparent conductive
thin
silver
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PCT/CN2018/099038
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English (en)
French (fr)
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王进
彭福国
胡德政
徐希翔
李沅民
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君泰创新（北京）科技有限公司
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Priority to CN201880001489.0A priority Critical patent/CN110168750A/zh
Priority to CA3013818A priority patent/CA3013818A1/en
Priority to EP18188531.0A priority patent/EP3486953A1/en
Publication of WO2019095731A1 publication Critical patent/WO2019095731A1/zh

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    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
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    • H01L31/022491—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers composed of a thin transparent metal layer, e.g. gold
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    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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    • H01L31/1884—Manufacture of transparent electrodes, e.g. TCO, ITO
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    • H01L31/1884—Manufacture of transparent electrodes, e.g. TCO, ITO
    • H01L31/1888—Manufacture of transparent electrodes, e.g. TCO, ITO methods for etching transparent electrodes
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • the present application relates to, but is not limited to, the field of solar cell technology, and in particular, but not limited to, a heterojunction solar cell and a method of fabricating the same.
  • the slurry used for screen printing is a low-temperature silver paste.
  • the low-temperature silver paste has a low welding tensile force, generally 1 N/cm or even lower.
  • the welding tension is very important for the preparation of the components and the reliability of the later components. The risk of low welding tension is: first, the battery can not be made into components; second, even if it is barely made into components, it may not be reliable through the components. Sex test.
  • the present application provides a heterojunction solar cell and a preparation method thereof, which increase the welding tension of the low-temperature silver paste main grid line and improve the yield and reliability of the solar photovoltaic module.
  • the embodiment of the present application provides a method for preparing a heterojunction solar cell, the method comprising the steps of: sequentially forming an intrinsic layer on at least one side of a crystalline silicon substrate, forming a doped silicon layer, and forming a transparent conductive film layer. a step of forming a thin metal layer and forming an electrode layer.
  • the embodiment of the present application further provides a heterojunction solar cell, the heterojunction solar cell comprising: an intrinsic layer, a doped silicon layer, a transparent conductive film layer, which are sequentially disposed on at least one side of the crystalline silicon substrate, Thin metal layer and electrode layer.
  • a main gate line electrode is formed by screen printing on each of the two thin silver layers.
  • the embodiment of the present application further provides a heterojunction solar cell, the heterojunction solar cell comprising:
  • An intrinsic amorphous silicon layer disposed on the front and back sides of the crystalline silicon substrate;
  • An N-type amorphous silicon layer disposed on the intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate;
  • a transparent conductive film layer disposed on the N-type amorphous silicon layer and the P-type amorphous silicon layer;
  • a main gate line electrode is disposed on the two of the silver thin layers.
  • FIG. 1 is a flow chart of a method for preparing a heterojunction solar cell according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a heterojunction solar cell according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a heterojunction solar cell according to another embodiment of the present application.
  • the embodiment of the present application provides a method for preparing a heterojunction solar cell, and the method may include the steps of sequentially forming an intrinsic layer on at least one side of a crystalline silicon substrate, forming a doped silicon layer, and forming a transparent conductive film. a step of forming a thin metal layer and forming an electrode layer.
  • the thin metal layer may be selected from at least one of a thin layer of silver, a thin layer of silver aluminum, and a thin layer of nickel vanadium.
  • the thin metal layer may have a thickness ranging from 10 nm to 200 nm.
  • the electrode layer may further include a fine gate line electrode in which the fine gate line electrode is formed.
  • the doping types of the two doped silicon layers are different.
  • the step of forming the thin metal layer on the transparent conductive film layer may include:
  • the thin metal layer is deposited on a main gate region on the transparent conductive film layer.
  • the step of forming the thin metal layer on the transparent conductive film layer may include:
  • Coating the transparent conductive film layer with a photoresist exposing the main gate region on the transparent conductive film layer by photolithography; depositing the metal thin layer in the main gate region; removing the transparent conductive film layer A photoresist on the non-main gate region.
  • the step may include:
  • a thin metal layer is deposited on the transparent conductive film layer on the front and back sides of the crystalline silicon substrate.
  • the thin metal layer may be deposited by physical vapor deposition.
  • the physical vapor deposition method may be a magnetron sputtering method
  • the sputtering power may be 1 W/cm 2 to 10 W/cm 2
  • the sputtering pressure may be 0.1 Pa to 0.5 Pa
  • the sputtering gas may be It can be argon.
  • the magnetron sputtering method may have a sputtering power of 2.5 W/cm 2 , a sputtering pressure of 0.2 Pa, and a sputtering gas of argon.
  • the forming the main gate line electrode on the thin metal layer may include forming the main gate line electrode by screen printing on the thin metal layer.
  • a main gate line electrode of the electrode layer is formed on the thin metal layer, and the electrode layer is formed in a non-main gate region of the transparent conductive film layer where the metal thin layer is located
  • the steps of the fine grid line electrode may include:
  • the electrode layer is formed by screen printing in synchronization with a non-main gate region of the transparent conductive film layer where the metal thin layer is located. Fine grid line electrode.
  • the metal layer may be selected from at least one of a silver layer, a silver aluminum layer, and a nickel vanadium layer.
  • the method may further include: before the intrinsic layer is formed on the front and back sides of the crystalline silicon substrate,
  • the crystalline silicon substrate after the texturing process is cleaned.
  • the method may further include: after forming a thin metal layer on the transparent conductive film layer of at least one side, before forming the main gate line electrode of the electrode layer on the thin metal layer, the repairing station A thin layer of metal.
  • the step of repairing the thin metal layer may include repairing the thin metal layer by annealing.
  • the step of repairing the thin metal layer may include repairing the thin metal layer with an anneal of no more than 200 °C.
  • the intrinsic layer may be an intrinsic amorphous silicon layer.
  • the doped silicon layer may be an N-type doped silicon layer or a P-type doped silicon layer as long as the doping silicon layers of the front and back sides of the crystalline silicon substrate have different doping types. That is, the doped silicon layer on one side is an N-type doped silicon layer, and the doped silicon layer on the other side is a P-type doped silicon layer.
  • the doped silicon layer may be an amorphous silicon doped silicon layer or a microcrystalline silicon doped layer.
  • the thin metal layer may be selected from at least one of a thin layer of silver, a thin layer of silver aluminum, and a thin layer of nickel vanadium.
  • the thin metal layer may have a thickness ranging from 10 nm to 200 nm.
  • the transparent conductive film layer may include a main gate region and a non-main gate region, and the metal thin layer may be disposed on the main gate region; the electrode layer may include a main gate line electrode, The main gate line electrode is disposed on the thin metal layer.
  • the number of the main gate line electrodes may be 2 to 6.
  • the electrode layer may further include a fine gate line electrode, and the fine gate line electrode may be disposed on the non-primary gate region.
  • the diameter of the fine gate line electrode may range from 20 ⁇ m to 60 ⁇ m.
  • the heterojunction solar cell may include:
  • An intrinsic layer disposed on the front and back sides of the crystalline silicon substrate
  • a thin metal layer disposed on at least one side of the transparent conductive film layer
  • the main gate line electrode disposed on the thin metal layer; or the main gate line electrode disposed on the thin metal layer, and the transparent conductive film layer disposed on the thin metal layer The fine grid line electrode on the non-main gate region;
  • the heterojunction solar cell may further include a metal layer or an electrode layer disposed on the transparent conductive film layer not provided with a thin metal layer;
  • the doping types of the two doped silicon layers are different.
  • the metal layer may be selected from at least one of a silver layer, a silver aluminum layer, and a nickel vanadium layer.
  • the heterojunction solar cell when the heterojunction solar cell further includes a metal layer disposed on a transparent conductive film layer not provided with a thin metal layer, the metal layer may be disposed over the entire transparent conductive film layer On the surface.
  • the crystalline silicon substrate may have a thickness ranging from 100 ⁇ m to 250 ⁇ m.
  • the intrinsic layer may have a thickness ranging from 1 nm to 20 nm.
  • the doped silicon layer may be an amorphous silicon doped silicon layer or a microcrystalline silicon doped layer.
  • the intrinsic layer may be an intrinsic amorphous silicon layer.
  • a main gate line electrode is formed by screen printing on each of the two thin silver layers.
  • the step of depositing a thin layer of silver on each of the two transparent conductive film layers may include:
  • the silver thin layer is deposited on a main gate region on the transparent conductive film layer.
  • the method may further include: depositing a first intrinsic amorphous silicon layer on a front side of the crystalline silicon substrate, and depositing a second intrinsic amorphous silicon layer on a back side of the crystalline silicon substrate; Or depositing the first intrinsic amorphous silicon layer on the back side of the crystalline silicon substrate, before depositing the second intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate,
  • the crystalline silicon substrate after the texturing process is cleaned.
  • the thin silver layer may be deposited by physical vapor deposition.
  • the thin silver layer may be deposited by magnetron sputtering, the sputtering power may be 2.5 W/cm 2 , the sputtering pressure may be 0.2 Pa, and the sputtering gas may be argon.
  • the method may further include: after depositing a thin layer of silver on the transparent conductive film layers on the front and back sides of the crystalline silicon substrate, respectively
  • the thin silver layer is repaired by low temperature thermal implantation or low temperature light injection annealing.
  • the embodiment of the present application further provides a heterojunction solar cell, and the heterojunction solar cell may include:
  • a P-type amorphous silicon layer disposed on the intrinsic amorphous silicon layer on the back side of the crystalline silicon substrate;
  • a transparent conductive film layer disposed on the N-type amorphous silicon layer and the P-type amorphous silicon layer;
  • a main gate line electrode is disposed on the two of the silver thin layers.
  • the thin layer of silver may have a thickness ranging from 10 nm to 200 nm.
  • the crystalline silicon substrate may have a thickness ranging from 100 ⁇ m to 250 ⁇ m.
  • the intrinsic amorphous silicon layer may have a thickness ranging from 1 nm to 20 nm.
  • the N-type amorphous silicon layer may have a thickness ranging from 1 nm to 20 nm.
  • the P-type amorphous silicon layer may have a thickness ranging from 1 nm to 20 nm.
  • the heterojunction solar cell and the preparation method thereof provided by the embodiments of the present application, by depositing a thin metal layer between the transparent conductive film layer and the main gate electrode, and making a thin metal layer through the action of the resin in the metal paste It is solidified together with the main grid electrode, thereby enhancing the welding tension of the main grid electrode and improving the reliability of the solar photovoltaic module.
  • S100 depositing a first intrinsic layer on a front side of the crystalline silicon substrate, depositing a second intrinsic layer on a back side of the crystalline silicon substrate; or depositing the first intrinsic layer on a back side of the crystalline silicon substrate, The second intrinsic layer is deposited on a front side of the crystalline silicon substrate.
  • a thicker intrinsic layer may cause an increase in the series resistance of the solar cell, while blocking the transmission of sunlight, resulting in deterioration of the short-circuit current and overall efficiency; while a thinner intrinsic layer may weaken the built-in electric field, resulting in an open circuit The voltage is deteriorating. Therefore, the thickness of the intrinsic layer can be appropriately controlled.
  • the thickness value of the first intrinsic layer may be 12 nm
  • the thickness value of the second intrinsic layer may be 12 nm
  • the intrinsic layer of the thickness is relative to Other thicknesses of the intrinsic layer are more conducive to improving the performance of the heterojunction solar cell.
  • S200 depositing an N-type doped silicon layer on the first intrinsic layer and depositing a P-type doped silicon layer on the second intrinsic layer.
  • an N-type doped silicon layer may be deposited on the first intrinsic layer by a PECVD technique, and a P-type doped silicon layer may be deposited on the second intrinsic layer, wherein the N-type doped silicon layer
  • the thickness range may be from 1 nm to 20 nm.
  • the thickness of the N-type doped silicon layer may be 4 nm, 6 nm, 8 nm, 10 nm, 12 nm, 15 nm, and 18 nm, and the thickness range of the P-type doped silicon layer may also be 1 nm.
  • the P-type doped silicon layer may have a thickness value of 4 nm, 6 nm, 8 nm, 10 nm, 12 nm, 15 nm, and 18 nm. If the thickness of the N-type doped silicon layer is too large, it may bring about an increase in the series resistance of the solar cell, and hinder the transmission of sunlight, resulting in deterioration of the short-circuit current and overall efficiency; if the thickness of the N-type doped silicon layer is excessive Small, may not be able to form a built-in electric field of sufficient strength, resulting in deterioration of the open circuit voltage.
  • the N-type doped silicon layer may have a thickness value of 10 nm
  • the P-type doped silicon layer may have a thickness value of 10 nm.
  • S300 depositing a transparent conductive film layer on the surface of the N-type doped silicon layer and the surface of the P-type doped silicon layer, for example, magnetron sputtering technology on the surface of the N-type doped silicon layer and The surface of the P-type doped silicon layer is respectively plated with a transparent conductive film layer; wherein the thickness of the transparent conductive film layer may range from 50 nm to 150 nm, for example, the thickness of the transparent conductive film layer may be 60 nm, 80 nm, 1000 nm, 120 nm. , 140nm.
  • a thin layer of silver can be deposited by magnetron sputtering in a PVD process, and the sputtering power can be from 1 W/cm 2 to 10 W/ Cm 2 , the sputtering pressure may be 0.1 Pa to 0.5 Pa, the sputtering gas may be argon gas, in an exemplary embodiment, the sputtering power may be 2.5 W/cm 2 , the sputtering pressure may be 0.2 Pa, sputtering The gas can be a high purity argon gas, whereby high speed deposition of a thin layer of silver can be achieved at lower temperature conditions.
  • a slight interface plasma damage may be caused during the sputtering of the thin layer of silver, and in order to repair the damage, the method may further include after step S400:
  • S410 repairing the thin silver layer by low temperature heat injection or low temperature light injection annealing.
  • the annealing temperature does not exceed 200 ° C and may be 150 ° C.
  • the thickness of the silver thin layer may range from 10 nm to 200 nm.
  • the thickness of the thin layer of silver may be 30 nm, 50 nm, 70 nm, 90 nm, 110 m, 130 nm, 150 nm, 190 nm.
  • the thickness of the silver thin layer may be 110 nm.
  • the transparent conductive film layer may be a metal oxide, and the thin silver layer may be a pure metal. Therefore, after the thin silver layer is deposited on the transparent conductive film layer, the contact resistance generated at the interface is negligible.
  • the method may further include: after step S500:
  • a fine gate line electrode on a non-main gate region on the transparent conductive film layer on the front and back surfaces of the crystalline silicon substrate.
  • a fine grid line electrode can be formed by screen printing.
  • S402' depositing the thin layer of silver in the main gate region.
  • the incident light can be reflected on the surface of the crystalline silicon substrate, and the sunlight that is irradiated onto the surface of the solar cell cannot be fully utilized. Therefore, the light trapping structure may be important for the heterojunction solar cell, and the napping process is performed.
  • the crystalline silicon substrate can form a random pyramid-like structure on its surface, thereby improving the utilization of sunlight.
  • the main gate electrode is strengthened by depositing a thin layer of silver between the transparent conductive film layer and the main gate electrode and by solidifying the silver thin layer and the main gate electrode through the action of the resin in the silver paste.
  • the welding tension increases the reliability of the solar photovoltaic module.
  • other thin metal layers may be used instead of the thin silver layer, for example, at least one of a thin layer of silver and aluminum and a thin layer of nickel vanadium, and a thin layer of silver and a thin layer of silver and aluminum may be used. a composite thin layer of at least one of the thin layers of nickel vanadium.
  • the welding tension of the main grid line electrode can also be enhanced, and the reliability of the solar photovoltaic module can be improved.
  • the thin metal layer may have a thickness ranging from 10 nm to 200 nm.
  • a thin metal layer may be deposited only on the transparent conductive film layer on one side of the crystalline silicon substrate, that is, a thin metal layer is deposited on the transparent conductive film layer on the front or back side of the crystalline silicon substrate.
  • the welding tension of the main grid line electrode can also be enhanced, and the reliability of the solar photovoltaic module can be improved.
  • the main gate line electrode may be directly formed on the transparent conductive film layer on the back surface of the crystalline silicon substrate as an electrode layer or formed by the main gate line
  • the metal layer may be selected from at least one of a silver layer, a silver aluminum layer, and a nickel vanadium layer.
  • the main gate line electrode may be directly formed as an electrode layer or formed by the main gate line on the transparent conductive film layer on the front surface of the crystalline silicon substrate.
  • the embodiment of the present application further provides a heterojunction solar cell, which can be obtained by using a method for preparing a heterojunction solar cell according to any embodiment of the present application, the heterojunction solar cell including crystalline silicon.
  • the substrate 100, the intrinsic layer 200 disposed on the front and back surfaces of the crystalline silicon substrate 100, the N-type doped silicon layer 300 disposed on the intrinsic layer 200 on the front side of the crystalline silicon substrate 100, and the crystalline silicon substrate 100 are disposed.
  • a P-type doped silicon layer 400 on the intrinsic layer 200 on the back side a transparent conductive film layer 500 disposed on the N-type doped silicon layer 300 and the P-type doped silicon layer 400, disposed on the front side of the crystalline silicon substrate 100 and A thin silver layer 600 on the transparent conductive film layer 500 on the back side and a main gate line electrode 700 on the silver thin layer 600 on the front and back sides of the crystalline silicon substrate 100.
  • the transparent conductive film layer may be indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), or the like; the intrinsic layer may be an intrinsic amorphous silicon layer; the N-type doped silicon layer may be The N-type amorphous silicon doped silicon layer, and the P-type doped silicon layer may be a P-type amorphous silicon doped silicon layer.
  • ITO indium tin oxide
  • AZO aluminum-doped zinc oxide
  • the intrinsic layer may be an intrinsic amorphous silicon layer
  • the N-type doped silicon layer may be The N-type amorphous silicon doped silicon layer
  • the P-type doped silicon layer may be a P-type amorphous silicon doped silicon layer.
  • a thin layer of silver 600 is deposited between the transparent conductive film layer 500 and the main gate line electrode 700, and the main gate line electrode 700 and the silver thin layer 600 may be formed during the process of forming the main gate line electrode 700 by screen printing. Curing together, because the thin layer of silver is pure metal, and the material of the main gate electrode is mainly silver, and after the main gate electrode is formed by screen printing, the silver gate line formed by screen printing is subjected to a drying process.
  • Electrode drying and the general drying process is to place the screen printed battery sheet in the drying furnace, and use the hot air of the drying oven to dry and solidify the silver grid electrode on the battery sheet, and screen printing
  • the solvent is added to the silver paste to improve the flowability of the silver paste, so that during the drying process, the solvent is evaporated, and the resin in the silver paste is crosslinked, thereby curing the main grid electrode and the silver thin layer.
  • the main gate line is better in ohmic contact with the cell, and the resistance is smaller, thereby increasing the output power of the cell.
  • the material of the transparent conductive film layer may be a metal oxide, and the thin layer of silver is a pure metal.
  • the welding strength of the thin layer of silver and the transparent conductive film layer is relatively large, and both The ohmic contact is good, the contact resistance is small, and even negligible.
  • the thickness of the silver thin layer 600 may range from 10 nm to 200 nm.
  • the thickness of the silver thin layer 600 may be 30 nm, 50 nm, 70 nm, 90 nm, 110 m, 130 nm, 150 nm, 190 nm.
  • the thickness of the silver thin layer 600 may be 110 nm. .
  • the thickness of the crystalline silicon substrate 100 may range from 100 ⁇ m to 250 ⁇ m.
  • the thickness of the crystalline silicon substrate 100 may be 120 ⁇ m, 140 ⁇ m, 160 ⁇ m, 180 ⁇ m, 200 ⁇ m, 220 ⁇ m, 240 ⁇ m.
  • the intrinsic layer 200 may have a thickness value of from 1 nm to 20 nm; for example, the intrinsic layer 200 may have a thickness value of 4 nm, 8 nm, 12 nm, 15 nm, and 18 nm.
  • the thicker intrinsic layer 200 may bring about an increase in the series resistance of the solar cell, while blocking the transmission of sunlight, resulting in deterioration of the short circuit current and overall efficiency; while the thinner intrinsic layer 200 may weaken the built-in electric field, Causes the deterioration of the open circuit voltage. Therefore, the thickness of the intrinsic layer 200 can be appropriately controlled.
  • the thickness of the intrinsic layer 200 can be 12 nm, and the intrinsic layer 200 of the thickness is more advantageous for improving the intrinsic layer 200 than other thicknesses.
  • the properties of the solar cell are consolidated.
  • the thickness of the N-type doped silicon layer 300 may range from 1 nm to 20 nm; for example, the thickness of the N-type doped silicon layer 300 may be 4 nm, 6 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm. If the thickness of the N-type doped silicon layer 300 is too large, it may bring an increase in the series resistance of the solar cell, and hinder the transmission of sunlight, resulting in deterioration of the short-circuit current and overall efficiency; if the N-type doped silicon layer 300 If the thickness is too small, a built-in electric field having sufficient strength may not be formed, resulting in deterioration of the open circuit voltage. Therefore, in an exemplary embodiment, the N-type doped silicon layer 300 may have a thickness value of 10 nm.
  • the thickness of the P-type doped silicon layer 400 may range from 1 nm to 20 nm, and the thickness of the P-type doped silicon layer 400 may be 4 nm, 6 nm, 8 nm, 10 nm, 12 nm, 15 nm, and 18 nm, in order to ensure the transparency of sunlight. At the same time, a built-in electric field having sufficient strength can be formed, and the thickness of the P-type doped silicon layer 400 can be 10 nm.
  • the thickness of the transparent conductive film layer 500 may range from 50 nm to 150 nm.
  • the thickness of the transparent conductive film layer 500 may be 60 nm, 80 nm, 100 nm, 120 nm, and 140 nm.
  • the transparent conductive film layer 500 may be provided with a fine grid line electrode for collecting electrons or holes generated by photoexcitation, and transmitting the collected electrons or holes to the main gate line electrode, the fine grid line electrode There may be a plurality of strips, and the plurality of fine grid line electrodes have a uniform, dense distribution on the transparent conductive film layer 500.
  • the diameter of the fine grid line electrode may range from 20 ⁇ m to 60 ⁇ m, and in order to increase the distribution density of the fine grid line electrode, the output current is increased, and the connection strength between the fine gate line electrode and the transparent conductive film layer 500 is ensured.
  • the fine grid line electrode may have a diameter of 35 ⁇ m.
  • the fine gate line electrode is electrically connected to the main gate line electrode, and the number of the main gate line electrodes may be two to six, and in order to avoid waste of the silver paste, and enhance the bonding strength between the main gate line electrode and the fine grid line electrode,
  • the number of main gate line electrodes can be four.
  • the silver thin layer 600 may be disposed only on the transparent conductive film layer 500 on the front or back side of the crystalline silicon substrate 100, and the silver thin layer 600 is provided with the main gate line electrode 700.
  • the main gate electrode may be directly disposed on the transparent conductive film layer 500 on the back surface of the crystalline silicon substrate 100 as an electrode layer or disposed by the main An electrode layer composed of a gate line electrode and a fine grid line electrode, in this case, a double-sided heterojunction solar cell is obtained, the structure of which is shown in FIG. 3; and the entire transparent conductive film layer 500 on the back surface of the crystalline silicon substrate 100 is also A metal layer can be provided, in which case a single-sided heterojunction solar cell is obtained.
  • the metal layer may be selected from at least one of a silver layer, a silver aluminum layer, and a nickel vanadium layer.
  • the main gate electrode can be directly disposed as an electrode layer or disposed on the transparent conductive film layer 500 on the front surface of the crystalline silicon substrate 100.
  • other thin metal layers may be used instead of the thin silver layer, for example, at least one of a thin layer of silver and aluminum and a thin layer of nickel vanadium, and a thin layer of silver and a thin layer of silver and aluminum may be used. a composite thin layer of at least one of the thin layers of nickel vanadium.
  • the welding tension of the main grid line electrode can also be enhanced, and the reliability of the solar photovoltaic module can be improved.
  • the thin metal layer may have a thickness ranging from 10 nm to 200 nm.
  • the heterojunction solar cell and the preparation method thereof provided by the embodiments of the present application, by depositing a thin metal layer between the transparent conductive film layer and the main gate electrode, and making a thin metal layer through the action of the resin in the metal paste It is solidified together with the main grid electrode, thereby enhancing the welding tension of the main grid electrode and improving the reliability of the solar photovoltaic module.
  • the thin metal layer can be used to double the soldering force of the main gate electrode.
  • the DH (double 85) test and the TC (cold heat cycle) test were performed on the heterojunction solar cell of the embodiment of the present application, and the power loss of the component was measured to be reduced by 50%.

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Abstract

一种异质结太阳能电池的制备方法，包括：在晶硅衬底的至少一面上依次形成本征层、形成掺杂硅层、形成透明导电膜层、形成金属薄层和形成电极层。还提供了一种异质结太阳能电池。

Description

异质结太阳能电池及其制备方法
本申请主张申请日为2017年11月15日，在中国提交的申请号为201711132081.0的专利申请的优先权，其全部内容都引用在本申请中。
技术领域
本申请涉及但不限于太阳能电池技术领域，尤其涉及但不限于一种异质结太阳能电池及其制备方法。
背景技术
异质结太阳能电池具有高效率、低温度系数、无光致衰减(Light Induced Degradation，LID)和电势诱发衰减(Potential Induced Degradation，PID)效应、可双面发电以及成本下降空间大等优点，被视为下一代可量产的高效电池之一。
对于异质结太阳能电池的加工，由于其工艺温度要求低于200℃，所以其丝网印刷用到的浆料为低温银浆料。但是，低温银浆料的焊接拉力较低，一般为1N/cm，甚至更低。而焊接拉力对组件的制备及后期组件的可靠性非常重要，焊接拉力偏低带来的风险是：第一，电池无法做成组件；第二，即便勉强做成组件，也可能无法通过组件可靠性测试。
当前常用的改善异质结太阳能电池低温银浆料焊接拉力的方法如下：
1、增加低温银浆料中树脂的含量，但这样做的缺点是银含量会随之降低，导致浆料体电阻增大，做成电池后，电池填充因子会降低；
2、设计尺寸较大的丝印网版，以增加主栅线的宽度，但这样做的缺点是增大了遮光面积，电池的短路电流会降低，且浆料的用量会增大，成本增加；
3、调整丝印网版的设计尺寸或调整印刷工艺，以增加主栅线的高度，这样做的缺点是增大了浆料的用量，导致成本增加，且有可能造成印刷质量不良。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
针对现有技术中的问题，本申请提供了一种异质结太阳能电池及其制备方法，增大了低温银浆料主栅线的焊接拉力，提升了太阳能光伏组件的良率和可靠性。
本申请实施例提供了一种异质结太阳能电池的制备方法，所述方法包括如下步骤：在晶硅衬底的至少一面上依次形成本征层、形成掺杂硅层、形成透明导电膜层、形成金属薄层和形成电极层的步骤。
本申请实施例还提供了一种异质结太阳能电池，所述异质结太阳能电池包括：依次设置在晶硅衬底的至少一面上的本征层、掺杂硅层、透明导电膜层、金属薄层和电极层。
本申请实施例提供了一种异质结太阳能电池的制备方法，所述方法包括如下步骤：
在晶硅衬底的正面沉积第一本征非晶硅层，在所述晶硅衬底的背面沉积第二本征非晶硅层；或者在所述晶硅衬底的背面沉积所述第一本征非晶硅层，在所述晶硅衬底的正面沉积所述第二本征非晶硅层；
在所述第一本征非晶硅层上沉积N型非晶硅层，在所述第二本征非晶硅层上沉积P型非晶硅层；
在所述N型非晶硅层的表面和所述P型非晶硅层的表面分别沉积透明导电膜层；
在两个所述透明导电膜层上分别沉积银薄层；
在两个所述银薄层上分别通过丝网印刷形成主栅线电极。
本申请实施例还提供了一种异质结太阳能电池，所述异质结太阳能电池包括：
晶硅衬底；
设置在所述晶硅衬底正面和背面的本征非晶硅层；
设置在所述晶硅衬底正面的所述本征非晶硅层上的N型非晶硅层；
设置在所述晶硅衬底背面的所述本征非晶硅层上的P非晶硅层；
设置在所述N型非晶硅层和所述P型非晶硅层上的透明导电膜层；
设置在两个所述透明导电膜层上的银薄层；
设置在两个所述银薄层上的主栅线电极。
附图概述
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本申请实施例提供的异质结太阳能电池的制备方法的流程图；
图2为本申请实施例提供的异质结太阳能电池的结构示意图。
图3为本申请另一实施例提供的异质结太阳能电池的结构示意图。
附图标记说明：
100-晶硅衬底       200-本征层         300-N型掺杂硅层
400-P型掺杂硅层    500-透明导电膜层   600-银薄层
700-主栅线电极
详述
下面结合附图详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。
本申请实施例提供了一种异质结太阳能电池的制备方法，所述方法可以包括如下步骤：在晶硅衬底的至少一面上依次形成本征层、形成掺杂硅层、形成透明导电膜层、形成金属薄层和形成电极层的步骤。
在示例性实施例中，所述金属薄层可以选自银薄层、银铝薄层和镍钒薄层中的至少一种。
在示例性实施例中，所述金属薄层的厚度范围值可以为10nm至200nm。
在示例性实施例中，可以将所述透明导电膜层划分为主栅区域和非主栅区域，在所述主栅区域上形成所述金属薄层；所述电极层可以包括主栅线电极，在所述金属薄层上形成所述主栅线电极。
在示例性实施例中，所述电极层还可以包括细栅线电极，在所述非主栅区域形成所述细栅线电极。
在示例性实施例中，所述方法可以包括如下步骤：
在晶硅衬底的正面和背面形成本征层；
在晶硅衬底的正面和背面的本征层上形成掺杂硅层；
在两个所述掺杂硅层上分别形成透明导电膜层；
在至少一面的透明导电膜层上形成金属薄层；
在所述金属薄层上形成所述主栅线电极；或者，在所述金属薄层上形成所述主栅线电极，并在所述金属薄层所在的所述透明导电膜层的非主栅区域形成所述细栅线电极；
任选地，在未形成金属薄层的透明导电膜层上形成金属层或电极层；
其中，两个所述掺杂硅层的掺杂类型不同。
在示例性实施例中，在所述透明导电膜层上形成所述金属薄层的步骤可以包括：
将所述透明导电膜层划分为主栅区域和非主栅区域；
通过掩膜版遮挡所述透明导电膜层上的非主栅区域；以及
在所述透明导电膜层上的主栅区域沉积所述金属薄层。
在示例性实施例中，在所述透明导电膜层上形成所述金属薄层的步骤可以包括：
将所述透明导电膜层划分为主栅区域和非主栅区域；
将所述透明导电膜层上涂满光刻胶，采用光刻法暴露出所述透明导电 膜层上的主栅区域；在所述主栅区域沉积所述金属薄层；除去所述透明导电膜层上的非主栅区域的光刻胶。
在示例性实施例中，当在两个所述透明导电膜层上分别形成金属薄层时，该步骤可以包括：
先在所述晶硅衬底的正面的所述透明导电膜层上沉积金属薄层，后在所述晶硅衬底的背面的所述透明导电膜层上沉积金属薄层；
或者，先在所述晶硅衬底的背面的所述透明导电膜层上沉积金属薄层，后在所述晶硅衬底的正面的所述透明导电膜层上沉积金属薄层；
或者，同时在所述晶硅衬底的正面和背面的所述透明导电膜层上沉积金属薄层。
在示例性实施例中，所述金属薄层可以采用物理气相沉积法沉积。
在示例性实施例中，所述物理气相沉积法可以为磁控溅射法，溅射功率可以为1W/cm 2至10W/cm 2，溅射压强可以为0.1Pa至0.5Pa，溅射气体可以为氩气。
在示例性实施例中，所述磁控溅射法的溅射功率可以为2.5W/cm 2，溅射压强可以为0.2Pa，溅射气体可以为氩气。
在示例性实施例中，在所述金属薄层上形成所述主栅线电极的步骤可以包括：在所述金属薄层上通过丝网印刷形成所述主栅线电极。
在示例性实施例中，在所述金属薄层上形成所述电极层的主栅线电极，并在所述金属薄层所在的所述透明导电膜层的非主栅区域形成所述电极层的细栅线电极的步骤可以包括：
在所述金属薄层上形成所述电极层的主栅线电极之后，在所述金属薄层所在的所述透明导电膜层的非主栅区域通过丝网印刷形成所述电极层的细栅线电极；
或者，在所述金属薄层所在的所述透明导电膜层的非主栅区域通过丝网印刷形成所述电极层的细栅线电极之后，在所述金属薄层上形成所述电极层的主栅线电极；
或者，在所述金属薄层上形成所述电极层的主栅线电极时，同步在所 述金属薄层所在的所述透明导电膜层的非主栅区域通过丝网印刷形成所述电极层的细栅线电极。
在示例性实施例中，所述金属层可以选自银层、银铝层和镍钒层中的至少一种。
在示例性实施例中，在透明导电膜层上形成金属层可以为在所述透明导电膜层的整个表面上形成所述金属层。
在示例性实施例中，所述方法还可以包括：在晶硅衬底的正面和背面形成本征层之前，
通过制绒工艺对所述晶硅衬底进行表面处理；
清洗经过制绒工艺后的所述晶硅衬底。
在示例性实施例中，所述方法还可以包括：在至少一面的透明导电膜层上形成金属薄层之后，在所述金属薄层上形成所述电极层的主栅线电极之前，修复所述金属薄层。
在示例性实施例中，修复所述金属薄层的步骤可以包括：采用退火方式修复所述金属薄层。
在示例性实施例中，修复所述金属薄层的步骤可以包括：采用不超过200℃的退火修复所述金属薄层。
在示例性实施例中，所述本征层可以为本征非晶硅层。
在示例性实施例中，所述掺杂硅层可以为N型掺杂硅层或P型掺杂硅层，只要所述晶硅衬底的正面和背面的掺杂硅层的掺杂类型不同即可，即一面的掺杂硅层为N型掺杂硅层，另一面的掺杂硅层为P型掺杂硅层。
在示例性实施例中，所述掺杂硅层可以为非晶硅掺杂硅层或微晶硅掺杂层。
本申请实施例还提供了一种异质结太阳能电池，所述异质结太阳能电池可以包括：依次设置在晶硅衬底的至少一面上的本征层、掺杂硅层、透明导电膜层、金属薄层和电极层。
在示例性实施例中，所述金属薄层可以选自银薄层、银铝薄层和镍钒 薄层中的至少一种。
在示例性实施例中，所述金属薄层的厚度范围值可以为10nm至200nm。
在示例性实施例中，所述透明导电膜层可以包括主栅区域和非主栅区域，所述金属薄层可以设置在所述主栅区域上；所述电极层可以包括主栅线电极，所述主栅线电极设置在所述金属薄层上。
在示例性实施例中，所述主栅线电极的数量可以为2条至6条。
在示例性实施例中，所述电极层还可以包括细栅线电极，所述细栅线电极可以设置在所述非主栅区域上。
在示例性实施例中，所述细栅线电极的直径的范围值可以为20μm至60μm。
在示例性实施例中，所述异质结太阳能电池可以包括：
设置在晶硅衬底正面和背面的本征层；
设置在所述晶硅衬底的正面和背面的本征层上的掺杂硅层；
设置在两个所述掺杂硅层上的透明导电膜层；
设置在至少一面的透明导电膜层上的金属薄层；
设置在所述金属薄层上的所述主栅线电极；或者，设置在所述金属薄层上的所述主栅线电极，以及设置在所述金属薄层所在的所述透明导电膜层的非主栅区域上的所述细栅线电极；
任选地，所述异质结太阳能电池还可以包括设置在未设置金属薄层的透明导电膜层上的金属层或电极层；
其中，两个所述掺杂硅层的掺杂类型不同。
在示例性实施例中，所述金属层可以选自银层、银铝层和镍钒层中的至少一种。
在示例性实施例中，当所述异质结太阳能电池还包括设置在未设置金属薄层的透明导电膜层上的金属层时，所述金属层可以设置在所述透明导 电膜层的整个表面上。
在示例性实施例中，所述晶硅衬底的厚度范围值可以为100μm至250μm。
在示例性实施例中，所述本征层的厚度范围值可以为1nm至20nm。
在示例性实施例中，所述掺杂硅层的厚度范围值可以为1nm至20nm。
在示例性实施例中，所述掺杂硅层可以为非晶硅掺杂硅层或微晶硅掺杂层。
在示例性实施例中，所述透明导电膜层的厚度范围值可以为50nm至150nm。
在示例性实施例中，所述本征层可以为本征非晶硅层。
本申请实施例还提供了一种异质结太阳能电池的制备方法，所述方法可以包括如下步骤：
在晶硅衬底的正面沉积第一本征非晶硅层，在所述晶硅衬底的背面沉积第二本征非晶硅层；或者在所述晶硅衬底的背面沉积所述第一本征非晶硅层，在所述晶硅衬底的正面沉积所述第二本征非晶硅层；
在所述第一本征非晶硅层上沉积N型非晶硅层，在所述第二本征非晶硅层上沉积P型非晶硅层；
在所述N型非晶硅层的表面和所述P型非晶硅层的表面分别沉积透明导电膜层；
在两个所述透明导电膜层上分别沉积银薄层；
在两个所述银薄层上分别通过丝网印刷形成主栅线电极。
在示例性实施例中，在两个所述透明导电膜层上分别沉积银薄层的步骤可以包括：
在两个所述透明导电膜层上分别通过掩膜版遮挡所述透明导电膜层上的非主栅区域；
在所述透明导电膜层上的主栅区域沉积所述银薄层。
在示例性实施例中，所述方法还可以包括：在所述晶硅衬底的正面和背面的所述透明导电膜层的非主栅区域通过丝网印刷形成细栅线电极。
在示例性实施例中，所述方法还可以包括：在晶硅衬底的正面沉积第一本征非晶硅层，在所述晶硅衬底的背面沉积第二本征非晶硅层；或者在所述晶硅衬底的背面沉积所述第一本征非晶硅层，在所述晶硅衬底的正面沉积所述第二本征非晶硅层之前，
通过制绒工艺对所述晶硅衬底进行表面处理；
清洗经过制绒工艺后的所述晶硅衬底。
在示例性实施例中，所述银薄层可以采用物理气相沉积法沉积。
在示例性实施例中，所述银薄层可以采用磁控溅射法沉积，溅射功率可以为2.5W/cm 2，溅射压强可以为0.2Pa，溅射气体可以为氩气。
在示例性实施例中，所述方法还可以包括：在所述晶硅衬底的正面和背面的所述透明导电膜层上分别沉积银薄层之后，
采用低温热注入或低温光注入退火方式修复所述银薄层。
本申请实施例还提供了一种异质结太阳能电池，所述异质结太阳能电池可以包括：
晶硅衬底；
设置在所述晶硅衬底正面和背面的本征非晶硅层；
设置在所述晶硅衬底正面的所述本征非晶硅层上的N型非晶硅层；
设置在所述晶硅衬底背面的所述本征非晶硅层上的P型非晶硅层；
设置在所述N型非晶硅层和所述P型非晶硅层上的透明导电膜层；
设置在两个所述透明导电膜层上的银薄层；
设置在两个所述银薄层上的主栅线电极。
在示例性实施例中，所述银薄层的厚度范围值可以为10nm至200nm。
在示例性实施例中，所述晶硅衬底的厚度范围值可以为100μm至250μm。
在示例性实施例中，所述本征非晶硅层的厚度范围值可以为1nm至20nm。
在示例性实施例中，所述N型非晶硅层的厚度范围值可以为1nm至20nm。
在示例性实施例中，所述P型非晶硅层的厚度范围值可以为1nm至20nm。
在示例性实施例中，所述透明导电膜层的厚度范围值可以为50nm至150nm。
在示例性实施例中，所述透明导电膜层上可以设置有细栅线电极。
在示例性实施例中，所述细栅线电极的直径的范围值可以为20μm至60μm。
在示例性实施例中，所述主栅线电极的数量可以为2条至6条。
本申请实施例提供的异质结太阳能电池及其制备方法，通过在透明导电膜层和主栅线电极之间沉积一层金属薄层，并通过金属浆料中树脂的作用，使金属薄层和主栅线电极固化在一起，从而增强了主栅线电极的焊接拉力，提升了太阳能光伏组件的可靠性。
如图1所示，本申请实施例提供了一种异质结太阳能电池的制备方法，其包括如下步骤：
S100：在晶硅衬底的正面沉积第一本征层，在晶硅衬底的背面沉积第二本征层；或者在所述晶硅衬底的背面沉积所述第一本征层，在所述晶硅衬底的正面沉积所述第二本征层。
在示例性实施例中，可以采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)技术对晶硅衬底的正面和背面分别沉积第一本征层和第二本征层；其中，晶硅衬底的厚度范围值可以为100μm至250μm，其中，晶硅衬底的厚度值可以为120μm、140μm、160μm、180μm、200μm、220μm、240μm；第一本征层的厚度范围值可以为1nm至20nm，例如，第一本征层的厚度值可以为4nm、8nm、12nm、 15nm、18nm，第二本征层的厚度范围值也可以为1nm至20nm，例如，第二本征层的厚度值可以为4nm、8nm、12nm、15nm、18nm。较厚的本征层可能会带来太阳能电池串联电阻的增加，同时阻碍太阳光的透过，导致短路电流和整体效率的恶化；而较薄的本征层可能会削弱内建电场，导致开路电压的恶化。因此，本征层的厚度可以恰当控制，在示例性实施例中，第一本征层的厚度值可以为12nm，第二本征层的厚度值可以为12nm，该厚度的本征层相对于其它厚度的本征层更有利于提高异质结太阳能电池的各项性能。
在示例性实施例中，所述第一本征层可以为本征非晶硅层，所述第二本征层可以为本征非晶硅层。
S200：在所述第一本征层上沉积N型掺杂硅层，在所述第二本征层上沉积P型掺杂硅层。
在示例性实施例中，可以采用PECVD技术在第一本征层上沉积N型掺杂硅层，在第二本征层上沉积P型掺杂硅层，其中，N型掺杂硅层的厚度范围值可以为1nm至20nm，例如，N型掺杂硅层的厚度值可以为4nm、6nm、8nm、10nm、12nm、15nm、18nm，P型掺杂硅层的厚度范围值也可以为1nm至20nm，例如，P型掺杂硅层的厚度值可以为4nm、6nm、8nm、10nm、12nm、15nm、18nm。若N型掺杂硅层的厚度过大，可能会带来太阳能电池串联电阻的增加，同时阻碍太阳光的透过，导致短路电流和整体效率的恶化；若N型掺杂硅层的厚度过小，可能不能够形成强度足够的内建电场，导致开路电压的恶化。在示例性实施例中，N型掺杂硅层的厚度值可以为10nm，P型掺杂硅层的厚度值可以为10nm。
在示例性实施例中，所述N型掺杂硅层可以为N型非晶硅掺杂硅层，所述P型掺杂硅层可以为P型非晶硅掺杂硅层。
S300：在所述N型掺杂硅层的表面和所述P型掺杂硅层的表面分别沉积透明导电膜层，例如，可以采用磁控溅射技术在N型掺杂硅层的表面和P型掺杂硅层的表面分别镀上透明导电膜层；其中，透明导电膜层的厚度范围值可以为50nm至150nm，例如，透明导电膜层的厚度值可以是60nm、80nm、1000nm、120nm、140nm。
S400：在所述晶硅衬底的正面和背面的透明导电膜层上分别沉积银薄层，其中，可以先对晶硅衬底的一面沉积银薄层，再对晶硅衬底的另一面沉积银薄层，也可以同时在晶硅衬底的正面和背面沉积银薄层。银薄层可以采用物理气相沉积(Physical Vapor Deposition，PVD)工艺进行沉积，例如，银薄层可以采用PVD工艺中的磁控溅射法沉积，其溅射功率可以为1W/cm 2至10W/cm 2，溅射压强可以为0.1Pa至0.5Pa，溅射气体可以为氩气，在示例性实施例中，溅射功率可以为2.5W/cm 2，溅射压强可以为0.2Pa，溅射气体可以为高纯度的氩气，由此可以在较低的温度条件下实现银薄层的高速沉积。
其中，溅射的材料可以为纯度为4N至5N的纯银金属靶材。
溅射银薄层过程中可能会造成轻微界面等离子体损伤，而为了修复该损伤，所述方法在步骤S400之后还可以包括：
S410：采用低温热注入或低温光注入退火方式修复所述银薄层。
为了避免退火时过高的温度对太阳能电池材料带来损伤，在示例性实施例中，退火的温度不超过200℃，可以为150℃。
其中，银薄层的厚度范围值可以为10nm至200nm，例如，银薄层的厚度值可以是30nm、50nm、70nm、90nm、110m、130nm、150nm、190nm。为了使银薄层与主栅线电极结合后具有较高的焊接强度，同时不会影响异质结太阳能电池的性能，在示例性实施例中，银薄层的厚度值可以为110nm。另外，透明导电膜层可以为金属氧化物，银薄层可以为纯金属，故银薄层沉积到透明导电膜层上后，其界面产生的接触电阻可以忽略不计。
S500：在所述晶硅衬底的正面和背面的所述银薄层上分别形成主栅线电极。例如，可以通过丝网印刷形成主栅线电极。
在示例性实施例中，所述方法在步骤S500之后还可以包括：
S600：在所述晶硅衬底的正面和背面的所述透明导电膜层上的非主栅区域形成细栅线电极。例如，可以通过丝网印刷形成细栅线电极。
在示例性实施例中，可以先进行步骤S600后进行步骤S500，也可以同步进行步骤S500和S600。
银薄层可以具有一定的孔隙率，在丝网印刷过程中，银浆料中的树脂会渗入银薄层，将银薄层和主栅线电极固化为一整体，从而增大了主栅线电极的焊接拉力；同时，银薄层具有较好的导电能力，此外不会与银浆料或透明导电膜层产生不良的物理或化学反应。其中，细栅线电极与主栅线电极导电连接，细栅线电极用来收集光激发产生的电子或空穴，并将所收集的电子或空穴传输给主栅线电极。
步骤S400可以包括：
S401：在晶硅衬底的正面和背面的透明导电膜层上分别通过掩膜版遮挡住透明导电膜层上的非主栅区域，从而可以使银薄层均沉积在主栅区域，以便在通过丝网印刷形成主栅线电极时可以保证将银薄层和主栅线电极固化为一整体。
在向透明导电膜层上沉积银薄层前，可以使用掩膜版遮挡住非主栅区域，以使银薄层均沉积至主栅区域；待银薄层沉积完成后，将掩膜版取下，再通过丝网印刷工艺沉积主栅线电极。
S402：在透明导电膜层上的主栅区域沉积银薄层。
或者，步骤S400可以包括：
S401’：将所述晶硅衬底的正面和背面的所述透明导电膜层上分别涂满光刻胶，采用光刻法暴露出所述透明导电膜层上的主栅区域。
S402’：在所述主栅区域沉积所述银薄层。
S403’：除去所述透明导电膜层上的非主栅区域的光刻胶。所述方法还可以包括：在步骤S100之前，
S10：通过制绒工艺对晶硅衬底进行表面处理。
可以理解的是，入射光线可以在晶硅衬底表面发生反射，照射到太阳能电池表面的太阳光不能被完全利用，因此，陷光结构对异质结太阳能电池可能是重要的，经过制绒工艺的晶硅衬底在其表面可以形成随机金字塔状结构，由此可以提高对太阳光的利用率。
S20：清洗经过制绒工艺后的晶硅衬底，以去除晶硅衬底表面的颗粒及金属玷污。
通过在透明导电膜层和主栅线电极之间沉积一层银薄层，并通过银浆料中树脂的作用，使银薄层和主栅线电极固化在一起，从而增强了主栅线电极的焊接拉力，提升了太阳能光伏组件的可靠性。
在本申请提供的其他实施例中，可以采用其他金属薄层代替银薄层，例如，银铝薄层和镍钒薄层中的至少一种，还可以采用银薄层与银铝薄层和镍钒薄层中的至少一种的复合薄层。这种情况下也可以增强主栅线电极的焊接拉力，提升太阳能光伏组件的可靠性。
在示例性实施例中，所述金属薄层的厚度范围值可以为10nm至200nm。
在本申请提供的其他实施例中，可以仅在晶硅衬底的一面的透明导电膜层上沉积金属薄层，即在晶硅衬底的正面或背面的透明导电膜层上沉积金属薄层。这种情况下也可以增强主栅线电极的焊接拉力，提升太阳能光伏组件的可靠性。
当仅在晶硅衬底的正面的透明导电膜层上沉积金属薄层时，可以在晶硅衬底的背面的透明导电膜层上直接形成主栅线电极作为电极层或形成由主栅线电极和细栅线电极组成的电极层，此时得到的是双面的异质结太阳能电池；也可以在晶硅衬底的背面的透明导电膜层的整个表面上沉积金属层，此时得到的是单面的异质结太阳能电池。所述金属层可以选自银层、银铝层和镍钒层中的至少一种。
当仅在晶硅衬底的背面的透明导电膜层上沉积金属薄层时，可以在晶硅衬底的正面的透明导电膜层上直接形成主栅线电极作为电极层或形成由主栅线电极和细栅线电极组成的电极层，此时得到的是双面的异质结太阳能电池。
如图2所示，本申请实施例还提供了一种异质结太阳能电池，其可以采用本申请任意实施例提供的异质结太阳能电池的制备方法得到，该异质结太阳能电池包括晶硅衬底100、设置在晶硅衬底100正面和背面的本征层200、设置在晶硅衬底100正面的本征层200上的N型掺杂硅层300、设置在晶硅衬底100背面的本征层200上的P型掺杂硅层400、设置在N 型掺杂硅层300和P型掺杂硅层400上的透明导电膜层500、设置在晶硅衬底100正面和背面的透明导电膜层500上的银薄层600以及设置在晶硅衬底100正面和背面的银薄层600上的主栅线电极700。
所述透明导电膜层可以为氧化铟锡(ITO)、铝掺杂的氧化锌(AZO)等；所述本征层可以为本征非晶硅层；所述N型掺杂硅层可以为N型非晶硅掺杂硅层，所述P型掺杂硅层可以为P型非晶硅掺杂硅层。
其中，在透明导电膜层500和主栅线电极700之间沉积一层银薄层600，可以在通过丝网印刷形成主栅线电极700过程中，使主栅线电极700与银薄层600固化在一起，因为银薄层为纯金属，而主栅线电极的材料主要为银，且在丝网印刷形成主栅线电极后，要经过烘干工艺，将丝网印刷形成的银栅线电极烘干，而一般的烘干工艺，是将丝网印刷后的电池片放置在烘干炉内，利用烘干炉的热空气使得银栅线电极烘干固化在电池片上，且丝网印刷的银浆中添加了溶剂，提高了银浆的可流动性，从而在烘干过程中，溶剂被蒸发，同时银浆中的树脂发生交联，从而使得主栅线电极与银薄层固化效果更好，主栅线与电池片欧姆接触更好，电阻更小，从而增加了电池片的输出功率。
透明导电膜层其材料可以为金属氧化物，而银薄层为纯金属，银薄层设置在透明导电膜层上时，使得银薄层与透明导电膜层焊接结合力较大，且两者欧姆接触较好，接触电阻较小，甚至可以忽略不计。
从而增强了主栅线电极700的焊接拉力，提升了太阳能光伏组件的可靠性。
银薄层600的厚度范围值可以为10nm至200nm，例如，银薄层600的厚度值可以是30nm、50nm、70nm、90nm、110m、130nm、150nm、190nm。为了使银薄层600与主栅线电极700结合后具有较高的焊接强度，同时不会影响异质结太阳能电池的性能，在示例性实施例中，银薄层600的厚度值可以为110nm。
晶硅衬底100的厚度范围值可以为100μm至250um，例如，晶硅衬底100的厚度值可以为120μm、140μm、160μm、180μm、200μm、220μm、240μm。
本征层200的厚度值可以为1nm至20nm；例如，本征层200的厚度值可以为4nm、8nm、12nm、15nm、18nm。较厚的本征层200可能会带来太阳能电池串联电阻的增加，同时阻碍太阳光的透过，导致短路电流和整体效率的恶化；而较薄的本征层200可能会削弱内建电场，导致开路电压的恶化。因此，本征层200的厚度可以恰当控制，在示例性实施例中，本征层200的厚度可以为12nm，该厚度的本征层200相对于其它厚度的本征层200更有利于提高异质结太阳能电池的各项性能。
N型掺杂硅层300的厚度范围值可以为1nm至20nm；例如，N型掺杂硅层300的厚度值可以为4nm、6nm、8nm、10nm、12nm、15nm、18nm。若N型掺杂硅层300的厚度过大，可能会带来太阳能电池串联电阻的增加，同时阻碍太阳光的透过，导致短路电流和整体效率的恶化；若N型掺杂硅层300的厚度过小，可能不能够形成强度足够的内建电场，导致开路电压的恶化。因此，在示例性实施例中，N型掺杂硅层300的厚度值可以为10nm。
P型掺杂硅层400的厚度范围值可以为1nm至20nm，P型掺杂硅层400的厚度值可以为4nm、6nm、8nm、10nm、12nm、15nm、18nm，为了保证太阳光的透光率，同时可以形成强度足够的内建电场，P型掺杂硅层400的厚度值可以为10nm。
透明导电膜层500的厚度范围值可以为50nm至150nm，例如，透明导电膜层500的厚度值可以是60nm、80nm、100nm、120nm、140nm。
透明导电膜层500上可以设置有细栅线电极，细栅线电极用来收集光激发产生的电子或空穴，并将所收集的电子或空穴传输给主栅线电极，细栅线电极可以有多条，且多条细栅线电极在透明导电膜层500上呈均匀的、较密集的分布。其中，细栅线电极的直径的范围值可以是20μm至60μm，而为了增大细栅线电极分布密度，提高输出的电流，同时保证细栅线电极与透明导电膜层500的连接强度。在示例性实施例中，细栅线电极的直径可以为35μm。
细栅线电极与主栅线电极导电连接，主栅线电极的数量可以为2条至6条，而为了避免银浆料的浪费，同时增强主栅线电极和细栅线电极的结 合强度，主栅线电极的数量可以为4条。在本申请提供的其他实施例中，银薄层600可以仅设置在晶硅衬底100正面或背面的透明导电膜层500上，银薄层600上设置有主栅线电极700。
当银薄层600仅设置在晶硅衬底100正面的透明导电膜层500上时，晶硅衬底100背面的透明导电膜层500上可以直接设置主栅线电极作为电极层或设置由主栅线电极和细栅线电极组成的电极层，此时得到的是双面的异质结太阳能电池，其结构如图3所示；晶硅衬底100背面的整个透明导电膜层500上也可以设置金属层，此时得到的是单面的异质结太阳能电池。所述金属层可以选自银层、银铝层和镍钒层中的至少一种。
当银薄层600仅设置在晶硅衬底100背面的透明导电膜层500上时，晶硅衬底100正面的透明导电膜层500上可以直接设置主栅线电极作为电极层或设置由主栅线电极和细栅线电极组成的电极层，此时得到的是双面的异质结太阳能电池。
在本申请提供的其他实施例中，可以采用其他金属薄层代替银薄层，例如，银铝薄层和镍钒薄层中的至少一种，还可以采用银薄层与银铝薄层和镍钒薄层中的至少一种的复合薄层。这种情况下也可以增强主栅线电极的焊接拉力，提升太阳能光伏组件的可靠性。
在示例性实施例中，所述金属薄层的厚度范围值可以为10nm至200nm。
本申请实施例提供的异质结太阳能电池及其制备方法，通过在透明导电膜层和主栅线电极之间沉积一层金属薄层，并通过金属浆料中树脂的作用，使金属薄层和主栅线电极固化在一起，从而增强了主栅线电极的焊接拉力，提升了太阳能光伏组件的可靠性。
经测试，金属薄层的设置可以使主栅线电极的焊接拉力提升一倍。依据国际标准IEC61215，对本申请实施例的异质结太阳能电池进行DH(双85)测试和TC(冷热循环)测试，测得组件的功率损失降低了50％。
本公开内容是本申请实施例的原则的示例，并非对本申请作出任何形式上或实质上的限定，或将本申请限定到具体的实施方案。对本领域的技术人 员而言，很显然本申请实施例的技术方案的要素、方法和系统等，可以进行变动、改变、改动、演变，而不背离如上所述的本申请的实施例、技术方案的，如权利要求中所定义的原理、精神和范围。这些变动、改变、改动、演变的实施方案均包括在本申请的等同实施例内，这些等同实施例均包括在本申请的由权利要求界定的范围内。虽然可以许多不同形式来使本申请实施例具体化，但此处详细描述的是本申请的一些实施方案。此外，本申请的实施例包括此处所述的各种实施方案的一些或全部的任意可能的组合，也包括在本申请的由权利要求界定的范围内。在本申请中或在任一个引用的专利、引用的专利申请或其它引用的资料中任何地方所提及的所有专利、专利申请和其它引用资料据此通过引用以其整体并入。
以上公开内容规定为说明性的而不是穷尽性的。对于本领域技术人员来说，本说明书会暗示许多变化和可选择方案。所有这些可选择方案和变化旨在被包括在本权利要求的范围内，其中术语“包括”意思是“包括，但不限于”。在此完成了对本申请可选择的实施方案的描述。本领域技术人员可认识到此处所述的实施方案的其它等效变换，这些等效变换也为由附于本文的权利要求所包括。

Claims (16)

  1. 一种异质结太阳能电池的制备方法，所述方法包括如下步骤：在晶硅衬底的至少一面上依次形成本征层、形成掺杂硅层、形成透明导电膜层、形成金属薄层和形成电极层的步骤。
  2. 根据权利要求1所述的制备方法，其中，所述金属薄层选自银薄层、银铝薄层和镍钒薄层中的至少一种。
  3. 根据权利要求1或2所述的制备方法，其中，将所述透明导电膜层划分为主栅区域和非主栅区域，在所述主栅区域上形成所述金属薄层；所述电极层包括主栅线电极，在所述金属薄层上形成所述主栅线电极；
    任选地，所述电极层还包括细栅线电极，在所述非主栅区域形成所述细栅线电极。
  4. 根据权利要求3所述的制备方法，其中，所述方法包括如下步骤：
    在晶硅衬底的正面和背面形成本征层；
    在晶硅衬底的正面和背面的本征层上形成掺杂硅层；
    在两个所述掺杂硅层上形成透明导电膜层；
    在至少一面的透明导电膜层上形成金属薄层；
    在所述金属薄层上形成所述主栅线电极；或者，在所述金属薄层上形成所述主栅线电极，并在所述金属薄层所在的所述透明导电膜层的非主栅区域形成所述细栅线电极；以及
    任选地，在未形成金属薄层的透明导电膜层上形成金属层或电极层；
    其中，两个所述掺杂硅层的掺杂类型不同。
  5. 根据权利要求1至4中任一项所述的制备方法，其中，所述金属薄层采用物理气相沉积法形成；任选地，所述物理气相沉积法为磁控溅射法，溅射功率为1W/cm 2至10W/cm 2，溅射压强为0.1Pa至0.5Pa，溅射气体为氩气。
  6. 根据权利要求4所述的制备方法，其中，在透明导电膜层上形成 金属层为在所述透明导电膜层的整个表面上形成所述金属层。
  7. 一种异质结太阳能电池，所述异质结太阳能电池包括：依次设置在晶硅衬底的至少一面上的本征层、掺杂硅层、透明导电膜层、金属薄层和电极层。
  8. 根据权利要求7所述的异质结太阳能电池，其中，所述金属薄层选自银薄层、银铝薄层和镍钒薄层中的至少一种；任选地，所述金属薄层的厚度范围值为10nm至200nm。
  9. 根据权利要求7或8所述的异质结太阳能电池，其中，所述透明导电膜层包括主栅区域和非主栅区域，所述金属薄层设置在所述主栅区域上；所述电极层包括主栅线电极，所述主栅线电极设置在所述金属薄层上；
    任选地，所述电极层还包括细栅线电极，所述细栅线电极设置在所述非主栅区域上。
  10. 根据权利要求9所述的异质结太阳能电池，其中，所述异质结太阳能电池包括：
    设置在晶硅衬底正面和背面的本征层；
    设置在所述晶硅衬底的正面和背面的本征层上的掺杂硅层；
    设置在两个所述掺杂硅层上的透明导电膜层；
    设置在至少一面的透明导电膜层上的金属薄层；
    设置在所述金属薄层上的所述主栅线电极；或者，设置在所述金属薄层上的所述主栅线电极，以及设置在所述金属薄层所在的所述透明导电膜层的非主栅区域上的所述细栅线电极；
    任选地，所述异质结太阳能电池还包括设置在未设置金属薄层的透明导电膜层上的金属层或电极层；
    其中，两个所述掺杂硅层的掺杂类型不同。
  11. 根据权利要求10所述的异质结太阳能电池，其中，所述金属层设置在所述透明导电膜层的整个表面上。
  12. 一种异质结太阳能电池的制备方法，所述方法包括如下步骤：
    在晶硅衬底的正面沉积第一本征非晶硅层，在所述晶硅衬底的背面沉积第二本征非晶硅层；或者在所述晶硅衬底的背面沉积所述第一本征非晶硅层，在所述晶硅衬底的正面沉积所述第二本征非晶硅层；
    在所述第一本征非晶硅层上沉积N型非晶硅层，在所述第二本征非晶硅层上沉积P型非晶硅层；
    在所述N型非晶硅层的表面和所述P型非晶硅层的表面分别沉积透明导电膜层；
    在两个所述透明导电膜层上分别沉积银薄层；以及
    在两个所述银薄层上分别通过丝网印刷形成主栅线电极。
  13. 根据权利要求12所述的异质结太阳能电池的制备方法，其中，在两个所述透明导电膜层上分别沉积银薄层的步骤包括：
    在两个所述透明导电膜层上分别通过掩膜版遮挡所述透明导电膜层上的非主栅区域；并且
    在所述透明导电膜层上的主栅区域沉积所述银薄层。
  14. 根据权利要求12或13所述的异质结太阳能电池的制备方法，其中，所述银薄层采用磁控溅射法沉积，溅射功率为2.5W/cm 2，溅射压强为0.2Pa，溅射气体为氩气。
  15. 一种异质结太阳能电池，所述异质结太阳能电池包括：
    晶硅衬底；
    设置在所述晶硅衬底正面和背面的本征非晶硅层；
    设置在所述晶硅衬底正面的所述本征非晶硅层上的N型非晶硅层；
    设置在所述晶硅衬底背面的所述本征非晶硅层上的P型非晶硅层；
    设置在所述N型非晶硅层和所述P型非晶硅层上的透明导电膜层；
    设置在两个所述透明导电膜层上的银薄层；
    设置在两个所述银薄层上的主栅线电极。
  16. 根据权利要求15所述的异质结太阳能电池，其中，所述银薄层的厚度范围值为10nm至200nm。
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