WO2019095484A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2019095484A1
WO2019095484A1 PCT/CN2017/116303 CN2017116303W WO2019095484A1 WO 2019095484 A1 WO2019095484 A1 WO 2019095484A1 CN 2017116303 W CN2017116303 W CN 2017116303W WO 2019095484 A1 WO2019095484 A1 WO 2019095484A1
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WIPO (PCT)
Prior art keywords
signal
thin film
film transistor
node
electrically connected
Prior art date
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Ceased
Application number
PCT/CN2017/116303
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English (en)
French (fr)
Inventor
吕晓文
周依芳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/742,886 priority Critical patent/US10692454B2/en
Publication of WO2019095484A1 publication Critical patent/WO2019095484A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF) substrate, and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • each pixel is electrically connected to a thin film transistor (TFT), a gate of a thin film transistor is connected to a horizontal scan line, a source is connected to a vertical data line, and a drain (Drain) ) is connected to the pixel electrode.
  • TFT thin film transistor
  • Drain drain
  • Applying a sufficient voltage on the horizontal scanning line causes all the TFTs electrically connected to the horizontal scanning line to be turned on, so that the signal voltage on the data line can be written into the pixel, and the transmittance of different liquid crystals is controlled to control the color.
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly completed by an external integrated circuit (IC), and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • IC external integrated circuit
  • the GOA technology is an array substrate row driving technology, which is a driving method in which a gate driving circuit can be fabricated on a TFT array substrate by using an array process of a liquid crystal display panel to realize a gate-by-row scanning.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • the GOA circuit includes a multi-level GOA unit, and each level of the GOA unit includes a pull-up control module 100 ′, an output module 200 ′, and a pull-down module 300 ′.
  • the first pull-down maintaining module 400' and the second pull-down maintaining module 500' let N be a positive integer, except for the first to fourth-level GOA units and the last-to-fourth to last-level GOA Outside the unit, in the Nth stage GOA unit, the pull-up control module 100' includes an eleventh thin film transistor T11', and the gate of the eleventh thin film transistor T11' is connected to the fourth level of the N-4th stage.
  • the level signal ST(N-4)' of the GOA unit the source is connected to the high potential signal VDD, and the drain is electrically connected to the first node Q(N)';
  • the output module 200' includes the 21st thin film transistor T21', the twenty-second thin film transistor T22', and the first capacitor C1', the gate of the twenty-first thin film transistor T21' is electrically connected to the first node Q(N)', and the source is connected to the clock signal.
  • the drain output scan signal G(N)', the gate of the twenty-second thin film transistor T22' is electrically connected to the first node Q(N)', the source is connected to the clock signal CK', and the drain
  • the output stage transmits a signal ST(N)', one end of the first capacitor C1' is electrically connected to the first node Q(N)', and the other end is electrically connected to the drain of the 21st thin film transistor T21';
  • the pull-down module 300 ' including the forty-third thin film transistor T43', the gate of the forty-third thin film transistor T43' is electrically connected to the output terminal G of the lower four-stage N+4 stage GOA circuit (N+4
  • the source is connected to the low potential signal VSS, and the drain is electrically connected to the first node Q(N)';
  • the first pull-down maintaining module 400' includes the 31st thin film transistor T31', the forty first The thin film transistor T41', the fifty-first thin film transistor T51'
  • the gate and the source of the 51st thin film transistor T51' are connected to the first control signal LC1', and the drain Electrically connected to the second node P(N)', the gate of the fifty-second thin film transistor T52' is connected to the first node Q(N)', the source is connected to the low potential signal VSS, and the drain is electrically connected.
  • the second pull-down maintaining module 500' includes a thirty-second thin film transistor T32', a forty-second thin film transistor T42', and a sixth a thin film transistor T61', and a sixty-second thin film transistor T62', the gate of the thirty-second thin film transistor T32' is electrically connected to the third node T(N)', and the source is connected to the low potential signal VSS.
  • the drain is electrically connected to the drain of the 21st thin film transistor T21', the gate of the forty-second thin film transistor T42' is connected to the third node T(N)', and the source is connected to the low potential signal VSS.
  • the drain is electrically connected to the first node Q(N)', the gate and the source of the 61st thin film transistor T61' are connected to the second control signal LC2', and the drain is electrically connected to the third node T ( N)', the gate of the sixty-second thin film transistor T62' is connected to the first node Q(N)', the source is connected to the low potential signal VSS, and the drain is electrically connected to the third node T(N)'
  • the first control signal LC1' is opposite in phase to the second control signal LC2'.
  • the eleventh thin film transistor T11' is turned on to write the high potential signal VDD to the first node.
  • Q(N)', controlling the twenty-first thin film transistor T21' and the twenty-second thin film transistor T22' respectively output a scan signal G(N)' corresponding to the clock signal CK and a graded signal ST(N)', Simultaneously controlling the fifty-second thin film transistor T52' and the sixty-second thin film transistor T62' to turn on the low potential signal VSS to the forty-first thin film transistor T41', the forty-second thin film transistor T42', and the thirty-first film
  • the source of T32' is connected to the low potential signal V
  • the gate-to-source voltage difference is 0, and the purpose is to make the forty-th thin film transistor T41', the forty-second thin film transistor T42', the thirty-first thin film transistor T31', and the thirty-second thin film transistor T32' at the GOA.
  • the unit When the unit outputs the scanning signal G(N)' and the level-transmitting signal S(N)', it is turned off.
  • the gate-to-source voltage difference is 0, which is not a thin film transistor.
  • the point of least leakage This causes leakage of the forty-first thin film transistor T41', the forty-second thin film transistor T42', the thirty-first thin film transistor T31', and the thirty-second thin film transistor T32', affecting the first node Q(N)'
  • the potential is to improve the performance of the GOA circuit.
  • the current method is to set two low-potential signals with different potentials to make the gate-source of the thin-film transistor have a negative voltage to make the thin-film transistor leakage smaller.
  • the signal line needs to be added when using this method. It will increase the fanout layout space, which is not conducive to the realization of narrow borders, and will also increase the number of signals and increase product cost.
  • An object of the present invention is to provide a GOA circuit capable of effectively reducing leakage current of a thin film transistor in a first pull-down maintaining module, preventing leakage current from affecting a potential of the first node, improving stability of the circuit, and eliminating the need for additional Signal lines help reduce product costs and achieve narrow borders.
  • the present invention provides a GOA circuit, including: a multi-level GOA unit, each stage GOA unit includes: a pull-up control module, an output module, a pull-down module, and a first pull-down maintenance module;
  • N be a positive integer, in addition to the first to fourth level GOA units and the last to fourth level GOA units, in the Nth level GOA unit:
  • the pull-up control module accesses the level-transmitted signal and the high-potential signal of the upper four-level N-4th GOA unit, and is electrically connected to the first node for transmitting on the level-transmitted signal of the N-4th-level GOA unit. Pulling the potential of the first node to a high potential signal;
  • the output module is connected to the clock signal and electrically connected to the first node for outputting the scan signal and the level transmission signal under the potential control of the first node;
  • the pull-down module is connected to the lower four-level N+4 GOA unit Scanning signal and low potential signal, and electrically connected to the first node, according to the N+4
  • the scan signal of the stage GOA unit pulls down the potential of the first node to the low potential signal;
  • the first pull-down maintaining module accesses the first control signal, the low potential signal, the scan signal, and the circuit enable signal, and is electrically connected to the first node, and is configured to pull down the potential of the first node to the low potential signal after the pull-down module Maintaining the scan signal and the potential of the first node at a low potential signal;
  • the circuit enable signal is a pulse signal, and the low potential of the circuit enable signal is less than the potential of the low potential signal.
  • the first pull-down maintaining module includes a thirty-first thin film transistor, a forty-first thin film transistor, a fifty-first thin film transistor, a fifty-second thin film transistor; the gate of the thirty-first thin film transistor is electrically connected to the second node, the source is connected to the low potential signal, the drain is connected to the scan signal; and the gate of the forty-first thin film transistor is The second node is electrically connected to the second node, the source is connected to the low potential signal, and the drain is electrically connected to the first node; the gate and the source of the 51st thin film transistor are connected to the first control signal, and the drain is electrically The second node is connected to the second node; the gate of the fifty-second thin film transistor is connected to the first node, the source is connected to the circuit to activate the signal, and the drain is electrically connected to the second node.
  • Each level of the GOA unit further includes: a second pull-down maintenance module
  • the second pull-down maintaining module includes a thirty-second thin film transistor, a forty-second thin film transistor, a sixty-first thin film transistor, a TFT of the thirty-second thin film transistor; the gate of the thirty-second thin film transistor is electrically connected to the third node, the source is connected to the low potential signal, the drain is connected to the scan signal; and the gate of the forty-second thin film transistor is Electrically connected to the third node, the source is connected to the low potential signal, and the drain is electrically connected to the first node; the gate and the source of the 61st thin film transistor are connected to the second control signal, and the drain is electrically Connecting the third node; the gate of the sixty-second thin film transistor is connected to the first node, the source access circuit is activated, and the drain is electrically connected to the third node;
  • the first control signal is opposite in phase to the second control signal.
  • the clock signal includes: a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, and an eighth clock signal that are sequentially output,
  • X be a non-negative integer, a 1+8X-level GOA unit, a 2+8X-level GOA unit, a 3+8X-level GOA unit, a 4+8X-level GOA unit, a 5+8X-level GOA unit, and a 6+th
  • the clock signals connected in the 8X-level GOA unit, the 7+8X-level GOA unit, and the 8+8X-level GOA unit are the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, and the fifth a clock signal, a sixth clock signal, a seventh clock signal, and an eighth clock signal;
  • the time interval between rising edges of two clock signals of adjacent outputs is one eighth of one cycle of the clock signal, and the duty ratio of the clock signal is 0.4;
  • the duration of the high potential of the circuit enable signal is equal to three quarters of a period of the clock signal
  • the rising edge of the circuit enable signal is earlier than the rising edge of the first clock signal, and the time interval between the two is one quarter of one cycle of the clock signal.
  • the difference between the potential of the low potential signal and the low potential of the circuit enable signal is 1.5-2.5V.
  • the low level of the circuit enable signal is -8V, and the potential of the low potential signal is -6V.
  • the pull-up control module includes an eleventh thin film transistor; and the gate of the eleventh thin film transistor is connected to the fourth level N
  • the level-transmitting signal of the -4 level GOA unit, the source is connected to the high potential signal, and the drain is electrically connected to the first node.
  • the output module includes a 21st thin film transistor, a 22nd thin film transistor, and a first capacitor; a gate of the 21st thin film transistor is electrically connected to the first node, and the source is connected to the clock signal, and the drain a second output of the scan signal; the gate of the twenty-second thin film transistor is electrically connected to the first node, the source is connected to the clock signal, and the drain output is transmitted by the signal; and one end of the first capacitor is electrically connected to the first node The other end is electrically connected to the drain of the twenty-first thin film transistor.
  • the pull-down module includes a forty-third thin film transistor, and the gate of the forty-third thin film transistor is connected to the fourth level a scanning signal of the N+4 level GOA unit, the source is connected to the low potential signal, and the drain is electrically connected to the first node;
  • the pull-down module includes a forty-third thin film transistor, the gate of the forty-third thin film transistor is activated by a circuit, and the source is connected to a low potential signal. The drain is electrically connected to the first node.
  • the pull-up control module includes an eleventh thin film transistor; a gate of the eleventh thin film transistor is connected to a circuit enable signal, a source is connected to a high potential signal, and a drain is electrically connected to the first node;
  • the pull-down maintaining module includes a thirty-first thin film transistor, a forty-first thin film transistor, a fifty-first thin film transistor, and a fifty-second thin film transistor; the gate of the thirty-first thin film transistor is electrically connected to the second node
  • the source is connected to the low potential signal, and the drain is connected to the scan signal; the gate of the forty-th thin film transistor is electrically connected to the second node, the source is connected to the low potential signal, and the drain is electrically connected to the first node.
  • the gate and the source of the 51st thin film transistor are both connected to the first control signal, and the drain is electrically connected to the second node; the gate of the 52nd thin film transistor is connected to the first node, the source a pole is connected to the low potential signal, and the drain is electrically connected to the second node; the second pull-down maintaining module includes a thirty-second thin film transistor, a forty-second thin film transistor, a sixty-first thin film transistor, and a sixty-second film Transistor Thirty-gate thin film transistor is electrically connected to the third node, a source access low signal, the drain access scan signal; the forty-second film The gate of the transistor is electrically connected to the third node, the source is connected to the low potential signal, and the drain is electrically connected to the first node; the gate and the source of the 61st thin film transistor are connected to the second control signal, The drain is electrically connected to the third node; the gate of the sixty-second thin film transistor is connected to the first node, the source is connected to
  • the present invention also provides a GOA circuit, comprising: a multi-level GOA unit, each stage GOA unit includes: a pull-up control module, an output module, a pull-down module, and a first pull-down maintenance module;
  • N be a positive integer, in addition to the first to fourth level GOA units and the last to fourth level GOA units, in the Nth level GOA unit:
  • the pull-up control module accesses the level-transmitting signal and the high-potential signal of the N-4th GOA unit, and is electrically connected to the first node, and is used to pull up the first signal according to the level-transmitted signal of the N-4th GOA unit.
  • the output module accesses a clock signal and is electrically connected to the first node, and is configured to output a scan signal and a level transmission signal under the potential control of the first node;
  • the pull-down module is connected to the scan signal and the low-potential signal of the N+4th GOA unit, and is electrically connected to the first node for pulling down the potential of the first node to a low level according to the scan signal of the N+4th GOA unit.
  • the first pull-down maintaining module accesses the first control signal, the low potential signal, the scan signal, and the circuit enable signal, and is electrically connected to the first node, and is configured to pull down the potential of the first node to the low potential signal after the pull-down module Maintaining the scan signal and the potential of the first node at a low potential signal;
  • the circuit enable signal is a pulse signal, and the low potential of the circuit start signal is less than the potential of the low potential signal;
  • the first pull-down maintaining module includes a thirty-first thin film transistor, a forty-first thin film transistor, and a fifty-first thin film, in addition to the first to fourth-level GOA units, in the Nth-level GOA unit.
  • a transistor, a fifty-second thin film transistor a gate of the 31st thin film transistor is electrically connected to the second node, a source is connected to a low potential signal, and a drain is connected to the scan signal; and the 41st thin film transistor is The gate is electrically connected to the second node, the source is connected to the low potential signal, and the drain is electrically connected to the first node; the gate and the source of the 51st thin film transistor are both connected to the first control signal, and the drain Electrode is connected to the second node; the gate of the fifty-second thin film transistor is connected to the first node, the source is connected to the circuit to activate the signal, and the drain is electrically connected to the second node;
  • Each level of the GOA unit further includes: a second pull-down maintenance module
  • the second pull-down maintaining module includes a thirty-second thin film transistor, a forty-second thin film transistor, a sixty-first thin film transistor, a sixty-two thin film transistor;
  • the gate of the thirty-second thin film transistor is electrically connected to the third node, the source is connected to the low potential signal, and the drain is connected to the scan signal;
  • the gate of the membrane transistor is electrically connected to the third node, the source is connected to the low potential signal, and the drain is electrically connected to the first node;
  • the gate and the source of the 61st thin film transistor are connected to the second control signal
  • the drain is electrically connected to the third node;
  • the gate of the sixty-second thin film transistor is connected to the first node, the source is connected to the circuit to activate the signal, and the drain is electrically connected to the third node;
  • the first control signal is opposite in phase to the second control signal
  • the clock signal includes: a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, and an eighth clock that are sequentially output.
  • the clock signals connected in the 6+8X-level GOA unit, the 7+8X-level GOA unit, and the 8+8X-level GOA unit are the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively.
  • a fifth clock signal, a sixth clock signal, a seventh clock signal, and an eighth clock signal are the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively.
  • the time interval between rising edges of two clock signals of adjacent outputs is one eighth of one cycle of the clock signal, and the duty ratio of the clock signal is 0.4;
  • the duration of the high potential of the circuit enable signal is equal to three quarters of a period of the clock signal
  • the rising edge of the circuit enable signal is earlier than the rising edge of the first clock signal, and the time interval between the two is one quarter of a cycle of the clock signal;
  • the pull-up control module includes an eleventh thin film transistor; and the gate of the eleventh thin film transistor is connected to the N-th The level-transmitting signal of the 4-level GOA unit, the source is connected to the high-potential signal, and the drain is electrically connected to the first node;
  • the output module includes a 21st thin film transistor, a 22nd thin film transistor, and a first capacitor; a gate of the 21st thin film transistor is electrically connected to the first node, and the source is connected to the clock signal. a drain output scan signal; a gate of the twenty-second thin film transistor is electrically connected to the first node, a source is connected to the clock signal, and a drain output is a level-transmitting signal; and one end of the first capacitor is electrically connected One node is electrically connected to the drain of the twenty-first thin film transistor.
  • the present invention provides a GOA circuit in which a first pull-down maintaining module accesses a first control signal in each GOA unit except for the first to fourth-stage GOA units. a potential signal, a scan signal, and a circuit enable signal, and electrically connected to the first node, wherein the fifty-second thin film transistor gate in the first pull-down maintenance module is electrically connected to the first node, and the source access circuit starts the signal,
  • the drain is connected to the gates of the 31st and 41st thin film transistors, so that the gate-to-source voltage difference of the 31st and 41st thin film transistors is negative when the first node is high.
  • 1 is a circuit diagram of a conventional GOA circuit
  • FIG. 2 is a circuit diagram of a GOA circuit of the present invention
  • FIG. 3 is a circuit diagram of a first to fourth stage GOA unit in the GOA circuit of the present invention.
  • FIG. 4 is a circuit diagram of a fourth to last stage GOA unit in the GOA circuit of the present invention.
  • Figure 5 is a timing chart showing the operation of the GOA circuit of the present invention.
  • the present invention provides a GOA circuit, including: a multi-level GOA unit, each stage GOA unit includes: a pull-up control module 100, an output module 200, a pull-down module 300, and a first pull-down maintenance module 400;
  • N be a positive integer, in addition to the first to fourth level GOA units and the last to fourth level GOA units, in the Nth level GOA unit:
  • the pull-up control module 100 is connected to the level-transmitting signal ST(N-4) and the high-potential signal Vdd of the upper four-stage N-4th GOA unit, and is electrically connected to the first node Q(N) for The level signal ST(N-4) of the N-4th stage GOA unit pulls up the potential of the first node Q(N) to the high potential signal Vdd.
  • the pull-up control module 100 includes an eleventh thin film transistor T11; the gate of the eleventh thin film transistor T11 is connected The level signal ST(N-4) of the fourth-stage N-4th GOA unit is input, the source is connected to the high potential signal Vdd, and the drain is electrically connected to the first node Q(N).
  • the output module 200 is connected to the clock signal CK and electrically connected to the first node Q(N) for outputting the scan signal G(N) and the level transmission signal ST(N) under the potential control of the first node Q(N). ).
  • the output module 200 includes a twenty-first thin film transistor T21 and a twenty-second thin film. a film transistor T22 and a first capacitor C1; a gate of the 21st thin film transistor T21 is electrically connected to the first node Q(N), a source is connected to the clock signal CK, and a drain is outputting a scan signal G(N)
  • the gate of the twenty-second thin film transistor T22 is electrically connected to the first node Q(N), the source is connected to the clock signal CK, and the drain output is transmitted to the signal ST(N); the first capacitor C1 One end is electrically connected to the first node Q(N), and the other end is electrically connected to the drain of the 21st thin film transistor T21.
  • the pull-down module 300 accesses the scan signal G(N+4) and the low-potential signal Vss of the lower four-level N+4th GOA unit, and is electrically connected to the first node Q(N) for using the N+th
  • the scan signal G(N+4) of the 4-stage GOA unit pulls down the potential of the first node Q(N) to the low potential signal Vss.
  • the pull-down module 300 includes a forty-third thin film transistor T43, and a gate of the forty-third thin film transistor T43
  • the scanning signal G(N+4) of the lower four-stage N+4th GOA unit is connected, the source is connected to the low potential signal Vss, and the drain is electrically connected to the first node Q(N).
  • the first pull-down maintaining module 400 accesses the first control signal LC1, the low potential signal Vss, the scan signal G(N), and the circuit enable signal STV, and is electrically connected to the first node Q(N) for pulling down
  • the module 300 pulls down the potential of the first node Q(N) to the low potential signal Vss to maintain the potential of the scan signal G(N) and the first node Q(N) at the low potential signal Vss; the circuit start signal STV It is a pulse signal, and the low potential of the circuit enable signal STV is smaller than the potential of the low potential signal Vss.
  • the first pull-down maintaining module 400 includes a thirty-first thin film transistor T31, a forty-first thin film transistor T41, and a first 51th thin film transistor T51, fifty-second thin film transistor T52; the gate of the 31st thin film transistor T31 is electrically connected to the second node P(N), the source is connected to the low potential signal Vss, and the drain is connected The scan signal G(N) is input; the gate of the forty-th thin film transistor T41 is electrically connected to the second node P(N), the source is connected to the low potential signal Vss, and the drain is electrically connected to the first node Q ( N); the gate and the source of the 51st thin film transistor T51 are both connected to the first control signal LC1, the drain is electrically connected to the second node P(N); and the 52nd thin film transistor T52 The gate is connected to the first node Q(N), the source is connected to the circuit start signal
  • each level of the GOA unit further includes: a second pull-down maintaining module 500, the second pull-down module 500 alternates with the first pull-down maintaining module 400, and pulls down the first node Q in the pull-down module 300 ( The potential of the N) to the low potential signal Vss maintains the potential of the scan signal G(N) and the first node Q(N) at the low potential signal Vss.
  • the second pull-down maintaining module 500 includes a thirty-second thin film transistor T32, a forty-second thin film transistor T42, and a sixth Eleven thin film transistor T61, sixty-second thin film transistor T62; the thirtieth The gate of the second thin film transistor T32 is electrically connected to the third node T(N), the source is connected to the low potential signal Vss, the drain is connected to the scan signal G(N), and the gate of the forty-second thin film transistor T42 is Electrically connected to the third node T(N), the source is connected to the low potential signal Vss, and the drain is electrically connected to the first node Q(N); the gate and the source of the 61st thin film transistor T61 are connected Into the second control signal LC2, the drain is electrically connected to the third node T(N); the gate of the sixty-second thin film transistor T62 is connected to the first node Q(N), and the source access circuit starts
  • the clock signal CK includes: a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, a fourth clock signal CK4, a fifth clock signal CK5, and a sixth clock signal CK6, which are sequentially output.
  • the clock signals CK accessed in the 5+8X-level GOA unit, the 6+8X-level GOA unit, the 7+8X-level GOA unit, and the 8+8X-level GOA unit are respectively the first clock signal CK1 and the second clock.
  • the time interval between the edges is one eighth of one cycle of the clock signal CK, the duty ratio of the clock signal CK is 0.4; the duration of the high potential of the circuit enable signal STV is equal to four minutes of one cycle of the clock signal CK Third; the rising edge of the circuit enable signal STV is earlier than the first clock signal CK1 Direction, and the time interval between the two one-quarter of a cycle of the clock signal CK.
  • the difference between the potential of the low potential signal Vss and the low potential of the circuit enable signal STV is 1.5-2.5V.
  • the low potential of the circuit enable signal STV is -8V
  • the potential of the low potential signal Vss is -6V.
  • the pull-up control module 100 includes an eleventh thin film transistor T11; the gate of the eleventh thin film transistor T11 is connected to the circuit enable signal STV, the source is connected to the high potential signal Vdd, and the drain is electrically connected to the first node.
  • the first pull-down maintaining module 400 includes a thirty-first thin film transistor T31, a forty-first thin film transistor T41, a fifty-first thin film transistor T51, and a fifty-second thin film transistor T52;
  • the gate of the 31-th thin film transistor T31 is electrically connected to the second node P(N), the source is connected to the low potential signal Vss, and the drain is connected to the scan signal G(N);
  • the 41st thin film transistor T41 is The gate is electrically connected to the second node P(N), the source is connected to the low potential signal Vss, and the drain is electrically connected to the first node Q(N);
  • the gate and the source of the 51st thin film transistor T51 Each is connected to the first control signal LC1, and the drain is electrically connected to the second node P(N);
  • the gate of the film transistor T52 is connected to the first node Q(N), the source is connected to the low potential signal Vss, and the drain is electrically connected to the second node P
  • the potential signal Vss the drain is electrically connected to the first node Q(N); the gate and the source of the 61st thin film transistor T61 are both connected to the second control signal LC2, and the drain is electrically connected to the third node T (N); the gate of the sixty-second thin film transistor T62 is connected to the first node Q(N), the source is connected to the low potential signal Vss, and the drain is electrically connected to the third node T(N).
  • the pull-down module 300 includes a forty-third thin film transistor T43, and the gate access circuit of the forty-third thin film transistor T43
  • the start signal STV the source is connected to the low potential signal Vss, and the drain is electrically connected to the first node Q(N); the pull-up control module 100, the output module 200, the first pull-down maintaining module 400, and the second pull-down maintaining module
  • the 500 is the same as the pull-up control module 100, the output module 200, the first pull-down maintaining module 400, and the second pull-down maintaining module 500 in the fifth-level to fifth-order GOA unit.
  • the working process of the GOA circuit of the present invention is: first, the circuit enable signal STV provides a high potential, and the eleventh thin film transistor T11 of the first to fourth stage GOA units is turned on, the first stage is The potential of the first node in the fourth-stage GOA cell rises to a high potential, and the twenty-first thin film transistor T21 and the twenty-second thin film transistor T22 in the first- to fourth-stage GOA unit are both turned on, and then the first clock signal CK1 outputs a high potential, the first stage GOA unit outputs a scan signal and a level transfer signal, then the second clock signal CK2 outputs a high potential, the second stage GOA unit outputs a scan signal and a level transfer signal, and then the third clock signal CK3 outputs a high potential.
  • the third-stage GOA unit outputs a scan signal and a level-transmitted signal, and then the fourth clock signal CK4 outputs a high potential, and the fourth-stage GOA unit outputs a scan signal and a level-transmitted signal, the first-stage GOA unit and the second-stage GOA unit.
  • the level-transmitting signals of the third-stage GOA unit and the fourth-level GOA unit are respectively transmitted to the pull-up control module 100 of the fifth-level GOA unit, the sixth-level GOA unit, the seventh-level GOA unit, and the eighth-level GOA unit, and are received.
  • the eleventh thin film transistor T11 of the fifth-level GOA unit, the sixth-level GOA unit, the seventh-level GOA unit, and the eighth-level GOA unit are sequentially turned on, and the fifth clock signal CK5, sixth The clock signal CK6, the seventh clock signal CK7, and the eighth clock signal CK8 sequentially start to provide a high potential, and the fifth-level GOA unit, the sixth-level GOA unit, the seventh-level GOA unit, and the eighth-level GOA unit are respectively in the fifth stage.
  • Clock signal CK5, sixth clock signal CK6, seventh clock signal CK7, eighth clock signal The scan signal and the level transfer signal are output during the high potential period of the CK8, and the pull-down module 300 of the first stage GOA unit, the second stage GOA unit, the third stage GOA unit, and the fourth stage GOA unit respectively receive the fifth level GOA unit,
  • the scanning signals of the sixth-level GOA unit, the seventh-level GOA unit, and the eighth-level GOA unit respectively pull down the first-level GOA unit, the second-level GOA unit, the third-level GOA unit, and the fourth-level GOA unit.
  • the node is connected to the potential of the low potential signal Vss, and then the first pull-down maintaining unit 400 or the second pull-down maintaining unit 500 maintains the potential of the first node and the scan signal at the potential of the low potential signal Vss, and so on, until the fourth last level The GOA unit, the third-order GOA unit, the second-order GOA unit, and the last-stage GOA unit sequentially output a scan signal and a level-transmitted signal, and then the circuit enable signal STV again provides a high potential to the fourth-order GOA unit, the last number The third-level GOA unit, the penultimate-level GOA unit, and the pull-down module 300 of the last-stage GOA unit, the fourth-order GOA unit, the third-order GOA unit, the second-order GOA unit, and the last one GOA node unit down to the low potential Vss signal, the first pull-down and then maintained on the low potential Vss, the signal potential of the potential or the second pull-down unit 400 maintain the first node
  • the eleventh is made. After the thin film transistor T11 is turned on, the high potential signal Vdd charges the first node Q(N) to become a high potential.
  • the fifty-second thin film transistor T52 and the sixtieth controlled by the first node Q(N) The second thin film transistor T62 is turned on, so that the low potential of the circuit enable signal STV is input to the gates of the forty-first, thirty-first, forty-second, and thirty-second thin film transistors T41, T31, T42, and T32, and The sources of the forty-first, thirty-first, forty-second, and thirty-second thin film transistors T41, T31, T42, and T32 are all connected to the low potential signal Vss, and the low potential of the circuit start signal STV is set low.
  • Leakage currents of T41, T31, T42, and T32 prevent leakage current from affecting the potential of the first node Q(N), improve the stability of the circuit, and the circuit start signal STV is an existing signal in the existing GOA circuit. No additional signal lines are required, which helps to reduce product cost and achieve a narrow bezel.
  • the GOA circuit in each of the GOA units except the first to fourth stage GOA units accesses the first control signal, the low potential signal, and the scan
  • the signal and the circuit start signal are electrically connected to the first node, wherein the fifty-second thin film transistor gate in the first pull-down maintaining module is electrically connected to the first node, the source access circuit is activated, and the drain is connected.
  • the eleventh thin film transistor gate made at the first node
  • the gate-to-source voltage difference of the 31st and 41st thin film transistors is negative, which can effectively reduce the leakage current of the thin film transistor in the first pull-down sustaining unit, and avoid leakage current to the first node.
  • the potential affects the circuit, improves the stability of the circuit, and eliminates the need for additional signal lines, which helps to reduce product cost and achieve a narrow bezel.

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Abstract

一种GOA电路，该GOA电路在除第一至第四级GOA单元外的每级GOA单元中，第一下拉维持模块（400）接入第一控制信号（LC1）、低电位信号（Vss）、扫描信号（G（N））及电路启动信号（STV），并电性连接第一节点（Q（N）），其中第一下拉维持模块（400）中的第五十二薄膜晶体管（T52）栅极电性连接第一节点（Q（N）），源极接入电路启动信号（STV），漏极连接第三十一薄膜晶体管（T31）、第四十一薄膜晶体管（T41）的栅极，使在第一节点（Q（N））为高电位时，第三十一薄膜晶体管（T31）、第四十一薄膜晶体管（T41）的栅源极电压差均为负值，能够有效降低第一下拉维持单元（400）中薄膜晶体管的漏电流，避免漏电流对第一节点（Q（N））的电位产生影响，提高电路的稳定性，且无需增加额外的信号线，有利于降低产品成本并实现窄边框。

Description

GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片(Color Filter，CF)基板之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，源极(Source)连接至垂直方向的数据线，漏极(Drain)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。
而GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
如图1所示，为现有的一种GOA电路的电路图，该GOA电路包括多级GOA单元，每一级GOA单元均包括上拉控制模块100’、输出模块200’、下拉模块300’、第一下拉维持模块400’、及第二下拉维持模块500’，设N为正整数，除了第一至第四级GOA单元以及倒数第四级至最后一级GOA 单元外，在第N级GOA单元中，所述上拉控制模块100’包括第十一薄膜晶体管T11’，所述第十一薄膜晶体管T11’的栅极接入上四级第N-4级GOA单元的级传信号ST(N-4)’，源极接入高电位信号VDD，漏极电性连接第一节点Q(N)’；所述输出模块200’包括第二十一薄膜晶体管T21’、第二十二薄膜晶体管T22’、及第一电容C1’，所述第二十一薄膜晶体管T21’的栅极电性连接第一节点Q(N)’，源极接入时钟信号CK’，漏极输出扫描信号G(N)’，所述第二十二薄膜晶体管T22’的栅极电性连接第一节点Q(N)’，源极接入时钟信号CK’，漏极输出级传信号ST(N)’，第一电容C1’一端电性连接第一节点Q(N)’，另一端电性连接第二十一薄膜晶体管T21’的漏极；所述下拉模块300’包括第四十三薄膜晶体管T43’，所述第四十三薄膜晶体管T43’的栅极电性连接下四级第N+4级GOA电路的输出端G(N+4)’，源极接入低电位信号VSS，漏极电性连接第一节点Q(N)’；所述第一下拉维持模块400’包括第三十一薄膜晶体管T31’、第四十一薄膜晶体管T41’、第五十一薄膜晶体管T51’、及第五十二薄膜晶体管T52’，所述第三十一薄膜晶体管T31’的栅极电性连接第二节点P(N)’，源极接入低电位信号VSS，漏极电性连接第二十一薄膜晶体管T21’的漏极，所述第四十一薄膜晶体管T41’的栅极接入第二节点P(N)’，源极接入低电位信号VSS，漏极电性连接第一节点Q(N)’，所述第五十一薄膜晶体管T51’的栅极及源极均接入第一控制信号LC1’，漏极电性连接第二节点P(N)’，所述第五十二薄膜晶体管T52’的栅极接入第一节点Q(N)’，源极接入低电位信号VSS，漏极电性连接第二节点P(N)’；所述第二下拉维持模块500’包括第三十二薄膜晶体管T32’、第四十二薄膜晶体管T42’、第六十一薄膜晶体管T61’、及第六十二薄膜晶体管T62’，所述第三十二薄膜晶体管T32’的栅极电性连接第三节点T(N)’，源极接入低电位信号VSS，漏极电性连接第二十一薄膜晶体管T21’的漏极，所述第四十二薄膜晶体管T42’的栅极接入第三节点T(N)’，源极接入低电位信号VSS，漏极电性连接第一节点Q(N)’，所述第六十一薄膜晶体管T61’的栅极及源极均接入第二控制信号LC2’，漏极电性连接第三节点T(N)’，所述第六十二薄膜晶体管T62’的栅极接入第一节点Q(N)’，源极接入低电位信号VSS，漏极电性连接第三节点T(N)’，所述第一控制信号LC1’与第二控制信号LC2’的相位相反。在此GOA电路的架构下，当第N-4级GOA单元的级传信号ST(N-4)’为高电位时，第十一薄膜晶体管T11’打开使高电位信号VDD写入第一节点Q(N)’，控制第二十一薄膜晶体管T21’及第二十二薄膜晶体管T22’分别输出与时钟信号CK对应的扫描信号G(N)’及级传信号ST(N)’， 同时控制第五十二薄膜晶体管T52’和第六十二薄膜晶体管T62’打开使低电位信号VSS写入第四十一薄膜晶体管T41’、第四十二薄膜晶体管T42’、第三十一薄膜晶体管T31’、第三十二薄膜晶体管T32’的栅极，由于第四十一薄膜晶体管T41’、第四十二薄膜晶体管T42’、第三十一薄膜晶体管T31’、第三十二薄膜晶体管T32’的源极均接入低电位信号VSS，使此时第四十一薄膜晶体管T41’、第四十二薄膜晶体管T42’、第三十一薄膜晶体管T31’、第三十二薄膜晶体管T32’的栅源极电压差为0，目的是使第四十一薄膜晶体管T41’、第四十二薄膜晶体管T42’、第三十一薄膜晶体管T31’、第三十二薄膜晶体管T32’在GOA单元输出扫描信号G(N)’和级传信号S(N)’时关闭，然而在现有常采用非晶硅薄膜晶体管制作GOA电路的情况下，栅源极电压差为0并不是薄膜晶体管漏电最小的点，这会使第四十一薄膜晶体管T41’、第四十二薄膜晶体管T42’、第三十一薄膜晶体管T31’、第三十二薄膜晶体管T32’产生漏电，影响第一节点Q(N)’的电位，为提升GOA电路的性能，目前的方法是设置两个电位不同的低电位信号来使薄膜晶体管的栅源极为负电压使薄膜晶体管的漏电更小，但使用此方法需要增设信号线，会增加扇出走线(Layout)空间，不利于实现窄边框，同时也会增加信号数量，增加产品成本。
发明内容
本发明的目的在于提供一种GOA电路，能够有效降低第一下拉维持模块中薄膜晶体管的漏电流，避免漏电流对第一节点的电位产生影响，提高电路的稳定性，且无需增加额外的信号线，有利于降低产品成本并实现窄边框。
为实现上述目的，本发明提供一种GOA电路，包括：多级GOA单元，每一级GOA单元均包括：上拉控制模块、输出模块、下拉模块、第一下拉维持模块；
设N为正整数，除第一级至第四级GOA单元和倒数第四级至最后一级GOA单元外，在第N级GOA单元中：
所述上拉控制模块接入上四级第N-4级GOA单元的级传信号和高电位信号，并电性连接第一节点，用于根据第N-4级GOA单元的级传信号上拉第一节点的电位至高电位信号；
所述输出模块接入时钟信号并电性连接第一节点，用于在第一节点的电位控制下输出扫描信号和级传信号；所述下拉模块接入下四级第N+4级GOA单元的扫描信号和低电位信号，并电性连接第一节点，用于根据第N+4 级GOA单元的扫描信号下拉第一节点的电位至低电位信号；
所述第一下拉维持模块接入第一控制信号、低电位信号、扫描信号及电路启动信号，并电性连接第一节点，用于在下拉模块下拉第一节点的电位至低电位信号后将所述扫描信号及第一节点的电位维持在低电位信号；
所述电路启动信号为一脉冲信号，且该电路启动信号的低电位小于低电位信号的电位。
除第一级至第四级GOA单元外，在第N级GOA单元中：所述第一下拉维持模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管；所述第三十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极接入扫描信号；所述第四十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极电性连接第一节点；所述第五十一薄膜晶体管的栅极及源极均接入第一控制信号，漏极电性连接第二节点；所述第五十二薄膜晶体管的栅极接入第一节点，源极接入电路启动信号，漏极电性连接第二节点。
每一级GOA单元还包括：第二下拉维持模块；
除第一级至第四级GOA单元外，在第N级GOA单元中：所述第二下拉维持模块包括第三十二薄膜晶体管、第四十二薄膜晶体管、第六十一薄膜晶体管、第六十二薄膜晶体管；所述第三十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极接入扫描信号；所述第四十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极电性连接第一节点；所述第六十一薄膜晶体管的栅极及源极均接入第二控制信号，漏极电性连接第三节点；所述第六十二薄膜晶体管的栅极接入第一节点，源极接入电路启动信号，漏极电性连接第三节点；
所述第一控制信号与第二控制信号相位相反。
所述时钟信号包括：依次输出的第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号、及第八时钟信号，设X为非负整数，第1+8X级GOA单元、第2+8X级GOA单元、第3+8X级GOA单元、第4+8X级GOA单元、第5+8X级GOA单元、第6+8X级GOA单元、第7+8X级GOA单元、第8+8X级GOA单元中接入的时钟信号分别为第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号、第八时钟信号；
相邻输出的两个时钟信号的上升沿之间的时间间隔为时钟信号一个周期的八分之一，所述时钟信号的占空比为0.4；
所述电路启动信号的高电位的时长等于时钟信号一个周期的四分之三；
所述电路启动信号的上升沿早于第一时钟信号的上升沿，且两者之间的时间间隔为时钟信号一个周期的四分之一。
所述低电位信号的电位与电路启动信号的低电位的差值为1.5-2.5V。
所述电路启动信号的低电位为-8V，低电位信号的电位为-6V。
除第一级至第四级GOA单元外，在第N级GOA单元中：所述上拉控制模块包括第十一薄膜晶体管；所述第十一薄膜晶体管的栅极接入上四级第N-4级GOA单元的级传信号，源极接入高电位信号，漏极电性连接第一节点。
所述输出模块包括第二十一薄膜晶体管、第二十二薄膜晶体管、及第一电容；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出扫描信号；所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出级传信号；所述第一电容的一端电性连接第一节点，另一端电性连接第二十一薄膜晶体管的漏极。
除倒数第四级至最后一级GOA单元外，在第N级GOA单元中：所述下拉模块包括第四十三薄膜晶体管，所述第四十三薄膜晶体管的栅极接入下四级第N+4级GOA单元的扫描信号，源极接入低电位信号，漏极电性连接第一节点；
在倒数第四级至最后一级GOA单元中：所述下拉模块包括第四十三薄膜晶体管，所述第四十三薄膜晶体管的栅极接入电路启动信号，源极接入低电位信号，漏极电性连接第一节点。
在第一级至第四级GOA单元中：
所述上拉控制模块包括第十一薄膜晶体管；所述第十一薄膜晶体管的栅极接入电路启动信号，源极接入高电位信号，漏极电性连接第一节点；所述第一下拉维持模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管；所述第三十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极接入扫描信号；所述第四十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极电性连接第一节点；所述第五十一薄膜晶体管的栅极及源极均接入第一控制信号，漏极电性连接第二节点；所述第五十二薄膜晶体管的栅极接入第一节点，源极接入低电位信号，漏极电性连接第二节点；所述第二下拉维持模块包括第三十二薄膜晶体管、第四十二薄膜晶体管、第六十一薄膜晶体管、第六十二薄膜晶体管；所述第三十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极接入扫描信号；所述第四十二薄膜 晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极电性连接第一节点；所述第六十一薄膜晶体管的栅极及源极均接入第二控制信号，漏极电性连接第三节点；所述第六十二薄膜晶体管的栅极接入第一节点，源极接入低电位信号，漏极电性连接第三节点。
本发明还提供一种GOA电路，包括：多级GOA单元，每一级GOA单元均包括：上拉控制模块、输出模块、下拉模块、第一下拉维持模块；
设N为正整数，除第一级至第四级GOA单元和倒数第四级至最后一级GOA单元外，在第N级GOA单元中：
所述上拉控制模块接入第N-4级GOA单元的级传信号和高电位信号，并电性连接第一节点，用于根据第N-4级GOA单元的级传信号上拉第一节点的电位至高电位信号；
所述输出模块接入时钟信号并电性连接第一节点，用于在第一节点的电位控制下输出扫描信号和级传信号；
所述下拉模块接入第N+4级GOA单元的扫描信号和低电位信号，并电性连接第一节点，用于根据第N+4级GOA单元的扫描信号下拉第一节点的电位至低电位信号；
所述第一下拉维持模块接入第一控制信号、低电位信号、扫描信号及电路启动信号，并电性连接第一节点，用于在下拉模块下拉第一节点的电位至低电位信号后将所述扫描信号及第一节点的电位维持在低电位信号；
所述电路启动信号为一脉冲信号，且该电路启动信号的低电位小于低电位信号的电位；
其中，除第一级至第四级GOA单元外，在第N级GOA单元中：所述第一下拉维持模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管；所述第三十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极接入扫描信号；所述第四十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极电性连接第一节点；所述第五十一薄膜晶体管的栅极及源极均接入第一控制信号，漏极电性连接第二节点；所述第五十二薄膜晶体管的栅极接入第一节点，源极接入电路启动信号，漏极电性连接第二节点；
其中，每一级GOA单元还包括：第二下拉维持模块；
除第一级至第四级GOA单元外，在第N级GOA单元中：所述第二下拉维持模块包括第三十二薄膜晶体管、第四十二薄膜晶体管、第六十一薄膜晶体管、第六十二薄膜晶体管；所述第三十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极接入扫描信号；所述第四十二薄 膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极电性连接第一节点；所述第六十一薄膜晶体管的栅极及源极均接入第二控制信号，漏极电性连接第三节点；所述第六十二薄膜晶体管的栅极接入第一节点，源极接入电路启动信号，漏极电性连接第三节点；
所述第一控制信号与第二控制信号相位相反；
其中，所述时钟信号包括：依次输出的第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号、及第八时钟信号，设X为非负整数，第1+8X级GOA单元、第2+8X级GOA单元、第3+8X级GOA单元、第4+8X级GOA单元、第5+8X级GOA单元、第6+8X级GOA单元、第7+8X级GOA单元、第8+8X级GOA单元中接入的时钟信号分别为第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号、第八时钟信号；
相邻输出的两个时钟信号的上升沿之间的时间间隔为时钟信号一个周期的八分之一，所述时钟信号的占空比为0.4；
所述电路启动信号的高电位的时长等于时钟信号一个周期的四分之三；
所述电路启动信号的上升沿早于第一时钟信号的上升沿，且两者之间的时间间隔为时钟信号一个周期的四分之一；
其中，除第一级至第四级GOA单元外，在第N级GOA单元中：所述上拉控制模块包括第十一薄膜晶体管；所述第十一薄膜晶体管的栅极接入第N-4级GOA单元的级传信号，源极接入高电位信号，漏极电性连接第一节点；
其中，所述输出模块包括第二十一薄膜晶体管、第二十二薄膜晶体管、及第一电容；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出扫描信号；所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出级传信号；所述第一电容的一端电性连接第一节点，另一端电性连接第二十一薄膜晶体管的漏极。
本发明的有益效果：本发明提供的一种GOA电路，该GOA电路在除第一至第四级GOA单元外的每级GOA单元中，第一下拉维持模块接入第一控制信号、低电位信号、扫描信号及电路启动信号，并电性连接第一节点，其中第一下拉维持模块中的第五十二薄膜晶体管栅极电性连接第一节点，源极接入电路启动信号，漏极连接第三十一、第四十一薄膜晶体管的栅极，使在第一节点为高电位时，第三十一、第四十一薄膜晶体管的栅源极电压差均为负值，能够有效降低第一下拉维持单元中薄膜晶体管的漏电 流，避免漏电流对第一节点的电位产生影响，提高电路的稳定性，且无需增加额外的信号线，有利于降低产品成本并实现窄边框。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种GOA电路的电路图；
图2为本发明的GOA电路的电路图；
图3为本发明的GOA电路中第一级至第四级GOA单元的电路图；
图4为本发明的GOA电路中倒数第四级至最后一级GOA单元的电路图；
图5为本发明的GOA电路的工作时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种GOA电路，包括：多级GOA单元，每一级GOA单元均包括：上拉控制模块100、输出模块200、下拉模块300、第一下拉维持模块400；
设N为正整数，除第一级至第四级GOA单元和倒数第四级至最后一级GOA单元外，在第N级GOA单元中：
所述上拉控制模块100接入上四级第N-4级GOA单元的级传信号ST(N-4)和高电位信号Vdd，并电性连接第一节点Q(N)，用于根据第N-4级GOA单元的级传信号ST(N-4)上拉第一节点Q(N)的电位至高电位信号Vdd。
具体地，除第一级至第四级GOA单元外，在第N级GOA单元中：所述上拉控制模块100包括第十一薄膜晶体管T11；所述第十一薄膜晶体管T11的栅极接入上四级第N-4级GOA单元的级传信号ST(N-4)，源极接入高电位信号Vdd，漏极电性连接第一节点Q(N)。
所述输出模块200接入时钟信号CK并电性连接第一节点Q(N)，用于在第一节点Q(N)的电位控制下输出扫描信号G(N)和级传信号ST(N)。
具体地，所述输出模块200包括第二十一薄膜晶体管T21、第二十二薄 膜晶体管T22、及第一电容C1；所述第二十一薄膜晶体管T21的栅极电性连接第一节点Q(N)，源极接入时钟信号CK，漏极输出扫描信号G(N)；所述第二十二薄膜晶体管T22的栅极电性连接第一节点Q(N)，源极接入时钟信号CK，漏极输出级传信号ST(N)；所述第一电容C1的一端电性连接第一节点Q(N)，另一端电性连接第二十一薄膜晶体管T21的漏极。
所述下拉模块300接入下四级第N+4级GOA单元的扫描信号G(N+4)和低电位信号Vss，并电性连接第一节点Q(N)，用于根据第N+4级GOA单元的扫描信号G(N+4)下拉第一节点Q(N)的电位至低电位信号Vss。
具体地，除倒数第四级至最后一级GOA单元外，在第N级GOA单元中：所述下拉模块300包括第四十三薄膜晶体管T43，所述第四十三薄膜晶体管T43的栅极接入下四级第N+4级GOA单元的扫描信号G(N+4)，源极接入低电位信号Vss，漏极电性连接第一节点Q(N)。
所述第一下拉维持模块400接入第一控制信号LC1、低电位信号Vss、扫描信号G(N)及电路启动信号STV，并电性连接第一节点Q(N)，用于在下拉模块300下拉第一节点Q(N)的电位至低电位信号Vss后将所述扫描信号G(N)及第一节点Q(N)的电位维持在低电位信号Vss；所述电路启动信号STV为一脉冲信号，且该电路启动信号STV的低电位小于低电位信号Vss的电位。
具体地，除第一级至第四级GOA单元外，在第N级GOA单元中：所述第一下拉维持模块400包括第三十一薄膜晶体管T31、第四十一薄膜晶体管T41、第五十一薄膜晶体管T51、第五十二薄膜晶体管T52；所述第三十一薄膜晶体管T31的栅极电性连接第二节点P(N)，源极接入低电位信号Vss，漏极接入扫描信号G(N)；所述第四十一薄膜晶体管T41的栅极电性连接第二节点P(N)，源极接入低电位信号Vss，漏极电性连接第一节点Q(N)；所述第五十一薄膜晶体管T51的栅极及源极均接入第一控制信号LC1，漏极电性连接第二节点P(N)；所述第五十二薄膜晶体管T52的栅极接入第一节点Q(N)，源极接入电路启动信号STV，漏极电性连接第二节点P(N)。
进一步地，请参阅图2，每一级GOA单元还包括：第二下拉维持模块500，该第二下拉模块500与第一下拉维持模块400交替工作，在下拉模块300下拉第一节点Q(N)的电位至低电位信号Vss后将所述扫描信号G(N)及第一节点Q(N)的电位维持在低电位信号Vss。
具体地，除第一级至第四级GOA单元外，在第N级GOA单元中：所述第二下拉维持模块500包括第三十二薄膜晶体管T32、第四十二薄膜晶体管T42、第六十一薄膜晶体管T61、第六十二薄膜晶体管T62；所述第三十 二薄膜晶体管T32的栅极电性连接第三节点T(N)，源极接入低电位信号Vss，漏极接入扫描信号G(N)；所述第四十二薄膜晶体管T42的栅极电性连接第三节点T(N)，源极接入低电位信号Vss，漏极电性连接第一节点Q(N)；所述第六十一薄膜晶体管T61的栅极及源极均接入第二控制信号LC2，漏极电性连接第三节点T(N)；所述第六十二薄膜晶体管T62的栅极接入第一节点Q(N)，源极接入电路启动信号STV，漏极电性连接第三节点T(N)。具体地，所述第一控制信号LC1与第二控制信号LC2相位相反。
具体地，所述时钟信号CK包括：依次输出的第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4、第五时钟信号CK5、第六时钟信号CK6、第七时钟信号CK7、及第八时钟信号CK8，设X为非负整数，第1+8X级GOA单元、第2+8X级GOA单元、第3+8X级GOA单元、第4+8X级GOA单元、第5+8X级GOA单元、第6+8X级GOA单元、第7+8X级GOA单元、第8+8X级GOA单元中接入的时钟信号CK分别为第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4、第五时钟信号CK5、第六时钟信号CK6、第七时钟信号CK7、第八时钟信号CK8；相邻输出的两个时钟信号CK的上升沿之间的时间间隔为时钟信号CK一个周期的八分之一，所述时钟信号CK的占空比为0.4；所述电路启动信号STV的高电位的时长等于时钟信号CK一个周期的四分之三；所述电路启动信号STV的上升沿早于第一时钟信号CK1的上升沿，且两者之间的时间间隔为时钟信号CK一个周期的四分之一。
具体地，所述低电位信号Vss的电位与电路启动信号STV的低电位的差值为1.5-2.5V。
优选地，所述电路启动信号STV的低电位为-8V，低电位信号Vss的电位为-6V。
特别地，请参阅图3，在第一级至第四级GOA单元中：
所述上拉控制模块100包括第十一薄膜晶体管T11；所述第十一薄膜晶体管T11的栅极接入电路启动信号STV，源极接入高电位信号Vdd，漏极电性连接第一节点Q(N)；所述第一下拉维持模块400包括第三十一薄膜晶体管T31、第四十一薄膜晶体管T41、第五十一薄膜晶体管T51、第五十二薄膜晶体管T52；所述第三十一薄膜晶体管T31的栅极电性连接第二节点P(N)，源极接入低电位信号Vss，漏极接入扫描信号G(N)；所述第四十一薄膜晶体管T41的栅极电性连接第二节点P(N)，源极接入低电位信号Vss，漏极电性连接第一节点Q(N)；所述第五十一薄膜晶体管T51的栅极及源极均接入第一控制信号LC1，漏极电性连接第二节点P(N)；所述第五十二薄 膜晶体管T52的栅极接入第一节点Q(N)，源极接入低电位信号Vss，漏极电性连接第二节点P(N)；所述第二下拉维持模块500包括第三十二薄膜晶体管T32、第四十二薄膜晶体管T42、第六十一薄膜晶体管T61、第六十二薄膜晶体管T62；所述第三十二薄膜晶体管T32的栅极电性连接第三节点T(N)，源极接入低电位信号Vss，漏极接入扫描信号G(N)；所述第四十二薄膜晶体管T42的栅极电性连接第三节点T(N)，源极接入低电位信号Vss，漏极电性连接第一节点Q(N)；所述第六十一薄膜晶体管T61的栅极及源极均接入第二控制信号LC2，漏极电性连接第三节点T(N)；所述第六十二薄膜晶体管T62的栅极接入第一节点Q(N)，源极接入低电位信号Vss，漏极电性连接第三节点T(N)。
特别地，请参阅图4，在倒数第四级至最后一级GOA单元中：所述下拉模块300包括第四十三薄膜晶体管T43，所述第四十三薄膜晶体管T43的栅极接入电路启动信号STV，源极接入低电位信号Vss，漏极电性连接第一节点Q(N)；上拉控制模块100、输出模块200、第一下拉维持模块400、及第二下拉维持模块500均与第五级至倒数第五级GOA单元中的上拉控制模块100、输出模块200、第一下拉维持模块400、及第二下拉维持模块500相同。
结合图2至图5，本发明的GOA电路的工作过程为：首先电路启动信号STV提供高电位，第一级至第四级GOA单元中的第十一薄膜晶体管T11均打开，第一级至第四级GOA单元中的第一节点的电位上升至高电位，第一级至第四级GOA单元中的第二十一薄膜晶体管T21和第二十二薄膜晶体管T22均打开，接着第一时钟信号CK1输出高电位，第一级GOA单元输出扫描信号和级传信号，接着第二时钟信号CK2输出高电位，第二级GOA单元输出扫描信号和级传信号，接着第三时钟信号CK3输出高电位，第三级GOA单元输出扫描信号和级传信号，接着第四时钟信号CK4输出高电位，第四级GOA单元输出扫描信号和级传信号，所述第一级GOA单元、第二级GOA单元、第三级GOA单元、第四级GOA单元的级传信号分别传递给第五级GOA单元、第六级GOA单元、第七级GOA单元、第八级GOA单元的上拉控制模块100，接收到相应的级传信号后，所述第五级GOA单元、第六级GOA单元、第七级GOA单元、第八级GOA单元的第十一薄膜晶体管T11依次打开，第五时钟信号CK5、第六时钟信号CK6、第七时钟信号CK7、第八时钟信号CK8依次开始提供高电位，所述第五级GOA单元、第六级GOA单元、第七级GOA单元、第八级GOA单元分别在第五时钟信号CK5、第六时钟信号CK6、第七时钟信号CK7、第八时钟信号 CK8的高电位期间输出扫描信号和级传信号，第一级GOA单元、第二级GOA单元、第三级GOA单元、第四级GOA单元的下拉模块300先后分别接收到第五级GOA单元、第六级GOA单元、第七级GOA单元、第八级GOA单元的扫描信号，相应先后下拉第一级GOA单元、第二级GOA单元、第三级GOA单元、第四级GOA单元的第一节点至低电位信号Vss的电位，而后第一下拉维持单元400或第二下拉维持单元500将第一节点以及扫描信号的电位维持在低电位信号Vss的电位，依次类推，直至倒数第四级GOA单元、倒数第三级GOA单元、倒数第二级GOA单元、最后一级GOA单元依次输出扫描信号和级传信号，而后电路启动信号STV再次提供高电位至倒数第四级GOA单元、倒数第三级GOA单元、倒数第二级GOA单元、最后一级GOA单元的下拉模块300，将倒数第四级GOA单元、倒数第三级GOA单元、倒数第二级GOA单元、最后一级GOA单元的第一节点下拉至低电位信号Vss的电位，而后第一下拉维持单元400或第二下拉维持单元500将第一节点及扫描信号的电位维持在低电位信号Vss的电位。
需要说明的是，在除第一级至第四级GOA单元外的第N级GOA单元中，当第N-4级GOA单元的级传信号ST(N-4)为高电位使第十一薄膜晶体管T11打开后，高电位信号Vdd为第一节点Q(N)充电使其变为高电位，此时，受第一节点Q(N)控制的第五十二薄膜晶体管T52及第六十二薄膜晶体管T62打开，使电路启动信号STV的低电位输入第四十一、第三十一、第四十二、及第三十二薄膜晶体管T41、T31、T42、T32的栅极，而第四十一、第三十一、第四十二、及第三十二薄膜晶体管T41、T31、T42、T32的源极均接入低电位信号Vss，由于设置了电路启动信号STV的低电位低于低电位信号Vss的电位，使在第一节点Q(N)为高电位时，第四十一、第三十一、第四十二、及第三十二薄膜晶体管T41、T31、T42、T32的栅源极电压差均为负值，能够有效降低此时第四十一、第三十一、第四十二、及第三十二薄膜晶体管T41、T31、T42、T32的漏电流，避免漏电流对第一节点Q(N)的电位产生影响，提高电路的稳定性，且电路启动信号STV是现有的GOA电路中已有的信号，无需增加额外的信号线，有利于降低产品成本并实现窄边框。
综上所述，本发明的GOA电路，该GOA电路在除第一至第四级GOA单元外的每级GOA单元中，第一下拉维持模块接入第一控制信号、低电位信号、扫描信号及电路启动信号，并电性连接第一节点，其中第一下拉维持模块中的第五十二薄膜晶体管栅极电性连接第一节点，源极接入电路启动信号，漏极连接第三十一、第四十一薄膜晶体管的栅极，使在第一节点 为高电位时，第三十一、第四十一薄膜晶体管的栅源极电压差均为负值，能够有效降低第一下拉维持单元中薄膜晶体管的漏电流，避免漏电流对第一节点的电位产生影响，提高电路的稳定性，且无需增加额外的信号线，有利于降低产品成本并实现窄边框。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (15)

  1. 一种GOA电路，包括：多级GOA单元，每一级GOA单元均包括：上拉控制模块、输出模块、下拉模块、第一下拉维持模块；
    设N为正整数，除第一级至第四级GOA单元和倒数第四级至最后一级GOA单元外，在第N级GOA单元中：
    所述上拉控制模块接入第N-4级GOA单元的级传信号和高电位信号，并电性连接第一节点，用于根据第N-4级GOA单元的级传信号上拉第一节点的电位至高电位信号；
    所述输出模块接入时钟信号并电性连接第一节点，用于在第一节点的电位控制下输出扫描信号和级传信号；
    所述下拉模块接入第N+4级GOA单元的扫描信号和低电位信号，并电性连接第一节点，用于根据第N+4级GOA单元的扫描信号下拉第一节点的电位至低电位信号；
    所述第一下拉维持模块接入第一控制信号、低电位信号、扫描信号及电路启动信号，并电性连接第一节点，用于在下拉模块下拉第一节点的电位至低电位信号后将所述扫描信号及第一节点的电位维持在低电位信号；
    所述电路启动信号为一脉冲信号，且该电路启动信号的低电位小于低电位信号的电位。
  2. 如权利要求1所述的GOA电路，其中，除第一级至第四级GOA单元外，在第N级GOA单元中：所述第一下拉维持模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管；所述第三十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极接入扫描信号；所述第四十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极电性连接第一节点；所述第五十一薄膜晶体管的栅极及源极均接入第一控制信号，漏极电性连接第二节点；所述第五十二薄膜晶体管的栅极接入第一节点，源极接入电路启动信号，漏极电性连接第二节点。
  3. 如权利要求2所述的GOA电路，其中，每一级GOA单元还包括：第二下拉维持模块；
    除第一级至第四级GOA单元外，在第N级GOA单元中：所述第二下拉维持模块包括第三十二薄膜晶体管、第四十二薄膜晶体管、第六十一薄膜晶体管、第六十二薄膜晶体管；所述第三十二薄膜晶体管的栅极电性连 接第三节点，源极接入低电位信号，漏极接入扫描信号；所述第四十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极电性连接第一节点；所述第六十一薄膜晶体管的栅极及源极均接入第二控制信号，漏极电性连接第三节点；所述第六十二薄膜晶体管的栅极接入第一节点，源极接入电路启动信号，漏极电性连接第三节点；
    所述第一控制信号与第二控制信号相位相反。
  4. 如权利要求1所述的GOA电路，其中，所述时钟信号包括：依次输出的第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号、及第八时钟信号，设X为非负整数，第1+8X级GOA单元、第2+8X级GOA单元、第3+8X级GOA单元、第4+8X级GOA单元、第5+8X级GOA单元、第6+8X级GOA单元、第7+8X级GOA单元、第8+8X级GOA单元中接入的时钟信号分别为第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号、第八时钟信号；
    相邻输出的两个时钟信号的上升沿之间的时间间隔为时钟信号一个周期的八分之一，所述时钟信号的占空比为0.4；
    所述电路启动信号的高电位的时长等于时钟信号一个周期的四分之三；
    所述电路启动信号的上升沿早于第一时钟信号的上升沿，且两者之间的时间间隔为时钟信号一个周期的四分之一。
  5. 如权利要求1所述的GOA电路，其中，所述低电位信号的电位与电路启动信号的低电位的差值为1.5-2.5V。
  6. 如权利要求5所述的GOA电路，其中，所述电路启动信号的低电位为-8V，低电位信号的电位为-6V。
  7. 如权利要求1所述的GOA电路，其中，除第一级至第四级GOA单元外，在第N级GOA单元中：所述上拉控制模块包括第十一薄膜晶体管；所述第十一薄膜晶体管的栅极接入第N-4级GOA单元的级传信号，源极接入高电位信号，漏极电性连接第一节点。
  8. 如权利要求1所述的GOA电路，其中，所述输出模块包括第二十一薄膜晶体管、第二十二薄膜晶体管、及第一电容；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出扫描信号；所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出级传信号；所述第一电容的一端电性连接第一节点，另一端电性连接第二十一薄膜晶体管的漏极。
  9. 如权利要求1所述的GOA电路，其中，除倒数第四级至最后一级 GOA单元外，在第N级GOA单元中：所述下拉模块包括第四十三薄膜晶体管，所述第四十三薄膜晶体管的栅极接入第N+4级GOA单元的扫描信号，源极接入低电位信号，漏极电性连接第一节点；
    在倒数第四级至最后一级GOA单元中：所述下拉模块包括第四十三薄膜晶体管，所述第四十三薄膜晶体管的栅极接入电路启动信号，源极接入低电位信号，漏极电性连接第一节点。
  10. 如权利要求3所述的GOA电路，其中，在第一级至第四级GOA单元中：
    所述上拉控制模块包括第十一薄膜晶体管；所述第十一薄膜晶体管的栅极接入电路启动信号，源极接入高电位信号，漏极电性连接第一节点；所述第一下拉维持模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管；所述第三十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极接入扫描信号；所述第四十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极电性连接第一节点；所述第五十一薄膜晶体管的栅极及源极均接入第一控制信号，漏极电性连接第二节点；所述第五十二薄膜晶体管的栅极接入第一节点，源极接入低电位信号，漏极电性连接第二节点；所述第二下拉维持模块包括第三十二薄膜晶体管、第四十二薄膜晶体管、第六十一薄膜晶体管、第六十二薄膜晶体管；所述第三十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极接入扫描信号；所述第四十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极电性连接第一节点；所述第六十一薄膜晶体管的栅极及源极均接入第二控制信号，漏极电性连接第三节点；所述第六十二薄膜晶体管的栅极接入第一节点，源极接入低电位信号，漏极电性连接第三节点。
  11. 一种GOA电路，包括：多级GOA单元，每一级GOA单元均包括：上拉控制模块、输出模块、下拉模块、第一下拉维持模块；
    设N为正整数，除第一级至第四级GOA单元和倒数第四级至最后一级GOA单元外，在第N级GOA单元中：
    所述上拉控制模块接入第N-4级GOA单元的级传信号和高电位信号，并电性连接第一节点，用于根据第N-4级GOA单元的级传信号上拉第一节点的电位至高电位信号；
    所述输出模块接入时钟信号并电性连接第一节点，用于在第一节点的电位控制下输出扫描信号和级传信号；
    所述下拉模块接入第N+4级GOA单元的扫描信号和低电位信号，并 电性连接第一节点，用于根据第N+4级GOA单元的扫描信号下拉第一节点的电位至低电位信号；
    所述第一下拉维持模块接入第一控制信号、低电位信号、扫描信号及电路启动信号，并电性连接第一节点，用于在下拉模块下拉第一节点的电位至低电位信号后将所述扫描信号及第一节点的电位维持在低电位信号；
    所述电路启动信号为一脉冲信号，且该电路启动信号的低电位小于低电位信号的电位；
    其中，除第一级至第四级GOA单元外，在第N级GOA单元中：所述第一下拉维持模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管；所述第三十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极接入扫描信号；所述第四十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极电性连接第一节点；所述第五十一薄膜晶体管的栅极及源极均接入第一控制信号，漏极电性连接第二节点；所述第五十二薄膜晶体管的栅极接入第一节点，源极接入电路启动信号，漏极电性连接第二节点；
    其中，每一级GOA单元还包括：第二下拉维持模块；
    除第一级至第四级GOA单元外，在第N级GOA单元中：所述第二下拉维持模块包括第三十二薄膜晶体管、第四十二薄膜晶体管、第六十一薄膜晶体管、第六十二薄膜晶体管；所述第三十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极接入扫描信号；所述第四十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极电性连接第一节点；所述第六十一薄膜晶体管的栅极及源极均接入第二控制信号，漏极电性连接第三节点；所述第六十二薄膜晶体管的栅极接入第一节点，源极接入电路启动信号，漏极电性连接第三节点；
    所述第一控制信号与第二控制信号相位相反；
    其中，所述时钟信号包括：依次输出的第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号、及第八时钟信号，设X为非负整数，第1+8X级GOA单元、第2+8X级GOA单元、第3+8X级GOA单元、第4+8X级GOA单元、第5+8X级GOA单元、第6+8X级GOA单元、第7+8X级GOA单元、第8+8X级GOA单元中接入的时钟信号分别为第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号、第八时钟信号；
    相邻输出的两个时钟信号的上升沿之间的时间间隔为时钟信号一个周 期的八分之一，所述时钟信号的占空比为0.4；
    所述电路启动信号的高电位的时长等于时钟信号一个周期的四分之三；
    所述电路启动信号的上升沿早于第一时钟信号的上升沿，且两者之间的时间间隔为时钟信号一个周期的四分之一；
    其中，除第一级至第四级GOA单元外，在第N级GOA单元中：所述上拉控制模块包括第十一薄膜晶体管；所述第十一薄膜晶体管的栅极接入第N-4级GOA单元的级传信号，源极接入高电位信号，漏极电性连接第一节点；
    其中，所述输出模块包括第二十一薄膜晶体管、第二十二薄膜晶体管、及第一电容；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出扫描信号；所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出级传信号；所述第一电容的一端电性连接第一节点，另一端电性连接第二十一薄膜晶体管的漏极。
  12. 如权利要求11所述的GOA电路，其中，所述低电位信号的电位与电路启动信号的低电位的差值为1.5-2.5V。
  13. 如权利要求11所述的GOA电路，其中，所述电路启动信号的低电位为-8V，低电位信号的电位为-6V。
  14. 如权利要求11所述的GOA电路，其中，除倒数第四级至最后一级GOA单元外，在第N级GOA单元中：所述下拉模块包括第四十三薄膜晶体管，所述第四十三薄膜晶体管的栅极接入第N+4级GOA单元的扫描信号，源极接入低电位信号，漏极电性连接第一节点；
    在倒数第四级至最后一级GOA单元中：所述下拉模块包括第四十三薄膜晶体管，所述第四十三薄膜晶体管的栅极接入电路启动信号，源极接入低电位信号，漏极电性连接第一节点。
  15. 如权利要求11所述的GOA电路，其中，在第一级至第四级GOA单元中：
    所述上拉控制模块包括第十一薄膜晶体管；所述第十一薄膜晶体管的栅极接入电路启动信号，源极接入高电位信号，漏极电性连接第一节点；所述第一下拉维持模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管；所述第三十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极接入扫描信号；所述第四十一薄膜晶体管的栅极电性连接第二节点，源极接入低电位信号，漏极电性连接第一节点；所述第五十一薄膜晶体管的栅极及源极均接入第一控制信号，漏极电性连接第二节点；所述第五十二薄膜晶体管的栅极接入 第一节点，源极接入低电位信号，漏极电性连接第二节点；所述第二下拉维持模块包括第三十二薄膜晶体管、第四十二薄膜晶体管、第六十一薄膜晶体管、第六十二薄膜晶体管；所述第三十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极接入扫描信号；所述第四十二薄膜晶体管的栅极电性连接第三节点，源极接入低电位信号，漏极电性连接第一节点；所述第六十一薄膜晶体管的栅极及源极均接入第二控制信号，漏极电性连接第三节点；所述第六十二薄膜晶体管的栅极接入第一节点，源极接入低电位信号，漏极电性连接第三节点。
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