WO2019090908A1 - 一种液晶显示面板和栅极驱动电路 - Google Patents

一种液晶显示面板和栅极驱动电路 Download PDF

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Publication number
WO2019090908A1
WO2019090908A1 PCT/CN2017/117313 CN2017117313W WO2019090908A1 WO 2019090908 A1 WO2019090908 A1 WO 2019090908A1 CN 2017117313 W CN2017117313 W CN 2017117313W WO 2019090908 A1 WO2019090908 A1 WO 2019090908A1
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Prior art keywords
signal
gate
data
pixel
driving
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PCT/CN2017/117313
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English (en)
French (fr)
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李文英
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/742,504 priority Critical patent/US10475408B2/en
Priority to EP17931182.4A priority patent/EP3709286A4/en
Priority to JP2020517338A priority patent/JP2020535470A/ja
Priority to KR1020207015952A priority patent/KR20200075004A/ko
Publication of WO2019090908A1 publication Critical patent/WO2019090908A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the liquid crystal display panel is widely used in various electronic products because of its high display quality, low price, convenient carrying, etc. With the continuous development of liquid crystal display technology, a new driving method is needed to cope with the gradually reduced panel cost, generally adopting reduced data.
  • the number of signal lines, and the gate side is implemented by GOA (Gate driver on Array) technology.
  • GOA Gate driver on Array
  • In the liquid crystal display panel if a positive voltage or a negative voltage is always used to drive the liquid crystal molecules, it is easy to cause damage to the liquid crystal molecules. Therefore, in order to protect the liquid crystal molecules from the driving voltage, it is necessary to drive the liquid crystal molecules using a positive and negative voltage interaction.
  • common polarity inversion methods include frame inversion, line inversion, column inversion, and dot inversion.
  • the dot inversion method can achieve the best picture effect, so it is widely used.
  • the charging rate of the pixel unit in which polarity inversion occurs during charging is low, and the charging rate of the pixel unit in which polarity inversion does not occur during charging is high.
  • the difference in charging rate causes dark lines on the display panel to reduce the display effect and affect the user experience.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display panel and a gate driving circuit, which can reduce the difference in brightness on the display panel and improve the display effect.
  • a technical solution adopted by the present invention is to provide a liquid crystal display panel including: a plurality of pixel units arranged in a matrix manner; a plurality of scanning lines, each of which is described in two The scan lines correspond to the pixel units in the same row and are alternately connected to the pixel units in the same row of pixel units; a gate driving circuit is configured to sequentially provide gate driving signals on the scan lines to control the The pixel unit connected to the scan line is turned on; a plurality of data lines, each of which is connected to two adjacent columns of the pixel unit; and a data driving circuit for inverting the data line to the data line Providing a data driving signal to charge the pixel unit connected to the data line and in an open state; wherein gate driving signals corresponding to two scanning lines of the same row of pixel units have different Driving capability, thereby eliminating charging differences caused by polarity inversion of the data drive signal.
  • another technical solution adopted by the present invention is to provide a gate driving circuit mounted in a liquid crystal display panel, the gate driving circuit including a first driving stage and a second driving stage, The first driving stage receives the first clock signal and outputs a first gate driving signal in response to the first clock signal, the second driving stage receives the second clock signal, and outputs the second gate in response to the second clock signal a pole drive signal, wherein the first clock signal and the second clock signal are disposed such that a driving capability of the first gate driving signal is different from a driving capability of the second gate driving signal.
  • the beneficial effects of the present invention are: different from the prior art, the present invention achieves elimination by making the gate driving signals on the two scanning lines corresponding to the same row of pixel units in the display panel have different driving capabilities.
  • FIG. 1 is a schematic structural view of a first embodiment of a liquid crystal display panel provided by the present invention
  • FIG. 2 is a schematic diagram of a first embodiment of a clock signal, a gate driving signal, and a charging voltage of a pixel unit provided by the present invention
  • FIG. 3 is a schematic diagram of a second embodiment of a clock signal, a gate driving signal, and a charging voltage of a pixel unit provided by the present invention
  • FIG. 4 is a schematic diagram of a third embodiment of a clock signal, a gate driving signal, and a charging voltage of a pixel unit provided by the present invention
  • FIG. 1 is a partial structural diagram of an embodiment of a liquid crystal display panel provided by the present invention.
  • the liquid crystal display panel 30 includes a plurality of pixel units such as Pixel 11, Pixel 12, Pixel 13, Pixel 14, Pixel 21, Pixel 22, Pixel 23, Pixel 24. These pixel units are arranged in a matrix.
  • the gate driving circuit 31 is located at one side of the liquid crystal display panel 30 and includes a first driving stage 311, a second driving stage 312, a third driving stage 313, and a fourth driving stage 314.
  • the gate driving circuit 31 is connected to the scan line for sequentially providing gate driving signals on the plurality of scanning lines to control the pixel units connected to the scanning lines to be turned on line by line.
  • the scan line G1 is connected to the first driver stage 311, the scan line G2 is connected to the second driver stage 312, the scan line G3 is connected to the third driver stage 313, and the scan line G4 is connected to the fourth driver stage 314.
  • Each of the two scan lines corresponds to a pixel unit of the same row, and is alternately connected to a pixel unit in the same row of pixel units.
  • the scan line G1 and the scan line G2 correspond to the pixel unit Pixel 11, Pixel 12, Pixel 21, Pixel 22 of the same row
  • the scan line G1 is connected to the pixel unit Pixel 11
  • the scan line G2 is connected in the same row as the pixel unit Pixel 11
  • the adjacent pixel unit Pixel 12 is connected to the adjacent pixel unit Pixel 21 in the same row as the pixel unit Pixel 12
  • the scanning line G2 is connected to the adjacent pixel unit Pixel 22 in the same row as the pixel unit Pixel 21.
  • the data driving circuit 32 is located at one side of the liquid crystal display panel 30, and is connected to a plurality of data lines to charge the pixel unit connected to the data line and driven to be driven by the gate driving signal.
  • Each data line is connected to two adjacent columns of pixel units.
  • the data line D1 is simultaneously connected to a column in which the pixel unit Pixel 11, Pixel 13 is located, and a column in which the pixel units Pixel 12 and Pixel 14 adjacent to the column are located.
  • the scan line G1, the scan line G2, the scan line G3, and the scan line G4 are perpendicular to the data lines D1, D2, and D3, respectively. In other implementation scenarios, the scan line G1, the scan line G2, the scan line G3, and the scan line G4 are not necessarily perpendicular to the data lines D1, D2, and D3, and may have an angle of any size.
  • FIG. 2 is a schematic diagram of a pulse of a first embodiment of a pixel unit charging effect provided by the present invention.
  • the signal CK 1 is the first clock driving signal received by the first driving stage 311, the signal CK 2 is the second clock driving signal received by the second driving stage 312, and the signal CK 3 is the third clock driving signal received by the third driving stage 313.
  • the signal CK 4 is the fourth clock drive signal received by the fourth driver stage 314.
  • the signal CK 1, the signal CK 2, the signal CK 3 and the signal CK 4 have the same period, and the phases are sequentially shifted by a quarter of a period.
  • the signal Gate 1 is a first gate driving signal that the first driving stage 311 outputs to the gate line G1 according to the signal CK 1
  • the signal Gate 2 is a second gate that the second driving stage 312 outputs to the gate line G2 according to the signal CK 2
  • the pole drive signal, the signal Gate 3 is a third gate drive signal that the third driver stage 313 outputs to the gate line G3 according to the signal CK 3
  • the signal Gate 4 is the fourth driver stage 314 outputs the gate line G4 according to the signal CK 4 .
  • the signal Gate 1, the signal Gate 2, the signal Gate 3 and the signal Gate 4 have the same period, and the phases are sequentially shifted by a quarter of a cycle.
  • the signal Gate 1 drives the pixel unit Pixel 11 connected to the gate line G1
  • the signal Gate 2 drives the pixel unit Pixel 12 connected to the gate line G2
  • the signal Gate 3 drives the pixel unit Pixel connected to the gate line G3
  • the signal Gate 4 drives the gate.
  • Pixel 14 connected to the pixel line G1.
  • the signals CK 1 and CK 3 have the same pulse amplitude
  • the signals CK 2 and CK 4 have the same pulse amplitude
  • the pulse amplitudes of the signals CK 1 and CK 3 are higher than the pulse amplitudes of CK 2 and CK 4 by ⁇ V. . Therefore, the signal Gate 1 outputted from the signal CK 1 and the signal Gate 3 outputted according to the signal CK 3 have pulses of the same magnitude, and the signal Gate 2 outputted according to the signal CK 2 and the signal Gate 4 outputted according to the signal CK 4 have pulses of the same magnitude. Therefore, the pulse amplitudes of the signals Gate 1 and Signal 3 are higher than the pulse amplitudes of the signals Gate 2 and Signal 4 by ⁇ V.
  • the charging efficiency of the pixel units Pixel 11 and Pixel 13 driven by the signals Gate 1 and Signal Gate 3 is higher than that of the pixel units Pixel 12 and Pixel 14 driven by the signals Gate 2 and Signal Gate 4.
  • the pulse amplitudes of the signals CK 1 and CK 3 are greater than the pulse amplitudes of the signals CK 2 and CK 4 by increasing the pulse amplitudes of the signals CK 1 and CK 3 .
  • This can be achieved by reducing the pulse amplitude of the signal CK 2 and the signal CK 4, or simultaneously increasing the pulse amplitudes of the signals CK 1 and CK 3 and reducing the pulse amplitudes of the signals CK 2 and CK 4 .
  • the signal Data 1 is a data signal input from the data driving circuit 32 to the data line D1
  • the signal Data 2 is a data signal input from the data driving circuit 32 to the data line D2.
  • the signal Data 1 has the same period as the signal Data 2 and has opposite polarities.
  • the pixel unit Pixel 11 is turned on before the polarity of the signal Data 1 is inverted under the driving of the signal Gate 1, and the pixel unit Pixel 11 is received in the first quarter of the period when the pixel unit Pixel 11 is in the on state.
  • the high level charge of the Data 1 input receives the low level charge input by the Data 1 input in the last quarter of the cycle when the Gate 1 is driven, and the polarity reversal occurs during the charging time.
  • the charging is not complete.
  • the pixel unit Pixel 12 is turned on after the polarity of the signal Data 1 is inverted by the driving of the signal Gate 2, and the pixel unit Pixel 12 is in the open state for all the time, receiving the low level charge input by the Data 1, and the pole is not present. Sexual reversal, charging is complete.
  • the charging efficiency of the pixel unit Pixel 11 driven by the signal Gate 1 is higher than that of the pixel unit Pixel 12 driven by the signal Gate 2, so that although the pixel unit Pixel 11 undergoes polarity inversion during charging, the charging amount of the pixel unit Pixel 11 is The difference in pixel unit Pixel 12 is small.
  • the same pixel unit Pixel 13 is turned on before the polarity of the signal Data 1 is reversed under the driving of the signal Gate 3, and the input by the Data 1 is received in the first quarter of the period when the pixel unit Pixel 13 is in the on state.
  • Low-level charging receiving the high-level charge input by Data 1 during the last quarter of the period when the Gate 3 is turned on, the polarity is reversed during the charging time, and the charging is incomplete.
  • the pixel unit Pixel 14 is turned on after the polarity of the signal Data 1 is inverted under the driving of the signal Gate 4, and the pixel unit Pixel 13 is in the open state for all time, receiving the high level charge input by the Data 1 without polarity. Reverse, charging is complete.
  • the charging efficiency of the pixel unit Pixel 13 driven by the signal Gate 3 is higher than that of the pixel unit Pixel 14 driven by the signal Gate 4, so although the pixel unit Pixel 13 undergoes polarity inversion during charging, the charging amount of the pixel unit Pixel 13 is The difference in pixel unit Pixel 14 is small.
  • the charging principle of the pixel unit Pixel 21, Pixel 22, Pixel 23, and Pixel 24 is similar to that of the pixel unit Pixel 11, Pixel 12, Pixel 13, and Pixel 14, and will not be described herein.
  • the gate driving circuit may further include six or eight or more driving stages, and only the number of driving stages is required to be an even number.
  • the present embodiment improves the charging efficiency of the pixel driving signals of the pixel units that are used to drive the polarity inversion when charging is performed, so that the polarity inversion occurs during charging.
  • the difference between the amount of charge of the pixel unit and the amount of charge of the pixel unit in which the polarity is not reversed during charging is reduced, thereby reducing the difference in brightness of the screen and improving the display effect.
  • FIG. 3 is a schematic diagram of a pulse of a second embodiment of the charging effect of the pixel unit provided by the present invention.
  • the signal CK 1 is the first clock driving signal received by the first driving stage 311, the signal CK 2 is the second clock driving signal received by the second driving stage 312, and the signal CK 3 is the third clock driving signal received by the third driving stage 313.
  • the signal CK 4 is the fourth clock drive signal received by the fourth driver stage 314.
  • the signal CK 1, the signal CK 2, the signal CK 3 and the signal CK 4 have the same period, and the phases are sequentially shifted by a quarter of a period.
  • the signal Gate 1 is a first gate driving signal that the first driving stage 311 outputs to the gate line G1 according to the signal CK 1
  • the signal Gate 2 is a second gate that the second driving stage 312 outputs to the gate line G2 according to the signal CK 2
  • the pole drive signal, the signal Gate 3 is a third gate drive signal that the third driver stage 313 outputs to the gate line G3 according to the signal CK 3
  • the signal Gate 4 is the fourth driver stage 314 outputs the gate line G4 according to the signal CK 4 .
  • the signal Gate 1, the signal Gate 2, the signal Gate 3 and the signal Gate 4 have the same period, and the phases are sequentially shifted by a quarter of a cycle.
  • the signal Gate 1 drives the pixel unit Pixel 11 connected to the gate line G1
  • the signal Gate 2 drives the pixel unit Pixel 12 connected to the gate line G2
  • the signal Gate 3 drives the pixel unit Pixel connected to the gate line G3
  • the signal Gate 4 drives the gate.
  • Pixel 14 connected to the pixel line G1.
  • Signal CK 1 and signal CK 3 have the same pulse amplitude
  • signal CK 2 and signal CK 4 have the same pulse amplitude
  • the second half of the pulse amplitude of signal CK 1 and signal CK 3 is larger than the pulse of CK 2 and signal CK 4
  • the amplitude is higher than ⁇ V. Therefore, the signal Gate 1 outputted from the signal CK 1 and the signal Gate 3 outputted according to the signal CK 3 have pulses of the same magnitude, and the signal Gate 2 outputted according to the signal CK 2 and the signal Gate 4 outputted according to the signal CK 4 have pulses of the same magnitude. Therefore, the second half of the pulse amplitude of the signals Gate 1 and Signal Gate 3 is higher than the pulse amplitude of the signals Gate 2 and Signal 4 by ⁇ V.
  • the charging efficiency of the pixel units Pixel 11 and Pixel 13 driven by the signals Gate 1 and Signal Gate 3 is higher than that of the pixel units Pixel 12 and Pixel 14 driven by the signals Gate 2 and Signal Gate 4.
  • the pulse amplitudes of the signals CK 1 and CK 3 are greater than the pulse amplitudes of the signals CK 2 and CK 4 by increasing the pulse amplitudes of the second half of the signals CK 1 and CK 3 , in other embodiments. In the middle, it is also possible to reduce the pulse amplitude of the signal CK 2 and the signal CK 4, or simultaneously increase the pulse amplitude of the second half of the signals CK 1 and CK 3 and reduce the pulse amplitudes of the signals CK 2 and CK 4 . .
  • the ratio of the time of the high pulse of the signal CK 1 and the signal CK 3 may be any ratio, not necessarily the ratio of 50% as shown in FIG.
  • the signal Data 1 is a data signal input from the data driving circuit 32 to the data line D1
  • the signal Data 2 is a data signal input from the data driving circuit 32 to the data line D2.
  • the signal Data 1 has the same period as the signal Data 2 and has opposite polarities.
  • the pixel unit Pixel 11 is turned on before the polarity of the signal Data 1 is inverted under the driving of the signal Gate 1, and the pixel unit Pixel 11 is received in the first quarter of the period when the pixel unit Pixel 11 is in the on state.
  • the high level charge of the Data 1 input receives the low level charge input by the Data 1 input in the last quarter of the cycle when the Gate 1 is driven, and the polarity reversal occurs during the charging time.
  • the charging is not complete.
  • the pixel unit Pixel 12 is turned on after the polarity of the signal Data 1 is inverted by the driving of the signal Gate 2, and the pixel unit Pixel 12 is in the open state for all the time, receiving the low level charge input by the Data 1, and the pole is not present. Sexual reversal, charging is complete.
  • the charging efficiency of the pixel unit Pixel 11 driven by the signal Gate 1 is higher than that of the pixel unit Pixel 12 driven by the signal Gate 2, so that although the pixel unit Pixel 11 undergoes polarity inversion during charging, the charging amount of the pixel unit Pixel 11 is The difference in pixel unit Pixel 12 is small.
  • the same pixel unit Pixel 13 is turned on before the polarity of the signal Data 1 is reversed under the driving of the signal Gate 3, and the input by the Data 1 is received in the first quarter of the period when the pixel unit Pixel 13 is in the on state.
  • Low-level charging receiving the high-level charge input by Data 1 during the last quarter of the period when the Gate 3 is turned on, the polarity is reversed during the charging time, and the charging is incomplete.
  • the pixel unit Pixel 14 is turned on after the polarity of the signal Data 1 is inverted under the driving of the signal Gate 4, and the pixel unit Pixel 13 is in the open state for all time, receiving the high level charge input by the Data 1 without polarity. Reverse, charging is complete.
  • the charging efficiency of the pixel unit Pixel 13 driven by the signal Gate 3 is higher than that of the pixel unit Pixel 14 driven by the signal Gate 4, so although the pixel unit Pixel 13 undergoes polarity inversion during charging, the charging amount of the pixel unit Pixel 13 is The difference in pixel unit Pixel 14 is small.
  • the charging principle of the pixel unit Pixel 21, Pixel 22, Pixel 23, and Pixel 24 is similar to that of the pixel unit Pixel 11, Pixel 12, Pixel 13, and Pixel 14, and will not be described herein.
  • FIG. 4 is a schematic diagram of a pulse of a third embodiment of the charging effect of the pixel unit provided by the present invention.
  • the signal CK 1 is the first clock driving signal received by the first driving stage 311, the signal CK 2 is the second clock driving signal received by the second driving stage 312, and the signal CK 3 is the third clock driving signal received by the third driving stage 313.
  • the signal CK 4 is the fourth clock drive signal received by the fourth driver stage 314.
  • the signal CK 1, the signal CK 2, the signal CK 3 and the signal CK 4 have the same period, and the phases are sequentially shifted by a quarter of a period.
  • the signal Gate 1 is a first gate driving signal that the first driving stage 311 outputs to the gate line G1 according to the signal CK 1
  • the signal Gate 2 is a second gate that the second driving stage 312 outputs to the gate line G2 according to the signal CK 2
  • the pole drive signal, the signal Gate 3 is a third gate drive signal that the third driver stage 313 outputs to the gate line G3 according to the signal CK 3
  • the signal Gate 4 is the fourth driver stage 314 outputs the gate line G4 according to the signal CK 4 .
  • the signal Gate 1, the signal Gate 2, the signal Gate 3 and the signal Gate 4 have the same period, and the phases are sequentially shifted by a quarter of a cycle.
  • the signal Gate 1 drives the pixel unit Pixel 11 connected to the gate line G1
  • the signal Gate 2 drives the pixel unit Pixel 12 connected to the gate line G2
  • the signal Gate 3 drives the pixel unit Pixel connected to the gate line G3
  • the signal Gate 4 drives the gate.
  • Pixel 14 connected to the pixel line G1.
  • the signal CK 1 and the signal CK 3 have the same pulse width
  • the signal CK 2 and the signal CK 4 have the same pulse width
  • the pulse widths of the signals CK 1 and CK 3 are larger than the pulse widths of the signals CK 2 and CK 4 . Therefore, the signal Gate 1 outputted from the signal CK 1 and the signal Gate 3 outputted according to the signal CK 3 have pulses of the same width, and the signal Gate 2 outputted according to the signal CK 2 and the signal Gate 4 outputted according to the signal CK 4 have pulses of the same width. And the pulse widths of the signals Gate 1 and Signal 3 are larger than the pulse widths of the signals Gate 2 and Signal 4 .
  • the pixel units Pixel 11 and Pixel 13 driven by the signals Gate 1 and Signal Gate 3 have a longer charging time than the pixel units Pixel 12 and Pixel 14 driven by the signals Gate 2 and Signal Gate 4.
  • the pulse widths of the signals CK 1 and CK 3 are made larger than the signal CK 2 by increasing the pulse widths of the signals CK 1 and CK 3 and decreasing the pulse widths of the signals CK 2 and CK 4 .
  • the pulse width of the signal CK 4 can also be achieved by reducing the pulse width of the signal CK 2 and the signal CK 4 or increasing the pulse width of the signal CK 1 and the signal CK 3 in other embodiments.
  • the signal Data 1 is a data signal input from the data driving circuit 32 to the data line D1
  • the signal Data 2 is a data signal input from the data driving circuit 32 to the data line D2.
  • the signal Data 1 has the same period as the signal Data 2 and has opposite polarities.
  • the pixel unit Pixel 11 is turned on before the polarity of the signal Data 1 is inverted under the driving of the signal Gate 1, and the pixel unit Pixel 11 is received in the first quarter of the period when the pixel unit Pixel 11 is in the on state.
  • the high level charge of the Data 1 input receives the low level charge input by the Data 1 input in the last quarter of the cycle when the Gate 1 is driven, and the polarity reversal occurs during the charging time. The charging is not complete.
  • the pixel unit Pixel 12 is turned on after the polarity of the signal Data 1 is inverted by the driving of the signal Gate 2, and the pixel unit Pixel 12 is in the open state for all the time, receiving the low level charge input by the Data 1, and the pole is not present.
  • the pulse width of the signal Gate 1 is large, and the pixel unit Pixel 11 has a longer time to charge after the polarity is reversed, and can charge more power, and the pulse width of the signal Gate 2 is smaller, and the pixel unit Pixel 12
  • the charging time is short and the charging amount is small, so the difference between the charging amount of the pixel unit Pixel 11 and the pixel unit Pixel 12 is small.
  • the same pixel unit Pixel 13 receives the low level charge input by Data 1 in the first quarter of the period when the signal Gate 3 is driven in the open state, and is turned on when the Gate 3 is driven.
  • the time after the last quarter of the cycle receives the high level charge input by Data 1, the polarity is reversed during the charging time, and the charging is incomplete.
  • the pixel unit Pixel 14 receives the high level charge input by the Data 1 for the entire time in which the signal Gate 4 is driven to be turned on, and the polarity inversion does not occur, and the charging is completed.
  • the pulse width of the signal Gate 3 is large, and the pixel unit Pixel 13 has a longer time to charge after the polarity is reversed, and can charge more power, and the pulse width of the signal Gate 4 is smaller, and the pixel unit Pixel 14
  • the charging time is short and the charging amount is small, so the difference between the charging amount of the pixel unit Pixel 13 and the pixel unit Pixel 14 is small.
  • the charging principle of the pixel unit Pixel 21, Pixel 22, Pixel 23, and Pixel 24 is similar to that of the pixel unit Pixel 11, Pixel 12, Pixel 13, and Pixel 14, and will not be described herein.
  • the gate driving circuit may further include six or eight or more driving stages, and only the number of driving stages is required to be an even number.
  • the present embodiment extends the charging time of the pixel driving signals of the pixel units for inverting the polarity when driving the charging, so that the charging time of the pixel units is prolonged, so that the polarity is reversed during charging.
  • the difference between the amount of charge of the rotated pixel unit and the amount of charge of the pixel unit in which the polarity is not reversed during charging is reduced, thereby reducing the difference in brightness of the screen and improving the display effect.
  • the gate driving signals on the two scanning lines of the pixel row of the same row on the liquid crystal display panel of the present invention have different driving capabilities, so that the pixel unit with polarity inversion occurs during charging.
  • the difference between the amount of electricity and the amount of charge charged by the pixel unit in which the polarity is not reversed during charging is reduced, so that the difference in brightness of the screen is reduced, and the display effect is improved.

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Abstract

一种液晶显示面板和栅极驱动电路。该液晶显示面板（30）包括：多个以矩阵方式排列的像素单元（Pixel 11-Pixel 24）；多条扫描线（G1-G5），每两条所述扫描线对应同一行像素单元且交替与同一行像素单元内的像素单元连接；栅极驱动电路（31）；多条数据线（D1-D3），每条数据线分别与相邻的两列像素单元连接；数据驱动电路（32）；其中，对应于同一行像素单元的两条扫描线上的栅极驱动信号具有不同的驱动能力。通过上述方式，能够减轻显示面板（30）上的亮度差异，提升显示效果。

Description

一种液晶显示面板和栅极驱动电路 【背景技术】
液晶显示面板以其高显示品质、价格低廉、携带方便等优点广泛应用于各种电子产品中，随着液晶显示器技术不断发展，需要新的驱动方法来应对逐渐降低的面板成本，一般采用降低data信号线的条数，同时gate侧采用GOA(Gate driver on Array)技术来实现。在液晶显示面板中，如果一直使用正电压或者负电压来驱动液晶分子，很容易使液晶分子造成损害。因此，为了保护液晶分子不受驱动电压的破坏，必须使用正负电压交互的方式来驱动液晶分子。目前常见的极性反转方式有帧反转、行反转、列反转以及点反转。其中，点反转的方式能够达到最佳的画面效果，因此得到广泛的应用。然而，充电时发生极性反转的像素单元的充电率低，充电时未发生极性反转的像素单元的充电率高。充电率的差异会造成显示面板上出现暗线亮线，降低显示效果，影响用户体验。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示面板和栅极驱动电路，能够减轻显示面板上的亮度差异，提升显示效果。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示面板，包括：多个像素单元，所述多个像素单元以矩阵方式排列；多条扫描线，每两条所述扫描线对应同一行所述像素单元且交替与所述同一行像素单元内的所述像素单元连接；栅极驱动电路，用于依次在所述扫描线上提供栅极驱动信号，以控制所述扫描线所连接的所述像素单元打开；多条数据线，每条数据线分别与相邻的两列所述像素单元连接；数据驱动电路，用于以极性反转方式向所述数据线提供数据驱动信号，以对所述数据线所连接的且处于打开状态的所述像素单元进行充电；其 中，对应于所述同一行像素单元的两条扫描线上的栅极驱动信号具有不同的驱动能力，由此消除因所述数据驱动信号的极性反转所引起的充电差异。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种安装于液晶显示面板中的栅极驱动电路，所述栅极驱动电路包括第一驱动级和第二驱动级，所述第一驱动级接收第一时钟信号，并响应所述第一时钟信号输出第一栅极驱动信号，所述第二驱动级接收第二时钟信号，并响应所述第二时钟信号输出第二栅极驱动信号，其中所述第一时钟信号和所述第二时钟信号设置成使得所述第一栅极驱动信号的驱动能力不同于所述第二栅极驱动信号的驱动能力。
本发明的有益效果是：区别于现有技术的情况，本发明中通过使得对显示面板中对应于同一行像素单元的两条扫描线上的栅极驱动信号具有不同的驱动能力，来达到消除因所述数据驱动信号的极性反转所引起的充电差异的目的。
【附图说明】
图1是本发明提供的液晶显示面板第一实施例的结构示意图；
图2是本发明提供的时钟信号、栅极驱动信号以及像素单元的充电电压第一实施例示意图；
图3是本发明提供的时钟信号、栅极驱动信号以及像素单元的充电电压第二实施例示意图；
图4是本发明提供的时钟信号、栅极驱动信号以及像素单元的充电电压第三实施例示意图；
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术 人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本发明保护的范围。
请参阅图1，图1是本发明提供的液晶显示面板实施例局部结构示意图。液晶显示面板30包括多个像素单元，如Pixel 11、Pixel 12、Pixel 13、Pixel 14、Pixel 21、Pixel 22、Pixel 23、Pixel 24。这些像素单元以矩阵方式排列。栅极驱动电路31位于液晶显示面板30的一侧，包括第一驱动级311、第二驱动级312、第三驱动级313和第四驱动级314。栅极驱动电路31连接着扫描线，用于依次在多条扫描线上提供栅极驱动信号，以控制扫描线所连接的像素单元逐行打开。扫描线G1连接第一驱动级311、扫描线G2连接第二驱动级312、扫描线G3连接第三驱动级313、扫描线G4连接第四驱动级314。
每两条扫描线对应同一行的像素单元，且交替与同一行像素单元内的像素单元连接。例如，扫描线G1和扫描线G2对应同一行的像素单元Pixel 11、Pixel 12、Pixel 21、Pixel 22，扫描线G1连接像素单元Pixel 11，扫描线G2连接与像素单元Pixel 11在同一行且相邻的像素单元Pixel 12，扫描线G1连接与像素单元Pixel 12在同一行且相邻的像素单元Pixel 21，扫描线G2连接与像素单元Pixel 21在同一行且相邻的像素单元Pixel 22。
数据驱动电路32位于液晶显示面板30的一侧，连接多条数据线，以对所述数据线连接的且在栅极驱动信号的驱动下处于打开状态的像素单元进行充电。每条数据线与两列相邻的像素单元连接。例如，数据线D1同时连接像素单元Pixel 11、Pixel 13所在的一列，以及与这一列相邻的像素单元Pixel 12、Pixel 14所在的一列。
扫描线G1、扫描线G2、扫描线G3和扫描线G4分别与数据线D1、D2和D3垂直。在其他实施场景中，扫描线G1、扫描线G2、扫描线G3和扫描线G4与数据线D1、D2和D3不一定垂直，可以有一任意大小的夹角即可。
请结合参阅图2。图2是本发明提供的像素单元充电效果第一实施例的脉冲示意图。信号CK 1是第一驱动级311接收的第一时钟驱动信号，信号CK 2是第二驱动级312接收的第二时钟驱动信号，信号CK 3 是第三驱动级313接收的第三时钟驱动信号，信号CK 4是第四驱动级314接收的第四时钟驱动信号。信号CK 1、信号CK 2、信号CK 3和信号CK 4周期相同，且相位上依次错开四分之一个周期。信号Gate 1是第一驱动级311根据信号CK 1输出给栅极线G1的第一栅极驱动信号，信号Gate 2是第二驱动级312根据信号CK 2输出给栅极线G2的第二栅极驱动信号，信号Gate 3是第三驱动级313根据信号CK 3输出给栅极线G3的第三栅极驱动信号，信号Gate 4是第四驱动级314根据信号CK 4输出给栅极线G4的第四栅极驱动信号。信号Gate 1、信号Gate 2、信号Gate 3和信号Gate 4周期相同，且相位上依次错开四分之一个周期。信号Gate 1驱动栅极线G1连接的像素单元Pixel 11，信号Gate 2驱动栅极线G2连接的像素单元Pixel 12，信号Gate 3驱动栅极线G3连接的像素单元Pixel 13，信号Gate 4驱动栅极线G1连接的像素单元Pixel 14。
信号CK 1和信号CK 3具有相同的脉冲幅度，信号CK 2和信号CK 4具有相同的脉冲幅度，且信号CK 1和信号CK 3的脉冲幅度比CK 2和信号CK 4的脉冲幅度高出ΔV。所以根据信号CK 1输出的信号Gate 1和根据信号CK 3输出的信号Gate 3具有相同幅度的脉冲，根据信号CK 2输出的信号Gate 2和根据信号CK 4输出的信号Gate 4具有相同幅度的脉冲，因此信号Gate 1和信号Gate 3的脉冲幅度比信号Gate 2和信号Gate 4的脉冲幅度高出ΔV。栅极驱动信号的脉冲幅度越大，对像素单元的驱动效果越好，像素单元的充电效率越高。因此信号Gate 1和信号Gate 3驱动的像素单元Pixel 11和Pixel 13的充电效率高于信号Gate 2和信号Gate 4驱动的像素单元Pixel 12和Pixel 14。
在本实施例中，是通过增大信号CK 1和信号CK 3的脉冲幅度实现信号CK 1和信号CK 3的脉冲幅度大于信号CK 2和信号CK 4的脉冲幅度，在其他实施例中，还可以通过减小信号CK 2和信号CK 4的脉冲幅度，或者同时增大信号CK 1和信号CK 3的脉冲幅度以及减小信号CK 2和信号CK 4的脉冲幅度来实现。
信号Data 1是数据驱动电路32给数据线D1输入的数据信号，信号Data 2是数据驱动电路32给数据线D2输入的数据信号。信号Data 1与 信号Data 2周期相同，且极性相反。
如图2所示，像素单元Pixel 11在信号Gate 1的驱动下在信号Data 1的极性反转之前打开，像素单元Pixel 11处于打开状态时的前四分之一个周期的时间内接收由Data 1输入的高电平充电，在Gate 1的驱动下处于打开状态时的后四分之一个周期的时间接收由Data 1输入的低电平充电，在充电时间内出现了极性反转，充电不完全。像素单元Pixel 12在信号Gate 2的驱动下在信号Data 1的极性反转之后打开，像素单元Pixel 12处于打开状态的全部时间内，接收由Data 1输入的低电平充电，并未出现极性反转，充电完全。
信号Gate 1驱动的像素单元Pixel 11的充电效率高于信号Gate 2驱动的像素单元Pixel 12，因此像素单元Pixel 11虽然在充电过程中发生了极性反转，但是像素单元Pixel 11的充电量与像素单元Pixel 12的差距较小。
同理像素单元Pixel 13在信号Gate 3的驱动下在信号Data 1的极性反转之前打开，像素单元Pixel 13处于打开状态时的前四分之一个周期的时间内接收由Data 1输入的低电平充电，在Gate 3的驱动下处于打开状态时的后四分之一个周期的时间接收由Data 1输入的高电平充电，在充电时间内出现了极性反转，充电不完全。像素单元Pixel 14在信号Gate 4的驱动下信号Data 1的极性反转之后打开，像素单元Pixel 13处于打开状态的全部时间内，接收由Data 1输入的高电平充电，并未出现极性反转，充电完全。
信号Gate 3驱动的像素单元Pixel 13的充电效率高于信号Gate 4驱动的像素单元Pixel 14，因此虽然像素单元Pixel 13在充电过程中发生了极性反转，但是像素单元Pixel 13的充电量与像素单元Pixel 14的差距较小。
像素单元Pixel 21、Pixel 22、Pixel 23和Pixel 24充电原理与像素单元Pixel 11、Pixel 12、Pixel 13、Pixel 14类似，此处不再赘述。
在其他实施例中，栅极驱动电路还可以包括六个或者八个甚至更多个驱动级，只需要驱动级的个数为偶数即可。
通过上述描述可知，本实施例通过提升用于驱动充电时会发生极性反转的像素单元的栅极驱动信号的电压，提高这些像素单元的充电效率，使得这些充电时发生极性反转的像素单元的充电量与充电时未发生极性反转的像素单元充电量的差距缩小，从而使得屏幕的亮度差异缩小，提高显示效果。
请结合参阅图1和图3，图3是本发明提供的像素单元充电效果第二实施例的脉冲示意图。信号CK 1是第一驱动级311接收的第一时钟驱动信号，信号CK 2是第二驱动级312接收的第二时钟驱动信号，信号CK 3是第三驱动级313接收的第三时钟驱动信号，信号CK 4是第四驱动级314接收的第四时钟驱动信号。信号CK 1、信号CK 2、信号CK 3和信号CK 4周期相同，且相位上依次错开四分之一个周期。信号Gate 1是第一驱动级311根据信号CK 1输出给栅极线G1的第一栅极驱动信号，信号Gate 2是第二驱动级312根据信号CK 2输出给栅极线G2的第二栅极驱动信号，信号Gate 3是第三驱动级313根据信号CK 3输出给栅极线G3的第三栅极驱动信号，信号Gate 4是第四驱动级314根据信号CK 4输出给栅极线G4的第四栅极驱动信号。信号Gate 1、信号Gate 2、信号Gate 3和信号Gate 4周期相同，且相位上依次错开四分之一个周期。信号Gate 1驱动栅极线G1连接的像素单元Pixel 11，信号Gate 2驱动栅极线G2连接的像素单元Pixel 12，信号Gate 3驱动栅极线G3连接的像素单元Pixel 13，信号Gate 4驱动栅极线G1连接的像素单元Pixel 14。
信号CK 1和信号CK 3具有相同的脉冲幅度，信号CK 2和信号CK 4具有相同的脉冲幅度，且信号CK 1和信号CK 3的脉冲幅度的后半段比CK 2和信号CK 4的脉冲幅度高出ΔV。所以根据信号CK 1输出的信号Gate 1和根据信号CK 3输出的信号Gate 3具有相同幅度的脉冲，根据信号CK 2输出的信号Gate 2和根据信号CK 4输出的信号Gate 4具有相同幅度的脉冲，因此信号Gate 1和信号Gate 3的脉冲幅度的后半段比信号Gate 2和信号Gate 4的脉冲幅度高出ΔV。栅极驱动信号的脉冲幅度越大，对像素单元的驱动效果越好，像素单元的充电效率越高。因 此信号Gate 1和信号Gate 3驱动的像素单元Pixel 11和Pixel 13的充电效率高于信号Gate 2和信号Gate 4驱动的像素单元Pixel 12和Pixel 14。
在本实施例中，是通过增大信号CK 1和信号CK 3的后半段脉冲幅度实现信号CK 1和信号CK 3的脉冲幅度大于信号CK 2和信号CK 4的脉冲幅度，在其他实施例中，还可以通过减小信号CK 2和信号CK 4的脉冲幅度，或者同时增大信号CK 1和信号CK 3的后半段脉冲幅度以及减小信号CK 2和信号CK 4的脉冲幅度来实现。
在其他实施例中，信号CK 1和信号CK 3的高脉冲所占的时间比例可以为任意比例，不一定如图3所示50％的比例。
信号Data 1是数据驱动电路32给数据线D1输入的数据信号，信号Data 2是数据驱动电路32给数据线D2输入的数据信号。信号Data 1与信号Data 2周期相同，且极性相反。
如图3所示，像素单元Pixel 11在信号Gate 1的驱动下在信号Data 1的极性反转之前打开，像素单元Pixel 11处于打开状态时的前四分之一个周期的时间内接收由Data 1输入的高电平充电，在Gate 1的驱动下处于打开状态时的后四分之一个周期的时间接收由Data 1输入的低电平充电，在充电时间内出现了极性反转，充电不完全。像素单元Pixel 12在信号Gate 2的驱动下在信号Data 1的极性反转之后打开，像素单元Pixel 12处于打开状态的全部时间内，接收由Data 1输入的低电平充电，并未出现极性反转，充电完全。
信号Gate 1驱动的像素单元Pixel 11的充电效率高于信号Gate 2驱动的像素单元Pixel 12，因此像素单元Pixel 11虽然在充电过程中发生了极性反转，但是像素单元Pixel 11的充电量与像素单元Pixel 12的差距较小。
同理像素单元Pixel 13在信号Gate 3的驱动下在信号Data 1的极性反转之前打开，像素单元Pixel 13处于打开状态时的前四分之一个周期的时间内接收由Data 1输入的低电平充电，在Gate 3的驱动下处于打开状态时的后四分之一个周期的时间接收由Data 1输入的高电平充电，在充电时间内出现了极性反转，充电不完全。像素单元Pixel 14在信号Gate  4的驱动下信号Data 1的极性反转之后打开，像素单元Pixel 13处于打开状态的全部时间内，接收由Data 1输入的高电平充电，并未出现极性反转，充电完全。
信号Gate 3驱动的像素单元Pixel 13的充电效率高于信号Gate 4驱动的像素单元Pixel 14，因此虽然像素单元Pixel 13在充电过程中发生了极性反转，但是像素单元Pixel 13的充电量与像素单元Pixel 14的差距较小。
像素单元Pixel 21、Pixel 22、Pixel 23和Pixel 24充电原理与像素单元Pixel 11、Pixel 12、Pixel 13、Pixel 14类似，此处不再赘述。
请结合参阅图1和图4，图4是本发明提供的像素单元充电效果第三实施例的脉冲示意图。信号CK 1是第一驱动级311接收的第一时钟驱动信号，信号CK 2是第二驱动级312接收的第二时钟驱动信号，信号CK 3是第三驱动级313接收的第三时钟驱动信号，信号CK 4是第四驱动级314接收的第四时钟驱动信号。信号CK 1、信号CK 2、信号CK 3和信号CK 4周期相同，且相位上依次错开四分之一个周期。信号Gate 1是第一驱动级311根据信号CK 1输出给栅极线G1的第一栅极驱动信号，信号Gate 2是第二驱动级312根据信号CK 2输出给栅极线G2的第二栅极驱动信号，信号Gate 3是第三驱动级313根据信号CK 3输出给栅极线G3的第三栅极驱动信号，信号Gate 4是第四驱动级314根据信号CK 4输出给栅极线G4的第四栅极驱动信号。信号Gate 1、信号Gate 2、信号Gate 3和信号Gate 4周期相同，且相位上依次错开四分之一个周期。信号Gate 1驱动栅极线G1连接的像素单元Pixel 11，信号Gate 2驱动栅极线G2连接的像素单元Pixel 12，信号Gate 3驱动栅极线G3连接的像素单元Pixel 13，信号Gate 4驱动栅极线G1连接的像素单元Pixel 14。
信号CK 1和信号CK 3具有相同的脉冲宽度，信号CK 2和信号CK 4具有相同的脉冲宽度，且信号CK 1和信号CK 3的脉冲宽度大于信号CK 2和信号CK 4的脉冲宽度。所以根据信号CK 1输出的信号Gate 1和根据信号CK 3输出的信号Gate 3具有相同宽度的脉冲，根据信号CK  2输出的信号Gate 2和根据信号CK 4输出的信号Gate 4具有相同宽度的脉冲，且信号Gate 1和信号Gate 3的脉冲宽度大于信号Gate 2和信号Gate 4的脉冲宽度。栅极驱动信号的脉冲宽度越大，像素单元的充电时间越长，像素单元每次充电的电量越多。因此信号Gate 1和信号Gate 3驱动的像素单元Pixel 11和Pixel 13相较于信号Gate 2和信号Gate 4驱动的像素单元Pixel 12和Pixel 14有更长的充电时间。
在本实施例中，是通过增大信号CK 1和信号CK 3的脉冲宽度以及减小信号CK 2和信号CK 4的脉冲宽度来实现信号CK 1和信号CK 3的脉冲宽度大于信号CK 2和信号CK 4的脉冲宽度，在其他实施例中，还可以通过减小信号CK 2和信号CK 4的脉冲宽度，或者增大信号CK 1和信号CK 3的脉冲宽度来实现。
信号Data 1是数据驱动电路32给数据线D1输入的数据信号，信号Data 2是数据驱动电路32给数据线D2输入的数据信号。信号Data 1与信号Data 2周期相同，且极性相反。
如图4所示，像素单元Pixel 11在信号Gate 1的驱动下在信号Data 1的极性反转之前打开，像素单元Pixel 11处于打开状态时的前四分之一个周期的时间内接收由Data 1输入的高电平充电，在Gate 1的驱动下处于打开状态时的后四分之一个周期的时间接收由Data 1输入的低电平充电，在充电时间内出现了极性反转，充电不完全。像素单元Pixel 12在信号Gate 2的驱动下在信号Data 1的极性反转之后打开，像素单元Pixel 12处于打开状态的全部时间内，接收由Data 1输入的低电平充电，并未出现极性反转，充电完全。但是信号Gate 1的脉冲宽度较大，像素单元Pixel 11在极性反转后有较长的时间进行充电，可以充到较多的电量，信号Gate 2的脉冲宽度较小，像素单元Pixel 12的充电时间较短，充电电量较小，因此像素单元Pixel 11的充电量与像素单元Pixel 12的差距较小。
同理像素单元Pixel 13在信号Gate 3的驱动下于打开状态时的前四分之一个周期的时间内接收由Data 1输入的低电平充电，在Gate 3的驱动下处于打开状态时的后四分之一个周期的时间接收由Data 1输入的高 电平充电，在充电时间内出现了极性反转，充电不完全。像素单元Pixel 14在信号Gate 4的驱动下处于打开状态的全部时间内，接收由Data 1输入的高电平充电，并未出现极性反转，充电完全。
但是信号Gate 3的脉冲宽度较大，像素单元Pixel 13在极性反转后有较长的时间进行充电，可以充到较多的电量，信号Gate 4的脉冲宽度较小，像素单元Pixel 14的充电时间较短，充电电量较少，因此像素单元Pixel 13的充电量与像素单元Pixel 14的差距较小。。
像素单元Pixel 21、Pixel 22、Pixel 23和Pixel 24充电原理与像素单元Pixel 11、Pixel 12、Pixel 13、Pixel 14类似，此处不再赘述。
在其他实施例中，栅极驱动电路还可以包括六个或者八个甚至更多个驱动级，只需要驱动级的个数为偶数即可。
通过上述描述可知，本实施例通过延长用于驱动充电时会发生极性反转的像素单元的栅极驱动信号的脉冲宽度，让这些像素单元的充电时间延长，使得这些充电时发生极性反转的像素单元的充电量与充电时未发生极性反转的像素单元充电量的差距缩小，从而使得屏幕的亮度差异缩小，提高显示效果。
区别于现有技术，本发明液晶显示面板上同一行像素单元的连接的两条扫描线上的栅极驱动信号具有不同的驱动能力，使得在充电时发生极性反转的像素单元充到的电量与充电时不发生极性反转的像素单元充到的电量的差距减小，从而使得屏幕的亮度差异缩小，提高显示效果。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种液晶显示面板，其中，包括：
    多个像素单元，所述多个像素单元以矩阵方式排列；
    多条扫描线，每两条所述扫描线对应同一行所述像素单元且交替与所述同一行像素单元内的所述像素单元连接；
    栅极驱动电路，用于依次在所述扫描线上提供栅极驱动信号，以控制所述扫描线所连接的所述像素单元打开；
    多条数据线，所述数据线间隔设置在每列所述像素单元旁，每条数据线分别与相邻的两列所述像素单元连接；
    数据驱动电路，用于以极性反转方式向所述数据线提供数据驱动信号，以对所述数据线所连接的且处于打开状态的所述像素单元进行充电；
    其中，对应于所述同一行像素单元的两条扫描线中的第一条扫描线所连接的所述像素单元的打开发生在所述数据驱动信号的极性反转之前，第二条扫描线所连接的所述像素单元的打开发生在所述数据驱动信号的极性反转之后或同时发生，其中所述第一条扫描线上的所述栅极驱动信号的驱动能力大于所述第二条扫描线上的所述栅极驱动信号的驱动能力由此消除因所述数据驱动信号的极性反转所引起的充电差异；
    所述多条扫描线上的所述栅极驱动信号沿列方向依次错开所述数据驱动信号的极性反转周期的四分之一。
  2. 根据权利要求1所述的液晶显示面板，其中，所述第一条扫描线上的所述栅极驱动信号的脉冲高度至少部分大于所述第二条扫描线上的所述栅极驱动信号的脉冲高度。
  3. 根据权利要求1所述的液晶显示面板，其中，所述第一条扫描线上的所述栅极驱动信号的脉冲宽度大于所述第二条扫描线上的所述栅极驱动信号的脉冲宽度。
  4. 根据权利要求1所述的液晶显示面板，其中，所述栅极驱动电路位于所述液晶显示面板的一侧。
  5. 根据权利要求1所述的液晶显示面板，其中，所述数据驱动位于所述液晶显示面板的另一侧。
  6. 根据权利要求1所述的液晶显示面板，其中，所述多条扫描线与所述多条数据线相互垂直。
  7. 一种液晶显示面板，其中，包括：
    多个像素单元，所述多个像素单元以矩阵方式排列；
    多条扫描线，每两条所述扫描线对应同一行所述像素单元且交替与所述同一行像素单元内的所述像素单元连接；
    栅极驱动电路，用于依次在所述扫描线上提供栅极驱动信号，以控制所述扫描线所连接的所述像素单元打开；
    多条数据线，所述数据线间隔设置在每列所述像素单元旁，每条数据线分别与相邻的两列所述像素单元连接；
    数据驱动电路，用于以极性反转方式向所述数据线提供数据驱动信号，以对所述数据线所连接的且处于打开状态的所述像素单元进行充电；
    其中，对应于所述同一行像素单元的两条扫描线上的栅极驱动信号具有不同的驱动能力，由此消除因所述数据驱动信号的极性反转所引起的充电差异。
  8. 根据权利要求7所述的液晶显示面板，其中，对应于所述同一行像素单元的两条扫描线中的第一条扫描线所连接的所述像素单元的打开发生在所述数据驱动信号的极性反转之前，第二条扫描线所连接的所述像素单元的打开发生在所述数据驱动信号的极性反转之后或同时发生，其中所述第一条扫描线上的所述栅极驱动信号的驱动能力大于所述第二条扫描线上的所述栅极驱动信号的驱动能力。
  9. 根据权利要求8所述的液晶显示面板，其中，所述第一条扫描线上的所述栅极驱动信号的脉冲高度至少部分大于所述第二条扫描线上的所述栅极驱动信号的脉冲高度。
  10. 根据权利要求8所述的液晶显示面板，其中，所述第一条扫描线上的所述栅极驱动信号的脉冲宽度大于所述第二条扫描线上的所述栅极驱动信号的脉冲宽度。
  11. 根据权利要求7所述的液晶显示面板，其中，所述多条扫描线上的所述栅极驱动信号沿列方向依次错开所述数据驱动信号的极性反转周期的四分之一。
  12. 根据权利要求7所述的液晶显示面板，其中，所述栅极驱动电路位 于所述液晶显示面板的一侧。
  13. 根据权利要求7所述的液晶显示面板，其中，所述数据驱动位于所述液晶显示面板的另一侧。
  14. 根据权利要求7所述的液晶显示面板，其中，所述多条扫描线与所述多条数据线相互垂直。
  15. 一种安装于液晶显示面板中的栅极驱动电路，其中，所述栅极驱动电路包括第一驱动级和第二驱动级，所述第一驱动级接收第一时钟信号，并响应所述第一时钟信号输出第一栅极驱动信号，所述第二驱动级接收第二时钟信号，并响应所述第二时钟信号输出第二栅极驱动信号，其中所述第一时钟信号和所述第二时钟信号设置成使得所述第一栅极驱动信号的驱动能力不同于所述第二栅极驱动信号的驱动能力。
  16. 根据权利要求15所述的栅极驱动电路，其中，所述第一时钟信号的脉冲幅度大于所述第二时钟信号的脉冲幅度，以使得所述第一栅极驱动信号的脉冲幅度大于所述第二栅极驱动信号的脉冲幅度。
  17. 根据权利要求15所述的栅极驱动电路，其中，所述第一时钟信号的脉冲宽度大于所述第二时钟信号的脉冲宽度，以使得所述第一栅极驱动信号的脉冲宽度大于所述第二栅极驱动信号的脉冲宽度。
  18. 根据权利要求15所述的栅极驱动电路，其中，所述栅极驱动电路进一步包括第三驱动级和第四驱动级，所述第三驱动级接收第三时钟信号，并响应所述第三时钟信号输出第三栅极驱动信号，所述第四驱动级接收第四时钟信号，并响应所述第四时钟信号输出第四栅极驱动信号，所述第三时钟信号和所述第四时钟信号进一步设置成使得所述第三栅极驱动信号的驱动能力与所述第一栅极驱动信号的驱动能力相同，且所述第四栅极驱动信号的驱动能力与所述第二栅极驱动信号的驱动能力相同。
  19. 根据权利要求18所述的栅极驱动电路，其中，所述第一时钟信号到所述第四时钟信号的周期相同且相位上依次错开四分之一个周期，以使得所述第一栅极驱动信号到所述第四栅极驱动信号的周期相同且相位上依次错开四分之一个周期。
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CN107767832A (zh) 2018-03-06
JP2020535470A (ja) 2020-12-03

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