WO2015027630A1 - 极性反转驱动方法和极性反转驱动电路 - Google Patents

极性反转驱动方法和极性反转驱动电路 Download PDF

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Publication number
WO2015027630A1
WO2015027630A1 PCT/CN2013/089671 CN2013089671W WO2015027630A1 WO 2015027630 A1 WO2015027630 A1 WO 2015027630A1 CN 2013089671 W CN2013089671 W CN 2013089671W WO 2015027630 A1 WO2015027630 A1 WO 2015027630A1
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Prior art keywords
data voltage
voltage signal
gate line
data
gate
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PCT/CN2013/089671
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English (en)
French (fr)
Inventor
秦锋
姜清华
李小和
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合肥京东方光电科技有限公司
京东方科技集团股份有限公司
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Publication of WO2015027630A1 publication Critical patent/WO2015027630A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a polarity inversion driving method and a polarity inversion driving circuit. Background technique
  • the liquid crystal display is a commonly used flat panel display, wherein the thin film transistor liquid crystal display
  • the array substrate is an important component of the liquid crystal display.
  • the array substrate includes: a base substrate and gate lines and data lines formed on the base substrate, and the gate lines and the data lines define pixel units.
  • 1 is a schematic diagram of a pixel unit array of an array substrate in the prior art. As shown in FIG. 1, the gate lines G1 to G7 and the data lines D1 to D7 define a plurality of pixel units, and the gate lines G1 to G7 are both connected to a timing controller. .
  • the timing controller sequentially loads the scan signals on the gate lines G1 to G7, thereby sequentially turning on the row of pixel units corresponding to the gate lines; the pixel units in which the data lines D1 to D7 are turned on load the data voltage signals, thereby realizing the data to the pixel units.
  • polarity inversion In a liquid crystal display, since the polarity of a voltage signal applied across the liquid crystal capacitor Clc and the storage capacitor Cst must be inverted every predetermined time to avoid permanent polarization caused by polarization of the liquid crystal material, it is necessary to The pixel unit on the array substrate is driven by polarity inversion. Common polarity reversals include: frame inversion, column inversion, line inversion, and dot inversion.
  • the polarity of the voltage stored in the pixel unit on the entire frame is the same, and the polarity of the voltage is all positive or negative, which is called Frame inversion; if the polarity of the voltage stored in the pixel unit on the same column is the same, and the polarity of the voltage stored in the pixel unit on the left and right adjacent columns is opposite, it is called column inversion; if it is on the same line
  • the polarity of the voltages stored in the pixel units are the same, and the voltages stored in the pixel units on the adjacent rows are opposite in polarity, which is called row inversion; if the polarity of the voltage stored in each pixel unit is The polarity of the voltage stored in the pixel units adjacent to the top, bottom, left, and right is opposite, which is called dot inversion.
  • FIG. 2 is a driving timing diagram of a polarity inversion driving in the prior art.
  • FIG. 2 is a driving sequence diagram of a dot inversion, taking the data line D1 as an example to realize The dot inversion, the polarity of the data voltage signal loaded on the data line D1 needs to be inverted once when the scan signal (high level shown in Fig. 2) is loaded on each gate line.
  • the dot inversion driving method is adopted.
  • the data voltage signal loaded on the data line needs to be inverted once.
  • the data voltage signal loaded on the data line is frequently reversed in polarity, which greatly increases the power consumption of the display panel.
  • the present invention provides a polarity inversion driving method and a polarity inversion driving circuit for reducing power consumption of a display panel.
  • the present invention provides a polarity inversion driving method for driving an array substrate, the array substrate comprising: a substrate substrate and a substrate formed on the substrate a gate line and a data line on the substrate, the gate line and the data line defining a pixel unit, the gate line being divided into a first gate line and a second gate line, wherein adjacent N rows of the first gate line and adjacent The N rows of the second gate lines are alternately set, and N is an integer greater than or equal to 1;
  • the polarity inversion driving method includes:
  • the pixel unit corresponding to each first gate line is sequentially turned on by the first gate line, and the first data voltage signal is loaded through the pixel unit of the odd-numbered column data line and passes through the even-numbered data line.
  • the conductive pixel unit loads a second data voltage signal, and the first data voltage signal and the second data voltage signal are opposite in polarity;
  • Pixel units corresponding to each of the second gate lines are sequentially turned on by the second gate lines, and the third data voltage signal is loaded by the pixel units that are turned on by the odd-numbered column data lines and loaded by the pixel units that are turned on by the even-numbered data lines And a fourth data voltage signal, the third data voltage signal and the fourth data voltage signal are opposite in polarity.
  • the polarity of the first data voltage signal, the second data voltage signal, the third data voltage signal, and the fourth data voltage signal is every other frame when displayed every other frame The screen is reversed once.
  • the first data voltage signal in the adjacent two frames is different, and the second data voltage is different.
  • the signals are different, the third data voltage signal is different, and the fourth data voltage signal is different.
  • two rows of the first gate line and two rows of the second gate line are alternately disposed.
  • the absolute values of the voltages of the first data voltage signal, the second data voltage signal, the third data voltage signal, and the fourth data voltage signal are equal.
  • the polarity inversion driving method uses a four-frame picture as a polarity inversion driving period.
  • any one of the four frames is a start frame, and the polarity is reversed in a sequential or reverse manner of the four frames.
  • the present invention provides a polarity inversion driving circuit for driving an array substrate, the array substrate comprising: a substrate substrate and a substrate formed on the substrate a gate line and a data line on the substrate, the gate line and the data line defining a pixel unit, the gate line being divided into a first gate line and a second gate line, wherein adjacent N rows of the first gate line and adjacent The N rows of the second gate lines are alternately set, and N is an integer greater than or equal to 1;
  • the polarity inversion driving circuit includes: a gate line driving circuit connected to the first gate line and the second gate line; and a data driving circuit connected to the data line;
  • the gate line driving circuit is configured to sequentially turn on pixel units corresponding to each of the first gate lines through the first gate lines when displaying one frame of the screen, and sequentially turn on and each through the second gate lines a pixel unit corresponding to the second gate line;
  • the data driving circuit is configured to load the first data voltage signal through the pixel unit of the odd-numbered column data line when the pixel unit corresponding to the first gate line is turned on when the pixel unit corresponding to the first gate line is turned on, and is connected through the even-numbered data line.
  • the pixel unit loads the second data voltage signal, and loads the third data voltage signal through the pixel unit of the odd-numbered column data line when the pixel unit corresponding to the second gate line is turned on, and the pixel that is turned through the even-numbered data line
  • the unit loads the fourth data voltage signal, the first data voltage signal and the second data voltage signal are opposite in polarity, and the third data voltage signal and the fourth data voltage signal are opposite in polarity.
  • the polarity of the first data voltage signal, the second data voltage signal, the third data voltage signal, and the fourth data voltage signal is every other frame when displayed every other frame The screen is reversed once.
  • the gate line driving circuit includes: a first gate line driving sub-circuit and a second gate line driving sub-circuit, wherein the plurality of rows of the first gate lines are connected to the first gate line driving sub-circuit, The second gate line driving sub-circuit is connected to the second gate line driving sub-circuit;
  • the first gate line driving sub-circuit is configured to sequentially turn on pixel units corresponding to each first gate line through the first gate line, and the second gate line driving sub-circuit is used to sequentially pass through the second gate line A pixel unit corresponding to each of the second gate lines is turned on.
  • two rows of the first gate line and two rows of the second gate line are alternately disposed.
  • the first data voltage loaded by the pixel unit of the odd-numbered column data line in the process of scanning the first gate line is scanned.
  • the second data voltage signal loaded by the pixel unit of the signal and the even-numbered column data line is opposite in polarity, and the third data voltage signal and the even-numbered data line loaded by the pixel unit of the odd-numbered column data line in the process of scanning the second gate line are scanned.
  • the fourth data voltage signal loaded by the conductive pixel unit has the opposite polarity, which effectively reduces the number of polarity inversions, thereby reducing the power consumption of the display panel.
  • the polarities of the first data voltage signal, the second data voltage signal, the third data voltage signal, and the fourth data voltage signal are inverted once, so the data line loaded by the data line to the pixel unit in the present invention
  • the voltage signal is inverted once every other frame, which effectively reduces the number of polarity inversions, thereby reducing the power consumption of the display panel.
  • FIG. 1 is a schematic diagram of a pixel unit array of an array substrate in the prior art
  • FIG. 2 is a driving timing diagram of a polarity inversion driving in the prior art
  • FIG. 3 is a schematic view of an array substrate in the present invention.
  • FIG. 5 is a schematic diagram showing the polarity of each frame of the polarity inversion driving method in the second embodiment. detailed description
  • Embodiment 1 of the present invention provides a polarity inversion driving method, and the polarity inversion driving method The method is used to drive the array substrate.
  • the array substrate includes: a substrate substrate and gate lines and data lines formed on the base substrate, the gate lines and the data lines defining pixel units, the gate lines including: a first gate line and a second gate line, and a plurality of A gate line and a plurality of second gate lines are alternately arranged.
  • the polarity inversion driving method includes: when one frame is displayed, the pixel unit corresponding to the first gate line is sequentially turned on by the first gate line, and the first data voltage signal is loaded by the pixel unit that is turned on by the odd-numbered data line and Loading, by the pixel unit that is connected to the even-numbered data line, the second data voltage signal, the first data voltage signal and the second data voltage signal are opposite in polarity; and the pixel unit corresponding to the second gate line is sequentially turned on by the second gate line, The third data voltage signal is loaded by the pixel unit of the odd-numbered column data line and the fourth data voltage signal is loaded by the pixel unit of the even-numbered data line, the third data voltage signal and the fourth data voltage signal are opposite in polarity.
  • the first data voltage signal has opposite polarity
  • the second data voltage signal has opposite polarity
  • the third data voltage signal has opposite polarity
  • the fourth data voltage signal polarity is displayed every other frame display.
  • the first data voltage signals in the adjacent two frames are different, the second data voltage signals are different, the third data voltage signals are different, and the fourth data voltage signals are different.
  • two rows of first gate lines and two rows of second gate lines are alternately arranged. That is to say, on the array substrate, two rows of first gate lines are first disposed, and then two rows of second gate lines are disposed, and then the first gate lines and the second gate lines are sequentially arranged according to the above rule, thereby realizing two rows and first lines.
  • the absolute values of the voltages of the first data voltage signal, the second data voltage signal, the third data voltage signal, and the fourth data voltage signal are equal.
  • the polarity inversion driving method reverses the driving period with one frame as one polarity.
  • the first data voltage signal and the even column data line loaded by the pixel unit of the odd column data line in the process of scanning the first gate line are scanned.
  • the second data voltage signal loaded by the conductive pixel unit is opposite in polarity
  • the third data voltage signal loaded by the pixel unit of the odd-numbered column data line in the process of scanning the second gate line and the pixel unit of the even-numbered data line are loaded.
  • Fourth data voltage The opposite polarity of the signal effectively reduces the number of polarity reversals, which reduces the power consumption of the display panel.
  • the polarities of the first data voltage signal, the second data voltage signal, the third data voltage signal, and the fourth data voltage signal are inverted once, so that every other frame is displayed in this embodiment.
  • the data line is reversed in polarity by the data voltage signal loaded by the pixel unit, which further reduces the number of polarity inversions, thereby further reducing the power consumption of the display panel.
  • the array substrate includes: a substrate substrate (not specifically shown) and gate lines and data lines D1 to D7 formed on the substrate substrate, and gate lines and The data lines define pixel cells, and the gate lines may include: first gate lines G1, G2, G5 and G6 and second gate lines G3, G4, G7 and G8. And the two rows of the first gate lines and the two rows of the second gate lines are alternately disposed. Specifically, on the base substrate, the arrangement order of the gate lines is: the first gate line G1, the first gate line G2, and the second gate line G3.
  • a second gate line G4 a first gate line G5, a first gate line G6, a second gate line G7, and a second gate line G8.
  • the first gate line and the second gate line may be connected to the gate driving circuit, and the data line may be connected to the data driving circuit.
  • the gate driving circuit may include a first gate line driving sub-circuit and a second gate line driving sub-circuit, so that each of the rows of the first gate lines may be connected to the first gate line driving sub-circuit, the above-mentioned respective rows
  • the second gate line can be connected to the second gate line driving sub-circuit
  • the first gate line driving sub-circuit is configured to drive the first gate line to turn on the pixel unit corresponding to the first gate line
  • the second gate line driving sub-circuit Driving the second gate line to turn on the pixel unit corresponding to the second gate line.
  • the polarity inversion driving method provided in this embodiment is for driving the above array substrate in FIG.
  • the polarity inversion driving method takes a four-frame picture as one polarity inversion driving period.
  • a liquid crystal display having an operating frequency of 60 Hz is taken as an example, and the scanning time of one frame is 16.7 milliseconds.
  • the scan time (on time) of each row of gate lines is 21. 7 microseconds.
  • FIG. 4 is a driving timing chart of the polarity inversion driving method in the second embodiment
  • FIG. 5 is a schematic diagram showing the polarity of each frame in the polarity inversion driving method in the second embodiment, and it is necessary to say that:
  • FIG. 4 only shows The driving timing of some data lines is taken as an example.
  • the polarity inversion driver The law includes:
  • Step 101 When the first frame is displayed, the pixel unit corresponding to the first gate line is sequentially turned on by the first gate line, and the first data voltage signal is loaded through the pixel unit of the odd-numbered data line and the data is transmitted through the even column.
  • the line-passing pixel unit loads the second data voltage signal, the first data voltage signal is a forward voltage, and the second data voltage signal is a negative voltage.
  • Step 101 may specifically include:
  • the first gate line driving sub-circuit outputs a scan signal to the first gate line G1 to turn on the first gate line G1, the scan signal is a high level signal, and the remaining gate lines are turned off.
  • the first gate line G1 is turned on, a row of pixel cells corresponding to the first gate line G1 is turned on, and at this time, the odd-numbered column data lines D1, D3, D5, and D7 are turned on by the pixel unit to load a forward voltage (shown as The high level signal, shown in Figure 5, "+”), the even-numbered data lines D2, D4, D6, and D8 lead the pixel unit to load the negative voltage (shown as low level signal in Figure 4, Figure 5 The "_,,” shown.
  • the absolute values of the forward voltage and the negative voltage of the same pixel unit are equal; in other words, the present invention only applies to the data signal applied to the pixel unit.
  • the polarity is reversed and the polarity inversion does not change the amplitude of the original data signal.
  • the remaining first gate lines G2, G5, and G6 are sequentially turned on, and when one of the first gate lines is turned on, the odd-numbered column data lines D1, D3, D5, and D7 are turned on.
  • a row of pixel cells loads the forward voltage and a row of pixel cells that are passed through the even column data lines D2, D4, D6, and D8 to load the negative voltage until all of the first gate lines are scanned.
  • Step 102 sequentially turn on the pixel unit corresponding to the second gate line through the second gate line, load the third data voltage signal through the pixel unit in the odd-numbered column data line, and load the pixel unit through the even-numbered data line.
  • the fourth data voltage signal, the third data voltage signal is a forward voltage, and the fourth data voltage signal is a negative voltage.
  • Step 102 may specifically include:
  • the second gate line driving sub-circuit outputs a scan signal to the second gate line G3 to turn on the second gate line G3, the scan signal is a high level signal, and the remaining gate lines are turned off.
  • the second gate line G3 is turned on, a row of pixel units corresponding to the second gate line G3 is turned on, and at this time, the odd-numbered column data lines D1, D3, D5, and D7 are turned on by the pixel unit to load the forward voltage, and the even-numbered column data line D2.
  • the D4, D6, and D8 pass-through pixel cells are loaded with a negative voltage.
  • the remaining second gate lines G4, G7, and G8 are sequentially turned on, and when one of the second gate lines is turned on, the odd-numbered column data lines D1, D3, D5, and D7 are turned on.
  • a row of pixel cells loads the forward voltage and a row of pixel cells that are passed through the even column data lines D2, D4, D6, and D8 to load the negative voltage until all of the second gate lines are scanned.
  • each data line is loaded to the pixel unit corresponding to the first gate line.
  • the polarity of the data voltage signal is the same as the polarity of the data voltage signal loaded by the pixel unit corresponding to the second gate line of the data line, so the data voltage signal loaded by the data line to the pixel unit during the display of the first frame is not performed. Polarity is reversed.
  • Step 103 When the second frame is displayed, the pixel unit corresponding to the first gate line is sequentially turned on by the first gate line, and the first data voltage signal is loaded through the pixel unit of the odd-numbered data line and the data is passed through the even column.
  • the line-passing pixel unit loads the second data voltage signal, the first data voltage signal is a forward voltage, and the second data voltage signal is a negative voltage.
  • Step 103 may specifically include:
  • the first gate line driving sub-circuit outputs a scan signal to the first gate line G1 to turn on the first gate line G1, the scan signal is a high level signal, and the remaining gate lines are turned off.
  • the first gate line G1 is turned on, a row of pixel units corresponding to the first gate line G1 is turned on, and at this time, the odd-numbered column data lines D1, D3, D5, and D7 are turned on by the pixel unit to load the forward voltage, and the even-numbered column data line D2.
  • the D4, D6, and D8 pass-through pixel cells are loaded with a negative voltage.
  • the remaining first gate lines G2, G5, and G6 are sequentially turned on, and when one of the first gate lines is turned on, the odd-numbered column data lines D1, D3, D5, and D7 are turned on.
  • a row of pixel cells loads the forward voltage and a row of pixel cells that are passed through the even column data lines D2, D4, D6, and D8 to load the negative voltage until all of the first gate lines are scanned.
  • Step 104 sequentially turn on the pixel unit corresponding to the second gate line through the second gate line, load the third data voltage signal through the pixel unit in the odd-numbered column data line, and load the pixel unit through the even-numbered data line.
  • the fourth data voltage signal, the third data voltage signal is a negative voltage, and the fourth data voltage signal is a forward voltage.
  • Step 104 specifically includes:
  • the second gate line driving sub-circuit outputs a scan signal to the second gate line G3 to turn on the second gate line G3, the scan signal is a high level signal, and the remaining gate lines are turned off.
  • the second gate line G3 is turned on, a row of pixel units corresponding to the second gate line G3 is turned on, and at this time, the odd-numbered column data lines D1, D3, D5, and D7 are turned on by the pixel unit to load the negative voltage, and the even-numbered column data line D2.
  • the D4, D6, and D8-guided pixel cells are loaded with a forward voltage.
  • the remaining second gate lines G4, G7, and G8 are sequentially turned on, and when one of the second gate lines is turned on, the odd-numbered column data lines D1, D3, D5, and D7 are turned on.
  • a row of pixel cells loads the negative voltage and a row of pixel cells that are passed through the even column data lines D2, D4, D6, and D8 to load the forward voltage until all of the second gate lines are scanned.
  • each data line is loaded to the pixel unit corresponding to the first gate line.
  • the polarity of the data voltage signal is opposite to the polarity of the data voltage signal loaded by the pixel unit corresponding to the second gate line of the data line, so the data voltage signal loaded by the data line to the pixel unit during the second frame picture display process is performed.
  • One polarity reversal.
  • Step 105 When the third frame is displayed, the pixel unit corresponding to the first gate line is sequentially turned on by the first gate line, and the first data voltage signal is loaded through the pixel unit of the odd-numbered data line and the data is passed through the even column.
  • the line-passing pixel unit loads the second data voltage signal, the first data voltage signal is a negative voltage, and the second data voltage signal is a forward voltage.
  • Step 105 specifically includes:
  • the first gate line driving sub-circuit outputs a scan signal to the first gate line G1 to turn on the first gate line G1, the scan signal is a high level signal, and the remaining gate lines are turned off.
  • the first gate line G1 is turned on, a row of pixel units corresponding to the first gate line G1 is turned on, and at this time, the pixel units of the odd-numbered column data lines D1, D3, D5, and D7 are loaded with a negative voltage, and the even-numbered data lines are D2.
  • the D4, D6, and D8-guided pixel cells are loaded with a forward voltage.
  • Step 106 sequentially turn on the pixel unit corresponding to the second gate line through the second gate line, load the third data voltage signal through the pixel unit of the odd-numbered column data line, and load the pixel unit through the even-numbered data line.
  • the fourth data voltage signal, the third data voltage signal is a negative voltage, and the fourth data voltage signal is a forward voltage.
  • Step 106 specifically includes:
  • the second gate line driving sub-circuit outputs a scan signal to the second gate line G3 to turn on the second gate line G3, the scan signal is a high level signal, and the remaining gate lines are turned off.
  • the second gate line G3 is turned on, a row of pixel units corresponding to the second gate line G3 is turned on, and at this time, the odd-numbered column data lines D1, D3, D5, and D7 are turned on by the pixel unit to load the negative voltage, and the even-numbered column data line D2.
  • the D4, D6, and D8-guided pixel cells are loaded with a forward voltage.
  • the remaining second gate lines G4, G7, and G8 are sequentially turned on, and when one of the second gate lines is turned on, the odd-numbered column data lines D1, D3, D5, and D7 are turned on.
  • a row of pixel cells loads the negative voltage and a row of pixel cells that are passed through the even column data lines D2, D4, D6, and D8 to load the forward voltage until all of the second gate lines are scanned.
  • each data line is loaded to the pixel unit corresponding to the first gate line.
  • the polarity of the data voltage signal is the same as the polarity of the data voltage signal loaded by the pixel unit corresponding to the second gate line of the data line, so the data voltage signal loaded by the data line to the pixel unit during the third frame display process is not performed. Polarity is reversed.
  • Step 107 When the fourth frame is displayed, the pixel unit corresponding to the first gate line is sequentially turned on by the first gate line, and the first data voltage signal is loaded through the pixel unit of the odd-numbered data line and the data is transmitted through the even column.
  • the line-passing pixel unit loads the second data voltage signal, the first data voltage signal is a negative voltage, and the second data voltage signal is a forward voltage.
  • Step 107 specifically includes:
  • the first gate line driving sub-circuit outputs a scan signal to the first gate line G1 to turn on the first gate line G1, the scan signal is a high level signal, and the remaining gate lines are turned off.
  • the first gate line G1 is turned on, a row of pixel units corresponding to the first gate line G1 is turned on, and at this time, the pixel units of the odd-numbered column data lines D1, D3, D5, and D7 are loaded with a negative voltage, and the even-numbered data lines are D2.
  • the D4, D6, and D8-guided pixel cells are loaded with a forward voltage.
  • the remaining first gate lines G2, G5, and G6 are sequentially turned on, and when one of the first gate lines is turned on, the odd-numbered column data lines D1, D3, D5, and D7 are turned on.
  • a row of pixel cells loads the negative voltage and a row of pixel cells that are passed through the even column data lines D2, D4, D6, and D8 to load the forward voltage until all of the first gate lines are scanned.
  • Step 108 sequentially turn on the pixel unit corresponding to the second gate line through the second gate line, load the third data voltage signal through the pixel unit in the odd-numbered column data line, and load the pixel unit through the even-numbered data line.
  • the fourth data voltage signal, the third data voltage signal is a forward voltage, and the fourth data voltage signal is a negative voltage.
  • Step 108 may specifically include:
  • the second gate line driving sub-circuit outputs a scan signal to the second gate line G3 to turn on the second gate line G3, the scan signal is a high level signal, and the remaining gate lines are turned off.
  • the second gate line G3 is turned on, a row of pixel units corresponding to the second gate line G3 is turned on, and at this time, the odd-numbered column data lines D1, D3, D5, and D7 are turned on by the pixel unit to load the forward voltage, and the even-numbered column data line D2.
  • the D4, D6, and D8 pass-through pixel cells are loaded with a negative voltage.
  • the remaining second gate lines G4, G7, and G8 are sequentially turned on, and when one of the second gate lines is turned on, the odd-numbered column data lines D1, D3, D5, and D7 are turned on.
  • a row of pixel cells loads the forward voltage and a row of pixel cells that are passed through the even column data lines D2, D4, D6, and D8 to load the negative voltage until all of the second gate lines are scanned.
  • each data line is loaded to the pixel unit corresponding to the first gate line.
  • the polarity of the data voltage signal is opposite to the polarity of the data voltage signal loaded by the pixel unit corresponding to the second gate line of the data line, so the data voltage signal loaded by the data line to the pixel unit during the fourth frame picture display process is performed.
  • One polarity reversal.
  • the fifth frame picture may be displayed according to the method of displaying the first frame picture in steps 101 and 102, wherein the fifth frame picture has the same polarity as the voltage of each pixel unit in the first frame picture; and further, step 103 and steps may be followed.
  • the method for displaying the second frame picture in 104 displays the sixth frame picture, and the voltage polarity of each pixel unit in the sixth frame picture and the second frame picture is the same; and further, the method of displaying the third frame picture in steps 105 and 106 may be followed.
  • the voltage of each pixel unit in the third frame is the same as the polarity of the pixel in the third frame; and the eighth frame, the eighth frame and the fourth frame are displayed according to the method of displaying the fourth frame in steps 107 and 108.
  • the voltage polarity of the unit is the same.
  • the periodic screen display is performed with the four-frame picture as one polarity inversion driving period until the screen display ends.
  • the data voltage signal loaded by the pixel unit in the first frame picture display process does not undergo polarity inversion
  • the data voltage signal loaded by the pixel unit in the second frame picture display process has polarity inversion
  • the third frame During the display of the screen, the data voltage signal loaded by the pixel unit does not have polarity inversion, and the polarity of the data voltage signal loaded by the pixel unit during the fourth frame display is reversed, which means that every other frame is displayed.
  • the data line performs a polarity inversion on the data voltage signal loaded to the pixel unit.
  • any one of the four frames may be used as the start frame, and the picture may be displayed in the order of four frames or in reverse order.
  • the above four frames may be combined in an arbitrary order on the premise that the polarity of the data voltage signal loaded into the pixel unit every other frame is reversed.
  • the polarity inversion driving method may also invert the driving period by one of the other number of frame pictures.
  • the gate lines in this embodiment may be grouped into two adjacent gate lines as the first gate line and the second gate line, respectively, and in this case, the second embodiment is changed to every two frames ( That is, the second frame and the fourth frame shown in FIG.
  • the technical solution of the embodiment is a polarity inversion driving method of column inversion and dot inversion combining.
  • the polarity of the data voltage signal loaded by the data line to the pixel unit is displayed once every other frame, which can effectively reduce the power consumption of the display panel and avoid polarization of the liquid crystal material.
  • a third embodiment of the present invention provides a polarity inversion driving circuit for driving an array substrate, the array substrate comprising: a substrate substrate and a substrate formed on the substrate a gate line and a data line, the gate line and the data line defining a pixel unit, the gate line comprising: a first gate line and a second gate line, and a plurality of the first gate lines and the plurality of the first The two grid lines are alternately arranged.
  • the polarity inversion driving circuit includes: a gate line driving circuit connected to the first gate line and the second gate line; and a data driving circuit connected to the data line.
  • the gate line driving circuit is configured to sequentially turn on pixel units corresponding to the first gate lines through a first gate line, and sequentially turn on and the second through the second gate lines. a pixel unit corresponding to the gate line;
  • the data driving circuit is configured to load the first data voltage signal through the pixel unit of the odd-numbered column data line when the pixel unit corresponding to the first gate line is turned on when the pixel unit corresponding to the first gate line is turned on, and is connected through the even-numbered data line.
  • the pixel unit loads the second data voltage signal, and loads the third data voltage signal through the pixel unit of the odd-numbered column data line when the pixel unit corresponding to the second gate line is turned on, and the pixel that is turned through the even-numbered data line
  • the unit loads a fourth data voltage signal, the first data voltage signal and the second data voltage signal are opposite in polarity, and the third data voltage signal and the fourth data voltage signal are opposite in polarity.
  • the first data voltage signal has opposite polarity
  • the second data voltage signal has opposite polarity
  • the third data voltage signal has opposite polarity
  • the first The four data voltage signals have opposite polarities.
  • the first data voltage signals in the adjacent two frames are different, the second data voltage signals are different, the third data voltage signals are different, and the fourth data voltage signals are different.
  • the gate line driving circuit may include: a first gate line driving sub-circuit and a second gate line driving sub-circuit, wherein the plurality of rows of first gate lines may be connected to the first gate line driving sub-circuit, the plurality of rows
  • the second gate line can be connected to the second gate line driving sub-circuit, the first gate line driving sub-circuit is configured to sequentially turn on the pixel unit corresponding to the first gate line through the first gate line, and the second gate line driving sub-circuit is used The pixel unit corresponding to the second gate line is sequentially turned on through the second gate line.
  • the structure of the polarity inversion driving circuit can be seen in the above-mentioned Fig. 3.
  • two rows of the first gate line and two rows of the second gate line are alternately arranged.
  • the absolute values of the voltages of the first data voltage signal, the second data voltage signal, the third data voltage signal, and the fourth data voltage signal are equal.
  • the polarity inversion driving circuit uses a four-frame picture as a polarity inversion driving period.
  • the polarity inversion driving circuit provided in this embodiment can be used to implement the polarity inversion driving method provided in the first embodiment or the second embodiment.
  • the polarity inversion driving process refer to the first embodiment or the embodiment. The description in II will not be repeated here.
  • the polarity inversion driving circuit provided by the embodiment when the one frame is displayed, the first data voltage signal and the even data line loaded by the pixel unit of the odd column data line in the process of scanning the first gate line are scanned.
  • the second data voltage signal loaded by the conductive pixel unit is opposite in polarity, and the third data voltage signal loaded by the pixel unit of the odd-numbered column data line in the process of scanning the second gate line and the pixel unit of the even-numbered data line are loaded.
  • the fourth data voltage signal has the opposite polarity, which effectively reduces the number of polarity inversions, thereby reducing the power consumption of the display panel.
  • the polarity of the first data voltage signal is opposite
  • the polarity of the second data voltage signal is opposite
  • the polarity of the third data voltage signal is opposite
  • the polarity of the fourth data voltage signal is opposite, so in this embodiment,
  • the data voltage signal loaded by the data line to the pixel unit is inverted once in a frame display, which further reduces the number of polarity inversions, thereby further reducing the power consumption of the display panel.

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Abstract

一种极性反转驱动方法，包括：一帧画面显示时，通过第一栅线依次导通与该第一栅线对应的像素单元，通过奇数列数据线向导通的像素单元加载第一数据电压信号并通过偶数列数据线向导通的像素单元加载第二数据电压信号，第一数据电压信号和第二数据电压信号极性相反；通过第二栅线依次导通与该第二栅线对应的像素单元，通过奇数列数据线向导通的像素单元加载第三数据电压信号并通过偶数列数据线向导通的像素单元加载第四数据电压信号，第三数据电压信号和第四数据电压信号极性相反。该极性反转驱动方法降低了极性反转的次数，从而降低了显示面板的功耗。还公开了一种极性反转驱动电路。

Description

极性反转驱动方法和极性反转驱动电路 技术领域
本发明涉及显示技术领域， 特别涉及一种极性反转驱动方法和极性 反转驱动电路。 背景技术
液晶显示器是目前常用的平板显示器， 其中薄膜晶体管液晶显示器
(Thin Film Transistor Liquid Crystal Display, 简称 TFT- LCD)是液 晶显示器中的主流产品。 阵列基板是液晶显示器的重要部件。阵列基板包 括： 衬底基板和形成于衬底基板上的栅线和数据线， 栅线和数据线限定像 素单元。图 1为现有技术中阵列基板的像素单元阵列示意图，如图 1所示， 栅线 G1至 G7与数据线 D1至 D7限定出多个像素单元，栅线 G1至 G7均连 接至时序控制器。 时序控制器依次向栅线 G1至 G7上加载扫描信号， 从而 依次导通与栅线对应的各行像素单元；数据线 D1至 D7向导通的像素单元 加载数据电压信号，从而实现对像素单元的数据驱动以完成一帧画面的显 示， 其中， 数据电压信号可包括正向电压或者负向电压。
通常在液晶显示器中， 由于施加在液晶电容 Clc和存储电容 Cst两 端的电压信号的极性必须每隔一预定时间进行反转， 以避免液晶材料产生 极化而造成永久性的破坏，因此需要对阵列基板上的像素单元进行极性反 转驱动。 常见的极性反转包括： 帧反转、 列反转、 行反转和点反转四种。 其中， 在上一帧写入结束下一帧写入开始之前， 如果在整帧上的像素单元 所储存的电压极性都是相同的， 电压极性全部是正或全部是负）， 即称为 帧反转； 若是同一列上的像素单元所储存的电压极性都是相同的， 且左右 相邻列上的像素单元所储存的电压极性相反， 即称为列反转； 若是同一行 上的像素单元所储存的电压极性都是相同的，且上下相邻行上的像素单元 所储存的电压极性相反， 即称为行反转； 若是每个像素单元所储存的电压 极性与其上下左右相邻的像素单元所储存的电压极性均相反，即称为点反 转。为了提高整个显示画面的品质， 像素单元的点反转驱动方式已逐渐成 为目前主流的显示驱动方式。图 2为现有技术中极性反转驱动的驱动时序 图， 结合图 1和图 2所示， 图 2所示的为点反转的驱动时序图， 以数据线 D1为例， 若要实现点反转， 数据线 D1上加载的数据电压信号的极性需要 在每条栅线上加载扫描信号 （图 2中所示的高电平） 时反转一次。
综上所述， 现有技术中采用点反转驱动方式， 每扫描一行栅线时， 数据线上加载的数据电压信号就需要进行一次极性反转。在画面显示过程 中， 由于数据线上加载的数据电压信号频繁的进行极性反转， 从而极大的 增加了显示面板的功耗。 发明内容
本发明提供一种极性反转驱动方法和极性反转驱动电路， 用于降低 显示面板的功耗。
为实现上述目的， 本发明提供了一种极性反转驱动方法， 所述极性 反转驱动方法用于对阵列基板进行驱动， 所述阵列基板包括： 衬底基板和 形成于所述衬底基板上的栅线和数据线，所述栅线和所述数据线限定像素 单元， 所述栅线分成第一栅线和第二栅线， 其中相邻的 N行第一栅线和相 邻的 N行第二栅线交替设置， N为大于等于 1的整数；
所述极性反转驱动方法包括：
一帧画面显示时，通过所述第一栅线依次导通与每个第一栅线对应的 像素单元，通过奇数列数据线向导通的像素单元加载第一数据电压信号并 通过偶数列数据线向导通的像素单元加载第二数据电压信号，所述第一数 据电压信号和所述第二数据电压信号极性相反；
通过所述第二栅线依次导通与每个第二栅线对应的像素单元，通过奇 数列数据线向导通的像素单元加载第三数据电压信号并通过偶数列数据 线向导通的像素单元加载第四数据电压信号，所述第三数据电压信号和所 述第四数据电压信号极性相反。
可选地， 每隔一帧画面显示时， 所述第一数据电压信号、 所述第二 数据电压信号、所述第三数据电压信号以及所述第四数据电压信号的极性 每隔一帧画面反转一次。
可选地， 相邻两帧画面中的第一数据电压信号不同、 第二数据电压 信号不同、 第三数据电压信号不同以及第四数据电压信号不同。
可选地， 两行所述第一栅线和两行所述第二栅线交替设置。
可选地， 所述第一数据电压信号、 所述第二数据电压信号、 所述第 三数据电压信号和所述第四数据电压信号的电压绝对值相等。
可选地， 所述极性反转驱动方法以四帧画面为一个极性反转驱动周 期。
可选地， 所述四帧画面中任意一帧为起始帧， 以所述四帧画面的顺 序或者逆序方式进行极性反转。
为实现上述目的， 本发明提供了一种极性反转驱动电路， 所述极性 反转驱动电路用于对阵列基板进行驱动， 所述阵列基板包括： 衬底基板和 形成于所述衬底基板上的栅线和数据线，所述栅线和所述数据线限定像素 单元， 所述栅线分成第一栅线和第二栅线， 其中相邻的 N行第一栅线和相 邻的 N行第二栅线交替设置， N为大于等于 1的整数；
所述极性反转驱动电路包括： 与所述第一栅线和所述第二栅线连接 的栅线驱动电路和与所述数据线连接的数据驱动电路；
所述栅线驱动电路用于在一帧画面显示时通过所述第一栅线依次导 通与每个第一栅线对应的像素单元， 以及通过所述第二栅线依次导通与每 个第二栅线对应的像素单元；
数据驱动电路用于在一帧画面显示时当所述第一栅线对应的像素单 元导通时通过奇数列数据线向导通的像素单元加载第一数据电压信号并 通过偶数列数据线向导通的像素单元加载第二数据电压信号， 以及当所述 第二栅线对应的像素单元导通时通过奇数列数据线向导通的像素单元加 载第三数据电压信号并通过偶数列数据线向导通的像素单元加载第四数 据电压信号， 第一数据电压信号和第二数据电压信号极性相反， 第三数据 电压信号和第四数据电压信号极性相反。
可选地， 每隔一帧画面显示时， 所述第一数据电压信号、 所述第二 数据电压信号、所述第三数据电压信号以及所述第四数据电压信号的极性 每隔一帧画面反转一次。
可选地， 相邻两帧画面中的第一数据电压信号不同、 第二数据电压 信号不同、 第三数据电压信号不同以及第四数据电压信号不同。 可选地， 所述栅线驱动电路包括： 第一栅线驱动子电路和第二栅线 驱动子电路， 多行所述第一栅线均连接于所述第一栅线驱动子电路， 多行 所述第二栅线驱动子电路均连接于所述第二栅线驱动子电路；
所述第一栅线驱动子电路用于通过所述第一栅线依次导通与每个第 一栅线对应的像素单元，第二栅线驱动子电路用于通过所述第二栅线依次 导通与每个第二栅线对应的像素单元。
可选地， 两行所述第一栅线和两行所述第二栅线交替设置。
本发明具有以下有益效果：
本发明提供的极性反转驱动方法和极性反转驱动电路的技术方案 中， 一帧画面显示时， 扫描第一栅线过程中奇数列数据线向导通的像素单 元加载的第一数据电压信号以及偶数列数据线向导通的像素单元加载的 第二数据电压信号极性相反，扫描第二栅线过程中奇数列数据线向导通的 像素单元加载的第三数据电压信号以及偶数列数据线向导通的像素单元 加载的第四数据电压信号极性相反， 有效降低了极性反转的次数， 从而降 低了显示面板的功耗。每隔一帧画面显示时， 第一数据电压信号、第二数 据电压信号、 第三数据电压信号以及第四数据电压信号的极性反转一次， 因此本发明中数据线向像素单元加载的数据电压信号每隔一帧画面进行 一次极性反转，有效降低了极性反转的次数，从而降低了显示面板的功耗。 附图说明
图 1为现有技术中阵列基板的像素单元阵列示意图；
图 2为现有技术中极性反转驱动的驱动时序图；
图 3为本发明中阵列基板的示意图；
图 4为实施例二中极性反转驱动方法的驱动时序图；
图 5为实施例二中极性反转驱动方法的各帧极性示意图。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案， 下面结合附 图对本发明提供的极性反转驱动方法和极性反转驱动电路进行详细描述。
本发明实施例一提供了一种极性反转驱动方法， 该极性反转驱动方 法用于对阵列基板进行驱动。其中， 阵列基板包括： 衬底基板和形成于衬 底基板上的栅线和数据线， 栅线和数据线限定像素单元， 栅线包括： 第一 栅线和第二栅线， 且多个第一栅线和多个第二栅线交替设置。则极性反转 驱动方法包括： 一帧画面显示时，通过第一栅线依次导通与第一栅线对应 的像素单元，通过奇数列数据线向导通的像素单元加载第一数据电压信号 并通过偶数列数据线向导通的像素单元加载第二数据电压信号，第一数据 电压信号和第二数据电压信号极性相反；通过第二栅线依次导通与第二栅 线对应的像素单元，通过奇数列数据线向导通的像素单元加载第三数据电 压信号并通过偶数列数据线向导通的像素单元加载第四数据电压信号，第 三数据电压信号和第四数据电压信号极性相反。
本实施例中， 优选地， 每隔一帧画面显示时， 第一数据电压信号极 性相反、第二数据电压信号极性相反、第三数据电压信号极性相反以及第 四数据电压信号极性相反，这表明每隔一帧画面数据线向像素单元加载的 数据电压信号进行了一次极性反转。
本实施例中， 优选地， 相邻两帧画面中的第一数据电压信号不同、 第二数据电压信号不同、第三数据电压信号不同以及第四数据电压信号不 同。
本实施例中， 优选地， 两行第一栅线和两行第二栅线交替设置。 也 就是说， 在阵列基板上， 先设置两行第一栅线， 而后设置两行第二栅线， 再按照上述规律依次设置第一栅线和第二栅线，从而实现了两行第一栅线 和两行第二栅线的交替设置。
本实施例中， 优选地， 第一数据电压信号、 第二数据电压信号、 第 三数据电压信号和第四数据电压信号的电压绝对值相等。
本实施例中， 优选地， 极性反转驱动方法以四帧画面为一个极性反 转驱动周期。
本实施例提供的极性反转驱动方法的技术方案中， 一帧画面显示时， 扫描第一栅线过程中奇数列数据线向导通的像素单元加载的第一数据电 压信号以及偶数列数据线向导通的像素单元加载的第二数据电压信号极 性相反，扫描第二栅线过程中奇数列数据线向导通的像素单元加载的第三 数据电压信号以及偶数列数据线向导通的像素单元加载的第四数据电压 信号极性相反，有效降低了极性反转的次数，从而降低了显示面板的功耗。 每隔一帧画面显示时， 第一数据电压信号、第二数据电压信号、第三数据 电压信号以及第四数据电压信号的极性反转一次， 因此本实施例中每隔一 帧画面显示时数据线向像素单元加载的数据电压信号进行一次极性反转， 进一步降低了极性反转的次数， 从而进一步降低了显示面板的功耗。
下面通过一个具体的实施例二对本发明提供的极性反转驱动方法的 技术方案进行详细描述。
图 3为本发明中阵列基板的示意图， 如图 3所示， 阵列基板包括： 衬底基板（未具体画出）和形成于衬底基板上的栅线和数据线 D1至 D7， 栅线和数据线限定像素单元， 栅线可包括： 第一栅线 Gl、 G2、 G5与 G6和 第二栅线 G3、 G4、 G7与 G8。 且两行第一栅线和两行第二栅线交替设置， 具体地， 在衬底基板上， 栅线的设置顺序为： 第一栅线 Gl、 第一栅线 G2、 第二栅线 G3、 第二栅线 G4、 第一栅线 G5、 第一栅线 G6、 第二栅线 G7和 第二栅线 G8。需要说明的是： 图 3中仅画出了部分栅线和部分数据线，本 领域技术人员应当知晓图 3中的阵列基板上包括但不限于上述数量的栅线 和数据线。其中， 第一栅线和第二栅线可与栅极驱动电路连接， 数据线可 与数据驱动电路连接。作为一个优选实施例， 栅极驱动电路可包括第一栅 线驱动子电路和第二栅线驱动子电路， 因此上述各行第一栅线均可连接于 第一栅线驱动子电路， 上述各行第二栅线均可连接于第二栅线驱动子电 路，第一栅线驱动子电路用于驱动第一栅线以导通与第一栅线对应的像素 单元，第二栅线驱动子电路用于驱动第二栅线以导通与第二栅线对应的像 素单元。
本实施例提供的极性反转驱动方法用于驱动图 3中的上述阵列基板。 且本实施例中， 极性反转驱动方法以四帧画面为一个极性反转驱动周期。 本实施例中， 以工作频率为 60赫兹的液晶显示器为例， 其一帧的扫描时 间为 16. 7毫秒。假定液晶显示器的像素分辨率为 1024X768， 每一行栅线 的扫描时间 （打开时间） 为 21. 7微秒。
图 4为实施例二中极性反转驱动方法的驱动时序图， 图 5为实施例 二中极性反转驱动方法的各帧极性示意图， 需要说的是： 图 4中仅画出了 部分数据线的驱动时序作为示例。 如图 4、 图 5所示， 该极性反转驱动方 法包括：
步骤 101、在第一帧画面显示时，通过第一栅线依次导通与第一栅线 对应的像素单元，通过奇数列数据线向导通的像素单元加载第一数据电压 信号并通过偶数列数据线向导通的像素单元加载第二数据电压信号，第一 数据电压信号为正向电压， 第二数据电压信号为负向电压。
步骤 101具体可包括：
第一栅线驱动子电路向第一栅线 G1输出扫描信号以使第一栅线 G1 打开， 该扫描信号为高电平信号， 其余栅线关闭。 当第一栅线 G1打开时 导通与第一栅线 G1对应的一行像素单元， 此时奇数列数据线 Dl、 D3、 D5 和 D7向导通的像素单元加载正向电压（图 4中表示为高电平信号， 图 5 中所示的 "+" ) ， 偶数列数据线 D2、 D4、 D6和 D8向导通的像素单元加 载负向电压（图 4中表示为低电平信号， 图 5中所示的 "_，， ) 。 本实施 例中， 优选地， 针对同一像素单元的正向电压和负向电压的电压绝对值相 等； 换句话说， 本发明仅对施加到像素单元的数据信号的极性进行反转， 极性反转并不改变原数据信号的幅值。
按照打开第一栅线 G1的方式， 依次打开其余第一栅线 G2、 G5和 G6 等， 当其中某一行第一栅线打开时可通过奇数列数据线 Dl、 D3、 D5和 D7 向导通的一行像素单元加载正向电压以及通过偶数列数据线 D2、 D4、 D6 和 D8向导通的一行像素单元加载负向电压， 直至所有的第一栅线扫描完 毕。
步骤 102、通过第二栅线依次导通与第二栅线对应的像素单元，通过 奇数列数据线向导通的像素单元加载第三数据电压信号并通过偶数列数 据线向导通的像素单元加载第四数据电压信号，第三数据电压信号为正向 电压， 第四数据电压信号为负向电压。
步骤 102具体可包括：
第二栅线驱动子电路向第二栅线 G3输出扫描信号以使第二栅线 G3 打开， 该扫描信号为高电平信号， 其余栅线关闭。 当第二栅线 G3打开时 导通与第二栅线 G3对应的一行像素单元， 此时奇数列数据线 Dl、 D3、 D5 和 D7向导通的像素单元加载正向电压， 偶数列数据线 D2、 D4、 D6和 D8 向导通的像素单元加载负向电压。 按照打开第二栅线 G3的方式， 依次打开其余第二栅线 G4、 G7和 G8 等， 当其中某一行第二栅线打开时可通过奇数列数据线 Dl、 D3、 D5和 D7 向导通的一行像素单元加载正向电压以及通过偶数列数据线 D2、 D4、 D6 和 D8向导通的一行像素单元加载负向电压， 直至所有的第二栅线扫描完 毕。
至此， 第一帧画面显示完毕， 第一帧画面中各像素单元的电压极性 可参见图 5所示， 在显示第一帧画面过程中， 各个数据线向第一栅线对应 的像素单元加载的数据电压信号的极性与该数据线向第二栅线对应的像 素单元加载的数据电压信号的极性相同， 因此第一帧画面显示过程中数据 线向像素单元加载的数据电压信号未进行极性反转。
步骤 103、在第二帧画面显示时，通过第一栅线依次导通与第一栅线 对应的像素单元，通过奇数列数据线向导通的像素单元加载第一数据电压 信号并通过偶数列数据线向导通的像素单元加载第二数据电压信号，第一 数据电压信号为正向电压， 第二数据电压信号为负向电压。
步骤 103具体可包括：
第一栅线驱动子电路向第一栅线 G1输出扫描信号以使第一栅线 G1 打开， 该扫描信号为高电平信号， 其余栅线关闭。 当第一栅线 G1打开时 导通与第一栅线 G1对应的一行像素单元， 此时奇数列数据线 Dl、 D3、 D5 和 D7向导通的像素单元加载正向电压， 偶数列数据线 D2、 D4、 D6和 D8 向导通的像素单元加载负向电压。
按照打开第一栅线 G1的方式， 依次打开其余第一栅线 G2、 G5和 G6 等， 当其中某一行第一栅线打开时可通过奇数列数据线 Dl、 D3、 D5和 D7 向导通的一行像素单元加载正向电压以及通过偶数列数据线 D2、 D4、 D6 和 D8向导通的一行像素单元加载负向电压， 直至所有的第一栅线扫描完 毕。
步骤 104、通过第二栅线依次导通与第二栅线对应的像素单元，通过 奇数列数据线向导通的像素单元加载第三数据电压信号并通过偶数列数 据线向导通的像素单元加载第四数据电压信号，第三数据电压信号为负向 电压， 第四数据电压信号为正向电压。
步骤 104具体可包括： 第二栅线驱动子电路向第二栅线 G3输出扫描信号以使第二栅线 G3 打开， 该扫描信号为高电平信号， 其余栅线关闭。 当第二栅线 G3打开时 导通与第二栅线 G3对应的一行像素单元， 此时奇数列数据线 Dl、 D3、 D5 和 D7向导通的像素单元加载负向电压， 偶数列数据线 D2、 D4、 D6和 D8 向导通的像素单元加载正向电压。
按照打开第二栅线 G3的方式， 依次打开其余第二栅线 G4、 G7和 G8 等， 当其中某一行第二栅线打开时可通过奇数列数据线 Dl、 D3、 D5和 D7 向导通的一行像素单元加载负向电压以及通过偶数列数据线 D2、 D4、 D6 和 D8向导通的一行像素单元加载正向电压， 直至所有的第二栅线扫描完 毕。
至此， 第二帧画面显示完毕， 第二帧画面中各像素单元的电压极性 可参见图 5所示， 在显示第二帧画面过程中， 各个数据线向第一栅线对应 的像素单元加载的数据电压信号的极性与该数据线向第二栅线对应的像 素单元加载的数据电压信号的极性相反， 因此第二帧画面显示过程中数据 线向像素单元加载的数据电压信号进行了一次极性反转。
步骤 105、在第三帧画面显示时，通过第一栅线依次导通与第一栅线 对应的像素单元，通过奇数列数据线向导通的像素单元加载第一数据电压 信号并通过偶数列数据线向导通的像素单元加载第二数据电压信号，第一 数据电压信号为负向电压， 第二数据电压信号为正向电压。
步骤 105具体可包括：
第一栅线驱动子电路向第一栅线 G1输出扫描信号以使第一栅线 G1 打开， 该扫描信号为高电平信号， 其余栅线关闭。 当第一栅线 G1打开时 导通与第一栅线 G1对应的一行像素单元， 此时奇数列数据线 Dl、 D3、 D5 和 D7向导通的像素单元加载负向电压， 偶数列数据线 D2、 D4、 D6和 D8 向导通的像素单元加载正向电压。
按照打开第一栅线 G1的方式， 依次打开其余第一栅线 G2、 G5和 G6 等， 当其中某一行第一栅线打开时可通过奇数列数据线 Dl、 D3、 D5和 D7 向导通的一行像素单元加载负向电压以及通过偶数列数据线 D2、 D4、 D6 和 D8向导通的一行像素单元加载正向电压， 直至所有的第一栅线扫描完 毕。 步骤 106、通过第二栅线依次导通与第二栅线对应的像素单元，通过 奇数列数据线向导通的像素单元加载第三数据电压信号并通过偶数列数 据线向导通的像素单元加载第四数据电压信号，第三数据电压信号为负向 电压， 第四数据电压信号为正向电压。
步骤 106具体可包括：
第二栅线驱动子电路向第二栅线 G3输出扫描信号以使第二栅线 G3 打开， 该扫描信号为高电平信号， 其余栅线关闭。 当第二栅线 G3打开时 导通与第二栅线 G3对应的一行像素单元， 此时奇数列数据线 Dl、 D3、 D5 和 D7向导通的像素单元加载负向电压， 偶数列数据线 D2、 D4、 D6和 D8 向导通的像素单元加载正向电压。
按照打开第二栅线 G3的方式， 依次打开其余第二栅线 G4、 G7和 G8 等， 当其中某一行第二栅线打开时可通过奇数列数据线 Dl、 D3、 D5和 D7 向导通的一行像素单元加载负向电压以及通过偶数列数据线 D2、 D4、 D6 和 D8向导通的一行像素单元加载正向电压， 直至所有的第二栅线扫描完 毕。
至此， 第三帧画面显示完毕， 第三帧画面中各像素单元的电压极性 可参见图 5所示， 在显示第三帧画面过程中， 各个数据线向第一栅线对应 的像素单元加载的数据电压信号的极性与该数据线向第二栅线对应的像 素单元加载的数据电压信号的极性相同， 因此第三帧画面显示过程中数据 线向像素单元加载的数据电压信号未进行极性反转。
步骤 107、在第四帧画面显示时，通过第一栅线依次导通与第一栅线 对应的像素单元，通过奇数列数据线向导通的像素单元加载第一数据电压 信号并通过偶数列数据线向导通的像素单元加载第二数据电压信号，第一 数据电压信号为负向电压， 第二数据电压信号为正向电压。
步骤 107具体可包括：
第一栅线驱动子电路向第一栅线 G1输出扫描信号以使第一栅线 G1 打开， 该扫描信号为高电平信号， 其余栅线关闭。 当第一栅线 G1打开时 导通与第一栅线 G1对应的一行像素单元， 此时奇数列数据线 Dl、 D3、 D5 和 D7向导通的像素单元加载负向电压， 偶数列数据线 D2、 D4、 D6和 D8 向导通的像素单元加载正向电压。 按照打开第一栅线 G1的方式， 依次打开其余第一栅线 G2、 G5和 G6 等， 当其中某一行第一栅线打开时可通过奇数列数据线 Dl、 D3、 D5和 D7 向导通的一行像素单元加载负向电压以及通过偶数列数据线 D2、 D4、 D6 和 D8向导通的一行像素单元加载正向电压， 直至所有的第一栅线扫描完 毕。
步骤 108、通过第二栅线依次导通与第二栅线对应的像素单元，通过 奇数列数据线向导通的像素单元加载第三数据电压信号并通过偶数列数 据线向导通的像素单元加载第四数据电压信号，第三数据电压信号为正向 电压， 第四数据电压信号为负向电压。
步骤 108具体可包括：
第二栅线驱动子电路向第二栅线 G3输出扫描信号以使第二栅线 G3 打开， 该扫描信号为高电平信号， 其余栅线关闭。 当第二栅线 G3打开时 导通与第二栅线 G3对应的一行像素单元， 此时奇数列数据线 Dl、 D3、 D5 和 D7向导通的像素单元加载正向电压， 偶数列数据线 D2、 D4、 D6和 D8 向导通的像素单元加载负向电压。
按照打开第二栅线 G3的方式， 依次打开其余第二栅线 G4、 G7和 G8 等， 当其中某一行第二栅线打开时可通过奇数列数据线 Dl、 D3、 D5和 D7 向导通的一行像素单元加载正向电压以及通过偶数列数据线 D2、 D4、 D6 和 D8向导通的一行像素单元加载负向电压， 直至所有的第二栅线扫描完 毕。
至此， 第四帧画面显示完毕， 第四帧画面中各像素单元的电压极性 可参见图 5所示， 在显示第四帧画面过程中， 各个数据线向第一栅线对应 的像素单元加载的数据电压信号的极性与该数据线向第二栅线对应的像 素单元加载的数据电压信号的极性相反， 因此第四帧画面显示过程中数据 线向像素单元加载的数据电压信号进行了一次极性反转。
进一步地， 可按照步骤 101和步骤 102中显示第一帧画面的方法显 示第五帧画面， 第五帧画面与第一帧画面中各像素单元的电压极性相同； 进而可按照步骤 103和步骤 104中显示第二帧画面的方法显示第六帧画 面， 第六帧画面与第二帧画面中各像素单元的电压极性相同； 进而可按照 步骤 105和步骤 106中显示第三帧画面的方法显示第七帧画面，第七帧画 面与第三帧画面中各像素单元的电压极性相同；进而可按照步骤 107和步 骤 108中显示第四帧画面的方法显示第八帧画面，第八帧画面与第四帧画 面中各像素单元的电压极性相同。依照上述极性反转驱动方法， 以四帧画 面为一个极性反转驱动周期进行周期性画面显示， 直至画面显示结束。
本实施例中， 第一帧画面显示过程中像素单元加载的数据电压信号 未发生极性反转，第二帧画面显示过程中像素单元加载的数据电压信号发 生了极性反转，第三帧画面显示过程中像素单元加载的数据电压信号未发 生极性反转，第四帧画面显示过程中像素单元加载的数据电压信号发生了 极性反转， 由此可知， 每隔一帧画面显示时数据线向像素单元加载的数据 电压信号进行一次极性反转。
在实际应用中， 可选地， 可将四帧画面中任意一帧作为起始帧， 并 以四帧画面的顺序或者逆序方式显示画面。可选地， 在满足每隔一帧画面 向像素单元加载的数据电压信号进行一次极性反转的前提下，还可以将上 述四帧画面以任意顺序进行组合。另外， 可选地， 极性反转驱动方法还可 以以其它数量帧画面为一个极性反转驱动周期。作为变型例， 可以将本实 施例中的栅线分组为相邻的两行栅线分别为第一栅线和第二栅线， 此时， 将实施例二变成以每两帧为周期（即图 5所示的第二帧及第四帧）进行极 性反转驱动， 在每帧画面中进行极性反转。另外， 以相邻的 N (N>2)行栅 线分组为第一栅线、后续的 N行栅线为第二栅线、依次交替设置的情况与 实施例二的情形类似， 均是每隔一帧画面进行极性反转， 在此不再详述。
综上所述， 本实施例的技术方案是一种列反转和点反转复合的极性 反转驱动方法。每隔一帧画面显示时数据线向像素单元加载的数据电压信 号进行一次极性反转， 在有效降低显示面板功耗的同时， 还可以避免液晶 材料产生极化现象。
本发明实施例三提供了一种极性反转驱动电路， 该极性反转驱动电 路用于对阵列基板进行驱动， 所述阵列基板包括： 衬底基板和形成于所述 衬底基板上的栅线和数据线， 所述栅线和所述数据线限定像素单元， 所述 栅线包括： 第一栅线和第二栅线， 且多个所述第一栅线和多个所述第二栅 线交替设置。所述极性反转驱动电路包括： 与所述第一栅线和所述第二栅 线连接的栅线驱动电路和与所述数据线连接的数据驱动电路。 所述栅线驱动电路用于在一帧画面显示时通过第一栅线依次导通与 所述第一栅线对应的像素单元， 以及通过所述第二栅线依次导通与所述第 二栅线对应的像素单元；
数据驱动电路用于在一帧画面显示时当所述第一栅线对应的像素单 元导通时通过奇数列数据线向导通的像素单元加载第一数据电压信号并 通过偶数列数据线向导通的像素单元加载第二数据电压信号， 以及当所述 第二栅线对应的像素单元导通时通过奇数列数据线向导通的像素单元加 载第三数据电压信号并通过偶数列数据线向导通的像素单元加载第四数 据电压信号， 所述第一数据电压信号和所述第二数据电压信号极性相反， 所述第三数据电压信号和所述第四数据电压信号极性相反。
本实施例中， 优选地， 每隔一帧画面显示时， 所述第一数据电压信 号极性相反、第二数据电压信号极性相反、所述第三数据电压信号极性相 反以及所述第四数据电压信号极性相反。
本实施例中， 优选地， 相邻两帧画面中的第一数据电压信号不同、 第二数据电压信号不同、第三数据电压信号不同以及第四数据电压信号不 同。
作为一个优选实施例， 栅线驱动电路可包括： 第一栅线驱动子电路 和第二栅线驱动子电路， 多行第一栅线均可连接于第一栅线驱动子电路， 多行第二栅线均可连接于第二栅线驱动子电路，第一栅线驱动子电路用于 通过第一栅线依次导通与第一栅线对应的像素单元，第二栅线驱动子电路 用于通过第二栅线依次导通与第二栅线对应的像素单元。本实施例中， 极 性反转驱动电路的结构可参见上述附图 3中所示。
优选地， 两行所述第一栅线和两行所述第二栅线交替设置。
优选地， 第一数据电压信号、 所述第二数据电压信号、 所述第三数 据电压信号和所述第四数据电压信号的电压绝对值相等。
优选地， 所述极性反转驱动电路以四帧画面为一个极性反转驱动周 期。
本实施例提供的极性反转驱动电路可用于实现上述实施例一或者实 施例二提供的极性反转驱动方法，对极性反转驱动过程的具体描述可参见 上述实施例一或者实施例二中的描述， 此处不再赘述。 本实施例提供的极性反转驱动电路的技术方案中， 一帧画面显示时， 扫描第一栅线过程中奇数列数据线向导通的像素单元加载的第一数据电 压信号以及偶数列数据线向导通的像素单元加载的第二数据电压信号极 性相反，扫描第二栅线过程中奇数列数据线向导通的像素单元加载的第三 数据电压信号以及偶数列数据线向导通的像素单元加载的第四数据电压 信号极性相反，有效降低了极性反转的次数，从而降低了显示面板的功耗。 每隔一帧画面显示时， 第一数据电压信号极性相反、第二数据电压信号极 性相反、第三数据电压信号极性相反以及第四数据电压信号极性相反， 因 此本实施例中每隔一帧画面显示时数据线向像素单元加载的数据电压信 号进行一次极性反转， 进一步降低了极性反转的次数， 从而进一步降低了 显示面板的功耗。
可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而采用 的示例性实施方式， 然而本发明并不局限于此。对于本领域内的普通技术 人员而言， 在不脱离本发明的精神和实质的情况下， 可以做出各种变型和 改进， 这些变型和改进也视为本发明的保护范围。

Claims

权 利 要 求 书
1、 一种极性反转驱动方法， 其特征在于， 所述极性反转驱动方法用 于对阵列基板进行驱动， 所述阵列基板包括： 衬底基板和形成于所述衬底 基板上的栅线和数据线， 所述栅线和所述数据线限定像素单元， 所述栅线 分成第一栅线和第二栅线，其中相邻的 N行第一栅线和相邻的 N行第二栅 线交替设置， N为大于等于 1的整数；
所述极性反转驱动方法包括：
在一帧画面的显示过程中， 通过所述第一栅线依次导通与每个第一 栅线对应的像素单元，通过奇数列数据线向导通的像素单元加载第一数据 电压信号并通过偶数列数据线向导通的像素单元加载第二数据电压信号， 所述第一数据电压信号和所述第二数据电压信号极性相反；
通过所述第二栅线依次导通与每个第二栅线对应的像素单元， 通过 奇数列数据线向导通的像素单元加载第三数据电压信号并通过偶数列数 据线向导通的像素单元加载第四数据电压信号，所述第三数据电压信号和 所述第四数据电压信号极性相反。
2、 根据权利要求 1所述的极性反转驱动方法， 其特征在于， 所述第 一数据电压信号、所述第二数据电压信号、所述第三数据电压信号以及所 述第四数据电压信号的极性每隔一帧画面反转一次。
3、 根据权利要求 1所述的极性反转驱动方法， 其特征在于， 相邻两 帧画面中的第一数据电压信号不同、第二数据电压信号不同、第三数据电 压信号不同以及第四数据电压信号不同。
4、 根据权利要求 1所述的极性反转驱动方法， 其特征在于， 相邻的 两行所述第一栅线和相邻的两行所述第二栅线交替设置。
5、 根据权利要求 1所述的极性反转驱动方法， 其特征在于， 所述第 一数据电压信号、所述第二数据电压信号、所述第三数据电压信号和所述 第四数据电压信号的电压绝对值相等。
6、 根据权利要求 4所述的极性反转驱动方法， 其特征在于， 所述极 性反转驱动方法以四帧画面为一个极性反转驱动周期。
7、 根据权利要求 6所述的极性反转驱动方法， 其特征在于， 以所述 四帧画面的顺序或者逆序方式进行极性反转。
8、 一种极性反转驱动电路， 其特征在于， 所述极性反转驱动电路用 于对阵列基板进行驱动， 所述阵列基板包括： 衬底基板和形成于所述衬底 基板上的栅线和数据线， 所述栅线和所述数据线限定像素单元， 所述栅线 分成第一栅线和第二栅线，其中相邻的 N行第一栅线和相邻的 N行第二栅 线交替设置， N为大于等于 1的整数；
所述极性反转驱动电路包括： 与所述第一栅线和所述第二栅线连接 的栅线驱动电路和与所述数据线连接的数据驱动电路；
所述栅线驱动电路用于在一帧画面显示时通过所述第一栅线依次导 通与每个第一栅线对应的像素单元， 以及通过所述第二栅线依次导通与每 个第二栅线对应的像素单元；
数据驱动电路用于在一帧画面显示时当所述第一栅线对应的像素单 元导通时通过奇数列数据线向导通的像素单元加载第一数据电压信号并 通过偶数列数据线向导通的像素单元加载第二数据电压信号， 以及当所述 第二栅线对应的像素单元导通时通过奇数列数据线向导通的像素单元加 载第三数据电压信号并通过偶数列数据线向导通的像素单元加载第四数 据电压信号， 所述第一数据电压信号和所述第二数据电压信号极性相反， 所述第三数据电压信号和所述第四数据电压信号极性相反。
9、 根据权利要求 8所述的极性反转驱动电路， 其特征在于， 所述第 一数据电压信号、所述第二数据电压信号、所述第三数据电压信号以及所 述第四数据电压信号的极性每隔一帧画面反转一次。
10、 根据权利要求 8所述的极性反转驱动电路， 其特征在于， 相邻 两帧画面中的第一数据电压信号不同、第二数据电压信号不同、第三数据 电压信号不同以及第四数据电压信号不同。
11、 根据权利要求 8所述的极性反转驱动电路， 其特征在于， 所述 栅线驱动电路包括： 第一栅线驱动子电路和第二栅线驱动子电路， 多行所 述第一栅线均连接于所述第一栅线驱动子电路，多行所述第二栅线驱动子 电路均连接于所述第二栅线驱动子电路；
所述第一栅线驱动子电路用于通过所述第一栅线依次导通与所述第 一栅线对应的像素单元，第二栅线驱动子电路用于通过所述第二栅线依次 导通与所述第二栅线对应的像素单元。
12、 根据权利要求 8所述的极性反转驱动电路， 其特征在于， 相邻 的两行所述第一栅线和相邻的两行所述第二栅线交替设置。
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