WO2019085051A1 - 薄膜晶体管阵列基板及其制备方法、显示装置 - Google Patents

薄膜晶体管阵列基板及其制备方法、显示装置 Download PDF

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WO2019085051A1
WO2019085051A1 PCT/CN2017/112062 CN2017112062W WO2019085051A1 WO 2019085051 A1 WO2019085051 A1 WO 2019085051A1 CN 2017112062 W CN2017112062 W CN 2017112062W WO 2019085051 A1 WO2019085051 A1 WO 2019085051A1
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film transistor
array substrate
transistor array
thin film
layer
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PCT/CN2017/112062
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English (en)
French (fr)
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查国伟
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武汉华星光电技术有限公司
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Priority to US15/578,267 priority Critical patent/US10692889B2/en
Publication of WO2019085051A1 publication Critical patent/WO2019085051A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133502—Antiglare, refractive index matching layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133302—Rigid substrates, e.g. inorganic substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array substrate and a method for fabricating the same, and to a display device including the thin film transistor array substrate.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • LCD liquid crystal display
  • OLED organic light emitting display
  • a Thin Film Transistor (TFT) array substrate is an important component of a flat panel display device and can be formed on a glass substrate or a plastic substrate, and is used as a light-emitting device and a driving device such as an LCD or an OLED.
  • FIG. 1 is a schematic structural view of a conventional thin film transistor array substrate.
  • the layer 8 and the pixel electrode layer 9 are mainly composed of an active layer 3, a gate insulating layer 4, a gate layer 5, an interlayer dielectric layer 6, and a source/drain layer 7.
  • the buffer layer 2 is first disposed on the substrate substrate 1, and then the buffer layer is provided. 2
  • a film layer structure for forming a thin film transistor is prepared, and the material of the buffer layer 2 is made of a high density of SiN x , which causes a problem of loss of transmittance of the array substrate.
  • the conventional improvement of the transmittance of the display panel or the brightness performance by improving the aperture ratio, the color resistivity, the backlight brightness, the liquid crystal efficiency, etc. has gradually faced a bottleneck, and how to balance the thin film transistor Improving the transmittance of the array substrate under the premise that the electrical performance is not attenuated becomes a key technical problem.
  • the present invention provides a thin film transistor array substrate and a method for fabricating the same, which improves the light transmittance of the array substrate by improving the connection interface between the substrate substrate and the buffer layer in the array substrate.
  • a thin film transistor array substrate includes a glass substrate and a buffer layer and a pixel structure layer disposed on the first surface of the glass substrate, wherein the first surface of the glass substrate is formed with a plurality of patterned microscopic micro The structure, the buffer layer and the first surface are in mesh with each other.
  • the area of the cross section of the three-dimensional microstructure gradually decreases along the height direction of the three-dimensional microstructure.
  • the three-dimensional microstructure is a conical structure or a truncated cone structure.
  • the height of the three-dimensional microstructure is H
  • the diameter of the bottom of the three-dimensional microstructure is R1
  • the diameter of the top of the three-dimensional microstructure is R2; wherein, 100 nm ⁇ R1 ⁇ 500 nm, 100 nm ⁇ R1 ⁇ 400 nm, 0 ⁇ R2 ⁇ 400 nm, and R2 ⁇ R1.
  • the material of the buffer layer is SiN x .
  • the pixel structure layer comprises a plurality of conductive functional layers and an interlayer insulating layer between any two conductive functional layers, and the material of the interlayer insulating layer is SiO x .
  • the plurality of stereoscopic microstructures are arranged in a regular array on the first surface.
  • the present invention also provides a method of fabricating a thin film transistor array substrate as described above, comprising the steps of:
  • S1 providing a glass substrate, preparing a first surface comprising a plurality of patterned micro-structures on the glass substrate; specifically comprising: S11, applying an anodizing process to prepare a porous alumina stencil having a concave-convex structure; S12, Coating a photoresist layer on the glass substrate, transferring a pattern of the porous alumina stencil to the photoresist layer by using an imprint process to form a photoresist mask; S13, in the photolithography Etching the surface of the glass substrate under the protection of the offset mask to prepare a first surface comprising a plurality of patterned micro-structures;
  • Another aspect of the present invention is to provide a display device including the thin film transistor array substrate as described above.
  • the thin film transistor array substrate provided in the embodiment of the invention is improved by connecting the connection interface between the substrate substrate and the buffer layer in the array substrate, in particular, a plurality of patterned three-dimensional microstructures are arranged between the connection interfaces of the two. That is, the moth eye film tapered structure is formed, thereby forming a connection gradient interface structure between the base substrate and the buffer layer, reducing the reflection of the light on the connection interface, and effectively improving the light transmittance of the array substrate. .
  • FIG. 1 is a schematic structural view of a conventional thin film transistor array substrate
  • FIG. 2 is a schematic structural diagram of a thin film transistor array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a three-dimensional microstructure in an embodiment of the present invention.
  • Figure 4 is a cross-sectional view taken along line X-Y in Figure 3;
  • FIG. 5 is a process flow diagram of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • FIG. 6 is a process flow diagram of preparing a plurality of three-dimensional microstructures formed by patterning in an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention.
  • the thin film transistor array substrate includes a glass substrate 10 and a buffer layer 20 and a pixel structure disposed on the first surface 10a of the glass substrate 10.
  • Layer 30 The thin film transistor array substrate includes a glass substrate 10 and a buffer layer 20 and a pixel structure disposed on the first surface 10a of the glass substrate 10.
  • the material of the buffer layer 20 is selected to be SiN x .
  • the use of the high-density SiN x as the material of the buffer layer 20 can block the ions contained in the glass substrate 10 or the water and oxygen generated in the preparation process, which adversely affects the performance of the thin film transistor. Further, in some further embodiments, may also be provided to add material on the layer of SiN x SiO x material layer, the material layer and the SiN x SiO x material layers together form a buffer layer.
  • a plurality of patterned micro-structures 11 are formed on the first surface 10a of the glass substrate 10.
  • the buffer layer 20 and the first surface 10a are mutually toothed. That is, the buffer layer 20 fills the gap of the stereoscopic microstructure 11 and covers the stereoscopic microstructure 11, and the buffer layer 20 is closely coupled with the first surface 10a. .
  • the area of the cross section of the stereoscopic microstructure 11 is gradually decreased, and the SiN x material correspondingly filled between the adjacent two stereoscopic microstructures 11 is correspondingly The cross section is gradually increasing.
  • connection interface forms a structure with a gradient of the refractive index, which reduces the reflection of light by the connection interface, and effectively improves the light transmittance of the array substrate.
  • the three-dimensional microstructure 11 is a truncated cone structure.
  • the height of the three-dimensional microstructure 11 is H
  • the diameter of the bottom of the three-dimensional microstructure 11 is R1
  • the diameter of the top of the three-dimensional microstructure 11 is R2.
  • the diameter R2 of the top of the three-dimensional microstructure 11 is preferably set to 0.
  • the three-dimensional microstructure 11 has a conical structure. It should be noted that only a few stereo microstructures 11 are exemplarily shown in FIGS. 3 and 4.
  • the duty ratio of the stereo microstructure 11 is k, 0.3 ⁇ k ⁇ 1.
  • the plurality of solid microstructures 11 are arranged in a regular array on the first surface 10a.
  • the pixel structure layer 30 comprises a plurality of conductive functional layers and an interlayer insulating layer between any two conductive functional layers.
  • the pixel structure layer 30 includes an active layer 31 formed on the buffer layer 20 , and a gate insulating layer 32 disposed on the active layer 31 .
  • the plurality of conductive functional layers include the active layer 31, the gate electrode 33, the source electrode 35 and the drain electrode 36, and the pixel electrode 38 and the like as described above;
  • the interlayer insulating layer includes the gate electrode as described above The insulating layer 32, the interlayer dielectric layer 34, the flat layer 37, and the like.
  • the plurality of conductive materials further includes some conductive structures not shown in FIG. 2, such as data lines and scan lines, etc., and the interlayer insulating layer may also include other spacers as shown in FIG. The insulating layer structure of the conductive functional layer.
  • the active layer 31, the gate electrode 33, the source electrode 35, and the drain electrode 36 constitute a functional component of the thin film transistor.
  • the thin film transistor provided in the present embodiment employs a thin film transistor of a top gate structure. In still other embodiments, a thin film transistor using a bottom gate structure may also be used.
  • the material of the interlayer insulating layer in the pixel structure layer 30 is selected to be SiO x .
  • the preparation method includes the steps of:
  • a process for preparing a patterned three-dimensional microstructure includes:
  • an electrochemical reaction platform is constructed in which an electrolyte such as oxalic acid or sulfuric acid is used, and an aluminum and a carbon electrode are used as an anode and a cathode, respectively.
  • the surface of the aluminum electrode is formed into a porous structure by applying a direct current voltage, and the aluminum electrode is placed in a phosphoric acid solution. Due to the large specific surface area at the porous structure, the diameter of the porous structure is increased by the oxidation of phosphoric acid, and the depth is increased. . Repeating the above electrochemical and phosphoric acid oxidation process allows the diameter and depth of the porous aluminum to meet the requirements of the desired nanoimprint template to form a porous alumina stencil.
  • the embossing process may be a roll-to-roll nanoimprint process.
  • the surface of the glass substrate is etched under the protection of the photoresist mask to prepare a first surface including a plurality of patterned three-dimensional microstructures.
  • the etching process is a wet etching process.
  • the buffer layer may be obtained by a plasma enhanced chemical vapor deposition process (PECVD).
  • PECVD plasma enhanced chemical vapor deposition process
  • the pixel junction includes a plurality of electrically conductive functional layers and an interlayer insulating layer between any two electrically conductive functional layers.
  • the specific structure of each structural film layer in the pixel structure layer and the preparation process thereof can be carried out with reference to the prior art.
  • the embodiment further provides a display device in which the thin film transistor array substrate provided by the embodiment of the present invention is used.
  • the display device can be, for example, a liquid crystal display device (LCD) or an organic electroluminescence display device (OLED).
  • the thin film transistor array substrate provided by the embodiment of the invention can make the display device have better light transmittance and enhance the display device.
  • the liquid crystal display device is taken as an example. Referring to FIG. 7 , the liquid crystal display device includes a liquid crystal panel 100 and a backlight module 200 .
  • the liquid crystal panel 100 is disposed opposite to the backlight module 200 , and the backlight module 200 is provided.
  • a light source is displayed to the liquid crystal panel 100 to cause the liquid crystal panel 100 to display an image.
  • the liquid crystal panel 100 includes an array substrate 101 and a filter substrate 102 disposed opposite to each other, and further includes a liquid crystal layer 103 between the array substrate 101 and the filter substrate 102.
  • the array substrate 101 adopts the thin film transistor array substrate provided by the embodiment of the invention.
  • the thin film transistor array substrate provided in the embodiment of the present invention improves the connection interface between the substrate substrate and the buffer layer in the array substrate, specifically, the patterning between the connection interfaces of the two is provided.
  • a three-dimensional microstructure that is, a moth-eye cone structure is formed, thereby forming a connection gradient interface between the base substrate and the buffer layer, reducing the reflection of the light at the connection interface, and effectively improving the array substrate Light transmission rate.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本发明涉及显示器技术领域，具体是公开了一种薄膜晶体管阵列基板，其包括玻璃基板以及设置在所述玻璃基板的第一表面上的缓冲层和像素结构层，其中，所述玻璃基板的第一表面上形成有图案化的多个立体微结构，所述缓冲层与所述第一表面相互齿合。本发明还公开了如上所述阵列基板的制备方法以及包含该阵列基板的显示装置。本发明提供的薄膜晶体管阵列基板，提高了阵列基板的光线透过率。

Description

薄膜晶体管阵列基板及其制备方法、显示装置 技术领域
本发明涉及显示器技术领域，尤其涉及一种薄膜晶体管阵列基板及其制备方法，还涉及包含该薄膜晶体管阵列基板的显示装置。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。薄膜晶体管(Thin Film Transistor，TFT)阵列基板是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，作为开光装置和驱动装置用在诸如LCD、OLED。
图1是现有的一种典型的薄膜晶体管阵列基板的结构示意图。如图1所示，所述薄膜晶体管阵列基板衬底基板1、缓冲层2、有源层3、栅极绝缘层4、栅极层5、层间介质层6、源漏极层7、平坦层8和像素电极层9，其中，薄膜晶体管的结构主要是由有源层3、栅极绝缘层4、栅极层5、层间介质层6和源漏极层7构成。为了衬底基板中含有的离子或者制程中带来的水氧等对薄膜晶体管的性能产生影响，如图1所示，通过是先在衬底基板1上设置缓冲层2，然后再在缓冲层2制备形成薄膜晶体管的个膜层结构，并且缓冲层2的材料采用高致密度的SiNx，这将会造成阵列基板的穿透率损失的问题。
随着显示器的分辨率进一步提高，传统的通过改善开口率、色阻穿透率、背光亮度、液晶效率等方式改善显示面板的穿透率或者亮度表现已经逐渐面临瓶颈，如何在兼顾薄膜晶体管的电学性能不衰减的前提下改善阵列基板的穿透率成为关键的技术难题。
发明内容
有鉴于此，本发明提供了一种薄膜晶体管阵列基板及其制备方法，通过对阵列基板中的衬底基板和缓冲层的连接界面进行改进，有效地提高了阵列基板的光线透过率。
为了实现上述目的，本发明采用了如下的技术方案：
一种薄膜晶体管阵列基板，包括玻璃基板以及设置在所述玻璃基板的第一表面上的缓冲层和像素结构层，其中，所述玻璃基板的第一表面上形成有图案化的多个立体微结构，所述缓冲层与所述第一表面相互齿合。
其中，在沿所述立体微结构的高度方向上，所述立体微结构的横截面的面积逐渐减小。
其中，所述立体微结构为圆锥结构或圆台结构。
其中，所述立体微结构的高度为H，所述立体微结构底部的直径为R1，所述立体微结构顶部的直径为R2；其中，100nm≤R1≤500nm，100nm≤R1≤400nm，0≤R2＜400nm，并且R2＜R1。
其中，所述立体微结构的占空比为k，0.3≤k≤1；其中，所述占空比定义为：k＝R1/L，L是指相邻的两个立体微结构的底部中心点的间距。
其中，所述缓冲层的材料为SiNx。
其中，所述像素结构层包括多个导电功能层和位于任意两个导电功能层之间的层间绝缘层，所述层间绝缘层的材料为SiOx。
其中，所述多个立体微结构在所述第一表面上呈规则的阵列排布。
本发明还提供了如上所述的薄膜晶体管阵列基板的制备方法，其包括步骤：
S1、提供玻璃基板，在所述玻璃基板上制备形成包含有图案化的多个立体微结构的第一表面；具体包括：S11、应用阳极氧化工艺制备具有凹凸结构的多孔氧化铝模版；S12、在所述玻璃基板上涂覆光刻胶层，应用压印工艺将所述多孔氧化铝模版的图案转移到所述光刻胶层，形成光刻胶掩膜版；S13、在所述光刻胶掩膜版的保护下对所述玻璃基板的表面进行刻蚀处理，制备形成包含有图案化的多个立体微结构的第一表面；
S2、在所述第一表面上制备形成缓冲层，所述缓冲层填充所述立体微结构的间隙并覆盖在所述立体微结构上，所述缓冲层与所述第一表面相互齿合；
S3、在所述缓冲层上制备形成像素结构层。
本发明的另一方面是提供一种显示装置，其包括如上所述的薄膜晶体管阵列基板。
本发明实施例中提供的薄膜晶体管阵列基板，通过对阵列基板中的衬底基板和缓冲层的连接界面进行改进，具体是在两者的连接界面之间设置图案化的多个立体微结构，即形成蛾眼膜锥状结构，由此使得衬底基板和缓冲层的连接界面形成折射率渐变的结构，减少了所述连接界面对光线的反射，有效地提高了阵列基板的光线透过率。
附图说明
图1是现有的一种薄膜晶体管阵列基板的结构示意图；
图2是本发明实施例提供的薄膜晶体管阵列基板的结构示意图；
图3是本发明实施例中的立体微结构的结构示意图；
图4是如图3中沿X-Y线的剖面图；
图5是本发明实施例提供的薄膜晶体管阵列基板的制备方法的工艺流程图；
图6是本发明实施例中制备形成图案化的多个立体微结构的工艺流程图；
图7是本发明实施例提供的显示装置的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
本实施例首先提供了一种薄膜晶体管阵列基板，如图1所示，所述薄膜晶体管阵列基板包括玻璃基板10以及设置在所述玻璃基板10的第一表面10a上的缓冲层20和像素结构层30。
在本实施例中，所述缓冲层20的材料选择为SiNx。采用高致密度的SiNx作为缓冲层20的材料，可以阻挡所述玻璃基板10中含有的离子或者制备工艺制程中带来的水氧等对薄膜晶体管的性能产生不良影响。进一步地，在另外的 一些实施例中，还可以在所述SiNx材料层上再增加设置一层SiOx材料层，由所述SiNx材料层和SiOx材料层共同组成缓冲层。
在本实施例中，参阅图2和图3，所述玻璃基板10的第一表面10a上形成有图案化的多个立体微结构11，所述缓冲层20与所述第一表面10a相互齿合，也就是说，所述缓冲层20填充所述立体微结构11的间隙并覆盖在所述立体微结构11上，所述缓冲层20与所述第一表面10a之间是紧密结合的连接。具体地，在沿所述立体微结构11的高度方向上，所述立体微结构11的横截面的面积逐渐减小，而相应填充在相邻两个立体微结构11之间的SiNx材料的横截面则是逐渐增大。如上的结构中，通过在玻璃基板10和缓冲层20的连接界面之间设置图案化的多个立体微结构11，即形成蛾眼膜锥状结构，由此使得玻璃基板10和缓冲层20的连接界面形成折射率渐变的结构，减少了所述连接界面对光线的反射，有效地提高了阵列基板的光线透过率。
具体到本实施例中，参阅图3和图4，所述立体微结构11为圆台结构。所述立体微结构11的高度为H，所述立体微结构11底部的直径为R1，所述立体微结构11顶部的直径为R2。其中，100nm≤R1≤500nm，100nm≤R1≤400nm，0≤R2＜400nm，并且R2＜R1。需要说明的是，所述立体微结构11顶部的直径R2优选设置为0，此时，所述所述立体微结构11为圆锥结构。需要说明的是，图3和图4中仅示例性地示出了若干个立体微结构11。
进一步地，所述立体微结构11的占空比为k，0.3≤k≤1。其中，所述占空比定义为：k＝R1/L，L是指相邻的两个立体微结构11的底部中心点的间距。
在优选的实施例方案中，所述多个立体微结构11在所述第一表面10a上呈规则的阵列排布。
其中，所述像素结构层30包括多个导电功能层和位于任意两个导电功能层之间的层间绝缘层。具体地，如图1所示，所述像素结构层30包括形成在所述缓冲层20上的有源层31、覆设于所述有源层31上的栅极绝缘层32、形成于所述栅极绝缘层32上的栅电极33、覆设于所述栅电极33上的层间介质层34、形成于所述层间介质层34上的源电极35和漏电极36、覆设于所述源电极35和漏电极36上的平坦层37以及形成于所述平坦层37上的像素电极38。其中，所述多个导电功能层包括如上所述的有源层31、栅电极33、源电极35和漏电极36、以及像素电极38等；所述层间绝缘层包括如上所述的栅极绝缘层32、层间介质层34以及平坦层37等。进一步地，在薄膜晶体管阵列基板中，所述多个导电 功能层还包括如图2中未示出的一些导电的结构，例如数据线和扫描线等，而所述层间绝缘层也还可以包括如图2中未示出的其他用于间隔两个导电功能层的绝缘层结构。
另外，如上所述的像素结构层30中，所述有源层31、栅电极33、源电极35和漏电极36组成了薄膜晶体管的功能部件。并且，如图2所示，在本实施例中提供的薄膜晶体管采用了顶栅结构的薄膜晶体管。在另外的一些实施例中，也可以是采用底栅结构的薄膜晶体管。
进一步地，为了使得所述薄膜晶体管阵列基板获得更高的光线透过率，所述像素结构层30中的层间绝缘层的材料选择为SiOx。
下面介绍如上所述的薄膜晶体管阵列基板的制备方法，如图5所示，所述制备方法包括步骤：
S1、提供玻璃基板，在所述玻璃基板上制备形成包含有图案化的多个立体微结构的第一表面。参阅图6，制备形成图案化的立体微结构的工艺包括：
S11、应用阳极氧化工艺制备具有凹凸结构的多孔氧化铝模版。具体地，搭建电化学反应平台，其中电解液采用草酸或者硫酸等，采用铝与碳电极分别用作阳极和阴极。通过施加直流电压，使所述铝电极表面形成多孔结构，将所述铝电极放入磷酸溶液中，由于多孔结构处的比表面积较大，通过磷酸的氧化作用使得多孔结构直径变大，深度增加。重复上述电化学与磷酸氧化流程可以使得多孔铝的直径与深度达到所需纳米压印模板的要求，形成多孔氧化铝模版。
S12、在所述玻璃基板上涂覆光刻胶层，应用压印工艺将所述多孔氧化铝模版的图案转移到所述光刻胶层，形成光刻胶掩膜版。其中的压印工艺可以是采用卷对卷的纳米压印工艺。
S13、在所述光刻胶掩膜版的保护下对所述玻璃基板的表面进行刻蚀处理，制备形成包含有图案化的多个立体微结构的第一表面。其中的刻蚀工艺是采用湿法刻蚀工艺。
S2、在所述第一表面上制备形成缓冲层，所述缓冲层填充所述立体微结构的间隙并覆盖在所述立体微结构上，所述缓冲层与所述第一表面相互齿合。所述缓冲层可以是通过等离子体增强化学气相沉积工艺(PECVD)制备获得。
S3、在所述缓冲层上制备形成像素结构层。其中，如前所述，所述像素结 构层包括多个导电功能层和位于任意两个导电功能层之间的层间绝缘层。所述像素结构层中的各个结构膜层的具体结构及其制备工艺可以参照现有技术进行。
本实施例还提供了一种显示装置，其中采用了本发明实施例提供的薄膜晶体管阵列基板。该显示装置例如可以是液晶显示装置(LCD)或有机电致发光显示装置(OLED)，采用了本发明实施例提供的薄膜晶体管阵列基板，可以使得显示装置具有更加优良的光线透过率，提升显示装置的显示品质。具体地，以液晶显示装置为例，参阅图7，该液晶显示装置包括液晶面板100及背光模组200，所述液晶面板100与所述背光模组200相对设置，所述背光模组200提供显示光源给所述液晶面板100，以使所述液晶面板100显示影像。其中，液晶面板100包括相对设置的阵列基板101和滤光基板102，还包括位于阵列基板101和滤光基板102之间的液晶层103。其中，阵列基板101即采用了本发明实施例提供的薄膜晶体管阵列基板。
综上所述，本发明实施例中提供的薄膜晶体管阵列基板，通过对阵列基板中的衬底基板和缓冲层的连接界面进行改进，具体是在两者的连接界面之间设置图案化的多个立体微结构，即形成蛾眼膜锥状结构，由此使得衬底基板和缓冲层的连接界面形成折射率渐变的结构，减少了所述连接界面对光线的反射，有效地提高了阵列基板的光线透过率。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个......”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1. 一种薄膜晶体管阵列基板，包括玻璃基板以及设置在所述玻璃基板的第一表面上的缓冲层和像素结构层，其中，所述玻璃基板的第一表面上形成有图案化的多个立体微结构，所述缓冲层与所述第一表面相互齿合。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中，在沿所述立体微结构的高度方向上，所述立体微结构的横截面的面积逐渐减小。
  3. 根据权利要求2所述的薄膜晶体管阵列基板，其中，所述立体微结构为圆锥结构或圆台结构。
  4. 根据权利要求3所述的薄膜晶体管阵列基板，其中，所述立体微结构的高度为H，所述立体微结构底部的直径为R1，所述立体微结构顶部的直径为R2；其中，100nm≤R1≤500nm，100nm≤R1≤400nm，0≤R2＜400nm，并且R2＜R1。
  5. 根据权利要求4所述的薄膜晶体管阵列基板，其中，所述立体微结构的占空比为k，0.3≤k≤1；其中，所述占空比定义为：k＝R1/L，L是指相邻的两个立体微结构的底部中心点的间距。
  6. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述缓冲层的材料为SiNx；所述像素结构层包括多个导电功能层和位于任意两个导电功能层之间的层间绝缘层，所述层间绝缘层的材料为SiOx。
  7. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述多个立体微结构在所述第一表面上呈规则的阵列排布。
  8. 一种薄膜晶体管阵列基板的制备方法，其特征在于，包括步骤：
    S1、提供玻璃基板，在所述玻璃基板上制备形成包含有图案化的多个立体微结构的第一表面；具体包括：
    S11、应用阳极氧化工艺制备具有凹凸结构的多孔氧化铝模版；
    S12、在所述玻璃基板上涂覆光刻胶层，应用压印工艺将所述多孔氧化铝模版的图案转移到所述光刻胶层，形成光刻胶掩膜版；
    S13、在所述光刻胶掩膜版的保护下对所述玻璃基板的表面进行刻蚀处理，制备形成包含有图案化的多个立体微结构的第一表面；
    S2、在所述第一表面上制备形成缓冲层，所述缓冲层填充所述立体微结构的间隙并覆盖在所述立体微结构上，所述缓冲层与所述第一表面相互齿合；
    S3、在所述缓冲层上制备形成像素结构层。
  9. 根据权利要求8所述的薄膜晶体管阵列基板的制备方法，其中，在沿所述立体微结构的高度方向上，所述立体微结构的横截面的面积逐渐减小。
  10. 根据权利要求9所述的薄膜晶体管阵列基板的制备方法，其中，所述立体微结构为圆锥结构或圆台结构。
  11. 根据权利要求10所述的薄膜晶体管阵列基板的制备方法，其中，所述立体微结构的高度为H，所述立体微结构底部的直径为R1，所述立体微结构顶部的直径为R2；其中，100nm≤R1≤500nm，100nm≤R1≤400nm，0≤R2＜400nm，并且R2＜R1。
  12. 根据权利要求11所述的薄膜晶体管阵列基板的制备方法，其中，所述立体微结构的占空比为k，0.3≤k≤1；其中，所述占空比定义为：k＝R1/L，L是指相邻的两个立体微结构的底部中心点的间距。
  13. 根据权利要求8所述的薄膜晶体管阵列基板的制备方法，其中，所述缓冲层的材料为SiNx；所述像素结构层包括多个导电功能层和位于任意两个导电功能层之间的层间绝缘层，所述层间绝缘层的材料为SiOx。
  14. 一种显示装置，包括薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括玻璃基板以及设置在所述玻璃基板的第一表面上的缓冲层和像素结构层，其中，所述玻璃基板的第一表面上形成有图案化的多个立体微结构，所述缓冲层与所述第一表面相互齿合。
  15. 根据权利要求14所述的显示装置，其中，在沿所述立体微结构的高度方向上，所述立体微结构的横截面的面积逐渐减小。
  16. 根据权利要求15所述的显示装置，其中，所述立体微结构为圆锥结构或圆台结构。
  17. 根据权利要求16所述的显示装置，其中，所述立体微结构的高度为H，所述立体微结构底部的直径为R1，所述立体微结构顶部的直径为R2；其中，100nm≤R1≤500nm，100nm≤R1≤400nm，0≤R2＜400nm，并且R2＜R1。
  18. 根据权利要求17所述的显示装置，其中，所述立体微结构的占空比为k，0.3≤k≤1；其中，所述占空比定义为：k＝R1/L，L是指相邻的两个立体微结构的底部中心点的间距。
  19. 根据权利要求14所述的显示装置，其中，所述缓冲层的材料为SiNx；所述像素结构层包括多个导电功能层和位于任意两个导电功能层之间的层间绝缘层，所述层间绝缘层的材料为SiOx。
  20. 根据权利要求14所述的显示装置，其中，所述多个立体微结构在所述第一表面上呈规则的阵列排布。
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