WO2019071814A1 - 阵列基板及其应用的显示面板 - Google Patents

阵列基板及其应用的显示面板 Download PDF

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Publication number
WO2019071814A1
WO2019071814A1 PCT/CN2017/117079 CN2017117079W WO2019071814A1 WO 2019071814 A1 WO2019071814 A1 WO 2019071814A1 CN 2017117079 W CN2017117079 W CN 2017117079W WO 2019071814 A1 WO2019071814 A1 WO 2019071814A1
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WIPO (PCT)
Prior art keywords
line
interfaces
array substrate
output
input
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PCT/CN2017/117079
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English (en)
French (fr)
Inventor
李泽尧
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/745,550 priority Critical patent/US10680048B2/en
Publication of WO2019071814A1 publication Critical patent/WO2019071814A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the field of wiring technologies, and in particular, to an array substrate and a display panel thereof.
  • TFT-LCD active switch-liquid crystal display
  • the display driving method includes: the system motherboard transmits a color (for example: R/G/B) compression signal, a control signal, and a power source to the control board.
  • the signal is processed by the Timing Controller (TCON) on the control board, and then transmitted to the source circuit and the gate circuit of the printed circuit board, through the gate line, data line, power supply and other lines on the substrate, which will be necessary.
  • TCON Timing Controller
  • the data and power are transmitted to the display area, so that the display obtains power and signals for presenting the picture.
  • the internal firmware read and write mode can adjust the signal output mode of the chip/integrated circuit through specific software, and the component needs to be tested after adjustment. In order to ensure that the function is correct, this will result in an extension of the design time of the display panel line, and also relatively increase the design cost.
  • an object of the present application is to provide an array substrate and a display panel thereof, and adjust the signal receiving timing of the display area line by the cross-line design.
  • An array substrate includes: a substrate including a display area and a peripheral wiring area thereof, wherein a plurality of active switches, a plurality of pixel units, and a plurality of signal lines are disposed in the display area,
  • the plurality of pixel units are respectively coupled to the plurality of active switches, the plurality of active switches are electrically coupled to the plurality of signal lines, and the plurality of input interfaces of the plurality of signal lines are disposed on the wiring
  • a driving module configured in the routing area
  • the driving module includes a plurality of output interfaces, and a plurality of connecting lines disposed between the plurality of input interfaces and the plurality of output interfaces to enable the plurality of
  • the input interface is electrically coupled to the plurality of output interfaces, wherein at least one of the plurality of connection lines is configured as an over-the-line, and the line configuration order of the plurality of input interfaces and the plurality of output
  • a line configuration order of the plurality of input interfaces and the plurality of output interfaces is different.
  • the plurality of connection lines include a multi-line combination, and at least one of the multi-line combinations is a cross-line configuration.
  • the multi-line combination includes at least one of a two-line combination, a three-line combination, and a four-line combination.
  • the driving module outputs a control signal through the plurality of output interfaces in a first order, and the control signal receiving order of the plurality of input interfaces is input in a second order, wherein And the plurality of connection lines acquire the control signal from the plurality of output interfaces in the first sequence, and output the control signal to the plurality of input interfaces in the second sequence.
  • the driving module includes a flip chip that is pressed over an edge of the substrate, and the flip chip includes the plurality of output interfaces.
  • the flip chip is at least one of a gate flip chip and a source flip chip.
  • the plurality of connection lines are disposed in a fan-out area of the wiring area.
  • the second object of the present application is an array substrate, comprising: a substrate, a wiring area including a display area and a periphery thereof, a plurality of active switches, a plurality of pixel units, and a plurality of signal lines disposed in the display area,
  • the plurality of pixel units are respectively coupled to the plurality of active switches, and the plurality of active switches are electrically coupled to the plurality of signals, and the plurality of input interfaces of the plurality of signal lines are disposed in the wiring area.
  • the plurality of input interfaces include a first input interface and a second input interface; the drive module includes a first output interface and a second output interface; and a combination of two lines is disposed between the drive module and the substrate, the two lines
  • the combination includes a first line connected between the first output interface and the second input interface, and a second line connected between the second output interface and the first input interface,
  • the second line is configured for a fold line, a straight line, a curve, or a diagonal line, and the first line is configured in an over-line manner.
  • a further object of the present application is a display panel comprising an array substrate and an opposite substrate disposed opposite to each other; wherein the array substrate comprises: a substrate, a wiring area including a display area and a periphery thereof, a plurality of active switches, and a plurality of The plurality of pixel units are respectively coupled to the display area, and the plurality of pixel units are respectively coupled to the plurality of active switches, and the plurality of active switches are electrically coupled to the plurality of signal lines, respectively.
  • a plurality of input interfaces of the plurality of signal lines are disposed in the wiring area; a driving module is disposed in the wiring area, the driving module includes a plurality of output interfaces; and a plurality of connecting lines are disposed on the plurality of inputs Between the interface and the plurality of output interfaces, the plurality of input interfaces are electrically coupled to the plurality of output interfaces, wherein at least one of the plurality of connection lines is configured across the line, The line configuration order of the plurality of input interfaces and the plurality of output interfaces is different.
  • the application can not significantly change the premise of the existing production process, and can maintain the original process requirements and product costs, and can change the control signal receiving timing of the display area through the wiring design, without changing the driving module (such as the driving IC, the driving control circuit)
  • the control signal output timing can reduce the adjustment cost of the drive module.
  • FIG. 1a is a schematic diagram of the architecture of an exemplary display device.
  • FIG. 1b is a schematic diagram of an exemplary pixel unit configuration.
  • Figure 1c is a schematic illustration of the wiring of the fan-out region of an exemplary display device.
  • 2a is a schematic diagram showing the wiring of an array substrate according to an embodiment of the method of the present application.
  • 2b is a schematic diagram showing the wiring of an array substrate according to an embodiment of the method of the present application.
  • 2c is a schematic diagram showing the wiring of an array substrate according to an embodiment of the method of the present application.
  • FIG. 3 is a schematic diagram showing the wiring of an array substrate according to an embodiment of the method of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • FIG. 1a is a schematic diagram of the architecture of an exemplary display device.
  • a liquid crystal display includes: a control board 100, the control board 101 includes a Timing Controller (TCON) 101, and a printed circuit board 103, and a flexible flat cable is passed between the control board ( The flexible flat cable (FFC) 102 is connected to each other; the source flip chip 104 and the gate flip chip 105 are respectively connected to the source line 104a and the gate line 105a in the display region 106.
  • TCON Timing Controller
  • FFC Flexible flat cable
  • the driving manner of the display device includes: the system motherboard provides color (eg, R/G/B) compression signals, control signals, and power transmission to the control board 100.
  • the timing controller 101 on the control board 100 processes the signals, and together with the power source processed by the driving circuit, is transmitted to the source circuit of the printed circuit board 103 through a flexible flat cable (FFC) 102, for example.
  • the gate circuit transmits the necessary data and power to the display area 106 through the source flip chip 104 and the gate flip chip 105, thereby enabling the display to obtain power and signals for presenting the picture.
  • FIG. 1b is a schematic diagram of an exemplary pixel unit configuration. Please cooperate with Figure 1a to facilitate understanding.
  • the gate driving unit 105 supplies a scan signal to the gate line 105a row by row, and provides a scan signal to one row of gate lines 105a for each scan period.
  • the source line 104a of the display panel is turned on row by row, and the source driving unit 104 supplies data to the pixel unit P through the source line 104a.
  • FIG. 1c is a schematic diagram of the wiring of the fan-out area of an exemplary display device. Please refer to FIG. 1a and FIG. 1b for understanding.
  • the flip chip is provided with a corresponding integrated circuit (IC).
  • the channels of the integrated circuit are substantially connected to the conductive lines of the display region 106 according to their order.
  • the connected conductive lines are also different.
  • the gate integrated circuit is connected to a scan line (gate line), such as a source integrated circuit that is connected to a data line (source line).
  • the channel arrangement order of the gate integrated circuit 107 is g1 to gn, and the signal output timing of the gate integrated circuit is also adjusted as the channel signal output timing.
  • the array substrate includes: a substrate 200, a display area 106 and a peripheral wiring area 108 thereof, a plurality of active switches T, a plurality of pixel units P and more
  • the plurality of signal units 210 are respectively coupled to the display area 106, and the plurality of pixel units P are respectively coupled to the plurality of active switches T, and the plurality of active switches T are electrically coupled to the plurality of signal lines 210, respectively.
  • the plurality of input interfaces 211 of the plurality of signal lines 210 are disposed in the wiring area 108; the driving module 220 is disposed in the wiring area 108, the driving module 220 includes a plurality of output interfaces 222; and a plurality of connecting lines
  • the plurality of input interfaces 211 are electrically coupled to the plurality of output interfaces 222 respectively, wherein the plurality of input interfaces 211 are electrically coupled to the plurality of output interfaces 222;
  • At least one of the connection lines 230 is configured as an overhead line, and the plurality of output interfaces 222 and the plurality of input interfaces 211 have a different line configuration order.
  • the plurality of connection lines comprise a multi-line combination, and at least one of the multi-line combinations is a cross-line configuration.
  • the driving module 210 outputs control signals through the plurality of output interfaces 222 in a first order, and the control signal receiving order of the plurality of input interfaces 211 is input in a second order, wherein The plurality of connection lines 230 obtain the control signals from the plurality of output interfaces 222 in the first order, and output the control signals to the plurality of input interfaces 211 in the second order.
  • the multi-line combination includes a two-line combination 232.
  • the two line combination includes a first line 232a and a second line 232b.
  • the second line 232b is configured in a fold line manner, and the first line 232a is configured in an over-line manner.
  • the first line is connected between the output interface g1 and the input interface G2, and the second line is connected between the output interface g2 and the input interface G1. It is assumed that the timing of the control signal passing through the output interface is (g1->g2), and the timing at which the control signal reaches the input interface is (G2->G1).
  • the multi-line combination includes a three-line combination 233.
  • the three-line combination 233 includes a first line 233a, a second line 233b, and a third line 233c.
  • the second line 233b and the third line 233c are arranged in a fold line manner, and the first line 233a is arranged in an overlapping manner.
  • the first line 233a is connected between the output interface g1 and the input interface G3, the second line is connected between the output interface g2 and the input interface G1, and the third line is connected to the output interface g3 and the input interface G2. between. It is assumed that the timing of the control signal passing through the output interface is (g1->g2->g3), and the timing at which the control signal reaches the input interface is (G3->G1->G2).
  • the multi-line combination includes a four-line combination.
  • the four-line combination includes a first line 234a, a second line 234b, a third line 234c, and a fourth line 234d.
  • the second line 234b, the third line 234c, and the fourth line 234d are arranged in a fold line manner, and the first line 234a is arranged in an overlapping manner.
  • the first line 234a is connected between the output interface g1 and the input interface G4, the second line 234b is connected between the output interface g2 and the input interface G1, and the third line 234c is connected to the output interface g3 and the input interface. Between G2, the fourth line 234d is connected between the output interface g4 and the input interface G3. Assuming that the timing of the control signal passing through the output interface is (g1->g2->g3->g4), the timing of the control signal reaching the input interface is (G4->G1->G2->G3) .
  • the multiple connection lines include a fold line, a straight line, a curved line, a diagonal line, and the like, but are not limited thereto, and the configuration manner depends on the needs of the designer.
  • the plurality of output interfaces of the integrated circuit are ordered (g1-g12), and the timing of the control signal output is (g2->g1->g3-> G4->g7->g8->g5->g6->g12->g9->g10->g11), which is different from the ordering of the plurality of output interfaces.
  • the timing requirement for the plurality of input interfaces to receive the control signal is (G1->G12).
  • the plurality of connection lines include the two line combination 232, the three line combination 233, the four line combination 234, and the docking line 231, wherein the two line combination 232 includes the first Line 232a and second line 232b.
  • the first line 232a is configured in a fold line manner, and the second line 232b is disposed in an over-line manner.
  • the first line 232a is connected between the output interface g1 and the input interface G2, and the second line 232b is connected between the output interface g2 and the input interface G1.
  • the three-line combination 233 includes a first line 233a, a second line 233b, and a third line 233c.
  • the first line 233a and the second line 233b are arranged in a fold line manner, and the third line 233c is arranged in an over-line manner.
  • the first line 233a is connected between the output interface g5 and the input interface G6, the second line 233b is connected between the output interface g6 and the input interface G7, and the third line 233c is connected to the output interface g7 and the input interface. Between G5.
  • the four lines 234 combination includes a first line 234a, a second line 234b, a third line 234c, and a fourth line 234d.
  • the first line 234a, the second line 234b, and the third line 234c are arranged in a fold line manner, and the fourth line 234d is arranged in an over-line manner.
  • the first line 234a is connected between the output interface g9 and the input interface G10
  • the second line 234b is connected between the output interface g10 and the input interface G11
  • the third line 234c is connected to the output interface g11 and the input interface.
  • the third line 234d is connected between the output interface g12 and the input interface G9.
  • the docking lines 231 are respectively disposed between the output interface g3 and the input interface G3, between the output interface g4 and the input interface G4, and between the output interface g8 and the input interface G8.
  • the timing of the control signal output of the integrated circuit is (g2->g1->g3->g4->g7->g5->g6->g8->g12->g9->g10->g11
  • the timing at which the plurality of input interfaces receive the control signal may meet the requirements of (G1->G12).
  • the driving module 220 includes a flip chip that is overlaid on an edge of the substrate 200, and the flip chip includes the plurality of output interfaces 221.
  • the flip chip is a gate flip chip 105.
  • the flip chip is a source flip chip 104.
  • the plurality of connection lines 230 are disposed in a fan-out area of the wiring area 108.
  • an array substrate of the present application includes: a substrate 200, a wiring area 108 including a display area 106 and its periphery, a plurality of active switches T, a plurality of pixel units P, and a plurality of signal lines
  • the plurality of pixel units P are respectively coupled to the plurality of active switches T, and the plurality of active switches T are electrically coupled to the plurality of signal lines 210, respectively.
  • a plurality of input interfaces 211 of the plurality of signal lines 210 are disposed in the wiring area 108, the plurality of input interfaces 106 include a first input interface g1 and a second input interface g2; and the driving module 220 includes a first output interface G1 and The second output interface G2 is disposed between the driving module 150 and the substrate 200.
  • the two line combination 232 includes a first line 232a and a second line 232b, and the first line 232a is connected to the first line 232a.
  • the second line 232b is connected between the second output interface g2 and the first input interface G1, and the second line 232b is a fold line, a straight line, a curve or an oblique line.
  • the first line 232a is Configured in an inter-line manner.
  • a display panel of the present application includes: an array substrate and an opposite substrate disposed opposite to each other; wherein the array substrate includes: a substrate 200 including a display area 106 and a peripheral wiring area thereof 108.
  • the plurality of active switches T, the plurality of pixel units P, and the plurality of signal lines 210 are disposed in the display area 106, and the plurality of pixel units P are respectively coupled to the plurality of active switches T, the plurality of The active switch T is electrically coupled to the plurality of signal lines 210, and the plurality of input interfaces 211 of the plurality of signal lines 210 are disposed in the wiring area 108.
  • the driving module 220 is disposed in the wiring area 108.
  • the driving module 220 includes a plurality of output interfaces 222.
  • the plurality of connection lines 230 are disposed between the plurality of input interfaces 211 and the plurality of output interfaces 222, so that the plurality of input interfaces 211 are respectively
  • the output interfaces 222 are electrically coupled to each other; wherein at least one of the plurality of connection lines 230 is an over-the-line configuration, and the plurality of output interfaces 222 and the plurality of input interfaces 211 have a different line configuration order.
  • the array substrate further comprises any of the previously described embodiments.
  • the display panel of the present application may be, for example, a liquid crystal display panel, but is not limited thereto, and may also be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, and a curved surface. Display panel or other type of display panel.
  • the application can not significantly change the premise of the existing production process, and can maintain the original process requirements and product costs, and can change the control signal receiving timing of the display area through the wiring design, without changing the driving module (such as the driving IC, the driving control circuit)
  • the control signal output timing can reduce the adjustment cost of the drive module.

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Abstract

本申请一种阵列基板及其应用的显示面板。此阵列基板包括：基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线配置于此显示区，此多个像素单元分别耦接于此多个主动开关，此主动开关分别电性耦接此多条信号线，此多条信号线的多个输入接口配置于此布线区；驱动模块，配置于此布线区，此驱动模块包括多个输出接口；多个连接线路，设置于此多个输入接口与此多个输出接口之间，使此多个输入接口分别与此多个输出接口电性耦接；其中，此多个连接线路中至少一条线路为跨线配置，此多个输入接口与此多个输出接口的线路配置顺序为相异。

Description

阵列基板及其应用的显示面板 技术领域
本申请涉及一种布线技术领域，特别涉及一种阵列基板及其应用的显示面板。
背景技术
TFT-LCD(主动开关-液晶显示器)面板正常显示时，需要栅级驱动线路(Gate Driver)、源极驱动线路(Source Driver)，结合基板上纵横交错的栅极线(Gate line)、数据线(Data line)以控制各个像素，实现图像的显示。
显示器驱动方式包括：系统主板将颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板。信号经过控制板上的时序控制器(Timing Controller，TCON)处理后，传输至印刷电路板的源极电路及栅极电路，通过基板上的栅极线、数据线、电源等线路，将必要性的数据与电源传输于显示区，从而使得显示器获得呈现画面需求的电源、信号。
然而，显示面板上所使用的集成电路(IC)，控制芯片(Chip)…等传输信号的重要组件，一般不是显示器厂商一体制作。因此，设计人员需要取得芯片/集成电路的信号输出的时序及真值表等相关信息，内部韧体读写方式，才能通过特定软件调整芯片/集成电路的信号输出模式，元件调节后也需要测试以确保功能是正确，如此会造成显示面板线路于设计时间的延长，也相对提高了设计成本。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种阵列基板及其应用的显示面板，通过跨线设计，调整显示区线路的信号接收时序。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种阵列基板，所述阵列基板包括：基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线配置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线的多个输入接口配置于所述布线区；驱动模块，配置于所述布线区，所述驱动模块包括多个输出接口；多个连接线路，设置于所述多个输入接口与所述多个输出接口之间，使所述多个输入接口分别与所述多个输出接口电性耦接；其中，所述多个连接线路中至少一条线路为跨线配置，所述多个输入接口与所述多个输出接口的线路配置顺序为相异。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，所述多个输入接口与所述多个输出接口的线路配置顺序为相异。
在本申请的一实施例中，所述多个连接线路包括多线路组合，所述多线路组合中的至少一条线路为跨线配置。
在本申请的一实施例中，所述多线路组合包括二线路组合、三线路组合与四线路组合中至少其一者。
在本申请的一实施例中，所述驱动模块将控制信号通过所述多个输出接口以第一顺序输出，所述多个输入接口的所述控制信号接收顺序是以第二顺序输入，其中，所述多个连接线路自所述多个输出接口以所述第一顺序取得所述控制信号，以所述第二顺序输出所述控制信号至所述多个输入接口。
在本申请的一实施例中，所述驱动模块包括覆晶薄膜，压覆在所述基板的边缘，所述覆晶薄膜包括所述多个输出接口。
在本申请的一实施例中，所述覆晶薄膜为栅极覆晶薄膜与源极覆晶薄膜中至少其一者。
在本申请的一实施例中，所述多个连接线路配置于所述布线区的扇出区。
本申请的次一目的为一种阵列基板，其包括：基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线配置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号，所述多条信号线的多个输入接口配置于所述布线区，所述多个输入接口包括第一输入接口与第二输入接口；驱动模块，包括第一输出接口与第二输出接口；二线路组合，设置于所述驱动模块与基板之间，所述二线路组合包括第一线路与第二线路，所述第一线路连接于第一输出接口与第二输入接口之间，所述第二线路连接于第二输出接口与第一输入接口之间，所述第二线路是为折线、直线、曲线或斜线方式配置，所述第一线路是以跨线方式配置。
本申请的又一目的为一种显示面板，其包括相对设置的阵列基板与对向基板；其中，所述阵列基板包括：基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线配置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线的多个输入接口配置于所述布线区；驱动模块，配置于所述布线区，所述驱动模块包括多个输出接口；多个连接线路，设置于所述多个输入接口与所述多个输出接口之间，使所述多个输入接口分别与所述多个输出接口电性耦接；其中，所述多个连接线路中至少一条线路为跨线配置，所述多个输入接口与所述多个输出接口的线路配置顺序为相异。
本申请可以不大幅改变现有生产流程的前提，较能维持原制程需求和产品成本，通过布线设计即能改变显示区的控制信号接收时序，无需更动驱动模块(如驱动IC，驱动控制电路)的控制信号输 出时序，较能降低驱动模块的调节成本。
附图说明
图1a为范例性的显示装置的架构示意图。
图1b为范例性的像素单元配置示意图。
图1c为范例性的显示装置的扇出区的布线示意图。
图2a为显示依据本申请的方法，一实施例的阵列基板的布线示意图。
图2b为显示依据本申请的方法，一实施例的阵列基板的布线示意图。
图2c为显示依据本申请的方法，一实施例的阵列基板的布线示意图。
图3为显示依据本申请的方法，一实施例的阵列基板的布线示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本发明不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度，亦夸大电路的配置范围。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度，亦夸大电路的配置范围。将理解的是，当例如层、膜、区域、电路或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体实施例，对依据本发明提出的一种阵列基板及其应用的显示面板，其具体实施方式、结构、特征及其功效，详细说明如后。
图1a为范例性的显示装置的架构示意图。请参照图1a，一种液晶显示器，包括：控制板100，所述控制板101包括时序控制器(Timing Controller，TCON)101；印刷电路板103，与所述控制板之间通过柔性扁平电缆(Flexible Flat Cable，FFC)102相连接；源极覆晶薄膜104和栅极覆晶薄膜105，分别与显示区106内的源极线104a及栅极线105a连接。
在一些实施例中，显示装置的驱动方式包括：系统主板提供颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板100。控制板100上的时序控制器101处理此等信号后，连同被驱动电路处理的电源，通过如柔性扁平电缆(Flexible Flat Cable，FFC)102，一并传输至印刷电路板103的源极电路及栅极电路，通过源极覆晶薄膜104和栅极覆晶薄膜105将必要性的数据与电源传输于显示区106，从而使得显示器获得呈现画面需求的电源、信号。
图1b为范例性的像素单元配置示意图。请配合图1a以利于了解。栅极驱动单元105是逐行提供扫瞄信号给栅极线105a，每一扫瞄周期提供扫瞄信号给一行栅极线105a。显示面板的源极线104a会被逐行打开，源极驱动单元104通过源极线104a提供数据至像素单元P。
图1c为范例性的显示装置的扇出区的布线示意图，请配合图1a及图1b以利于了解。如1c所绘示，覆晶薄膜上配置有对应的集成电路(IC)，在一些实施例中，集成电路的通道大体上是依据其顺序而分别与显示区106的导电线路相连接。依据集成电路的不同，所连接的导电线路亦不相同。如栅极集成电路即连接扫瞄线(栅极线)，如源极集成电路即连接数据线(源极线)。
如图1c所绘示，以栅极集成电路107为例，所述栅极集成电路107的通道排列顺序为g1至gn，栅极集成电路的信号输出时序也是被调整如同据通道信号输出时序。
然而，此类集成电路(IC)、控制芯片(Chip)等组件，其输出通道及信号输出时序并不见得图1c所示，还需要设计人员先行调适。然此等组件不见得是由显示器厂商自行设计与制作。所以，设计人员需要取得集成电路的信号输出的时序及真值表等相关信息，内部韧体读写方式，才能通过特定软件调整芯片/集成电路的信号输出模式，元件调节后也需要测试以确保功能是正确，相当的劳力费时。
图2a为显示依据本申请的方法，一实施例的阵列基板的布线示意图。现有的显示面板组件配置请配合图1a至图1c以利于理解。请参照图2a，在本申请一实施例中，所述一种阵列基板，包括：基板200，包括显示区106及其外围的布线区108，多个主动开关T、多个像素单元P和多条信号线210配置于所述显示区106，所述多个像素单元P分别耦接于所述多个主动开关T，所述多个主动开关T分别电性耦接所述多条信号线210，所述多条信号线210的多个输入接口211配置于所述布线区108；驱动模块220，配置于所述布线区108，所述驱动模块220包括多个输出接口222；多个连接线路230，设置于所述多个输入接口211与所述多个输出接口222之间，使所述多个输入接口211分别与所述多个输出接口222电性耦接；其中，所述多个连接线路230中至少一条线路为跨线配置，所述多个输出接口222与所述多个输入接口211的线路配置顺序为相异。
在一些实施例中，所述多个连接线路包括多线路组合，所述多线路组合中的至少一条线路为跨线配置。
在一些实施例中，所述驱动模块210将控制信号通过所述多个输出接口222以第一顺序输出，所述多个输入接口211的所述控制信号接收顺序是以第二顺序输入，其中，所述多个连接线路230自所述多个输出接口222以所述第一顺序取得所述控制信号，以所述第二顺序输出所述控制信号至所述多个输入接口211。
如图2a所绘示，在一些实施例中，所述多线路组合包括二线路组合232。所述二线路组合包括第一线路232a与第二线路232b。所述第二线路232b是以折线方式配置，所述第一线路232a是以跨线方式配置。所述第一线路连接于输出接口g1与输入接口G2之间，所述第二线路连接于输出接口g2与输入接口G1之间。假定控制信号的通过所述输出接口的时序为(g1->g2)，所述控制信号到达所述输入接口的时序则为(G2->G1)。
图2b为显示依据本申请的方法，一实施例的阵列基板的布线示意图。请参照图2b，在一些实施例中，所述多线路组合包括三线路组合233。所述三线路组合233包括第一线路233a、第二线路233b与第三线路233c。所述第二线路233b及所述第三线路233c是以折线方式配置，第一线路233a是以跨线方式配置。所述第一线路233a连接于输出接口g1与输入接口G3之间，所述第二线路连接于输出接口g2与输入接口G1之间，所述第三线路连接于输出接口g3与输入接口G2之间。假定控制信号的通过所述输出接口的时序为(g1->g2->g3)，所述控制信号到达所述输入接口的时序则为(G3->G1->G2)。
图2c为显示依据本申请的方法，一实施例的阵列基板的布线示意图。请参照图2c，在一些实施例中，所述多线路组合包括四线路组合。所述四线路组合包括第一线路234a、第二线路234b、第三线路234c与第四线路234d。所述第二线路234b、所述第三线路234c与所述第四线路234d是以折线方式配置，所述第一线路234a是以跨线方式配置。所述第一线路234a连接于输出接口g1与输入接口G4之间，所述第二线路234b连接于输出接口g2与输入接口G1之间，所述第三线路234c连接于输出接口g3与输入接口G2之间，所述第四线路234d连接于输出接口g4与输入接口G3之间。假定控制信号的通过所述输出接口的时序为(g1->g2->g3->g4)，所述控制信号到达所述输入接口的时序则为(G4->G1->G2->G3)。
在一些实施例中，除跨线配置外，所述多个连接线路包括折线、直线、曲线、斜线等配置方式，但不以此为限，配置方式视设计人员需求而定。
图3为显示依据本申请的方法，一实施例的阵列基板的布线示意图。请参照图3，在一些实施例中，所述集成电路的所述多个输出接口的排序为(g1-g12)，所述控制信号输出的时序却是(g2->g1->g3->g4->g7->g8->g5->g6->g12->g9->g10->g11)，此与所述多个输出接口的排序相异。所述多个输入接口接收所述控制信号的时序要求为(G1->G12)。因此，可混用多种不同的所述多线路组 合以及对接线路于所述多个输出接口及所述多个输入接口之间。其中，所述对接线路可使同顺序的输入接口及输出接口对接。
如图3所绘示，所述多个连接线路包括所述二线路组合232、所述三线路组合233、所述四线路组合234及对接线路231，其中，所述二线路组合232包括第一线路232a与第二线路232b。所述第一线路232a是以折线方式配置，所述第二线路232b是以跨线方式配置。所述第一线路232a连接于输出接口g1与输入接口G2之间，所述第二线路232b连接于输出接口g2与输入接口G1之间。
所述三线路组合233包括第一线路233a、第二线路233b与第三线路233c。所述第一线路233a及所述第二线路233b是以折线方式配置，第三线路233c是以跨线方式配置。所述第一线路233a连接于输出接口g5与输入接口G6之间，所述第二线路233b连接于输出接口g6与输入接口G7之间，所述第三线路233c连接于输出接口g7与输入接口G5之间。
所述四线路234组合包括第一线路234a、第二线路234b、第三线路234c与第四线路234d。所述第一线路234a、所述第二线路234b与所述第三线路234c是以折线方式配置，所述第四线路234d是以跨线方式配置。所述第一线路234a连接于输出接口g9与输入接口G10之间，所述第二线路234b连接于输出接口g10与输入接口G11之间，所述第三线路234c连接于输出接口g11与输入接口G12之间，所述第三线路234d连接于输出接口g12与输入接口G9之间。
所述对接线路231分别设置于输出接口g3与输入接口G3之间，输出接口g4与输入接口G4之间，输出接口g8与输入接口G8之间。
如此，所述集成电路的所述控制信号输出的时序是(g2->g1->g3->g4->g7->g5->g6->g8->g12->g9->g10->g11)，但所述多个输入接口接收所述控制信号的时序却可符合(G1->G12)的要求。
在一些实施例中，所述驱动模块220包括覆晶薄膜，压覆在所述基板200的边缘，所述覆晶薄膜包括所述多个输出接口221。
在一些实施例中，所述覆晶薄膜为栅极覆晶薄膜105。
在一些实施例中，所述覆晶薄膜为源极覆晶薄膜104。
在一些实施例中，所述多个连接线路230配置于所述布线区108的扇出区。
在本申请一实施例中，本申请的一种阵列基板，其包括：基板200，包括显示区106及其外围的布线区108，多个主动开关T、多个像素单元P和多条信号线210配置于所述显示区106，所述多个像素单元P分别耦接于所述多个主动开关T，所述多个主动开关T分别电性耦接所述多条信号线210，所述多条信号线210的多个输入接口211配置于所述布线区108，所述多个输入接口106 包括第一输入接口g1与第二输入接口g2；驱动模块220，包括第一输出接口G1与第二输出接口G2；二线路组合232，设置于所述驱动模块150与基板200之间，所述二线路组合232包括第一线路232a与第二线路232b，所述第一线路232a连接于第一输出接口g1与第二输入接口G2之间，所述第二线路232b连接于第二输出接口g2与第一输入接口G1之间，所述第二线路232b是为折线、直线、曲线或斜线方式配置，所述第一线路232a是以跨线方式配置。
在本申请一实施例中，本申请的一种显示面板，其包括：相对设置的阵列基板与对向基板；其中，所述阵列基板包括：基板200，包括显示区106及其外围的布线区108，多个主动开关T、多个像素单元P和多条信号线210配置于所述显示区106，所述多个像素单元P分别耦接于所述多个主动开关T，所述多个主动开关T分别电性耦接所述多条信号线210，所述多条信号线210的多个输入接口211配置于所述布线区108；驱动模块220，配置于所述布线区108，所述驱动模块220包括多个输出接口222；多个连接线路230，设置于所述多个输入接口211与所述多个输出接口222之间，使所述多个输入接口211分别与所述多个输出接口222电性耦接；其中，所述多个连接线路230中至少一条线路为跨线配置，所述多个输出接口222与所述多个输入接口211的线路配置顺序为相异。
在一些实施例中，所述阵列基板更包括先前所述任一种实施方式。
在某些实施例中，本申请所述显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED显示面板，W-OLED显示面板，QLED显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
本申请可以不大幅改变现有生产流程的前提，较能维持原制程需求和产品成本，通过布线设计即能改变显示区的控制信号接收时序，无需更动驱动模块(如驱动IC，驱动控制电路)的控制信号输出时序，较能降低驱动模块的调节成本。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。此用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种阵列基板，包括：
    基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线配置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线的多个输入接口配置于所述布线区；
    驱动模块，配置于所述布线区，所述驱动模块包括多个输出接口；
    多个连接线路，设置于所述多个输入接口与所述多个输出接口之间，使所述多个输入接口分别与所述多个输出接口电性耦接；
    其中，所述多个连接线路中至少一条线路为跨线配置，所述多个输入接口与所述多个输出接口的线路配置顺序为相异。
  2. 如权利要求1所述的阵列基板，所述多个连接线路包括多线路组合。
  3. 如权利要求2所述的阵列基板，其中，所述多线路组合中的至少一条线路为跨线配置。
  4. 如权利要求2所述的阵列基板，所述多线路组合包括二线路组合、三线路组合与四线路组合中至少其一者。
  5. 如权利要求2所述的阵列基板，其中，所述驱动模块将控制信号通过所述多个输出接口以第一顺序输出，所述多个输入接口的所述控制信号接收顺序是以第二顺序输入，其中，所述多个连接线路自所述多个输出接口以所述第一顺序取得所述控制信号，以所述第二顺序输出所述控制信号至所述多个输入接口。
  6. 如权利要求1所述的阵列基板，所述驱动模块包括覆晶薄膜，压覆在所述基板的边缘。
  7. 如权利要求6所述的阵列基板，所述覆晶薄膜包括所述多个输出接口。
  8. 如权利要求6所述的阵列基板，其中，所述覆晶薄膜为栅极覆晶薄膜。
  9. 如权利要求6所述的阵列基板，其中，所述覆晶薄膜为源极覆晶薄膜。
  10. 如权利要求1所述的阵列基板，其中，所述多个连接线路配置于所述布线区的扇出区。
  11. 一种阵列基板，包括：
    基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线配置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线的多个输入接口配置于所述布线区，所述多个输入接口包括第一输入接口与第二输入接口；
    驱动模块，包括第一输出接口与第二输出接口；
    二线路组合，设置于所述驱动模块与基板之间，所述二线路组合包括第一线路与第二线路，所 述第一线路连接于第一输出接口与第二输入接口之间，所述第二线路连接于第二输出接口与第一输入接口之间，所述第二线路是为折线、直线、曲线或斜线方式配置，所述第一线路是以跨线方式配置。
  12. 一种显示面板，包括：
    阵列基板：
    对向基板，与所述阵列基板相对设置；
    其中，所述阵列基板包括：
    基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线配置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线的多个输入接口配置于所述布线区；
    驱动模块，配置于所述布线区，所述驱动模块包括多个输出接口；
    多个连接线路，设置于所述多个输入接口与所述多个输出接口之间，使所述多个输入接口分别与所述多个输出接口电性耦接；
    其中，所述多个连接线路中至少一条线路为跨线配置，所述多个输入接口与所述多个输出接口的线路配置顺序为相异。
  13. 如权利要求12所述的显示面板，所述多个连接线路包括多线路组合。
  14. 如权利要求13所述的显示面板，其中，所述多线路组合中的至少一条线路为跨线配置。
  15. 如权利要求13所述的显示面板，所述多线路组合包括二线路组合、三线路组合与四线路组合中至少其一者。
  16. 如权利要求13所述的显示面板，其中，所述驱动模块将控制信号通过所述多个输出接口以第一顺序输出，所述多个输入接口的所述控制信号接收顺序是以第二顺序输入，其中，所述多个连接线路自所述多个输出接口以所述第一顺序取得所述控制信号，以所述第二顺序输出所述控制信号至所述多个输入接口。
  17. 如权利要求12所述的显示面板，所述驱动模块包括覆晶薄膜，压覆在所述基板的边缘。
  18. 如权利要求17所述的显示面板，所述覆晶薄膜包括所述多个输出接口。
  19. 如权利要求17所述的显示面板，其中，所述覆晶薄膜为栅极覆晶薄膜。
  20. 如权利要求17所述的显示面板，其中，所述覆晶薄膜为源极覆晶薄膜。
PCT/CN2017/117079 2017-10-12 2017-12-19 阵列基板及其应用的显示面板 WO2019071814A1 (zh)

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CN112530379A (zh) * 2019-09-18 2021-03-19 咸阳彩虹光电科技有限公司 一种显示装置及其接口类型选择方法
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