WO2018010412A1 - I2c传输电路及显示装置 - Google Patents

I2c传输电路及显示装置 Download PDF

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Publication number
WO2018010412A1
WO2018010412A1 PCT/CN2017/071597 CN2017071597W WO2018010412A1 WO 2018010412 A1 WO2018010412 A1 WO 2018010412A1 CN 2017071597 W CN2017071597 W CN 2017071597W WO 2018010412 A1 WO2018010412 A1 WO 2018010412A1
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Prior art keywords
transistor
selection circuit
circuit
selection
input end
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PCT/CN2017/071597
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English (en)
French (fr)
Inventor
黄笑宇
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深圳市华星光电技术有限公司
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Priority to US15/500,119 priority Critical patent/US10467950B2/en
Publication of WO2018010412A1 publication Critical patent/WO2018010412A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an I2C transmission circuit and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the main driving principle of the liquid crystal display is that the system motherboard connects the red, green, and blue compression signals, control signals, and driving signals to the connectors on the driving circuit board through the wires.
  • the data is processed by a Timing Controller (T-CON) chip, and then driven through the circuit board 1 through a Data-Chip on Film (S-COF) 2 and scanning.
  • a gate-on-film (G-COF) 3 is connected to the circuit and the original in the array substrate 4, so that the liquid crystal display obtains a desired driving signal and realizes image display.
  • an integrated circuit bus (Inter-Integrated Circuit, I2C) protocol is generally used in the process of communication between the driver circuit board and the driver circuit board and the outside.
  • the I2C bus is connected to each device through a serial data line and a serial clock line for signal transmission.
  • I2C Inter-Integrated Circuit
  • the present invention provides an I2C transmission circuit including a first selection circuit, a second selection circuit, and a selection signal line;
  • the input end of the first selection circuit is used to connect a serial clock line, and the input end of the second selection circuit is used to connect a serial data line;
  • the selection signal line is connected to the control ends of the first selection circuit and the second selection circuit;
  • the input end of the first selection circuit is electrically connected to the first output end, and the input end of the second selection circuit is electrically connected to the first output end;
  • an input end of the first selection circuit is electrically connected to a second output end, and an input end of the second selection circuit is electrically connected to the second output end.
  • the first selection circuit comprises a first transistor and a second transistor, and the first transistor is an NMOS and the second transistor is a PMOS.
  • the selection signal line connects the gates of the first transistor and the second transistor
  • the sources of the first transistor and the second transistor are connected to an input end of the first selection circuit
  • the drain of the first transistor is connected to the first output end of the first selection circuit
  • the drain of the second transistor is coupled to the second output of the first selection circuit.
  • the second selection circuit includes a third transistor and a fourth transistor, and the third transistor is an NMOS, and the fourth transistor is a PMOS.
  • the selection signal line connects the gates of the third transistor and the fourth transistor
  • the sources of the third transistor and the fourth transistor are connected to an input end of the second selection circuit
  • the drain of the third transistor is connected to the first output end of the second selection circuit
  • the drain of the fourth transistor is coupled to the second output of the second selection circuit.
  • the invention also provides a display device comprising a driving circuit board and the above-mentioned I2C transmission circuit;
  • the I2C bus in the drive circuit board is connected to other devices through the I2C transmission circuit.
  • the display device further includes an array substrate, a color filter substrate, and a liquid crystal layer filled between the array substrate and the color filter substrate.
  • the I2C transmission circuit is formed on the array substrate.
  • the I2C transmission circuit is located in a fan-out line area of the array substrate.
  • the I2C bus in the driving circuit board is connected to the I2C transmission circuit through a flip chip.
  • the I2C transmission circuit provided by the present invention includes a first selection circuit and a second Select the circuit.
  • the input end of the first selection circuit is used to connect the serial clock line, the two output ends are respectively used to transmit the clock signal to different devices;
  • the input end of the second selection circuit is used to connect the serial data line, two The outputs are used to transmit data signals to different devices, respectively.
  • the I2C transmission circuit provided by the present invention can control the output ports of the first selection circuit and the second selection circuit by selecting signal lines, thereby avoiding erroneous writing and erroneous reading during I2C communication.
  • FIG. 1 is a schematic view of a conventional liquid crystal display
  • FIG. 2 is a schematic diagram of an I2C transmission circuit according to Embodiment 1 of the present invention.
  • FIG. 3 is a circuit diagram of an I2C transmission circuit in a display device according to Embodiment 2 of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • an embodiment of the present invention provides an I2C transmission circuit including a first selection circuit, a second selection circuit, and a selection signal line A.
  • the selection signal line A is connected to the control ends of the first selection circuit and the second selection circuit. .
  • the input end of the first selection circuit is used to connect the serial clock line SCL, and the two output terminals SCL_1 and SCL_2 are respectively used to transmit the clock signal to the clock signal interface of the two devices; the input of the second selection circuit The terminal is used to connect the serial data line SDA, and the two outputs SDA_1 and SDA_2 are respectively used to transmit data signals to the data signal interfaces of the two devices.
  • SCL_1 and SDA_1 are respectively connected to the clock data interface and the data signal interface of the first device
  • SCL_2 and SDA_2 are respectively connected to the clock data interface and the data signal interface of the second device.
  • the selection signal line A When the selection signal line A is at a low level, the input end of the first selection circuit is turned on with the first output terminal SCL_1, and the second output terminal SCL_2 is in an off state; and the input end of the second selection circuit and the first output terminal SDA_1 Turned on, and the second output terminal SDA_2 is in an off state.
  • the serial clock line SCL and the serial data line SDA communicate with the first device through the first selection circuit and the second selection circuit, respectively, thereby transmitting the clock signal and the data signal to the first device.
  • the input end of the first selection circuit is turned on with the second output terminal SCL_2, and the first output terminal SCL_1 is in an off state; and the input end of the second selection circuit and the second output terminal SDA_2 Turned on, and the first output terminal SDA_1 is in an off state.
  • the serial clock line SCL and the serial data line SDA communicate with the second device through the first selection circuit and the second selection circuit, respectively, thereby transmitting the clock signal and the data signal to the second device.
  • the I2C transmission circuit provided by the embodiment of the present invention can control the output ports of the first selection circuit and the second selection circuit by selecting the signal line A, thereby avoiding erroneous writing and erroneous reading during I2C communication.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the embodiment of the invention provides a display device, which can be a large display device such as a liquid crystal television, or a display device with a touch function, such as a mobile phone or a tablet computer.
  • the display device comprises a driving circuit board and an I2C transmission circuit provided in the first embodiment.
  • the I2C bus in the driving circuit board is connected to other devices through an I2C transmission circuit.
  • the display device provided by the embodiment of the invention further includes an array substrate, a color filter substrate, and a liquid crystal layer filled between the array substrate and the color filter substrate.
  • the I2C transmission circuit can be formed on the array substrate, so that the I2C transmission circuit can be formed by a photolithography process in synchronization with a circuit structure such as a thin film transistor in the display region.
  • the I2C transmission circuit in this embodiment can be fabricated by a Complementary Metal Oxide Semiconductor (CMOS) process, using ultra-high carrier mobility of Low Temperature Poly-silicon (LTPS).
  • CMOS Complementary Metal Oxide Semiconductor
  • LTPS Low Temperature Poly-silicon
  • the I2C transmission circuit is formed in a fanout area of the array substrate, and the I2C bus in the driving circuit board can be connected to the I2C transmission circuit through the flip chip, so that the area of the array substrate is not due to the I2C transmission circuit. increase.
  • an I2C transmission circuit is formed on the array substrate 10.
  • the serial clock line SCL and the serial data line SDA are taken out from the driving circuit board 20.
  • the selection signal line A of the I2C transmission circuit is also The drive circuit board 20 is led out.
  • the first selection circuit in the I2C transmission circuit includes a first transistor M1 and a second transistor M2, and the first transistor M1 is an NMOS and the second transistor M2 is a PMOS.
  • the gates of the first transistor M1 and the second transistor M2 serve as control terminals of the first selection circuit, and are connected to the selection signal line A.
  • the sources of the first transistor M1 and the second transistor M2 serve as inputs to the first selection circuit and are connected to the serial clock line SCL.
  • the drain of the first transistor M1 serves as a first output terminal SCL_1 of the first selection circuit, and is connected to a clock signal interface of the first device.
  • the drain of the second transistor M2 serves as a second output terminal SCL_2 of the first selection circuit, and is connected to the clock signal interface of the second device.
  • the first device and the second device are two different devices, for example, the first device may be a driver for displaying a signal, and the second device may be a driver for a touch signal. As can be seen from FIG. 3, the first device and the second device in this embodiment are also disposed on the driving circuit board 20.
  • the second selection circuit in the I2C transmission circuit includes a third transistor M3 and a fourth transistor M4, and the third transistor M3 is an NMOS, and the fourth transistor M4 is a PMOS.
  • the gates of the third transistor M3 and the fourth transistor M4 serve as control terminals of the second selection circuit, and are connected to the selection signal line A.
  • the sources of the third transistor M3 and the fourth transistor M4 serve as inputs to the second selection circuit and are connected to the serial data line SDA.
  • the drain of the third transistor M3 serves as a first output terminal SDA_1 of the second selection circuit, and is connected to the data signal interface of the first device.
  • the drain of the fourth transistor M4 serves as a second output terminal SDA_2 of the second selection circuit, and is connected to the data signal interface of the second device.
  • the selection signal line A When the selection signal line A is at a low level (usually designed to be 0V), the first transistor M1 in the first selection circuit is turned on, and the second transistor M2 is turned off, and the serial clock line SCL is only the first of the first selection circuit. An output terminal SCL_1 is turned on. At the same time, the third transistor M3 in the second selection circuit is turned on, and the fourth transistor M4 is turned off, and the serial data line SDA is only turned on with the first output terminal SDA_1 of the second selection circuit. At this time, the serial clock line SCL and the serial data line SDA are respectively communicated with the first device through the first selection circuit and the second selection circuit, thereby transmitting the clock signal and the data signal to the first device to implement the first device. The read and write are disconnected from the second device.
  • the selection signal line A When the selection signal line A is at a high level (typically designed to be 3.3V), the first transistor M1 in the first selection circuit is turned off, and the second transistor M2 is turned on, and the serial clock line SCL is only connected to the first selection circuit. The second output terminal SCL_2 is turned on. At the same time, the third transistor M3 in the second selection circuit is turned off, and the fourth transistor M4 is turned on, and the serial data line SDA is only turned on with the second output terminal SDA_2 of the second selection circuit.
  • a high level typically designed to be 3.3V
  • serial clock line SCL and the serial data line SDA communicate with the second device through the first selection circuit and the second selection circuit, respectively, thereby turning the clock signal And the data signal is transmitted to the second device to enable reading and writing to the second device, and is disconnected from the first device.
  • the display device provided by the embodiment of the present invention can control the output ports of the first selection circuit and the second selection circuit by selecting the signal line A by using the above-mentioned I2C transmission circuit, thereby avoiding erroneous writing during I2C communication. And mis-reading improves the reliability of the display device during display.
  • the I2C transmission circuit is formed synchronously with the circuit structure of the thin film transistor in the display area by using a photolithography process, so that the I2C transmission circuit can be realized without adding additional production cost, so The inventive embodiments have very high feasibility.

Abstract

一种I2C传输电路及显示装置，解决了在I2C通信过程中，容易对目标器件之外的器件发生误写入的技术问题。该I2C传输电路包括第一选择电路、第二选择电路和选择信号线（A）；第一选择电路的输入端用于连接串行时钟线（SCL），第二选择电路的输入端用于连接串行数据线（SDA）；选择信号线（A）连接第一选择电路和第二选择电路的控制端。

Description

I2C传输电路及显示装置
本申请要求享有2016年7月14日提交的名称为“I2C传输电路及显示装置”的中国专利申请CN201610556217.X的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体的说，涉及一种I2C传输电路及显示装置。
背景技术
随着显示技术的发展，液晶显示屏已经成为最为常见的显示装置。其中，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)是当前平面显示装置的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。
液晶显示器的主要驱动原理是，系统主板将红色、绿色、蓝色压缩信号、控制信号及驱动信号通过线材与驱动电路板上的连接器相连。如图1所示，数据经过时序控制器(Timing Controller，简称T-CON)芯片处理后，经驱动电路板1，通过数据覆晶薄膜(Source-Chip on Film，简称S-COF)2和扫描覆晶薄膜(Gate-Chip on Film，简称G-COF)3与阵列基板4中的电路、原件连接，从而使得液晶显示器获得所需的驱动信号，实现图像的显示。
其中，在驱动电路板内部及驱动电路板与外部的通信过程中，普遍会采用集成电路总线(Inter-Integrated Circuit，简称I2C)协议。I2C总线通过串行数据线和串行时钟线在连接到各个器件，实现信号传输。在实际的应用中，因为所有的器件都是同时连接在I2C总线上的，因此在I2C通信过程中，容易导致对目标器件之外的器件发生误写入或误读取的问题，而影响了液晶显示器的正常显示效果。
发明内容
本发明的目的在于提供一种I2C传输电路及显示装置，以解决在I2C通信过程中，容易对目标器件之外的器件发生误写入的技术问题。
本发明提供一种I2C传输电路，包括第一选择电路、第二选择电路和选择信号线；
所述第一选择电路的输入端用于连接串行时钟线，第二选择电路的输入端用于连接串行数据线；
所述选择信号线连接所述第一选择电路和所述第二选择电路的控制端；
当所述选择信号线为低电平时，所述第一选择电路的输入端与第一输出端导通，所述第二选择电路的输入端与第一输出端导通；
当所述选择信号线为高电平时，所述第一选择电路的输入端与第二输出端导通，所述第二选择电路的输入端与第二输出端导通。
优选的是，所述第一选择电路包括第一晶体管和第二晶体管，且所述第一晶体管为NMOS，所述第二晶体管为PMOS。
进一步的是，所述选择信号线连接所述第一晶体管和所述第二晶体管的栅极，
所述第一晶体管和所述第二晶体管的源极连接所述第一选择电路的输入端；
所述第一晶体管的漏极连接所述第一选择电路的第一输出端；
所述第二晶体管的漏极连接所述第一选择电路的第二输出端。
优选的是，所述第二选择电路包括第三晶体管和第四晶体管，且所述第三晶体管为NMOS，所述第四晶体管为PMOS。
进一步的是，所述选择信号线连接所述第三晶体管和所述第四晶体管的栅极，
所述第三晶体管和所述第四晶体管的源极连接所述第二选择电路的输入端；
所述第三晶体管的漏极连接所述第二选择电路的第一输出端；
所述第四晶体管的漏极连接所述第二选择电路的第二输出端。
本发明还提供一种显示装置，包括驱动电路板和上述的I2C传输电路；
所述驱动电路板中的I2C总线通过所述I2C传输电路连接至其他器件。
进一步的是，该显示装置还包括阵列基板、彩膜基板，以及填充与所述阵列基板与所述彩膜基板之间的液晶层。
优选的是，所述I2C传输电路形成于所述阵列基板上。
进一步的是，所述I2C传输电路位于所述阵列基板的扇出线区域。
优选的是，所述驱动电路板中的I2C总线通过覆晶薄膜与所述I2C传输电路连接。
本发明带来了以下有益效果：本发明提供的I2C传输电路中包括第一选择电路、第二 选择电路。其中，第一选择电路的输入端用于连接串行时钟线，两个输出端分别用于将时钟信号传输至不同的器件；第二选择电路的输入端用于连接串行数据线，两个输出端分别用于将数据信号传输至不同的器件。
当选择信号线为低电平时，第一选择电路的输入端仅与第一输出端导通，所述第二选择电路的输入端仅与第一输出端导通，此时时钟信号和数据信号分别通过第一选择电路和第二选择电路传输至同一个器件。当选择信号线为高电平时，第一选择电路的输入端仅与第二输出端导通，所述第二选择电路的输入端仅与第二输出端导通，此时时钟信号和数据信号分别通过第一选择电路和第二选择电路传输至另一个器件。因此，本发明提供的I2C传输电路能够通过选择信号线控制第一选择电路和第二选择电路的输出端口，从而避免了I2C通信过程中发生误写入和误读取。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分的从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚的说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是现有的液晶显示器的示意图；
图2是本发明实施例一提供的I2C传输电路的示意图；
图3是本发明实施例二提供的显示装置中I2C传输电路的电路图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一：
如图2所示，本发明实施例提供一种I2C传输电路，包括第一选择电路、第二选择电路和选择信号线A，选择信号线A连接第一选择电路和第二选择电路的控制端。
本实施例中，第一选择电路的输入端用于连接串行时钟线SCL，两个输出端SCL_1和SCL_2分别用于将时钟信号传输至两个器件的时钟信号接口；第二选择电路的输入端用于连接串行数据线SDA，两个输出端SDA_1和SDA_2分别用于将数据信号传输至两个器件的数据信号接口。其中，SCL_1和SDA_1分别连接在第一器件的时钟数据接口和数据信号接口，SCL_2和SDA_2分别连接在第二器件的时钟数据接口和数据信号接口。
当选择信号线A为低电平时，第一选择电路的输入端与第一输出端SCL_1导通，而第二输出端SCL_2处于截止状态；同时第二选择电路的输入端与第一输出端SDA_1导通，而第二输出端SDA_2处于截止状态。此时，串行时钟线SCL和串行数据线SDA分别通过第一选择电路和第二选择电路与第一器件实现通信，从而将时钟信号和数据信号传输至第一器件。
当选择信号线A为高电平时，第一选择电路的输入端与第二输出端SCL_2导通，而第一输出端SCL_1处于截止状态；同时第二选择电路的输入端与第二输出端SDA_2导通，而第一输出端SDA_1处于截止状态。此时，串行时钟线SCL和串行数据线SDA分别通过第一选择电路和第二选择电路与第二器件实现通信，从而将时钟信号和数据信号传输至第二器件。
因此，本发明实施例提供的I2C传输电路，能够通过选择信号线A控制第一选择电路和第二选择电路的输出端口，从而避免了I2C通信过程中发生误写入和误读取。
实施例二：
本发明实施例提供一种显示装置，可以液晶电视机等大型显示装置，也可以是手机、平板电脑等具有触控功能的显示装置。该显示装置包括驱动电路板和上述实施例一提供的I2C传输电路，驱动电路板中的I2C总线通过I2C传输电路连接至其他器件。
本发明实施例提供的显示装置还包括阵列基板、彩膜基板，以及填充与阵列基板与彩膜基板之间的液晶层。I2C传输电路可以形成于阵列基板上，使I2C传输电路可以通过光刻工艺，与显示区域中的薄膜晶体管等电路结构同步形成。本实施例中的I2C传输电路可以采用互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称CMOS)工艺制成，利用低温多晶硅(Low Temperature Poly-silicon，简称LTPS)的超高载流子迁移率的特性，可以在制作包括PMOS和NMOS两种晶体管。
作为一个优选方案，I2C传输电路形成于阵列基板的扇出线(fanout)区域，驱动电路板中的I2C总线可以通过覆晶薄膜与I2C传输电路连接，使阵列基板的面积不会因为I2C传输电路而增加。
如图3所示，本实施例中，I2C传输电路形成于阵列基板10上，串行时钟线SCL和串行数据线SDA由驱动电路板20中引出，I2C传输电路的选择信号线A也由驱动电路板20中引出。
I2C传输电路中的第一选择电路包括第一晶体管M1和第二晶体管M2，且第一晶体管M1为NMOS，第二晶体管M2为PMOS。第一晶体管M1和第二晶体管M2的栅极作为第一选择电路的控制端，与选择信号线A连接。第一晶体管M1和第二晶体管M2的源极作为第一选择电路的输入端，与串行时钟线SCL连接。第一晶体管M1的漏极作为第一选择电路的第一输出端SCL_1，连接第一器件的时钟信号接口。第二晶体管M2的漏极作为第一选择电路的第二输出端SCL_2，连接第二器件的时钟信号接口。
上述第一器件与第二器件是不同的两个器件，比如第一器件可以是显示信号的驱动器，第二器件可以是触控信号的驱动器。从图3中可以看出，本实施例中的第一器件和第二器件也设置于驱动电路板20上。
I2C传输电路中的第二选择电路包括第三晶体管M3和第四晶体管M4，且第三晶体管M3为NMOS，第四晶体管M4为PMOS。第三晶体管M3和第四晶体管M4的栅极作为第二选择电路的控制端，与选择信号线A连接。第三晶体管M3和第四晶体管M4的源极作为第二选择电路的输入端，与串行数据线SDA连接。第三晶体管M3的漏极作为第二选择电路的第一输出端SDA_1，连接第一器件的数据信号接口。第四晶体管M4的漏极作为第二选择电路的第二输出端SDA_2，连接第二器件的数据信号接口。
当选择信号线A为低电平(通常设计为0V)时，第一选择电路中的第一晶体管M1导通，第二晶体管M2截止，则串行时钟线SCL仅与第一选择电路的第一输出端SCL_1导通。同时，第二选择电路中的第三晶体管M3导通，第四晶体管M4截止，则串行数据线SDA仅与第二选择电路的第一输出端SDA_1导通。此时，串行时钟线SCL和串行数据线SDA分别通过第一选择电路和第二选择电路与第一器件实现通信，从而将时钟信号和数据信号传输至第一器件，实现对第一器件的读取和写入，而与第二器件之间是断开连接的。
当选择信号线A为高电平(通常设计为3.3V)时，第一选择电路中的第一晶体管M1截止，第二晶体管M2导通，则串行时钟线SCL仅与第一选择电路的第二输出端SCL_2导通。同时，第二选择电路中的第三晶体管M3截止，第四晶体管M4导通，则串行数据线SDA仅与第二选择电路的第二输出端SDA_2导通。此时，串行时钟线SCL和串行数据线SDA分别通过第一选择电路和第二选择电路与第二器件实现通信，从而将时钟信号 和数据信号传输至第二器件，实现对第二器件的读取和写入，而与第一器件之间是断开连接的。
因此，本发明实施例提供的显示装置，通过采用上述的I2C传输电路，能够通过选择信号线A控制第一选择电路和第二选择电路的输出端口，从而避免了I2C通信过程中发生误写入和误读取，提高了显示装置在显示过程中的可靠性。
另外，本实施例中采用光刻工艺，将I2C传输电路与显示区域中的薄膜晶体管等电路结构同步形成，从而能够在不增加额外生产成本的前提下，实现该I2C传输电路的制作，因此本发明实施例具有非常高的可行性。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种I2C传输电路，包括第一选择电路、第二选择电路和选择信号线；
    所述第一选择电路的输入端用于连接串行时钟线，第二选择电路的输入端用于连接串行数据线；
    所述选择信号线连接所述第一选择电路和所述第二选择电路的控制端；
    当所述选择信号线为低电平时，所述第一选择电路的输入端与第一输出端导通，所述第二选择电路的输入端与第一输出端导通；
    当所述选择信号线为高电平时，所述第一选择电路的输入端与第二输出端导通，所述第二选择电路的输入端与第二输出端导通。
  2. 根据权利要求1所述的I2C传输电路，其中，所述第一选择电路包括第一晶体管和第二晶体管，且所述第一晶体管为NMOS，所述第二晶体管为PMOS。
  3. 根据权利要求2所述的I2C传输电路，其中，所述选择信号线连接所述第一晶体管和所述第二晶体管的栅极，
    所述第一晶体管和所述第二晶体管的源极连接所述第一选择电路的输入端；
    所述第一晶体管的漏极连接所述第一选择电路的第一输出端；
    所述第二晶体管的漏极连接所述第一选择电路的第二输出端。
  4. 根据权利要求1所述的I2C传输电路，其中，所述第二选择电路包括第三晶体管和第四晶体管，且所述第三晶体管为NMOS，所述第四晶体管为PMOS。
  5. 根据权利要求4所述的I2C传输电路，其中，所述选择信号线连接所述第三晶体管和所述第四晶体管的栅极，
    所述第三晶体管和所述第四晶体管的源极连接所述第二选择电路的输入端；
    所述第三晶体管的漏极连接所述第二选择电路的第一输出端；
    所述第四晶体管的漏极连接所述第二选择电路的第二输出端。
  6. 一种显示装置，包括驱动电路板和I2C传输电路；
    所述I2C传输电路，包括第一选择电路、第二选择电路和选择信号线；
    所述第一选择电路的输入端用于连接串行时钟线，第二选择电路的输入端用于连接串行数据线；
    所述选择信号线连接所述第一选择电路和所述第二选择电路的控制端；
    当所述选择信号线为低电平时，所述第一选择电路的输入端与第一输出端导通，所述第二选择电路的输入端与第一输出端导通；
    当所述选择信号线为高电平时，所述第一选择电路的输入端与第二输出端导通，所述第二选择电路的输入端与第二输出端导通；
    所述驱动电路板中的I2C总线通过所述I2C传输电路连接至其他器件。
  7. 根据权利要求6所述的显示装置，其中，所述第一选择电路包括第一晶体管和第二晶体管，且所述第一晶体管为NMOS，所述第二晶体管为PMOS。
  8. 根据权利要求7所述的显示装置，其中，所述选择信号线连接所述第一晶体管和所述第二晶体管的栅极，
    所述第一晶体管和所述第二晶体管的源极连接所述第一选择电路的输入端；
    所述第一晶体管的漏极连接所述第一选择电路的第一输出端；
    所述第二晶体管的漏极连接所述第一选择电路的第二输出端。
  9. 根据权利要求6所述的显示装置，其中，所述第二选择电路包括第三晶体管和第四晶体管，且所述第三晶体管为NMOS，所述第四晶体管为PMOS。
  10. 根据权利要求9所述的显示装置，其中，所述选择信号线连接所述第三晶体管和所述第四晶体管的栅极，
    所述第三晶体管和所述第四晶体管的源极连接所述第二选择电路的输入端；
    所述第三晶体管的漏极连接所述第二选择电路的第一输出端；
    所述第四晶体管的漏极连接所述第二选择电路的第二输出端。
  11. 根据权利要求6所述的显示装置，其中，还包括阵列基板、彩膜基板，以及填充与所述阵列基板与所述彩膜基板之间的液晶层。
  12. 根据权利要求7所述的显示装置，其中，还包括阵列基板、彩膜基板，以及填充与所述阵列基板与所述彩膜基板之间的液晶层。
  13. 根据权利要求8所述的显示装置，其中，还包括阵列基板、彩膜基板，以及填充与所述阵列基板与所述彩膜基板之间的液晶层。
  14. 根据权利要求9所述的显示装置，其中，还包括阵列基板、彩膜基板，以及填充与所述阵列基板与所述彩膜基板之间的液晶层。
  15. 根据权利要求10所述的显示装置，其中，还包括阵列基板、彩膜基板，以及填 充与所述阵列基板与所述彩膜基板之间的液晶层。
  16. 根据权利要求11所述的显示装置，其中，所述I2C传输电路形成于所述阵列基板上。
  17. 根据权利要求12所述的显示装置，其中，所述I2C传输电路形成于所述阵列基板上。
  18. 根据权利要求13所述的显示装置，其中，所述I2C传输电路形成于所述阵列基板上。
  19. 根据权利要求16所述的显示装置，其中，所述I2C传输电路位于所述阵列基板的扇出线区域。
  20. 根据权利要求19所述的显示装置，其中，所述驱动电路板中的I2C总线通过覆晶薄膜与所述I2C传输电路连接。
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