WO2020093451A1 - 显示装置的数据保护系统及保护方法 - Google Patents

显示装置的数据保护系统及保护方法 Download PDF

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Publication number
WO2020093451A1
WO2020093451A1 PCT/CN2018/116598 CN2018116598W WO2020093451A1 WO 2020093451 A1 WO2020093451 A1 WO 2020093451A1 CN 2018116598 W CN2018116598 W CN 2018116598W WO 2020093451 A1 WO2020093451 A1 WO 2020093451A1
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WO
WIPO (PCT)
Prior art keywords
switch
signal
control
terminal
electrically coupled
Prior art date
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PCT/CN2018/116598
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English (en)
French (fr)
Inventor
黄笑宇
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US16/334,122 priority Critical patent/US11264083B2/en
Publication of WO2020093451A1 publication Critical patent/WO2020093451A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1407—General aspects irrespective of display type, e.g. determination of decimal point position, display with fixed or driving decimal point, suppression of non-significant zeros
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/08—Arrangements within a display terminal for setting, manually or automatically, display parameters of the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits

Definitions

  • the present application relates to the field of display technology, and in particular to a data protection system and protection method of a display device.
  • the system board is connected to the control board (Control-Board, C-Board) by wires.
  • the control board is connected to the printed circuit board (PCB) through a flexible flat cable (FFC), and the printed circuit board passes through the source.
  • An extremely flip chip (Source-Chip Film, S-COF) and a gate flip chip (Gate-Chip Film, G-COF) are connected to the display area.
  • the display driving method includes: the system motherboard transmits the color (for example: R / G / B) compressed signal, control signal and power to the control board.
  • the signal is processed by the Timing Controller (TCON) and then transmitted to the source driver circuit (Source Driver) and gate driver circuit (Gate Driver). Necessary data and power are transmitted to the display area through the relevant integrated circuit or chip, so that the display can obtain the power and signals required to display the picture.
  • a programmable erasable memory (EEPROM) is provided, which is set to store the control data and settings (TCON Code) of the timing device.
  • EEPROM programmable erasable memory
  • the write protection signal (WriteProtect, WP) of the EEPROM is normally high (H), that is, it must be in the write protection state under normal conditions.
  • WP write protection signal
  • the write protection signal may also be invalidated. Then, there may be a malfunction that may cause the control data stored in the EEPROM to be rewritten, which may cause an abnormal display screen and frequent errors.
  • the object of the present application is to provide a data protection system and a protection method for a display device, which control the storage element's Data write-protect or read-write mechanism.
  • a data protection system for a display device includes: a memory having a protection control terminal and storing timing control data; a timing controller connected to the memory, the timing controller obtaining the timing control data to Providing a control signal; and a switch including a first input terminal, a second input terminal, a control terminal and an output terminal, the first input terminal is electrically coupled to a read-write control signal, and the second input terminal is electrically coupled Connected to a constant potential signal, the output terminal is connected to the protection control terminal, the control terminal transmits the control signal, and the switch selectively connects the constant potential signal and all the signals according to the potential change of the control signal
  • the read-write control signal is output to the protection control terminal; wherein, when the switch transmits the constant potential signal to the protection control terminal, the switch disconnects the read-write control signal and the protection
  • the control terminals are electrically coupled, the protection control terminals are electrically coupled to the constant potential signal, and the memory maintains write-protection of the timing control data.
  • the switch includes a first resistor, a first switch, and a trigger circuit; the first end of the first switch is electrically coupled to the read-write control signal, and the first switch
  • the second terminal of the first resistor is connected to the protection control terminal; the first terminal of the first resistor is electrically coupled to the constant potential signal, and the second terminal of the first resistor is electrically coupled to the first switch
  • the input terminal of the trigger circuit is the control terminal, and the output terminal of the trigger circuit is connected to the control terminal of the first switch;
  • the output terminal transmits a switch signal corresponding to the potential change of the control signal to turn on or turn off the first switch; the first switch is turned off, and at the same time disconnects between the read-write control signal and the protection control terminal Is electrically coupled, the protection control terminal is electrically coupled to the constant potential signal, the first switch is opened, and the protection control terminal is electrically coupled to the read-write control signal.
  • the trigger circuit includes a trigger and a second switch; the first end of the trigger is the control end, and the second end of the trigger is electrically coupled to the constant A potential signal; and, the first end of the second switch is connected to the output end of the trigger, and the second end of the second switch is connected to the control end of the first switch; wherein, the first switch and The control terminal of the second switch has the same polarity, and the trigger outputs the constant potential signal to the first terminal of the second switch according to the potential change of the control signal, and the control of the second switch The terminal is electrically coupled to the constant potential signal, the second switch is opened, and the constant potential signal is transmitted to the control end of the first switch.
  • control signal is a clock pulse signal
  • the flip-flop when the clock pulse signal is a rising edge, the flip-flop outputs the constant potential signal.
  • the unidirectional conduction component is disposed between the first switch and the second switch, and the input end of the unidirectional conduction component is connected to the second end of the second switch.
  • the output terminal of the one-way conducting component is connected to the control terminal of the first switch.
  • a second resistor is connected between the second switch and the unidirectional conduction component, and a first end of the second resistor is connected between the second switch and the unidirectional conduction component , The second end of the second resistor is grounded.
  • the unidirectional conducting component is a diode.
  • the memory, the timing controller, the first resistor, and the second switch are disposed on a driving board of the display device.
  • the trigger circuit is disposed in a frame area or a wiring area of the display panel.
  • the protection control terminal is electrically coupled to the read-write control signal, and the memory switches read / write of the timing control data according to the potential change of the read-write control signal Or write-proof.
  • the constant potential signal is a constant high potential signal.
  • the constant potential signal is a constant low potential signal.
  • Another object of the present application is a data protection method for a display device, including: providing a control signal through a timing controller; and selectively switching a constant potential signal and a read-write control signal according to the potential change of the control signal through a switcher Output to a memory; and, when the memory is electrically coupled to the constant potential signal, write-protection of timing control data is maintained.
  • the memory when the memory acquires the read-write control signal, the memory switches the read-write or write-protection of the timing control data according to the potential change of the read-write control signal .
  • the switcher includes a first switch and a trigger circuit; the switcher selectively outputs a constant potential signal and a read-write control signal according to the potential change of the control signal
  • the step of storing to the memory includes: controlling the opening and closing of the first switch through a switch signal output by the trigger circuit, wherein the potential change of the switch signal corresponds to the potential change of the control signal; when the first When the switch is on, the memory is electrically coupled to the read-write control signal through the first switch; when the first switch is off, the first switch turns off the memory and the read-write The control signal is electrically coupled, and the memory is electrically coupled to the constant potential signal.
  • Another object of the present application is a data protection system for a display device, including: a memory having a protection control terminal and storing timing control data; a timing controller connected to the memory, the timing controller obtaining the timing control data To provide a clock signal; a first switch, the first end of the first switch is electrically coupled to the read-write control signal, the second end of the first switch is connected to the protection control end; the first resistor, the The first end of the first resistor is electrically coupled to a constant high potential signal, and the second end of the first resistor is connected between the second end of the first switch and the protection control end; a trigger, the trigger The first end of the device is electrically coupled to the control signal, the second end of the trigger is electrically coupled to the constant high potential signal; the second switch, the first end of the second switch is electrically coupled to the trigger The output end of the second switch, the control end of the second switch is electrically coupled to a constant high potential signal, the second switch is open; a diode, the input end of the diode
  • the first switch is turned on, the protection control terminal is electrically coupled to the read-write control signal, and the memory switches read-write or write-protection of the timing control data according to the potential change of the read-write control signal ;
  • the clock pulse signal is a falling edge, low potential, or no signal
  • the trigger has no output, and the first switch is closed to disconnect the electrical connection between the protection control terminal and the read-write control signal
  • the memory is electrically coupled to the constant potential signal, the write-protection of the timing control data is maintained.
  • This application controls the data anti-write or read-write mechanism of the storage element through the connection and disconnection of the electrical coupling between the storage element and the read-write control signal. In this way, the memory write-protect state is prevented from being set by mistake, causing the timing control data to be rewritten, and the screen abnormality of the display device is more avoided.
  • FIG. 1 is a schematic structural diagram of an exemplary display device
  • FIG. 2 is a schematic structural diagram of a data protection system of a display device according to an embodiment of the application
  • FIG. 3 is a schematic structural diagram of a data protection system of a display device according to an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of a data protection system of a display device according to an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a data protection system of a display device according to an embodiment of the application.
  • FIG. 6 is a schematic diagram of a data protection process of a display device according to an embodiment of the application.
  • FIG. 1 is a schematic structural diagram of an exemplary display device.
  • a display device includes: a control board 100 including a timing device 101 (Timing Controller, TCON) 101; a printed circuit board 103 and a flexible flat cable (Flexible Flat Cable) between the control board and the control board FFC) 102 is connected; the source driving circuit 104 and the gate driving circuit 105 are connected to the data line and the scanning line in the display panel 106, respectively.
  • the gate driving circuit 105 and the source driving circuit 104 include, but are not limited to, flip-chip films.
  • the gate driver 105 includes but is not limited to a gate array drive (Gate On Array, GOA) form, and the gate drive circuit 105 may be divided into a level shifter and a shift register ( shift register), the booster is set on the control board, and the shift register is set on the active array substrate.
  • GOA Gate On Array
  • the driving method of the display device includes: the system motherboard provides color (for example: R / G / B) compressed signals, control signals, and power transmission to the control board 100. After processing these signals, the timing device 101 on the control board 100, together with the power processed by the drive circuit, is transmitted to the gate driver 105 of the printed circuit board 103 through a flexible flat cable (Flexible Flat Cable, FFC) 102 The source driver 104, the gate driver 105, and the source driver 104 transmit the necessary data and power to the display panel 106, so that the display device obtains the power and signals required to display the picture.
  • FFC Flexible Flat Cable
  • the opening of the panel is to open each data line by line-by-line scanning (Line By Line).
  • the specific implementation method is that the gate driver 105 receives the timing signal (row signal) provided by the timing device, and generates a digital signal every time the rising edge of a clock passes. Each digital signal corresponds to an output. Through digital-to-analog conversion, the high and low levels are converted to the high and low voltages required by the active switch to form a gate drive signal, so that the panel is opened line by line, and then charged through the pixel electrode.
  • a data protection system includes: a memory 210 having a protection control terminal 211 and storing timing control data 212; a timing controller 220 connected to the memory 210, The timing controller 220 obtains the timing control data 212 to provide the control signal S1; and, the switch 300 includes a first input terminal 301, a second input terminal 302, a control terminal 303, and an output terminal 304, the first The input terminal 301 is electrically coupled to the read-write control signal S2, the second input terminal 302 is electrically coupled to the constant potential signal S3, the output terminal is connected to the protection control terminal 211, and the control terminal transmits the control signal S1, the switch 300 selectively outputs the constant potential signal S3 and the read-write control signal S2 to the protection control terminal 211 according to the potential change of the control signal S1; wherein, the switch 300 transmits the constant potential signal S3 to
  • the switch 300 includes a first resistor 311, a first switch M1 and a trigger circuit 330; the first end of the first switch M1 is equivalent to the The first input terminal 301 is electrically coupled to the read-write control signal S2, the second terminal of the first switch M1 is equivalent to the output terminal 304, and is connected to the protection control terminal 211; the first The first terminal of a resistor 311 is equivalent to the second input terminal 302, which is electrically coupled to the constant potential signal S3, and the second terminal of the first resistor 311 is electrically coupled to the first switch M1 And the protection control terminal 211; and, the input terminal of the trigger circuit 330 is the control terminal 303, and the output terminal of the trigger circuit 330 is connected to the control terminal M13 of the first switch M1 ; Among them, the output end of the trigger circuit 330 is to transmit a switch signal S4
  • the trigger circuit 330 includes a flip-flop 331 and a second switch M2; the first terminal C of the flip-flop 331 is the control terminal 303, and the trigger The second terminal D of the device 331 is electrically coupled to the constant potential signal S3; and, the first terminal of the second switch M2 is connected to the output terminal Q of the flip-flop 331, and the second terminal of the second switch M2 Is connected to the control terminal M13 of the first switch M1; wherein, the control terminals (M13, M23) of the first switch M1 and the second switch M2 are of the same polarity, and the flip-flop 331 is based on the control The potential of the signal S1 changes to output the constant potential signal S3 to the first terminal of the second switch M2, the control terminal M23 of the second switch M2 is electrically coupled to the constant potential signal S3, the second The switch M2
  • the control signal S1 is a clock pulse signal.
  • the flip-flop 331 transmits the signal obtained from the second terminal D to the output terminal Q. Therefore, the flip-flop 331 outputs the constant potential signal S3.
  • the unidirectional conduction component 332 is disposed between the first switch M1 and the second switch M2, and the input end of the unidirectional conduction component 332 is connected to the In the second end of the second switch M2, the output end of the unidirectional conducting component 332 is connected to the control end of the first switch M1.
  • a second resistor 312 is connected to the second switch M2 and the unidirectional conducting component 332, and a first end of the second resistor 312 is connected to the second switch M2 and the single Between the conducting components 332, the second end of the second resistor 312 is connected to the ground GND.
  • the unidirectional conducting component 332 is a diode.
  • the memory 210, the timing controller 220, the first resistor 311, and the second switch M2 are disposed on a driving board of the display device (such as the aforementioned printed circuit board 103 )on.
  • the trigger circuit 330 is disposed in the frame area or the wiring area of the display panel 106.
  • the protection control terminal 211 is electrically coupled to the read-write control signal S2, and the memory 210 switches the timing control data according to the potential change of the read-write control signal S2 212 can be read, written, or write-protected.
  • the constant potential signal S3 is a constant high potential signal.
  • the constant potential signal S3 is a constant low potential signal.
  • conditional potential of the memory 210 for reading and writing or anti-writing, the potential of the read and write control signal S2, and the ground potential are adjusted correspondingly according to the potential of the constant potential signal S3.
  • the data protection method of the display device includes:
  • step S610 the timing controller 220 provides the control signal S1.
  • step S620 the switch 300 selectively outputs the constant potential signal S3 and the read-write control signal S2 to the memory 210 according to the potential change of the control signal S1.
  • Step S630 when the memory 210 is electrically coupled to the constant potential signal S3, write-protection of the timing control data 212 is maintained.
  • the memory 210 when the memory 210 obtains the read-write control signal S2, the memory 210 switches the timing control data 212 according to the potential change of the read-write control signal S2. Read-write or write-proof.
  • the switch 300 includes a first switch M1 and a trigger circuit 330; the switch 300 selectively selects the constant potential signal S3 and the read signal according to the potential change of the control signal S1.
  • the step of outputting the write control signal S2 to the memory 210 includes: controlling the opening and closing of the first switch M1 through the switch signal S4 output by the trigger circuit 330, wherein the potential change of the switch signal S4 corresponds to the control The potential of the signal S1 changes; when the first switch M1 is on, the memory 210 is electrically coupled to the read-write control signal S2 through the first switch M1; when the first switch M1 is off The first switch M1 disconnects the electrical coupling between the memory 210 and the read / write control signal S2, and the memory 210 is electrically coupled to the constant potential signal S3.
  • a data protection system for a display device includes: a memory 210 having a protection control terminal 211 and storing timing control data 212; a timing controller 220 connected to the memory 210, the timing The controller 220 obtains the timing control data 212 to provide a clock signal; a first switch M1, the first end of the first switch M1 is electrically coupled to the read-write control signal S2, and the second of the first switch M1 Is connected to the protection control terminal 211; a first resistor 311, the first terminal of the first resistor 311 is electrically coupled to a constant high potential signal, and the second terminal of the first resistor 311 is connected to the first switch M1 Between the second end of the switch and the protection control end 211; the flip-flop 331, the first end C of the flip-flop 331 is electrically coupled to the control signal S1, and the second end D of the flip-flop 331 is electrically coupled Constant high potential signal; the second switch M2, the first terminal of the second switch M2 is electrically coupled to
  • This application controls the data anti-write or read-write mechanism of the storage element through the connection and disconnection of the electrical coupling between the storage element and the read-write control signal. In this way, the memory write-protect state is prevented from being set by mistake, causing the timing control data to be rewritten, and the screen abnormality of the display device is more avoided.
  • This application does not need to significantly change the existing production process, and is suitable for the production process of various types of existing display devices.
  • the application can be set to many types of display panels, and the applicability is relatively high.
  • the display panel of the present application includes a first substrate and a second substrate.
  • the first substrate and the second substrate may be, for example, active array switch (Thin Film Transistor, TFT) substrates and color filter (CF) substrates.
  • active array switch Thin Film Transistor, TFT
  • CF color filter
  • the active array switch and the color filter layer of the present application may also be formed on the same substrate.
  • the display panel of the present application may be, for example, a liquid crystal display panel, but it is not limited thereto, it may also be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, a curved type Display panel or other types of display panels.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示装置的数据保护系统及保护方法，所述系统包括存储单元（210）、时序控制单元（220）、以及切换模块（300）。所述切换模块（300）根据控制信号（S1）的电位变化，选择性的将恒定电位信号（S3）和读写控制信号（S2）输出至所述存储单元（210）。所述切换模块（300）传输所述恒定电位信号（S3）输出至所述存储单元（210）时，会断开所述读写控制信号（S2）与保护控制端（211）之间的电性耦接。所述存储单元（210）依据取得的信号以保持对时序控制数据（212）的防写，或在可读写或防写之间进行切换。

Description

显示装置的数据保护系统及保护方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示装置的数据保护系统及保护方法。
背景技术
显示器中，系统主板通过线路连接至控制板(Control Board，C-Board)，控制板通过如柔性扁平电缆(Flexible Flat Cable，FFC)连接印制电路板(PCB)，印制电路板再通过源极覆晶薄膜(Source-Chip on Film，S-COF)和栅极覆晶薄膜(Gate-Chip on Film，G-COF)与显示区连接。显示器驱动方式包括：系统主板将颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板。信号经过时序器(Timing Controller，TCON)处理后，传输至源极驱动电路(Source Driver)及栅极驱动电路(Gate Driver)。通过相关的集成电路或芯片将必要性的数据与电源传输于显示区，从而使得显示器获得呈现画面需求的电源、信号。
在显示器的驱动板上，设置有可编程可擦除型存储器(EEPROM)，设置为存储时序器的控制数据与设定(TCON Code)。但时序器在读取数据时，经常容易发生EEPROM中存储的数据被改写的事情。在显示装置开机、系统导入或相关作业期间，时序器会读取EEPROM里面存储的控制数据，完成时序器的初始化设定。EEPROM的写保护信号(Write Protect，WP)，常态下为高电位(H)，即正常状态下都要处于写保护状态。然而，由于线材或其他干扰，可能会导致写保护信号也会被失效，那么就有可能会出现误动作而导致EEPROM里面存储的控制数据被改写，进而会造成显示画面异常，错误频出。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种显示装置的数据保护系统及保护方法，通过存储元件与读写控制信号之间的电性耦接的连通与断开，控制存储元件的数据防写或读写机制。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。
依据本申请提出的一种显示装置的数据保护系统，包括：存储器，具有保护控制端及存储有时序控制数据；时序控制器，连接所述存储器，所述时序控制器取得所述时序控制数据以提供控制信号；以及，切换器，包含第一输入端、第二输入端、控制端和输出端，所述第一输入端电性耦接读写控制信号，所述第二输入端电性耦接恒定电位信号，所述输出端连接所述保护控制端，所述控制端传输所述控制信号，所述切换器根据所述控制信号的电位变化，选择性的将所述恒定电位信号和所述读写控制信号输出至所述保护控制端；其中，所述切换 器传输所述恒定电位信号输出至所述保护控制端时，所述切换器断开所述读写控制信号与所述保护控制端之间的电性耦接，所述保护控制端电性耦接所述恒定电位信号，所述存储器保持对所述时序控制数据的防写。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，所述切换器包括第一电阻、第一开关与触发电路；所述第一开关的第一端电性耦接所述读写控制信号，所述第一开关的第二端连接所述保护控制端；所述第一电阻的第一端电性耦接所述恒定电位信号，所述第一电阻的第二端电性耦接所述第一开关的第二端与所述保护控制端之间；以及，所述触发电路的输入端为所述控制端，所述触发电路的输出端连接所述第一开关的控制端；其中，所述触发电路的输出端是传输对应所述控制信号的电位变化的开关信号，以开启或关闭所述第一开关；所述第一开关关闭，同时断开所述读写控制信号与所述保护控制端之间的电性耦接，所述保护控制端电性耦接所述恒定电位信号，所述第一开关打开，所述保护控制端电性耦接所述读写控制信号。
在本申请的一实施例中，所述触发电路包括触发器与第二开关；所述触发器的第一端为所述控制端，所述触发器的第二端电性耦接所述恒定电位信号；以及，所述第二开关的第一端连接所述触发器的输出端，所述第二开关的第二端连接所述第一开关的控制端；其中，所述第一开关与所述第二开关的控制端为相同极性，所述触发器依据所述控制信号的电位变化以输出所述恒定电位信号至所述第二开关的第一端，所述第二开关的控制端电性耦接所述恒定电位信号，所述第二开关打开，所述恒定电位信号被传输至所述第一开关的控制端。
在本申请的一实施例中，所述控制信号是时钟脉冲信号，所述时钟脉冲信号为上升沿时，所述触发器输出所述恒定电位信号。
在本申请的一实施例中，单向导通组件设置于所述第一开关与所述第二开关之间，所述单向导通组件的输入端连接所述第二开关的第二端，所述单向导通组件的输出端连接所述第一开关的控制端。
在本申请的一实施例中，第二电阻连接所述第二开关与所述单向导通组件，所述第二电阻的第一端连接所述第二开关与所述单向导通组件之间，所述第二电阻的第二端接地。
在本申请的一实施例中，所述单向导通组件为二极管。
在本申请的一实施例中，所述存储器、所述时序控制器、所述第一电阻与第二开关设置于所述显示装置的驱动板上。
在本申请的一实施例中，所述触发电路设置于显示面板的边框区或配线区。
在本申请的一实施例中，所述保护控制端电性耦接所述读写控制信号，所述存储器依据所述读写控制信号的电位变化，切换对所述时序控制数据的可读写或防写。
在本申请的一实施例中，所述恒定电位信号是恒定高电位信号。
在本申请的一实施例中，所述恒定电位信号是恒定低电位信号。
本申请的另一目的一种显示装置的数据保护方法，包括：通过时序控制器提供控制信号；通过切换器器根据所述控制信号的电位变化，选择性的将恒定电位信号和读写控制信号输出至存储器；以及，当所述存储器电性耦接所述恒定电位信号时，保持对时序控制数据的防写。
在本申请的一实施例中，当所述存储器取得所述读写控制信号时，所述存储器依据所述读写控制信号的电位变化，切换对所述时序控制数据的可读写或防写。
在本申请的一实施例中，所述切换器器包括第一开关与触发电路；所述通过切换器器根据所述控制信号的电位变化，选择性的将恒定电位信号和读写控制信号输出至存储器的步骤包括：通过所述触发电路输出的开关信号，控制所述第一开关的开启与关闭，其中，所述开关信号的电位变化对应所述控制信号的电位变化；当所述第一开关为开启时，所述存储器通过所述第一开关电性耦接所述读写控制信号；当所述第一开关为关闭时，所述第一开关断开所述存储器与所述读写控制信号的电性耦接，所述存储器电性耦接所述恒定电位信号。
本申请的又一目的一种显示装置的数据保护系统，包括：存储器，具有保护控制端及存储有时序控制数据；时序控制器，连接所述存储器，所述时序控制器取得所述时序控制数据以提供时钟脉冲信号；第一开关，所述第一开关的第一端电性耦接读写控制信号，所述第一开关的第二端连接所述保护控制端；第一电阻，所述第一电阻的第一端电性耦接恒定高电位信号，所述第一电阻的第二端连接所述第一开关的第二端与所述保护控制端之间；触发器，所述触发器的第一端电性耦接控制信号，所述触发器的第二端电性耦接恒定高电位信号；第二开关，所述第二开关的第一端电性耦接所述触发器的输出端，所述第二开关的控制端电性耦接恒定高电位信号，所述第二开关为打开；二极管，所述二极管的输入端连接所述第二开关的第二端，所述二极管的输出端连接所述第一开关的控制端；以及，第二电阻，所述第二电阻的第一端连接所述第二开关与单向导通组件之间，所述第二电阻的第二端接地；其中，所述时钟脉冲信号为上升沿时，所述触发器输出所述恒定高电位信号，所述恒定高电位信号通过所述第二开关与二极管传输至所述第一开关的控制端，所述第一开关打开，所述保护控制端电性耦接所述读写控制信号，所述存储器依据所述读写控制信号的电位变化，切换对所述时序控制数据的可读写或防写；所述时钟脉冲信号为下降沿、低电位或无信号时，所述触发器无输出，所述第一开关关闭以断开所述保护控制端与所述读写控制信号的电性耦接，所述存储器电性耦接所述恒定电位信号时，保持对时序控制数据的防写。
本申请通过存储元件与读写控制信号之间的电性耦接的连通与断开，控制存储元件的数据防写或读写机制。从而避免存储器防写状态被误设置，造成时序控制数据被改写，较能避免显示装置发生画面异常情况。
附图说明
图1为范例性的显示装置的架构示意图；
图2为本申请一实施例的显示装置的数据保护系统结构示意图；
图3为本申请一实施例的显示装置的数据保护系统结构示意图；
图4为本申请一实施例的显示装置的数据保护系统结构示意图；
图5为本申请一实施例的显示装置的数据保护系统结构示意图；
图6为本申请一实施例的显示装置的数据保护流程示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的器是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度，亦夸大电路的配置范围。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度，亦夸大电路的配置范围。将理解的是，当例如层、膜、区域、电路或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定申请目的所采取的技术手段及功效，以下结合附图及可选的实施例，对依据本申请提出的一种显示面板及其应用的显示装置，其具体实施方式、结构、特征及其功效，详细说明如后。
图1为范例性的显示装置的架构示意图。一种显示装置，包括：控制板100，所述控制板100包括时序器101(Timing Controller，TCON)101；印制电路板103，与所述控制板之间通过柔性扁平电缆(Flexible Flat Cable，FFC)102相连接；源极驱动电路104与栅极 驱动电路105分别与显示面板106内的数据线及扫描线连接。在一些实施例中，栅极驱动电路105及源极驱动电路104包括但不限制为覆晶薄膜形式。在一些实施例中，栅极驱动器105包括但不限于栅极阵列驱动(Gate On Array，GOA)形式，栅极驱动电路105可被分为升压器(level shifter)及移位寄位器(shift register)，升压器设置在控制板上，移位寄存器则是设置在主动阵列基板上。
显示装置的驱动方式包括：系统主板提供颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板100。控制板100上的时序器101于处理此等信号后，连同被驱动电路处理的电源，通过柔性扁平电缆(Flexible Flat Cable，FFC)102，一并传输至印制电路板103的栅极驱动器105及源极驱动器104，栅极驱动器105及源极驱动器104将必要性的数据与电源传输于显示面板106，从而使得显示装置获得呈现画面需求的电源、信号。
面板的打开是以逐线扫描(Line By Line)的方式把每一条数据线打开。具体实现方式为，栅极驱动器105接受时序器提供的时序信号(行信号)，每经过一个时钟的上升沿就产生出一个数字信号。而每一个数字信号对应一个输出。通过数模转换，将高低电平转换为主动开关需要的高低电压以形成栅极驱动信号，使面板逐行打开，再通过像素电极进行充电。
图2为本申请一实施例的显示装置的数据保护系统结构示意图。如图2绘示，在本申请的一实施例中，一种数据保护系统，包括：存储器210，具有保护控制端211及存储有时序控制数据212；时序控制器220，连接所述存储器210，所述时序控制器220取得所述时序控制数据212以提供控制信号S1；以及，切换器300，包含第一输入端301、第二输入端302、控制端303和输出端304，所述第一输入端301电性耦接读写控制信号S2，所述第二输入端302电性耦接恒定电位信号S3，所述输出端连接所述保护控制端211，所述控制端传输所述控制信号S1，所述切换器300根据所述控制信号S1的电位变化，选择性的将所述恒定电位信号S3和所述读写控制信号S2输出至所述保护控制端211；其中，所述切换器300传输所述恒定电位信号S3输出至所述保护控制端211时，所述切换器300断开所述读写控制信号S2与所述保护控制端211之间的电性耦接，所述保护控制端211电性耦接所述恒定电位信号S3，所述存储器210保持对所述时序控制数据212的防写。
图3为本申请一实施例的显示装置的数据保护系统结构示意图。如图3绘示，在本申请的一实施例中，所述切换器300包括第一电阻311、第一开关M1与触发电路330；所述第一开关M1的第一端等效于所述第一输入端301，其电性耦接所述读写控制信号S2，所述第一开关M1的第二端等效于所述输出端304，其连接所述保护控制端211；所述第一电阻311的第一端等效于所述第二输入端302，其电性耦接所述恒定电位信号S3，所述第一电阻311的第二端电性耦接所述第一开关M1的第二端与所述保护控制端211之间；以及，所述触发电 路330的输入端为所述控制端303，所述触发电路330的输出端连接所述第一开关M1的控制端M13；其中，所述触发电路330的输出端是传输对应所述控制信号S1的电位变化的开关信号S4，以开启或关闭所述第一开关M1；所述第一开关M1打开，所述保护控制端211电性耦接所述读写控制信号S2；所述第一开关M1关闭，同时断开所述读写控制信号S2与所述保护控制端211之间的电性耦接，所述保护控制端211电性耦接所述恒定电位信号S3。
图4为本申请一实施例的显示装置的数据保护系统结构示意图。如图4绘示，在本申请的一实施例中，所述触发电路330包括触发器331与第二开关M2；所述触发器331的第一端C为所述控制端303，所述触发器331的第二端D电性耦接所述恒定电位信号S3；以及，所述第二开关M2的第一端连接所述触发器331的输出端Q，所述第二开关M2的第二端连接所述第一开关M1的控制端M13；其中，所述第一开关M1与所述第二开关M2的控制端(M13,M23)为相同极性，所述触发器331依据所述控制信号S1的电位变化以输出所述恒定电位信号S3至所述第二开关M2的第一端，所述第二开关M2的控制端M23电性耦接所述恒定电位信号S3，所述第二开关M2打开，所述触发器331输出的所述恒定电位信号S3(由输出端Q所输出)被传输至所述第一开关M1的控制端M13。
在本申请的一实施例中，所述控制信号S1是时钟脉冲信号，所述时钟脉冲信号为上升沿时，所述触发器331会将由第二端D所取得的信号传递至输出端Q，故所述触发器331输出所述恒定电位信号S3。
图5为本申请一实施例的显示装置的数据保护系统结构示意图。如图5绘示，在本申请的一实施例中，单向导通组件332设置于所述第一开关M1与所述第二开关M2之间，所述单向导通组件332的输入端连接所述第二开关M2的第二端，所述单向导通组件332的输出端连接所述第一开关M1的控制端。
在本申请的一实施例中，第二电阻312连接所述第二开关M2与所述单向导通组件332，所述第二电阻312的第一端连接所述第二开关M2与所述单向导通组件332之间，所述第二电阻312的第二端连接接地GND。
在本申请的一实施例中，所述单向导通组件332为二极管。
在本申请的一实施例中，所述存储器210、所述时序控制器220、所述第一电阻311与第二开关M2设置于所述显示装置的驱动板(如前述的印制电路板103)上。
在本申请的一实施例中，所述触发电路330设置于显示面板106的边框区或配线区。
在本申请的一实施例中，所述保护控制端211电性耦接所述读写控制信号S2，所述存储器210依据所述读写控制信号S2的电位变化，切换对所述时序控制数据212的可读写或防写。
在本申请的一实施例中，所述恒定电位信号S3是恒定高电位信号。
在本申请的一实施例中，所述恒定电位信号S3是恒定低电位信号。
在本申请的一实施例中，所述存储器210进行读写或防写的条件电位、读写控制信号S2的电位、所述接地电位，依据所述恒定电位信号S3的电位而对应调整。
图6为本申请一实施例的显示装置的数据保护流程示意图。请同时配合图1至图5以利于理解。在本申请的一实施例中，显示装置的数据保护方法包括：
步骤S610，通过时序控制器220提供控制信号S1。
步骤S620，通过切换器300根据所述控制信号S1的电位变化，选择性的将恒定电位信号S3和读写控制信号S2输出至存储器210。
步骤S630，当所述存储器210电性耦接所述恒定电位信号S3时，保持对时序控制数据212的防写。
在本申请的一实施例中，当所述存储器210取得所述读写控制信号S2时，所述存储器210依据所述读写控制信号S2的电位变化，切换对所述时序控制数据212的可读写或防写。
在本申请的一实施例中，所述切换器300包括第一开关M1与触发电路330；所述通过切换器300根据所述控制信号S1的电位变化，选择性的将恒定电位信号S3和读写控制信号S2输出至存储器210的步骤包括：通过所述触发电路330输出的开关信号S4，控制所述第一开关M1的开启与关闭，其中，所述开关信号S4的电位变化对应所述控制信号S1的电位变化；当所述第一开关M1为开启时，所述存储器210通过所述第一开关M1电性耦接所述读写控制信号S2；当所述第一开关M1为关闭时，所述第一开关M1断开所述存储器210与所述读写控制信号S2的电性耦接，所述存储器210电性耦接所述恒定电位信号S3。
在本申请的一实施例中，一种显示装置的数据保护系统，包括：存储器210，具有保护控制端211及存储有时序控制数据212；时序控制器220，连接所述存储器210，所述时序控制器220取得所述时序控制数据212以提供时钟脉冲信号；第一开关M1，所述第一开关M1的第一端电性耦接读写控制信号S2，所述第一开关M1的第二端连接所述保护控制端211；第一电阻311，所述第一电阻311的第一端电性耦接恒定高电位信号，所述第一电阻311的第二端连接所述第一开关M1的第二端与所述保护控制端211之间；触发器331，所述触发器331的第一端C电性耦接控制信号S1，所述触发器331的第二端D电性耦接恒定高电位信号；第二开关M2，所述第二开关M2的第一端电性耦接所述触发器331的输出端Q，所述第二开关M2的控制端M23电性耦接恒定高电位信号，所述第二开关M2为打开；二极管，所述二极管的输入端连接所述第二开关M2的第二端，所述二极管的输出端连接所述第一开关M1的控制端M13；以及，第二电阻312，所述第二电阻312的第一端连接所述第二开关M2与单向导 通组件332之间，所述第二电阻312的第二端接地；其中，所述时钟脉冲信号为上升沿时，所述触发器331输出所述恒定高电位信号，所述恒定高电位信号通过所述第二开关M2与二极管传输至所述第一开关M1的控制端，所述第一开关M1打开，所述保护控制端211电性耦接所述读写控制信号S2，所述存储器210依据所述读写控制信号S2的电位变化，切换对所述时序控制数据212的可读写或防写；所述时钟脉冲信号为下降沿、低电位或无信号时，所述触发器331无输出，所述第一开关M1关闭以断开所述保护控制端211与所述读写控制信号S2的电性耦接，所述存储器210电性耦接所述恒定电位信号S3时，保持对时序控制数据212的防写。
本申请通过存储元件与读写控制信号之间的电性耦接的连通与断开，控制存储元件的数据防写或读写机制。从而避免存储器防写状态被误设置，造成时序控制数据被改写，较能避免显示装置发生画面异常情况。本申请不需大幅改变现有生产流程，适设置为现有各类显示装置的制程。本申请可以设置为许多类型的显示面板，适用性相对较高。
本申请的显示面板包括第一基板及第二基板，第一基板及第二基板可例如为主动阵列开关(Thin Film Transistor，TFT)基板、彩色滤光层(Color Filter，CF)基板。然不限于此，在一些实施例中，本申请的主动阵列开关及彩色滤光层亦可形成于同一基板上。
在一些实施例中，本申请的所述显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED显示面板，W-OLED显示面板，QLED显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。此用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的可选的实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以可选的实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (17)

  1. 一种显示装置的数据保护系统，包括：
    存储器，具有保护控制端及存储有时序控制数据；
    时序控制器，连接所述存储器，所述时序控制器取得所述时序控制数据以提供控制信号；以及
    切换器，包含第一输入端、第二输入端、控制端和输出端，所述第一输入端电性耦接读写控制信号，所述第二输入端电性耦接恒定电位信号，所述输出端连接所述保护控制端，所述控制端传输所述控制信号，所述切换器根据所述控制信号的电位变化，选择性的将所述恒定电位信号和所述读写控制信号输出至所述保护控制端；
    其中，所述切换器传输所述恒定电位信号输出至所述保护控制端时，所述切换器断开所述读写控制信号与所述保护控制端之间的电性耦接，所述保护控制端电性耦接所述恒定电位信号，所述存储器保持对所述时序控制数据的防写。
  2. 如权利要求1所述的显示装置的数据保护系统，
    所述切换器包括第一电阻、第一开关与触发电路；
    所述第一开关的第一端电性耦接所述读写控制信号，所述第一开关的第二端连接所述保护控制端；
    所述第一电阻的第一端电性耦接所述恒定电位信号，所述第一电阻的第二端电性耦接所述第一开关的第二端与所述保护控制端之间；以及
    所述触发电路的输入端为所述控制端，所述触发电路的输出端连接所述第一开关的控制端；其中，所述触发电路的输出端是传输对应所述控制信号的电位变化的开关信号，以开启或关闭所述第一开关；所述第一开关关闭，同时断开所述读写控制信号与所述保护控制端之间的电性耦接，所述保护控制端电性耦接所述恒定电位信号，所述第一开关打开，所述保护控制端电性耦接所述读写控制信号。
  3. 如权利要求2所述的显示装置的数据保护系统，
    所述触发电路包括触发器与第二开关；
    所述触发器的第一端为所述控制端，所述触发器的第二端电性耦接所述恒定电位信号；以及所述第二开关的第一端连接所述触发器的输出端，所述第二开关的第二端连接所述第一开关的控制端；
    其中，所述第一开关与所述第二开关的控制端为相同极性，所述触发器依据所述控制信号的电位变化以输出所述恒定电位信号至所述第二开关的第一端，所述第二开关的控制端电性耦接所述恒定电位信号，所述第二开关打开，所述恒定电位信号被传输至所述第一开关的控制 端。
  4. 如权利要求3所述的显示装置的数据保护系统，所述控制信号是时钟脉冲信号，所述时钟脉冲信号为上升沿时，所述触发器输出所述恒定电位信号。
  5. 如权利要求3所述的显示装置的数据保护系统，单向导通组件设置于所述第一开关与所述第二开关之间，所述单向导通组件的输入端连接所述第二开关的第二端，所述单向导通组件的输出端连接所述第一开关的控制端；第二电阻连接所述第二开关与所述单向导通组件，所述第二电阻的第一端连接所述第二开关与所述单向导通组件之间，所述第二电阻的第二端接地。
  6. 如权利要求3所述的显示装置的数据保护系统，所述存储器、所述时序控制器、所述第一电阻与第二开关设置于所述显示装置的驱动板上；所述触发电路设置于显示面板的边框区或配线区。
  7. 如权利要求1所述的显示装置的数据保护系统，所述恒定电位信号是恒定高电位信号；或者，所述恒定电位信号是恒定低电位信号。
  8. 一种显示装置的数据保护方法，包括：
    通过时序控制器提供控制信号；
    通过切换器根据所述控制信号的电位变化，选择性的将恒定电位信号和读写控制信号输出至存储器；以及
    当所述存储器电性耦接所述恒定电位信号时，保持对时序控制数据的防写。
  9. 如权利要求8所述的显示装置的数据保护方法，所述切换器包括第一开关与触发电路；所述通过切换器根据所述控制信号的电位变化，选择性的将恒定电位信号和读写控制信号输出至存储器的步骤包括：
    通过所述触发电路输出的开关信号，控制所述第一开关的开启与关闭，其中，所述开关信号的电位变化对应所述控制信号的电位变化；
    当所述第一开关为开启时，所述存储器通过所述第一开关电性耦接所述读写控制信号；
    当所述第一开关为关闭时，所述第一开关断开所述存储器与所述读写控制信号的电性耦接，所述存储器电性耦接所述恒定电位信号。
  10. 如权利要求9所述的显示装置的数据保护方法，所述触发电路包括触发器与第二开关，所述触发器的第一端为所述控制端，所述触发器的第二端电性耦接所述恒定电位信号。
  11. 如权利要求10所述的显示装置的数据保护方法，所述第二开关的第一端连接所述触发器的输出端，所述第二开关的第二端连接所述第一开关的控制端。
  12. 如权利要求10所述的显示装置的数据保护方法，所述第一开关与所述第二开关的控制端 为相同极性，所述触发器依据所述控制信号的电位变化以输出所述恒定电位信号至所述第二开关的第一端，所述第二开关的控制端电性耦接所述恒定电位信号，所述第二开关打开，所述恒定电位信号被传输至所述第一开关的控制端。
  13. 如权利要求12所述的显示装置的数据保护方法，所述控制信号是时钟脉冲信号，所述时钟脉冲信号为上升沿时，所述触发器输出所述恒定电位信号。
  14. 如权利要求12所述的显示装置的数据保护方法，所述恒定电位信号是恒定高电位信号；或者，所述恒定电位信号是恒定低电位信号。
  15. 一种显示装置的数据保护系统，包括：
    存储器，具有保护控制端及存储有时序控制数据；
    时序控制器，连接所述存储器，所述时序控制器取得所述时序控制数据以提供时钟脉冲信号；第一开关，所述第一开关的第一端电性耦接读写控制信号，所述第一开关的第二端连接所述保护控制端；
    第一电阻，所述第一电阻的第一端电性耦接恒定高电位信号，所述第一电阻的第二端连接所述第一开关的第二端与所述保护控制端之间；
    触发器，所述触发器的第一端电性耦接控制信号，所述触发器的第二端电性耦接恒定高电位信号；
    第二开关，所述第二开关的第一端电性耦接所述触发器的输出端，所述第二开关的控制端电性耦接恒定高电位信号，所述第二开关为打开；
    二极管，所述二极管的输入端连接所述第二开关的第二端，所述二极管的输出端连接所述第一开关的控制端；以及
    第二电阻，所述第二电阻的第一端连接所述第二开关与单向导通组件之间，所述第二电阻的第二端接地；
    其中，所述时钟脉冲信号为上升沿时，所述触发器输出所述恒定高电位信号，所述恒定高电位信号通过所述第二开关与二极管传输至所述第一开关的控制端，所述第一开关打开，所述保护控制端电性耦接所述读写控制信号，所述存储器依据所述读写控制信号的电位变化，切换对所述时序控制数据的可读写或防写；
    所述时钟脉冲信号为下降沿、低电位或无信号时，所述触发器无输出，所述第一开关关闭以断开所述保护控制端与所述读写控制信号的电性耦接，所述存储器电性耦接恒定电位信号时，保持对时序控制数据的防写。
  16. 如权利要求15所述的显示装置的数据保护系统，所述第一开关与所述第二开关的控制端为相同极性，所述触发器依据所述控制信号的电位变化以输出所述恒定电位信号至所述第 二开关的第一端，所述第二开关的控制端电性耦接所述恒定电位信号，所述第二开关打开，所述恒定电位信号被传输至所述第一开关的控制端。
  17. 如权利要求15所述的显示装置的数据保护系统，所述单向导通组件的输入端连接所述第二开关的第二端，所述单向导通组件的输出端连接所述第一开关的控制端；第二电阻连接所述第二开关与所述单向导通组件，所述第二电阻的第一端连接所述第二开关与所述单向导通组件之间，所述第二电阻的第二端接地。
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