WO2019127961A1 - 关断信号产生电路和显示装置 - Google Patents

关断信号产生电路和显示装置 Download PDF

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Publication number
WO2019127961A1
WO2019127961A1 PCT/CN2018/081246 CN2018081246W WO2019127961A1 WO 2019127961 A1 WO2019127961 A1 WO 2019127961A1 CN 2018081246 W CN2018081246 W CN 2018081246W WO 2019127961 A1 WO2019127961 A1 WO 2019127961A1
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Prior art keywords
switch
frequency
potential
electrically coupled
node
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PCT/CN2018/081246
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English (en)
French (fr)
Inventor
黄笑宇
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/461,976 priority Critical patent/US10825411B2/en
Publication of WO2019127961A1 publication Critical patent/WO2019127961A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present application relates to the field of control signal circuits, and in particular, to a turn-off signal generating circuit and a display device for providing a turn-off signal to a gate driving set circuit on a substrate.
  • a liquid crystal display device usually has a gate driving circuit, a source driving circuit, and a pixel array.
  • the pixel array has a plurality of pixel circuits, each of which is turned on and off according to a scan signal provided by the gate driving circuit, and displays a data picture according to the data signal provided by the source driving circuit.
  • the gate driving circuit usually has a multi-stage shift register, and outputs the scanning signal to the pixel array by means of the first-stage shift register being transferred to the next-stage shift register.
  • the pixel circuit is sequentially turned on to enable the pixel circuit to receive the data signal.
  • the gate driving circuit is directly fabricated on the array substrate instead of the driving chip fabricated by the external connection IC.
  • This is called Gate On Array (GOA) technology.
  • GAA Gate On Array
  • the current gate turn-off signal VSS is generated by a timing signal of two delays of 1/2 cycle, in conjunction with the associated logic module and associated circuitry. If these lines are not well designed, it is easy for the gate turn-off signal VSS to be unable to maintain a long-term fixed value, which may cause confusion in the operation of the line.
  • the active switch of the frequency register connected to the shift register is easy to cut when the frequency signal is cut into a low potential.
  • the low potential of the frequency signal is smaller than the gate turn-off signal VSS, causing the active opening and closing to be opened, causing the panel charging time to increase and excessive power consumption. In severe cases, the panel will malfunction and the panel will be damaged.
  • an object of the present application is to provide a shutdown signal generating circuit and a display device, which solve the problems of providing a stable gate turn-off signal and avoiding abnormal operation of the line.
  • a shutdown signal generating circuit is disposed on the array substrate, and includes: a first switch, the first end of the first switch is electrically coupled to the first frequency, and the control end of the first switch Electrically coupled to the first node, the second end of the first switch is electrically coupled to the second node; the second switch is electrically coupled to the second end of the second switch, the second The control end of the switch is electrically coupled to the first node, and the second end of the second switch is electrically coupled to the second node; wherein the first node is electrically coupled to the control signal, the first The two-node electrical output gate turn-off signal, the first switch is opposite to the potential control polarity of the control end of the second switch, and when the control signal is the first potential, the first switch is turned on, The second switch is turned off; when the control signal is at a second potential, the second switch is turned on, and the first switch is turned off.
  • the high potential values of the first frequency and the second frequency are equal or similar, and the low potential values of the first frequency and the second frequency are equal or similar.
  • the potential of the first frequency and the second frequency are different during the same time period.
  • the first switch and the second switch are transistors.
  • the transistors of the first switch and the second switch are opposite in polarity.
  • the first end of the first switch is a source, the control end of the first switch is a gate, and the second end of the first switch is a drain;
  • the first end of the second switch is a source, the control end of the second switch is a gate, and the second end of the second switch is a drain.
  • the first frequency when the first switch is turned on, the first frequency is output as a low potential, and when the second switch is turned on, the second frequency is output as a low potential.
  • a logic unit is disposed in a wiring area of the array substrate, and is electrically coupled to the first node, and the logic unit provides the control signal to adjust the first switch and the The potential of the control terminal of the second switch.
  • the first potential is greater than the second potential, the first potential is a high voltage of 3.3V, and the second potential is a low voltage of 0V.
  • the turn-off signal generating circuit is disposed on a wiring region on the gate driving line side.
  • the second object of the present application is a display device, comprising: a display panel comprising an array substrate and oppositely disposed opposite substrates; the array substrate comprising a display area and a peripheral wiring area thereof, a plurality of active switches, and more a pixel unit, a plurality of gate lines and a plurality of source lines are disposed in the display area, a gate driving circuit is disposed in the wiring area, and the gate driving circuit is disposed on both sides of the array substrate and is electrically The plurality of gate lines are coupled to each other; any one of the foregoing shutdown signal generating circuits is disposed on a wiring area of at least one of the two sides of the array substrate, and the signal of the shutdown signal generating circuit The output end is electrically coupled to the gate driving circuit.
  • a further object of the present application is a shutdown signal generating circuit, disposed on the array substrate, including: a first switch, the first end of the first switch is electrically coupled to the first frequency, and the first switch is The control terminal is electrically coupled to the first node, the second end of the first switch is electrically coupled to the second node, and the second switch is electrically coupled to the second frequency.
  • the control end of the second switch is electrically coupled to the first node, and the second end of the second switch is electrically coupled to the second node.
  • the first node is electrically coupled to the control signal, and the second node is electrically outputting the gate turnoff signal.
  • the high potential values of the first frequency and the second frequency are equal or similar, and the low potential values of the first frequency and the second frequency are equal or similar.
  • the first switch is opposite in polarity to the transistor of the second switch. In the first period, the control signal is a first potential, the first switch is turned on, the second switch is turned off, the gate turn-off signal is the first frequency, and in a second period The control signal is a second potential, the second switch is turned on, the first switch is turned off, and the gate turn-off signal is the second frequency.
  • This application can not significantly change the premise of the existing production process, maintain the process requirements and reduce the product cost, solve the problem of providing a stable gate turn-off signal and avoid the abnormal operation of the line.
  • FIG. 1a is a schematic diagram showing the configuration of an exemplary display device.
  • FIG. 1b is a waveform signal timing diagram of a gate turn-off signal of an exemplary liquid crystal display device.
  • 2a is a block diagram showing the shutdown signal generating circuit applied to a display panel according to the method of the present application.
  • 2b is a timing diagram showing waveform signals applied to a gate turn-off signal of a display panel in accordance with a method of the present application.
  • 2c is a timing diagram showing waveform signals applied to a gate turn-off signal of a display panel in accordance with a method of the present application.
  • 3a is a schematic diagram showing the operation of an embodiment applied to a shutdown signal generating circuit in accordance with the method of the present application.
  • FIG. 3b is a schematic diagram showing the operation of an embodiment of a method for applying a shutdown signal generating circuit according to the method of the present application.
  • FIG. 4 is a schematic diagram showing the structure of an embodiment applied to an array substrate according to the method of the present application.
  • the thickness of layers, films, panels, regions, etc. are exaggerated for clarity, and the representation of the circuit arrangement in the relevant regions is also exaggerated.
  • the thickness of layers and regions are exaggerated for the purposes of understanding and description, and the representation of the circuit arrangement in the relevant regions is also exaggerated. It will be understood that when an element such as a layer, a film, a region, a circuit, or a substrate is referred to as being "on" another component, the component may be directly on the other component, or Component.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • FIG. 1a is a schematic diagram showing the configuration of an exemplary display device.
  • a gate array drive (Gate On Array) display device 100 includes a control board 101, a printed circuit board 102, a color filter substrate 104, and an active array substrate 103.
  • the gate driver circuit 105 is divided into two parts, one is a level shifter 105a, and the other is a shift register 105b.
  • the boosting module 105a is disposed on the control board 101, and the shift register 105b is disposed on the active array substrate 104.
  • the shift register 105b is disposed on both sides of the active array substrate 104.
  • the shift register 105b can be disposed on the wiring area of the active array substrate 104. Since the area occupied by the shift register 105b is small, the gate array driving (GOA) panel can generally achieve an ultra-narrow bezel.
  • the system board provides color (eg, R/G/B) compression signals, control signals, and power to the control board 101.
  • the Timing Controller (TCON) 107 on the control board 101 and after processing the signals, together with the power source processed by the driving circuit, are transmitted to the printed circuit board through, for example, a flexible flat cable (FFC).
  • FIG. 1b is a waveform signal timing diagram of a gate turn-off signal of an exemplary liquid crystal display device.
  • the gate turn-off signal VSS is a timing signal of two delays of 1/2 cycle, which is generated by the associated logic module and associated circuitry, for example, alternately intercepting two timing signals at different periods. Low potential.
  • the logic module includes, by way of example, not limited to a timing control unit.
  • the lines are poorly designed, it is easy to make the gate turn-off signal VSS unable to maintain a long-term fixed value, thereby causing the circuit to operate in a chaotic manner.
  • the active switch of the gate driving circuit 105 connected to the frequency signal is turned on, and the panel charging time is increased. And excessive power consumption. In severe cases, the panel will malfunction and the panel will be damaged.
  • a shutdown signal generating circuit 200 includes: a first switch 210, the first end 211 of the first switch 210 is electrically coupled to a first frequency (Clock voltage pulse, CKV, a clock signal, the control terminal 213 of the first switch 210 is electrically coupled to the first node P1, the second end 212 of the first switch 210 is electrically coupled to the second node P2, and the second switch 220 The first end 221 of the second switch 220 is electrically coupled to the second frequency (Clock voltage pulse extend, CKVX, the extended clock signal), and the control end 223 of the second switch 220 is electrically coupled to the first node.
  • the second end 222 of the second switch 220 is electrically coupled to the second node P2; wherein the first node P1 is electrically coupled to the control signal, and the second node P2 is electrically outputted to the gate Turn off the signal VSS.
  • the first switch 210 and the second switch 220 are transistors.
  • the first end 211 of the first switch 210 is a source, the control end 213 of the first switch 210 is a gate, and the second end 212 of the first switch 210 is a drain;
  • the first end 221 of the second switch 220 is a source, the control end 223 of the second switch 220 is a gate, and the second end 222 of the second switch 220 is a drain.
  • FIG. 2b is a timing diagram showing waveform signals applied to a gate turn-off signal of a display panel in accordance with a method of the present application. Please cooperate with Figure 2a to facilitate understanding.
  • a printed circuit board 102 that interfaces with the display panel is used to provide the control signals.
  • the control signal has a first potential value and a second potential value, the first potential value being greater than the second potential value.
  • the first potential value is a high voltage of 3.3 V, but is not limited thereto
  • the second potential value is a low voltage of 0 V, but is not limited thereto.
  • the shutdown signal generating circuit 200 is coupled to the timing controller 107, which provides a first frequency CKV and a second frequency CKVX with a delay of 1/2 cycle, respectively. Received by the first end 211 of the first switch 210 and the first end 221 of the second switch 220.
  • the high potential values of the first frequency CKV and the second frequency CKVX are equal or similar, and the low potential values of the first frequency CKV and the second frequency CKVX are equal or similar .
  • the high potential value is a high voltage of 27V, but is not limited thereto, and the low potential value is a low voltage of -8V, but is not limited thereto.
  • the first frequency CKV is different from the potential of the second frequency CKVX during the same time period. As shown in FIG. 2b, in the first time period, the first frequency CKV is high, and the second frequency CKVX is low; in the second time period, the first frequency CKV is low, and the second frequency CKVX is High potential.
  • the first switch 210 and the second switch 220 have opposite transistor polarities. When the control signal is at a first potential, the first switch 210 is turned on, and the second switch 220 is When the control signal is the second potential, the second switch 220 is turned on, and the first switch 210 is turned off.
  • control signal is provided by a logic unit 300, which may be disposed in the wiring area or in combination with the control board 101 and the printed circuit board 102.
  • the logic unit 300 is electrically coupled to the timing controller 107 and controlled by the timing controller 107 to adjust the potential change of the control signal.
  • FIG. 3a is a schematic diagram showing the operation of an embodiment applied to a shutdown signal generating circuit in accordance with the method of the present application. Please cooperate with the waveform diagram shown in Figure 2b to facilitate understanding.
  • the control signal is at the second potential (low potential)
  • the first switch 210 is turned off
  • the second switch 220 is turned on.
  • the gate turn-off signal VSS is the second frequency CKVX.
  • FIG. 3b is a schematic diagram showing the operation of an embodiment of a method for applying a shutdown signal generating circuit according to the method of the present application. Please cooperate with the waveform diagram shown in Figure 2b to facilitate understanding.
  • the control signal is at the first potential (high potential)
  • the second switch 220 is turned off
  • the first switch 210 is turned on.
  • the gate turn-off signal VSS is the first frequency CKV.
  • the period of the control signal is the same as the first frequency CKV and the second frequency CKVX
  • the time point when the control signal is the first potential is the same as the time point when the CKV is the low voltage.
  • the time point at which the control signal is at the second potential is the same as the time at which CKVX is at the low voltage.
  • the gate turn-off voltage VSS is provided by the interaction of the low potential of the first frequency CKV and the second frequency CKVX, and can be maintained at a specific constant value or an approximation. In this example, the gate turn-off voltage VSS is equal to the low potential value of the first frequency CKV and the second frequency CKVX, but is not limited thereto.
  • the turn-off signal generating circuit 200 is disposed on a wiring region on the gate driving line side.
  • the turn-off signal generation circuit 200 is a gate array driven line configuration.
  • the substrate of the array substrate includes a display area and a wiring area.
  • the turn-off signal generating circuit is disposed in a fan-out manner of the array substrate in combination with the current gate array driving circuit configuration.
  • the turn-off signal generating circuit is the turn-off signal generating circuit 200 in any of the previous embodiments.
  • the turn-off signal generating circuit 200 can be combined with the gate driving circuit 105, and the first frequency CKV and the second frequency CKVX provided by the timing controller 107 are simultaneously supplied to the turn-off signal generating circuit 200 and the gate driving.
  • the circuit 105, the gate drive circuit 105 refers to the gate turn-off voltage VSS generated by the turn-off signal generating circuit 200.
  • a display device 100 includes a display panel including an array substrate 104 and opposite substrates disposed thereon, the opposite substrate including but not limited to a color filter substrate, or color
  • the opposite substrate can be a matching substrate required for design
  • the array substrate 104 includes a display area and a peripheral wiring area thereof
  • the gate driving circuit 105 is disposed in the wiring area, and multiple active The switch, the plurality of pixel units, the plurality of gate lines, and the plurality of source lines are disposed in the display area, and the plurality of pixel units are electrically coupled to the plurality of strips through the corresponding plurality of active switches
  • the intersection of the gate line and the plurality of source lines, the gate driving circuit 105 is disposed on both sides of the array substrate 104 and electrically coupled to the plurality of gate lines; and, any of the previous The turn-off signal generating circuit 200 is disposed in the embodiment; the turn-off signal generating circuit 200 is disposed on a wiring area of at least
  • the display panel of the present application may be, for example, a liquid crystal display panel, but is not limited thereto, and may also be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, and a curved surface. Display panel or other type of display panel.
  • This application can not significantly change the premise of the existing production process, maintain the process requirements and reduce the product cost, solve the problem of providing a stable gate turn-off signal and avoiding the abnormal operation of the line.

Abstract

提供了一种关断信号产生电路(200)和显示装置，关断信号产生电路(200)包括：第一开关(210)，此第一开关(210)的第一端(211)电性耦接第一频率(CKV)，此第一开关(210)的控制端(213)电性耦接第一节点(P1)，此第一开关(210)的第二端(212)电性耦接第二节点(P2)；第二开关(220)，此第二开关(220)的第一端(221)电性耦接第二频率(CKVX)，此第二开关(220)的控制端(223)电性耦接此第一节点(P1)，此第二开关(220)的第二端(222)电性耦接此第二节点(P2)；其中，此第一节点(P1)电性耦接控制信号，此第二节点(P2)电性输出栅极关断信号(VSS)。

Description

关断信号产生电路和显示装置 技术领域
本申请涉及一种控制信号电路技术领域，特别涉及一种提供关断信号至基板上的栅极驱动集电路的关断信号产生电路和显示装置。
背景技术
液晶显示设备中通常具有栅极驱动电路、源极驱动电路和像素阵列。像素阵列中具有多个像素电路，每一个像素电路依据栅极驱动电路提供的扫描讯号开启和关闭，并依据源极驱动电路提供的数据讯号，显示数据画面。以栅极驱动电路来说，栅极驱动电路通常具有多级移位寄存器，并藉由一级移位寄存器传递至下一级移位寄存器的方式，来输出扫描讯号到像素阵列中，以依序地开启像素电路，使像素电路接收数据讯号。
因此在驱动电路的制程中，便直接将栅极驱动电路制作在阵列基板上，来取代由外连接IC制作的驱动芯片，此种被称为栅极阵列驱动(Gate On Array，GOA)技术的应用可直接做在面板周围，减少制作程序、降低产品成本且使面板更薄型化。
然而，现行栅极关断信号VSS是以两个时延1/2周期的时序信号，配合相关逻辑模块及相关电路产生。此等线路若设计不佳，容易使栅极关断信号VSS无法保持长期定值，进而造成线路运作混乱，如移位寄存器连接频率讯号的主动开关，在频率讯号切入低电位时，很容易因为频率讯号的低电位小于栅极关断信号VSS，导致此主动开闭被打开，使面板充电时间增加而产生过度功耗。严重者，会造成面板运作失常，造成面板损坏的情形。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种关断信号产生电路和显示装置，解决提供稳定的栅极关断信号，避免线路运作失常等问题。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种关断信号产生电路，设置于阵列基板上，包括：第一开关，所述第一开关的第一端电性耦接第一频率，所述第一开关的控制端电性耦接第一节点，所述第一开关的第二端电性耦接第二节点；第二开关，所述第二开关的第一端电性耦接第二频率，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第二端电性耦接所述第二节点；其中，所述第一节点电性耦接控制信号，所述第二节点电性输出栅极关断信号，所述第一开关与所述第二开关的控制端的电位控制极性为相反，所述控制信号为第一电位时，所述第一开关被打开，所述第二开关被关闭；所述控制信号为第二电位时，所述 第二开关被打开，所述第一开关被关闭。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，所述第一频率及所述第二频率的高电位值为相等或相近似，所述第一频率及所述第二频率的低电位值相等或相近似。
在本申请的一实施例中，在同一时间周期，所述第一频率与所述第二频率的电位为相异。
在本申请的一实施例中，所述第一开关与所述第二开关为晶体管。
在本申请的一实施例中，所述第一开关与所述第二开关的晶体管极性相反。
在本申请的一实施例中，所述第一开关的第一端为源极，所述第一开关的控制端为栅极，所述第一开关的第二端为漏极；所述第二开关的第一端为源极，所述第二开关的控制端为栅极，所述第二开关的第二端为漏极。
在本申请的一实施例中，所述第一开关被打开时，输出所述第一频率为低电位，所述第二开关被打开时，输出所述第二频率为低电位。
在本申请的一实施例中，逻辑单元设置于所述阵列基板的布线区，并电性耦接所述第一节点，所述逻辑单元提供所述控制信号以调整所述第一开关与所述第二开关的控制端的电位。
在本申请的一实施例中，所述第一电位大于所述第二电位，所述第一电位为高电压3.3V，所述第二电位为低电压0V。
在本申请的一实施例中，所述关断信号产生电路设置于栅极驱动线路侧的布线区。
本申请的次一目的为一种显示装置，其包括：显示面板，包括阵列基板及其相对设置的对向基板；所述阵列基板包括显示区及其外围的布线区，多个主动开关、多个像素单元、多条栅极线与多条源极线设置于所述显示区，栅极驱动电路设置于所述布线区，所述栅极驱动电路设置于所述阵列基板的两侧且电性耦接所述多条栅极线；前述中任一种关断信号产生电路，其设置于所述阵列基板两侧中其至少一部位的布线区，且所述关断信号产生电路的信号输出端电性耦接于所述栅极驱动电路。
本申请的又一目的为一种关断信号产生电路，设置于阵列基板上，包括：第一开关，所述第一开关的第一端电性耦接第一频率，所述第一开关的控制端电性耦接第一节点，所述第一开关的第二端电性耦接第二节点；第二开关，所述第二开关的第一端电性耦接第二频率，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第二端电性耦接所述第二节点。其中，所述第一节点电性耦接控制信号，所述第二节点电性输出栅极关断信号。所述第一频率及所述第二频率的高电位值为相等或相近似，所述第一频率及所述第二频率的低电位值相等或相近似。所述第一开关与所述第二开关的晶体管极性相反。在第一周期内，所述控制信号为第一电位，所述第一开关被打开， 所述第二开关被关闭，所述栅极关断信号为所述第一频率；在第二周期内，所述控制信号为第二电位，所述第二开关被打开，所述第一开关被关闭，所述栅极关断信号为所述第二频率。
本申请可以不大幅改变现有生产流程的前提，维持制程需求与降低产品成本，解决线路解决提供稳定的栅极关断信号，避免线路运作失常等问题。
附图说明
图1a为范例性的显示装置的配置结构示意图。
图1b为范例性的液晶显示装置的栅极关断信号的波形信号时序图。
图2a为显示依据本申请的方法，一实施例应用于显示面板的关断信号产生电路的架构示意图。
图2b为显示依据本申请的方法，一实施例应用于显示面板的栅极关断信号的波形信号时序图。
图2c为显示依据本申请的方法，一实施例应用于显示面板的栅极关断信号的波形信号时序图。
图3a为显示依据本申请的方法，一实施例应用于关断信号产生电路的运作示意图。
图3b为显示依据本申请的方法，一实施例应用于关断信号产生电路的运作示意图。
图4为显示依据本申请的方法，一实施例应用于阵列基板的架构示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度，亦夸大了电路配置在相关区域的表示。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度，亦夸大了电路配置在相关区域的表示。将理解的是，当例如层、膜、区域、电路、基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种关断信号产生电路和显示装置，其具体实施方式、结构、特征及其功效，详细说明如后。
图1a为范例性的显示装置的配置结构示意图。请参照图1a，一种栅极阵列驱动(Gate On Array)的显示装置100，包括控制板101，印刷电路板102，彩色滤光片基板104、主动阵列基板103。栅极驱动电路(Gate Driver)105被分成了两部分，一是升压模块(level shifter)105a，一是移位寄存器(shift register)105b。所述升压模块105a设置在控制板101上，移位寄存器105b则是设置在主动阵列基板104上。在某些实施例中，移位寄存器105b会配置于主动阵列基板104两侧，依据线路设计，移位寄存器105b可设置于主动阵列基板104的布线区。由于移位寄存器105b占的面积很小，因此栅极阵列驱动(GOA)面板一般都可以做到超窄边框。
在一些实施例中，系统主板提供颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板101。控制板101上的时序控制器(Timing Controller，TCON)107与处理此等信号后，连同被驱动电路处理的电源，通过如柔性扁平电缆(Flexible Flat Cable，FFC)，一并传输至印刷电路板102的源极电路及栅极电路，通过源极覆晶薄膜109及配置在主动阵列基板104布线区的栅极阵列驱动电路，将必要性的数据与电源传输于显示区，从而使得显示装置获得呈现画面需求的电源、信号。
图1b为范例性的液晶显示装置的栅极关断信号的波形信号时序图。在某些实施例中，栅极关断信号VSS是以两个时延1/2周期的时序信号，其是配合相关逻辑模块及相关电路产生，例如在不同周期，交替的截取两时序信号的低电位。在某些实施例中，逻辑模块包括例不限于时序控制单元。
然而，若是此等线路若设计不佳，容易使栅极关断信号VSS无法保持长期定值，进而造成线路运作混乱，如栅极驱动电路105连接频率讯号的主动开关被打开，面板充电时间增加而产生过度功耗。严重者，会造成面板运作失常，造成面板损坏的情形。
图2a为显示依据本申请的方法，一实施例应用于显示面板的关断信号产生电路的架构示意图。在本申请一实施例中，一种关断信号产生电路200，包括：第一开关210，所述第一开关210的第一端211电性耦接第一频率(Clock voltage pulse，CKV，亦时钟脉冲信号)，所述第一开关210的控制端213电性耦接第一节点P1，所述第一开关210的第二端212电性耦接第二节点P2；第二开关220，所述第二开关220的第一端221电性耦接第二频率(Clock voltage pulse extend，CKVX，延展时钟脉冲信号)，所述第二开关220的控制端223电性耦接所述第一节点P1，所述第二开关220的第二端222电性耦接所述第二节点P2；其中，所述第一节点P1电性耦接控制信号，所述第二节点P2电性输出栅极关断信号VSS。
在一些实施例中，所述第一开关210与所述第二开关220为晶体管。
在一些实施例中，所述第一开关210的第一端211为源极，所述第一开关210的控制端213为栅极，所述第一开关210的第二端212为漏极；所述第二开关220的第一端221为源极，所述第二开关220的控制端223为栅极，所述第二开关220的第二端222为漏极。
图2b为显示依据本申请的方法，一实施例应用于显示面板的栅极关断信号的波形信号时序图。请配合图2a以利于理解。在一些实施例中，与显示面板相接的印刷电路板102用以提供所述控制信号。所述控制信号具有第一电位值以及第二电位值，所述第一电位值大于所述第二电位值。在一些实施例中，所述第一电位值为高电压3.3V，但不限于此，所述第二电位值为低电压0V，但不限于此。
在一些实施例中，所述关断信号产生电路200连接至时序控制器107，所述时序控制器107提供时延为1/2周期的第一频率CKV与第二频率CKVX，此二讯号分别由所述第一开关210的第一端211及所述第二开关220的第一端221所接收。
在一些实施例中，所述第一频率CKV及所述第二频率CKVX的高电位值为相等或相近似，所述第一频率CKV及所述第二频率CKVX的低电位值相等或相近似。如图2b，所述高电位值为高电压27V，但不限于此，所述低电位值为低电压-8V，但不限于此。
在一些实施例中，在同一时间周期，所述第一频率CKV与所述第二频率CKVX的电位为相异。如图2b所绘示，在第一时间周期时，第一频率CKV为高电位，第二频率CKVX为低电位；在第二时间周期时，第一频率CKV为低电位，第二频率CKVX为高电位。
在一些实施例中，所述第一开关210与所述第二开关220的晶体管极性相反，所述控制信号为第一电位时，所述第一开关210被打开，所述第二开关220被关闭；所述控制信号为第二电位时，所述第二开关220被打开，所述第一开关210被关闭。
图2c为显示依据本申请的方法，一实施例应用于显示面板的栅极关断信号的波形信号时序图。请配合图2a及图2b以利于理解，现有显示装置技术组件请配合图1a至图1b以利于了解。在一些实施例中，所述控制信号由一逻辑单元300所提供，所述逻辑单元300可设置于所述布线区，或是结合所述控制板101、所述印刷电路板102。
在一些实施例中，所述逻辑单元300电性耦接所述时序控制器107，并由时序控制器107控制，以调整控制信号的电位变化。
图3a为显示依据本申请的方法，一实施例应用于关断信号产生电路的运作示意图。请配合图2b绘示的波型示意图以利于理解。在第一周期T1，控制信号为第二电位(低电位)，所述第一开关210被关闭，所述第二开关220被打开。此时，所述栅极关断信号VSS为第二频率CKVX。
图3b为显示依据本申请的方法，一实施例应用于关断信号产生电路的运作示意图。请配合图2b绘示的波型示意图以利于理解。在第二周期T2，控制信号为第一电位(高电位)，所述第二开关220被关闭，所述第一开关210被打开。此时，所述栅极关断信号VSS为第一频率CKV。
在一些实施例中，所述控制信号的周期与所述第一频率CKV及所述第二频率CKVX相同，所述控制信号为第一电位的时间点与CKV为低电压的时间点相同，所述控制信号为第二电位的时间点与CKVX为低电压的时间点相同。所述栅极关断电压VSS即通过第一频率CKV与第二频率CKVX的低电位的交互提供，较能保持于特定的恒定值或是近似值。此例中，栅极关断电压VSS等同所述第一频率CKV及所述第二频率CKVX的低电位值为低电压-8V，但不限于此。
在一些实施例中，所述关断信号产生电路200设置于栅极驱动线路侧的布线区。
在一些实施例中，所述关断信号产生电路200为栅极阵列驱动的线路配置方式。
图4为显示依据本申请的方法，一实施例应用于阵列基板的架构示意图。在一些实施例中，所述阵列基板其基底包括显示区与布线区，在一些实施例中，关断信号产生电路是结合现行栅极阵列驱动电路配置方式，而设置于阵列基板的扇出处，其中，所述关断信号产生电路为先前任一实施例中的所述关断信号产生电路200。所述关断信号产生电路200可与栅极驱动电路105组合式设计，时序控制器107提供的第一频率CKV及第二频率CKVX提供同时提供至所述关断信号产生电路200与栅极驱动电路105，栅极驱动电路105则引用所述关断信号产生电路200产生的栅极关断电压VSS。
在本申请的一实施例中，一种显示装置100，包括：显示面板，其包括阵列基板104及其相对设置的对向基板，对向基板包括但不限于彩色滤光片基板，或是彩色滤光片设置于阵列基板时，对向基板可为设计需要的配套基板；所述阵列基板104包括显示区及其外围的布线区，栅极驱动电路105设置于所述布线区，多个主动开关、多个像素单元、多条栅极线与多条源极线设置于所述显示区，所述多个像素单元通过相应的所述多个主动开关，电性耦接于所述多条栅极线与所述多条源极线的交集处，所述栅极驱动电路105设置于所述阵列基板104的两侧且电性耦接所述多条栅极线；以及，先前任一实施例中所述关断信号产生电路200；所述关断信号产生电路200设置于所述阵列基板104两侧中其至少一部位的布线区，且所述关断信号产生电路200的信号输出端(第二节点P2，栅极关断电压VSS的输出端)电性耦接于所述栅极驱动电路105。
在一些实施例中，本申请的所述显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED显示面板，W-OLED显示面板，QLED显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
本申请可以不大幅改变现有生产流程的前提，维持制程需求与降低产品成本，解决线路解 决提供稳定的栅极关断信号，避免线路运作失常等问题。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。此用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种关断信号产生电路，设置于阵列基板上，其中，所述关断信号产生电路包括：
    第一开关，所述第一开关的第一端电性耦接第一频率，所述第一开关的控制端电性耦接第一节点，所述第一开关的第二端电性耦接第二节点；
    第二开关，所述第二开关的第一端电性耦接第二频率，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第二端电性耦接所述第二节点；
    其中，所述第一节点电性耦接控制信号，所述第二节点电性输出栅极关断信号，所述第一开关与所述第二开关的控制端的电位控制极性为相反，所述控制信号为第一电位时，所述第一开关被打开，所述第二开关被关闭；所述控制信号为第二电位时，所述第二开关被打开，所述第一开关被关闭。
  2. 如权利要求1所述的关断信号产生电路，其中，所述第一频率及所述第二频率的高电位值为相等或相近似，所述第一频率及所述第二频率的低电位值相等或相近似。
  3. 如权利要求1所述的关断信号产生电路，其中，在同一时间周期，所述第一频率与所述第二频率的电位为相异。
  4. 如权利要求1所述的关断信号产生电路，其中，所述第一开关与所述第二开关为晶体管。
  5. 如权利要求4所述的关断信号产生电路，其中，所述第一开关的第一端为源极，所述第一开关的控制端为栅极，所述第一开关的第二端为漏极；所述第二开关的第一端为源极，所述第二开关的控制端为栅极，所述第二开关的第二端为漏极。
  6. 如权利要求4所述的关断信号产生电路，其中，所述第一开关与所述第二开关的晶体管极性相反。
  7. 如权利要求1所述的关断信号产生电路，其中，所述第一开关被打开时，输出所述第一频率为低电位，所述第二开关被打开时，输出所述第二频率为低电位。
  8. 如权利要求1所述的关断信号产生电路，还包括逻辑单元，设置于所述阵列基板的布线区，并电性耦接所述第一节点，所述逻辑单元提供所述控制信号以调整所述第一开关与所述第二开关的控制端的电位。
  9. 如权利要求1所述的关断信号产生电路，其中，所述第一电位大于所述第二电位，所述第一电位为高电压3.3V，所述第二电位为低电压0V。
  10. 一种显示装置，包括：
    显示面板，包括阵列基板及其相对设置的对向基板，所述阵列基板包括显示区及其外围的布线区，多个主动开关、多个像素单元、多条栅极线与多条源极线设置于所述显示区；
    栅极驱动电路，设置于所述布线区，所述栅极驱动电路设置于所述阵列基板的两侧且电性耦接所述多条栅极线；以及
    关断信号产生电路，包括：
    第一开关，所述第一开关的第一端电性耦接第一频率，所述第一开关的控制端电性耦接第一节点，所述第一开关的第二端电性耦接第二节点；
    第二开关，所述第二开关的第一端电性耦接第二频率，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第二端电性耦接所述第二节点；
    其中，所述第一节点电性耦接控制信号，所述第二节点电性输出栅极关断信号，所述第一开关与所述第二开关的控制端的电位控制极性为相反，所述控制信号为第一电位时，所述第一开关被打开，所述第二开关被关闭；所述控制信号为第二电位时，所述第二开关被打开，所述第一开关被关闭；
    其中，所述关断信号产生电路设置于所述阵列基板两侧中其至少一部位的布线区，且所述关断信号产生电路的信号输出端电性耦接于所述栅极驱动电路。
  11. 如权利要求10所述的显示装置，其中，所述第一频率及所述第二频率的高电位值为相等或相近似。
  12. 如权利要求10所述的显示装置，其中，所述第一频率及所述第二频率的低电位值相等或相近似。
  13. 如权利要求10所述的显示装置，其中，在同一时间周期，所述第一频率与所述第二频率的电位为相异。
  14. 如权利要求10所述的显示装置，其中，所述第一开关与所述第二开关为晶体管。
  15. 如权利要求14所述的显示装置，其中，所述第一开关的第一端为源极，所述第一开关的控制端为栅极，所述第一开关的第二端为漏极；所述第二开关的第一端为源极，所述第二开关的控制端为栅极，所述第二开关的第二端为漏极。
  16. 如权利要求14所述的显示装置，其中，所述第一开关与所述第二开关的晶体管极性相反。
  17. 如权利要求10所述的显示装置，其中，所述第一开关被打开时，输出所述第一频率为低电位，所述第二开关被打开时，输出所述第二频率为低电位。
  18. 如权利要求10所述的显示装置，还包括逻辑单元，设置于所述阵列基板的布线区，并电性耦接所述第一节点，所述逻辑单元提供所述控制信号以调整所述第一开关与所述第二开关的控制端的电位。
  19. 如权利要求10所述的显示装置，其中，所述第一电位大于所述第二电位，所述第一电位为高电压3.3V，所述第二电位为低电压0V。
  20. 一种关断信号产生电路，设置于阵列基板上，其中，所述关断信号产生电路包括：
    第一开关，所述第一开关的第一端电性耦接第一频率，所述第一开关的控制端电性耦接第一节点，所述第一开关的第二端电性耦接第二节点；
    第二开关，所述第二开关的第一端电性耦接第二频率，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第二端电性耦接所述第二节点；
    其中，所述第一节点电性耦接控制信号，所述第二节点电性输出栅极关断信号；
    其中，所述第一频率及所述第二频率的高电位值为相等或相近似，所述第一频率及所述第二频率的低电位值相等或相近似；
    其中，所述第一开关与所述第二开关的晶体管极性相反；
    在第一周期内，所述控制信号为第一电位，所述第一开关被打开，所述第二开关被关闭，所述栅极关断信号为所述第一频率；
    在第二周期内，所述控制信号为第二电位，所述第二开关被打开，所述第一开关被关闭，所述栅极关断信号为所述第二频率。
PCT/CN2018/081246 2017-12-26 2018-03-30 关断信号产生电路和显示装置 WO2019127961A1 (zh)

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