WO2018218730A1 - 移位暂存电路及其应用的显示面板 - Google Patents

移位暂存电路及其应用的显示面板 Download PDF

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Publication number
WO2018218730A1
WO2018218730A1 PCT/CN2017/092140 CN2017092140W WO2018218730A1 WO 2018218730 A1 WO2018218730 A1 WO 2018218730A1 CN 2017092140 W CN2017092140 W CN 2017092140W WO 2018218730 A1 WO2018218730 A1 WO 2018218730A1
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Prior art keywords
switch
electrically coupled
node
signal
shift register
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PCT/CN2017/092140
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English (en)
French (fr)
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王明良
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/555,905 priority Critical patent/US20180342221A1/en
Publication of WO2018218730A1 publication Critical patent/WO2018218730A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present application relates to the field of display technologies, and in particular, to a display panel for a shift register circuit and an application thereof.
  • planar liquid crystal display driving circuit is mainly composed of an external IC connected to the panel, but this method cannot reduce the cost of the product and can not make the panel thinner.
  • a liquid crystal display device usually has a gate driving circuit, a source driving circuit, and a pixel array.
  • the pixel array has a plurality of pixel circuits, each of which is turned on and off according to a scan signal provided by the gate driving circuit, and displays a data picture according to the data signal provided by the source driving circuit.
  • the gate driving circuit usually has a multi-stage shift register, and outputs the scanning signal to the pixel array by means of the first-stage shift register being transferred to the next-stage shift register.
  • the pixel circuit is sequentially turned on to enable the pixel circuit to receive the data signal.
  • the gate driving circuit is directly fabricated on the array substrate instead of the driving chip fabricated by the external connection IC.
  • This is called Gate On Array (GOA) technology.
  • GAA Gate On Array
  • the original gate integrated circuit (Gate IC) is split into two parts: a level shifter IC and a shift register, and the boosting integrated circuit is used in the driving board.
  • the shift register is placed on the panel so that the gate integrated circuit is not needed, so the frame length can be further compressed.
  • the shift register when the shift register is connected to the active switch of the frequency signal, when the frequency signal is cut into a low potential, it is easy to cause the active opening and closing to be opened because the low potential of the frequency signal is lower than the low default potential VSS.
  • one line is only turned on once in one frame time, and most of the remaining time is turned off, so when such active switch is turned on, the power consumption is relatively high. This is especially true for large and high resolution panels.
  • the purpose of the present application is to provide a shift temporary storage circuit, which can prevent the active switch connected to the frequency signal from having a voltage difference across the voltage when the frequency signal is cut into a low potential, thereby avoiding the active switch. Leakage, being turned on, etc. produces extra power.
  • a shift register circuit comprising a multi-stage shift register, each shift register comprising: a first switch, the control end of the first switch being electrically coupled to the first node, the The first end of a switch is electrically coupled to the frequency signal; the second switch is electrically coupled to the second switch The control terminal is electrically coupled to the first node, the first end of the second switch is electrically coupled to the frequency signal, and the second end of the second switch is electrically coupled to the secondary frame signal; a third switch, the control end of the third switch is electrically coupled to the frame signal of the current stage, the second end of the third switch is electrically coupled to the first node, and the fourth switch is The control terminal is electrically coupled to the secondary frame signal, the first end of the fourth switch is electrically coupled to the second end of the first switch, and the second end of the fourth switch is electrically coupled to the current gate Extreme signal.
  • a fifth switch is further included, the control end of the fifth switch is electrically coupled to the second node, and the first end of the fifth switch is electrically coupled to the current gate The second end of the fifth switch is electrically coupled to the low default potential, and the second node is electrically coupled to the secondary gate signal.
  • a sixth switch is further included, the control end of the sixth switch is electrically coupled to the second node, and the first end of the sixth switch is electrically coupled to the first node, The second end of the sixth switch is electrically coupled to the low default potential, and the second node is electrically coupled to the secondary gate signal.
  • a sub-pull-down circuit is further included, which is electrically coupled to the first node, the local gate signal, and a low default potential.
  • the sub-pull-down circuit controller is further coupled to the low default potential and the sub-pull-down circuit.
  • the first end of the third switch is electrically coupled to the front gate signal.
  • the first end of the third switch is electrically coupled to the local frame signal.
  • the first end of the third switch is electrically coupled to the DC signal for providing power to precharge the shift register circuit.
  • the second object of the present application is a display panel, comprising: a first substrate and a second substrate disposed opposite to each other; and a shift temporary storage circuit disposed on the first substrate or the second substrate, including a shift register, each shift register includes: a first switch, the control end of the first switch is electrically coupled to the first node, the first end of the first switch is electrically coupled to the frequency signal; a switch, the control end of the second switch is electrically coupled to the first node, the first end of the second switch is electrically coupled to the frequency signal, and the second end of the second switch is electrically coupled a second switch, the control terminal of the third switch is electrically coupled to the frame signal of the current level, the second end of the third switch is electrically coupled to the first node, and the fourth switch is The control terminal of the fourth switch is electrically coupled to the secondary frame signal, the first end of the fourth switch is electrically coupled to the second end of the first switch, and the second end of the fourth switch is electrically It is coupled to the gate signal of this level.
  • a fifth switch is further included, the control end of the fifth switch is electrically coupled to the second node, and the first end of the fifth switch is electrically coupled to the current gate The second end of the fifth switch is electrically coupled to the low default potential, and the second node is electrically coupled to the secondary gate signal.
  • a sixth switch is further included, the control end of the sixth switch is electrically coupled to the second node, and the first end of the sixth switch is electrically coupled to the first node, The second end of the sixth switch is electrically coupled to the low default potential, and the second node is electrically coupled to the secondary gate signal.
  • a sub-pull-down circuit is further included, which is electrically coupled to the first node, the local gate signal, and a low default potential.
  • the sub-pull-down circuit controller is further coupled to the low default potential and the sub-pull-down circuit.
  • the first end of the third switch is electrically coupled to the front gate signal.
  • the first end of the third switch is electrically coupled to the local frame signal.
  • the first end of the third switch is electrically coupled to the DC signal.
  • the DC signal is used to increase the potential of the control terminal of the third switch.
  • a shift register circuit comprising a multi-stage shift register, each shift register comprising: a first switch, the control end of the first switch being electrically coupled to the first node, the The first end of the switch is electrically coupled to the frequency signal; the second switch is electrically coupled to the first node, and the first end of the second switch is electrically coupled to the first end a frequency signal, the second end of the second switch is electrically coupled to the secondary frame signal; the third switch, the control end of the third switch is electrically coupled to the frame signal of the current level, and the second end of the third switch The first end is electrically coupled to the first node; the fourth switch is electrically coupled to the second frame signal, and the first end of the fourth switch is electrically coupled to the first switch The second end of the fourth switch is electrically coupled to the gate signal of the current level; the fifth switch is electrically coupled to the second node of the fifth switch, and the fifth switch The first end is electrically coupled to
  • the application only needs to adjust the shift temporary storage circuit in a small and slight manner, as far as possible to maintain the original process requirements and product cost; when the frequency signal is cut into a low potential, the active switch connecting the frequency signal no longer has a pressure difference across the pressure. It avoids the leakage of the active switch, and is opened to generate extra power.
  • the improvement is simple and easy, and it also helps to improve the reliability of the circuit. It can be used for the manufacture of panels of various sizes with relatively high applicability.
  • Figure 1a is a schematic diagram of an exemplary liquid crystal display.
  • Figure 1b is a schematic diagram of an exemplary shift register circuit.
  • FIG. 1c is a waveform diagram of an exemplary gate drive circuit substrate.
  • FIG. 2 is a schematic diagram showing an embodiment applied to a shift register circuit in accordance with the method of the present application.
  • FIG. 3 is a schematic diagram showing an embodiment applied to a shift temporary storage circuit in accordance with the method of the present application.
  • FIG. 4 is a schematic diagram showing an embodiment applied to a shift temporary storage circuit in accordance with the method of the present application.
  • FIG. 5 is a schematic diagram showing an embodiment applied to a shift temporary storage circuit according to the method of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • the display panel of the present application is, for example, a liquid crystal display panel, an OLED display panel, a QLED display panel, or other display panel.
  • the liquid crystal display panel may include a thin film transistor (TFT) substrate and a color filter layer. (color filter, CF) substrate and a liquid crystal layer formed between the two substrates.
  • TFT thin film transistor
  • CF color filter
  • the display panel of the present application may be a curved display panel.
  • the active array (TFT) and color filter layer (CF) of the present application can be formed on the same substrate.
  • FIG. 1a is a schematic diagram of an exemplary liquid crystal display.
  • a gate array driven liquid crystal display 100 includes a color filter substrate 110 and an active array substrate 120.
  • the gate integrated circuit is divided into two parts, one is a boost module 103, and the other is a shift register 105.
  • the boosting module 103 is disposed on the driving circuit board 130, and the shift register 105 is disposed on the active array substrate 120. Since the area occupied by the shift register 105 is small, the gate array driving (GOA) panel is generally Can achieve ultra-narrow borders.
  • GOA gate array driving
  • FIG. 1b is a schematic diagram of an exemplary shift register circuit, typically derived from a modified design of Thompson circuitry.
  • a shift register circuit 200 includes an input pulse signal circuit 210 and a frequency signal circuit 220.
  • the frequency signal CLK is output by the boosting module 103
  • the gate signal G(N) is provided by a gate line (Gate Line) in the display panel
  • the low default potential VSS is a low level of the gate trace closed
  • STV(N) is the start signal.
  • the third switch T30 is turned on, and the front stage gate signal G(N-1) charges the first node P1, and the first switch T10 and the second switch T20 are turned on.
  • the secondary frame signal STV(N+1) and the local gate signal G(N) output a high level, wherein the secondary frame signal STV(N+1) is also The start signal of the first stage shift register circuit
  • the gate signal G(N) of the current stage not only opens the active switch (TFT) of the current Nth row gate trace connection of the display panel, but also serves as the next stage shift register circuit. Control signal.
  • the synchronization turns on the fifth switch T50 and the fourth switch T40 to output the gate signal G(N) of the current stage to the low default potential VSS, thereby turning off the display.
  • the active switch of the current Nth line of the panel In this way, the active switch of the next line is turned on, and the active switch of the previous line is turned off, so that the transfer is performed successively, and the active switch connected to all the gate traces is sequentially turned on.
  • FIG. 1c is a schematic diagram of a waveform of an exemplary gate driving circuit substrate, which is a waveform diagram of the circuit illustrated in FIG. 1b.
  • both the frequency signal CLK and the secondary frequency signal XCLK are signals of opposite polarity, and respectively control the charging operation of the odd-line and even-line active switching (TFT) of the gate trace.
  • the low adjustment potential of the frequency signal CLK and the secondary frequency signal XCLK is VSS1, and the voltage level of the low adjustment potential VSS1 is lower than the low default potential VSS, so that the frame signal STV is low.
  • the flat signal is also low adjustment potential VSS1, and the third switch T3 can be turned off better.
  • the gate signal G(N) of the current stage After the gate signal G(N) of the current stage is charged, the gate signal G(N) of the current stage and the first node P1 are kept at the low default potential VSS, that is, the control terminal T13 (G pole) of the first switch T10. And the second terminal T12 (S pole) is at a low default potential.
  • the frequency signal CLK is at a high potential
  • the first switch T10 can be completely turned off without a problem, but when the frequency signal CLK is at the low adjustment potential VSS1, since the voltage level of the low adjustment potential VSS1 is lower than the low default potential VSS, at this time A switch T10 is turned on, and the voltage across the first end T11 (D pole) and the second end T12 (S pole) of the first switch T10 is maintained.
  • the power consumption of the first switch T10 is large. Moreover, for the charging of the display panel, one line is only opened once in one frame time, and most of the remaining time is turned off, so the first switch T10 maintains a large amount of power consumption.
  • a shift register circuit 300 includes a multi-stage shift register, and the shift register of each stage is indicated by a virtual frame range, and includes: a first switch T10, and a control end of the first switch T10. T13 is electrically coupled to the first node P1, the first end T11 of the first switch T10 is electrically coupled to the frequency signal CLK, and the second switch T20 is electrically coupled to the control end T23 of the second switch T20.
  • the first node P1, the first end T21 of the second switch T20 is electrically coupled to the frequency signal CLK, and the second end T22 of the second switch T20 is electrically coupled to the secondary frame signal STV (N+1)
  • the third switch T30, the control terminal T33 of the third switch T30 is electrically coupled to the local stage frame signal STV(N), and the second end T32 of the third switch T30 is electrically coupled to the first node.
  • the fourth switch T40, the control terminal T43 of the fourth switch T40 is electrically coupled to the secondary frame signal STV(N+1), and the first end T41 of the fourth switch T40 is electrically coupled to the first
  • the second end T12 of the fourth switch T40 is electrically coupled to the gate signal G(N) of the first stage.
  • the shift register circuit 300 further includes a fifth switch T50, the control terminal T53 of the fifth switch T50 is electrically coupled to the second node P2, and the first end T51 of the fifth switch T50 is electrically The second terminal T52 of the fifth switch T50 is electrically coupled to the low default potential VSS.
  • the shift register circuit 300 further includes a sixth switch T60, the control terminal T63 of the sixth switch T60 is electrically coupled to the second node P2, and the first end T61 of the sixth switch T60 is electrically The second node T62 of the sixth switch T60 is electrically coupled to the low default potential VSS.
  • the second node P2 is electrically coupled to the secondary gate signal G(N+1).
  • the first end T31 of the third switch T30 is electrically coupled to the front stage gate signal G(N-1).
  • the gate line of the Nth row is normally charged, the first switch T10 and the second switch T20 are normally turned on, and the secondary frame signal STV(N+1) is high level.
  • the four switches T40 are also turned on, and the gate signal G(N) of this stage can be normally output.
  • the gate signal G(N) of the current stage is a low default potential VSS
  • the secondary frame signal STV(N+1) is a low adjustment potential VSS
  • the fourth switch T40 is turned off. Forming an open circuit, the first end T11 and the second end T12 of the first switch T10, that is, the voltage difference between the D pole and the S pole end is no longer generated, so the first switch T10 does not generate additional power consumption. .
  • the shift register circuit 300 further includes a sub-pull circuit 420 electrically coupled to the first node P1, the local gate signal G(N), and a low default. Potential VSS.
  • the shift register circuit 300 further includes a sub-pull circuit controller 410 electrically coupled to the low default potential VSS and the sub-pull circuit 420.
  • FIG. 4 is a schematic diagram showing an embodiment applied to a shift temporary storage circuit in accordance with the method of the present application.
  • the first end T31 of the third switch T30 is electrically coupled to the local stage frame signal STV(N).
  • FIG. 5 is a schematic diagram showing an embodiment applied to a shift temporary storage circuit according to the method of the present application.
  • the first end T31 of the third switch T30 is electrically coupled to the DC signal VDD_LC for providing power to precharge the shift register circuit.
  • the DC signal is used to boost the potential of the control terminal T33 of the third switch T30.
  • a display panel of the present application includes: a first substrate and a second substrate disposed opposite to each other; and a liquid crystal layer disposed between the first substrate and the second substrate; a polarizer disposed on an outer surface of the first substrate; and a second polarizer disposed on an outer surface of the second substrate, wherein polarization directions of the first polarizer and the second polarizer are mutually Parallel; and a shift register circuit including the features of any of the above embodiments.
  • the application can maintain the original process requirements and product cost without significantly changing the existing production process; when the frequency signal is cut into a low potential, the active switch connecting the frequency signal can no longer generate a pressure difference across the pressure, avoiding the active switch. Leakage, being turned on, etc. generate extra power; the improvement is simple and easy, and it also helps to improve the reliability of the circuit; it can be used for the manufacture of panels of various sizes, and the applicability is relatively high.

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Abstract

一种移位暂存电路及其应用的显示面板，移位暂存电路包括多级移位寄存器，每一移位寄存器（300）包括：第一开关（T10），此第一开关（T10）的控制端（T13）电性耦接第一节点（P1），此第一开关（T10）的第一端（T11）电性耦接频率讯号（CLK）；第二开关（T20），此第二开关（T20）的控制端（T23）电性耦接此第一节点（P1），此第二开关（T20）的第一端（T21）电性耦接此频率讯号（CLK），此第二开关（T20）的第二端（T22）电性耦接次级帧讯号（STV(N+1)）；第三开关（T30），此第三开关（T30）的控制端（T33）电性耦接本级帧讯号（STV（N）），此第三开关（T30）的第二端（T32）电性耦接此第一节点（P1）；第四开关（T40），此第四开关（T40）的控制端（T43）电性耦接次级帧讯号（STV（N+1）），此第四开关（T40）的第一端（T41）电性耦接此第一开关（T10）的第二端（T12），此第四开关（T40）的第二端（T42）电性耦接本级栅极讯号G(N)。

Description

移位暂存电路及其应用的显示面板 技术领域
本申请涉及一种显示技术领域，特别涉及一种移位暂存电路及其应用的显示面板。
背景技术
近年来，随着科技的进步，平面液晶显示器逐渐普及化，其具有轻薄等优点。目前平面液晶显示器驱动电路主要是由面板外连接IC来组成，但是此方法无法将产品的成本降低、也无法使面板更薄型化。
且液晶显示设备中通常具有栅极驱动电路、源极驱动电路和像素阵列。像素阵列中具有多个像素电路，每一个像素电路依据栅极驱动电路提供的扫描讯号开启和关闭，并依据源极驱动电路提供的数据讯号，显示数据画面。以栅极驱动电路来说，栅极驱动电路通常具有多级移位寄存器，并藉由一级移位寄存器传递至下一级移位寄存器的方式，来输出扫描讯号到像素阵列中，以依序地开启像素电路，使像素电路接收数据讯号。
因此在驱动电路的制程中，便直接将栅极驱动电路制作在阵列基板上，来取代由外连接IC制作的驱动芯片，此种被称为栅极阵列驱动(Gate On Array，GOA)技术的应用可直接做在面板周围，减少制作程序、降低产品成本且使面板更薄型化。
在栅极阵列驱动技术中，将原本的栅极集成电路(Gate IC)拆分成升压集成电路(level shifter IC)和移位寄存器(shift register)两部分，升压集成电路做在驱动板上，移位寄存器做在了面板上，这样便不需要栅极集成电路了，因此可以进一步压缩边框长度。
然而，移位寄存器连接频率讯号的主动开关，在频率讯号切入低电位时，很容易因为频率讯号的低电位小于低默认电位VSS，导致此主动开闭被打开。而且对于面板充电来说，在一帧的时间内，一行只被打开一次，剩下的绝大部分时间是关闭的，所以此类主动开关被打开即造成功耗相对较高的情形。对于大尺寸且高分辨率的面板来说更是如此。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种移位暂存电路，能在频率讯号切入低电位时，使连接频率讯号的主动开关不再有跨压的压差产生，避免主动开关漏电，被打开等产生额外功率。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种移位暂存电路，包括多级移位寄存器，每一移位寄存器包括：第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接频率讯号；第二开关，所述第二开 关的控制端电性耦接所述第一节点，所述第二开关的第一端电性耦接所述频率讯号，所述第二开关的第二端电性耦接次级帧讯号；第三开关，所述第三开关的控制端电性耦接本级帧讯号，所述第三开关的第二端电性耦接所述第一节点；第四开关，所述第四开关的控制端电性耦接次级帧讯号，所述第四开关的第一端电性耦接所述第一开关的第二端，所述第四开关的第二端电性耦接本级栅极讯号。
在本申请的一实施例中，更包括第五开关，所述第五开关的控制端电性耦接第二节点，所述第五开关的第一端电性耦接所述本级栅极讯号，所述第五开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号。
在本申请的一实施例中，更包括第六开关，所述第六开关的控制端电性耦接第二节点，所述第六开关的第一端电性耦接所述第一节点，所述第六开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号。
在本申请的一实施例中，更包括子下拉电路，电性耦接于所述第一节点、所述本级栅极讯号及低默认电位。
在本申请的一实施例中，更包括子下拉电路控制器，电性耦接于所述低默认电位及所述子下拉电路。
在本申请的一实施例中，所述第三开关的第一端电性耦接前级栅极讯号。
在本申请的一实施例中，所述第三开关的第一端电性耦接本级帧讯号。
在本申请的一实施例中，所述第三开关的第一端电性耦接直流讯号用以提供电源给予预充所述移位暂存电路。
本申请的次一目的为一种显示面板，其包括：相对设置的第一基板与第二基板；及移位暂存电路，设置于所述第一基板或所述第二基板上，包括多级移位寄存器，每一移位寄存器包括：第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接频率讯号；第二开关，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第一端电性耦接所述频率讯号，所述第二开关的第二端电性耦接次级帧讯号；第三开关，所述第三开关的控制端电性耦接本级帧讯号，所述第三开关的第二端电性耦接所述第一节点；第四开关，所述第四开关的控制端电性耦接次级帧讯号，所述第四开关的第一端电性耦接所述第一开关的第二端，所述第四开关的第二端电性耦接本级栅极讯号。
在本申请的一实施例中，更包括第五开关，所述第五开关的控制端电性耦接第二节点，所述第五开关的第一端电性耦接所述本级栅极讯号，所述第五开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号。
在本申请的一实施例中，更包括第六开关，所述第六开关的控制端电性耦接第二节点，所述第六开关的第一端电性耦接所述第一节点，所述第六开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号。
在本申请的一实施例中，更包括子下拉电路，电性耦接于所述第一节点、所述本级栅极讯号及低默认电位。
在本申请的一实施例中，更包括子下拉电路控制器，电性耦接于所述低默认电位及所述子下拉电路。
在本申请的一实施例中，所述第三开关的第一端电性耦接前级栅极讯号。
在本申请的一实施例中，所述第三开关的第一端电性耦接本级帧讯号。
在本申请的一实施例中，所述第三开关的第一端电性耦接直流讯号。
在本申请的一实施例中，所述直流讯号用以提升所述第三开关的控制端电位。
本申请解决其技术问题还可采用以下技术措施进一步实现。依据本申请提出的一种移位暂存电路，包括多级移位寄存器，每一移位寄存器包括：第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接频率讯号；第二开关，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第一端电性耦接所述频率讯号，所述第二开关的第二端电性耦接次级帧讯号；第三开关，所述第三开关的控制端电性耦接本级帧讯号，所述第三开关的第二端电性耦接所述第一节点；第四开关，所述第四开关的控制端电性耦接次级帧讯号，所述第四开关的第一端电性耦接所述第一开关的第二端，所述第四开关的第二端电性耦接本级栅极讯号；第五开关，所述第五开关的控制端电性耦接第二节点，所述第五开关的第一端电性耦接所述本级栅极讯号，所述第五开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号；第六开关，所述第六开关的控制端电性耦接第二节点，所述第六开关的第一端电性耦接所述第一节点，所述第六开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号；子下拉电路，电性耦接于所述第一节点、所述本级栅极讯号及低默认电位；其中，所述第三开关的第一端电性耦接前级栅极讯号、本级帧讯号或直流讯号。
有益效果
本申请仅需小微幅的调整移位暂存电路，尽可能维持原制程需求和产品成本；能在频率讯号切入低电位时，使连接频率讯号的主动开关不再有跨压的压差产生，避免主动开关漏电，被打开等产生额外功率；改进简便易行，亦有助提升电路可靠性；能使用于各种尺寸面板的制作，适用性相对较高。
附图说明
图1a为范例性的液晶显示器示意图。
图1b为范例性的移位寄存器电路示意图。
图1c为范例性的栅极驱动电路基板的波形示意图。
图2为显示依据本申请的方法，一实施例应用于移位暂存电路示意图。
图3为显示依据本申请的方法，一实施例应用于移位暂存电路示意图。
图4为显示依据本申请的方法，一实施例应用于移位暂存电路示意图。
图5为显示依据本申请的方法，一实施例应用于移位暂存电路示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种移位暂存电路及其应用的显示面板，其具体实施方式、结构、特征及其功效，详细说明如后。
本申请的显示面板例如为液晶显示面板、OLED显示面板、QLED显示面板或其他显示面板，以液晶显示面板为例，液晶显示面板可包括主动阵列(thin film transistor，TFT)基板、彩色滤光层(color filter，CF)基板与形成于两基板之间的液晶层。
在一些实施例中，本申请的显示面板可为曲面型显示面板。
在一些实施例中，本申请的主动阵列(TFT)及彩色滤光层(CF)可形成于同一基板上。
图1a为范例性的液晶显示器示意图。请参照图1a，一种栅极阵列驱动的液晶显示器100，包括一彩色滤光片基板110、一主动阵列基板120。栅极集成电路被分成了两部分，一是升压模块103，一是移位寄位器105。所述升压模块103设置在在驱动电路板130上，移位寄存器105则是设置在主动阵列基板120上，由于移位寄存器105占的面积很小，因此栅极阵列驱动(GOA)面板一般都可以做到超窄边框。
图1b为范例性的移位寄存器电路示意图，一般是通过汤普森电路改良设计而得。请参照图1b，一种移位寄存器电路200，包括一输入脉冲讯号电路210及一频率讯号电路220。频率讯号CLK是升压模块103输出的，栅极信号G(N)是由显示面板中的栅极走线(Gate Line)提供，低默认电位VSS是栅极走线关闭的低电平，帧讯号STV(N)是起始信号。
当本级帧讯号STV(N)启动后，第三开关T30被打开，前级栅极信号G(N-1)给第一节点P1充电，同时第一开关T10和第二开关T20被打开，这样当频率讯号CLK为高电平时，次级帧讯号STV(N+1)和本级栅极信号G(N)就输出高电平，其中次级帧讯号STV(N+1)也作为次一级移位寄存器电路的起始信号，本级栅极信号G(N)不仅打开显示面板当前第N行栅极走线连接的主动开关(TFT)，同时也作为次一级移位寄存器电路的控制信号。当次级G栅极信号(N+1)也输出高电平时，同步会打开第五开关T50和第四开关T40使本级栅极信号G(N)输出为低默认电位VSS，从而关闭显示面板当前第N行的主动开关。这样便完成了下一行主动开关被打开的同时，上一行主动开关被关闭，这样逐次进行传递，完成依次打开所有栅极走线所连接主动开关。
图1c为范例性的栅极驱动电路基板的波形示意图，其为图1b所绘示电路的波形示意图。请参照图1c，频率讯号CLK与次级频率讯号XCLK两者是为极性相反的信号，分别控制栅极走线奇数行与偶数行连接主动开关(TFT)的充电动作。
由于为了让第三开关T3更好的关闭，频率讯号CLK和次级频率讯号XCLK的低调整电位为VSS1，低调整电位VSS1的电压准位小于低默认电位VSS，这样帧讯号STV得到的低电平信号也是低调整电位VSS1，第三开关T3就可以关闭得比较好。
其中，本级栅极信号G(N)充电完毕后，本级栅极信号G(N)和第一节点P1一直保持为低默认电位VSS，即第一开关T10的控制端T13(G极)和第二端T12(S极)处于低默认电位。当频率讯号CLK为高电位时，第一开关T10可以完全关闭没有问题，可是当频率讯号CLK为低调整电位VSS1时，因为低调整电位VSS1的电压准位小于低默认电位VSS，所以这时第一开关T10会被打开，而且第一开关T10的第一端T11(D极)和第二端T12(S极)的跨压维持 为低默认电位VSS与低调整电位VSS1的压差值(VSS-VSS1)，第一开关T10的功耗就会较大。而且对于显示面板充电来说，在一帧的时间内，一行只被打开一次，剩下的绝大部分时间是关闭的，所以第一开关T10会维持大量的功耗。
图2为显示依据本申请的方法，一实施例应用于移位暂存电路示意图。请参照图2，一种移位暂存电路300，包括多级移位寄存器，以虚框范围表明每一级的移位寄存器，包括：第一开关T10，所述第一开关T10的控制端T13电性耦接第一节点P1，所述第一开关T10的第一端T11电性耦接频率讯号CLK；第二开关T20，所述第二开关T20的控制端T23电性耦接所述第一节点P1，所述第二开关T20的第一端T21电性耦接所述频率讯号CLK，所述第二开关T20的第二端T22电性耦接次级帧讯号STV(N+1)；第三开关T30，所述第三开关T30的控制端T33电性耦接本级帧讯号STV(N)，所述第三开关T30的第二端T32电性耦接所述第一节点P1；第四开关T40，所述第四开关T40的控制端T43电性耦接次级帧讯号STV(N+1)，所述第四开关T40的第一端T41电性耦接所述第一开关T10的第二端T12，所述第四开关T40的第二端T42电性耦接本级栅极讯号G(N)。
在一些实施例中，移位暂存电路300更包括第五开关T50，所述第五开关T50的控制端T53电性耦接第二节点P2，所述第五开关T50的第一端T51电性耦接所述本级栅极讯号G(N)，所述第五开关T50的第二端T52电性耦接低默认电位VSS。
在一些实施例中，移位暂存电路300更包括第六开关T60，所述第六开关T60的控制端T63电性耦接第二节点P2，所述第六开关T60的第一端T61电性耦接所述第一节点P1，所述第六开关T60的第二端T62电性耦接低默认电位VSS。
在一些实施例中，所述第二节点P2电性耦接次级栅极讯号G(N+1)。
在一些实施例中，所述第三开关T30的第一端T31电性耦接前级栅极讯号G(N-1)。
续请参考图2，当第N行栅极走线进行正常充电时，第一开关T10和第二开关T20照常被打开，此时次级帧讯号STV(N+1)为高电平，第四开关T40也被打开，本级栅极讯号G(N)可被正常输出。当第N行栅极走线充电完毕后，本级栅极信号G(N)为低默认电位VSS，次级帧讯号STV(N+1)为低调整电位VSS，第四开关T40被关闭而形成断路，第一开关T10的第一端T11和第二端T12，即其D极与S极两端不会再有跨压的压差产生，所以第一开关T10不会产生额外的功耗。
图3为显示依据本申请的方法，一实施例应用于移位暂存电路示意图。请参照图3，在一些实施例中，移位暂存电路300更包括子下拉电路420，电性耦接于所述第一节点P1、所述本级栅极讯号G(N)及低默认电位VSS。
在一些实施例中，移位暂存电路300更包括子下拉电路控制器410，电性耦接于所述低默认电位VSS及所述子下拉电路420。
图4为显示依据本申请的方法，一实施例应用于移位暂存电路示意图。请参照图5，在一些实施例中，所述第三开关T30的第一端T31电性耦接本级帧讯号STV(N)。
图5为显示依据本申请的方法，一实施例应用于移位暂存电路示意图。请参照图6，在一些实施例中，所述第三开关T30的第一端T31电性耦接直流讯号VDD_LC用以提供电源给予预充所述移位暂存电路。所述直流讯号用以提升所述第三开关T30的控制端T33电位。
在本申请一实施例中，本申请的一种显示面板，包括：相对设置的第一基板与第二基板；设置于所述第一基板与所述第二基板之间的液晶层；第一偏光片设置于所述第一基板的外表面上；以及第二偏光片设置于所述第二基板的外表面上，其中所述第一偏光片与所述第二偏光片的偏振方向为互相平行；及包括上述任何一种实施例的技术特征的移位暂存电路。
本申请可以不大幅改变现有生产流程的前提，维持原制程需求和产品成本；能在频率讯号切入低电位时，使连接频率讯号的主动开关不再有跨压的压差产生，避免主动开关漏电，被打开等产生额外功率；改进简便易行，亦有助提升电路可靠性；能使用于各种尺寸面板的制作，适用性相对较高。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请具体的实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种移位暂存电路，包括多级移位寄存器，每一移位寄存器包括：
    第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接频率讯号；
    第二开关，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第一端电性耦接所述频率讯号，所述第二开关的第二端电性耦接次级帧讯号；
    第三开关，所述第三开关的控制端电性耦接本级帧讯号，所述第三开关的第二端电性耦接所述第一节点；
    第四开关，所述第四开关的控制端电性耦接次级帧讯号，所述第四开关的第一端电性耦接所述第一开关的第二端，所述第四开关的第二端电性耦接本级栅极讯号。
  2. 如权利要求1所述的移位暂存电路，更包括第五开关，所述第五开关的控制端电性耦接第二节点，所述第五开关的第一端电性耦接所述本级栅极讯号，所述第五开关的第二端电性耦接低默认电位。
  3. 如权利要求2所述的移位暂存电路，其中，所述第二节点电性耦接次级栅极讯号。
  4. 如权利要求1所述的移位暂存电路，更包括第六开关，所述第六开关的控制端电性耦接第二节点，所述第六开关的第一端电性耦接所述第一节点，所述第六开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号。
  5. 如权利要求1所述的移位暂存电路，更包括子下拉电路，电性耦接于所述第一节点、所述本级栅极讯号及低默认电位。
  6. 如权利要求5所述的移位暂存电路，更包括子下拉电路控制器，电性耦接于所述低默认电位及所述子下拉电路。
  7. 如权利要求1所述的移位暂存电路，其中，所述第三开关的第一端电性耦接前级栅极讯号。
  8. 如权利要求1所述的移位暂存电路，其中，所述第三开关的第一端电性耦接本级帧讯号。
  9. 如权利要求1所述的移位暂存电路，其中，所述第三开关的第一端电性耦接直流讯号。
  10. 如权利要求9所述的移位暂存电路，其中，所述直流讯号用以提升所述第三开关的控制端电位。
  11. 一种显示面板，包括：
    第一基板；
    第二基板，与所述第一基板相对设置；以及
    移位暂存电路，设置于所述第一基板或所述第二基板上，包括多级移位寄存器，每一移位寄存器包括：
    第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接频率讯号；
    第二开关，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第一端电性耦接所述频率讯号，所述第二开关的第二端电性耦接次级帧讯号；
    第三开关，所述第三开关的控制端电性耦接本级帧讯号，所述第三开关的第二端电性耦接所述第一节点；
    第四开关，所述第四开关的控制端电性耦接次级帧讯号，所述第四开关的第一端电性耦接所述第一开关的第二端，所述第四开关的第二端电性耦接本级栅极讯号。
  12. 如权利要求11所述的显示面板，更包括第五开关，所述第五开关的控制端电性耦接第二节点，所述第五开关的第一端电性耦接所述本级栅极讯号，所述第五开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号。
  13. 如权利要求11所述的显示面板，更包括第六开关，所述第六开关的控制端电性耦接第二节点，所述第六开关的第一端电性耦接所述第一节点，所述第六开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号。
  14. 如权利要求11所述的显示面板，更包括子下拉电路，电性耦接于所述第一节点、所述本级栅极讯号及低默认电位。
  15. 如权利要求14所述的显示面板，更包括子下拉电路控制器，电性耦接于所述低默认电位及所述子下拉电路。
  16. 如权利要求11所述的显示面板，其中，所述第三开关的第一端电性耦接前级栅极讯号。
  17. 如权利要求11所述的显示面板，其中，所述第三开关的第一端电性耦接本级帧讯号。
  18. 如权利要求11所述的显示面板，其中，所述第三开关的第一端电性耦接直流讯号。
  19. 如权利要求18所述的显示面板，其中，所述直流讯号用以提升所述第三开关的控制端电位。
  20. 一种移位暂存电路，包括多级移位寄存器，每一移位寄存器包括：
    第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接频率讯号；
    第二开关，所述第二开关的控制端电性耦接所述第一节点，所述第二开关的第一端电性耦接所述频率讯号，所述第二开关的第二端电性耦接次级帧讯号；
    第三开关，所述第三开关的控制端电性耦接本级帧讯号，所述第三开关的第二端电性耦接所述第一节点；
    第四开关，所述第四开关的控制端电性耦接次级帧讯号，所述第四开关的第一端电性耦接所述 第一开关的第二端，所述第四开关的第二端电性耦接本级栅极讯号；
    第五开关，所述第五开关的控制端电性耦接第二节点，所述第五开关的第一端电性耦接所述本级栅极讯号，所述第五开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号；
    第六开关，所述第六开关的控制端电性耦接第二节点，所述第六开关的第一端电性耦接所述第一节点，所述第六开关的第二端电性耦接低默认电位，所述第二节点电性耦接次级栅极讯号；子下拉电路，电性耦接于所述第一节点、所述本级栅极讯号及低默认电位；
    其中，所述第三开关的第一端电性耦接前级栅极讯号、本级帧讯号或直流讯号。
PCT/CN2017/092140 2017-05-27 2017-07-07 移位暂存电路及其应用的显示面板 WO2018218730A1 (zh)

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