WO2020151065A1 - Goa器件及栅极驱动电路、显示面板 - Google Patents

Goa器件及栅极驱动电路、显示面板 Download PDF

Info

Publication number
WO2020151065A1
WO2020151065A1 PCT/CN2019/078191 CN2019078191W WO2020151065A1 WO 2020151065 A1 WO2020151065 A1 WO 2020151065A1 CN 2019078191 W CN2019078191 W CN 2019078191W WO 2020151065 A1 WO2020151065 A1 WO 2020151065A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
pull
electrically connected
source
Prior art date
Application number
PCT/CN2019/078191
Other languages
English (en)
French (fr)
Inventor
徐向阳
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020151065A1 publication Critical patent/WO2020151065A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • This application relates to the display field, and in particular to a GOA device, a gate drive circuit, and a display panel.
  • the Gate Drive ON Array (GOA) technology is to integrate the scan line drive circuit on the array substrate of the liquid crystal panel, thereby reducing product cost in terms of material cost and manufacturing process.
  • This application provides a GOA device, a gate drive circuit, and a display panel to realize the design of a narrow frame of the display panel.
  • This application proposes a GOA device, wherein the GOA device includes at least two GOA units, and the GOA unit includes:
  • the pull-up control module is configured to receive the first scan signal, and generate at least a 2N-1 level scan level signal and a 2N level scan level signal according to the control of the first scan signal;
  • At least one first pull-up module is configured to receive the scan level signal of the 2N-1 level and the clock signal of the 2N-1 level provided by the clock signal source, and is used to The scan level signal of the 2N-1 stage and the clock signal of the 2N-1 stage raise the scan signal of the 2N-1 stage;
  • At least one second pull-up module is configured to receive the scan level signal of the 2N level and the clock signal of the 2N level provided by the clock signal source, and is configured to The 2N-th stage scanning level signal and the 2N-th stage clock signal raise the 2N-th stage scanning signal;
  • a pull-down module for receiving a second scan signal and a constant voltage low level provided by a constant voltage low level source, and for outputting the constant voltage low level to the GOA unit according to the second scan signal
  • the output terminal
  • the pull-down sustaining module is used to maintain the scan level signal of the 2N-1 stage and the low level of the scan signal of the 2N-1 stage, the scan level signal of the 2N stage and the second Low level of 2N level scanning signal;
  • At least one first bootstrap capacitor where the first bootstrap capacitor is used to generate a high level of the scan level signal of the 2N-1th stage;
  • At least one second bootstrap capacitor where the second bootstrap capacitor is used to generate the high level of the 2Nth level scan level signal
  • N is a positive integer.
  • the GOA unit includes a first pull-up module and a second pull-up module
  • the first pull-up module includes a twenty-first thin film transistor, the gate of the twenty-first thin film transistor is electrically connected to the output terminal of the pull-up control module, the drain is electrically connected to the first clock signal source, and the source The pole is electrically connected to the output terminal of the scan signal of the 2N-1th stage;
  • the second pull-up module includes a seventieth thin film transistor, the gate of the seventieth thin film transistor is electrically connected to the output terminal of the pull-up control module, the drain is electrically connected to the second clock signal source, and the source is It is electrically connected to the output terminal of the scan signal of the 2Nth stage.
  • the pull-down module includes a thirty-first thin film transistor, a forty-first thin film transistor, and at least one seventy-first thin film transistor;
  • the gate of the thirty-first thin film transistor is electrically connected to the output terminal of the second scan signal, the source is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the 2N-1 stage The output terminal of the scanning signal;
  • the gate of the forty-first thin film transistor is electrically connected to the output terminal of the second scan signal, the source is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module ;
  • the gate of the seventy-first thin film transistor is electrically connected to the output terminal of the second scan signal, the source is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module .
  • the pull-down maintenance module includes a first pull-down maintenance unit and a second pull-down maintenance unit;
  • the first pull-down sustaining unit includes a fifty-first thin film transistor, a fifty-second thin film transistor, a fifty-third thin film transistor, a fifty-fourth thin film transistor, a forty-second thin film transistor, and a thirty-second thin film transistor , And at least one seventy-second thin film transistor;
  • the gate and drain of the fifty-first thin film transistor are connected to a first square wave signal, and the source is electrically connected to the drain of the fifty-second thin film transistor and the gate of the fifty-third thin film transistor ;
  • the gate of the fifty-second thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the drain of the fifty-third thin film transistor is connected to the first square wave signal, and the source is electrically connected to the drain of the fifty-fourth thin film transistor, the gate of the forty-second thin film transistor, and the The gate of the thirty-second thin film transistor;
  • the gate of the fifty-fourth thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the source of the forty-second thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module;
  • the source of the thirty-second thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the 2N-1th stage scanning signal;
  • the source of the seventy-second thin film transistor is electrically connected to the constant-voltage low-level source, and the drain is electrically connected to the output terminal of the 2N-th stage scanning signal;
  • the second pull-down sustain unit includes a 61st thin film transistor, a 62nd thin film transistor, a 63rd thin film transistor, a 64th thin film transistor, a 43rd thin film transistor, a 33rd thin film transistor, And at least one seventy-third thin film transistor;
  • the gate and drain of the sixty-first thin film transistor are connected to a second square wave signal, and the source is electrically connected to the drain of the sixty-second thin film transistor and the gate of the sixty-third thin film transistor ;
  • the gate of the 62nd thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the drain of the 63rd thin film transistor is connected to the second square wave signal, and the source is electrically connected to the drain of the 64th thin film transistor, the gate of the 43rd thin film transistor and the The gate of the thirty-third thin film transistor;
  • the gate of the 64th thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the source of the forty-third thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module;
  • the source of the thirty-third thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the scan signal of the 2N-1 stage;
  • the source of the seventy-third thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the 2N-th stage scanning signal.
  • the GOA unit includes at least a first bootstrap capacitor and a second bootstrap capacitor, and the number of the bootstrap capacitors is equal to the number of the pull-up modules.
  • the first bootstrap capacitor is arranged between the output terminal of the pull-up control module and the output terminal of the scan signal of the 2N-1 stage
  • the second bootstrap capacitor is arranged between the output terminal of the pull-up control module and the output terminal of the 2N-th stage scan signal.
  • the pull-up control module includes an eleventh thin film transistor, and the gate and drain of the eleventh thin film transistor are electrically connected to the scan signal G(2N-5 ), the source is electrically connected to the output terminal of the pull-up control module.
  • This application also proposes a gate drive circuit, which includes:
  • At least a first clock signal source where the first clock signal source is used to provide a 2N-1 level clock signal;
  • At least a second clock signal source where the second clock signal source is used to provide a 2N-th level clock signal
  • Constant voltage low level source used to provide constant voltage low level
  • the GOA device includes at least two GOA units, and the GOA units include:
  • the pull-up control module is configured to receive the first scan signal, and generate at least a 2N-1 level scan level signal and a 2N level scan level signal according to the control of the first scan signal;
  • At least one first pull-up module the first pull-up module is configured to receive the scan level signal of the 2N-1 level and the clock signal of the 2N-1 level provided by the first clock signal source, and Used to pull up the scan signal of the 2N-1 level according to the scan level signal of the 2N-1 level and the clock signal of the 2N-1 level;
  • At least one second pull-up module is configured to receive the scan level signal of the 2N level and the clock signal of the 2N level provided by the second clock signal source, and is used to The scan level signal of the 2N stage and the clock signal of the 2N stage raise the scan signal of the 2N stage;
  • a pull-down module for receiving a second scan signal and a constant voltage low level provided by a constant voltage low level source, and for outputting the constant voltage low level to the GOA unit according to the second scan signal
  • the output terminal
  • the pull-down sustaining module is used to maintain the scan level signal of the 2N-1 stage and the low level of the scan signal of the 2N-1 stage, the scan level signal of the 2N stage and the second Low level of 2N level scanning signal;
  • At least one first bootstrap capacitor where the first bootstrap capacitor is used to generate a high level of the scan level signal of the 2N-1th stage;
  • At least one second bootstrap capacitor where the second bootstrap capacitor is used to generate the high level of the 2Nth level scan level signal
  • the constant voltage low-level source is electrically connected to the pull-down maintaining module and the pull-down module
  • the first clock signal source is electrically connected to the first pull-up module
  • the second clock signal source is electrically connected to the pull-down module.
  • the second pull-up module is electrically connected;
  • N is a positive integer.
  • the GOA unit includes a first pull-up module and a second pull-up module
  • the first pull-up module includes a twenty-first thin film transistor, the gate of the twenty-first thin film transistor is electrically connected to the output terminal of the pull-up control module, the drain is electrically connected to the first clock signal source, and the source The pole is electrically connected to the output terminal of the scan signal of the 2N-1th stage;
  • the second pull-up module includes a seventieth thin film transistor, the gate of the seventieth thin film transistor is electrically connected to the output terminal of the pull-up control module, the drain is electrically connected to the second clock signal source, and the source is It is electrically connected to the output terminal of the scan signal of the 2Nth stage.
  • the pull-down module includes a thirty-first thin film transistor, a forty-first thin film transistor, and at least one seventy-first thin film transistor;
  • the gate of the thirty-first thin film transistor is electrically connected to the output terminal of the second scan signal, the source is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the 2N-1 stage The output terminal of the scanning signal;
  • the gate of the forty-first thin film transistor is electrically connected to the output terminal of the second scan signal, the source is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module ;
  • the gate of the seventy-first thin film transistor is electrically connected to the output terminal of the second scan signal, the source is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module .
  • the pull-down maintaining module includes a first pull-down maintaining unit and a second pull-down maintaining unit;
  • the first pull-down sustaining unit includes a fifty-first thin film transistor, a fifty-second thin film transistor, a fifty-third thin film transistor, a fifty-fourth thin film transistor, a forty-second thin film transistor, and a thirty-second thin film transistor , And at least one seventy-second thin film transistor;
  • the gate and drain of the fifty-first thin film transistor are connected to a first square wave signal, and the source is electrically connected to the drain of the fifty-second thin film transistor and the gate of the fifty-third thin film transistor ;
  • the gate of the fifty-second thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the drain of the fifty-third thin film transistor is connected to the first square wave signal, and the source is electrically connected to the drain of the fifty-fourth thin film transistor, the gate of the forty-second thin film transistor, and the The gate of the thirty-second thin film transistor;
  • the gate of the fifty-fourth thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the source of the forty-second thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module;
  • the source of the thirty-second thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the 2N-1th stage scanning signal;
  • the source of the seventy-second thin film transistor is electrically connected to the constant-voltage low-level source, and the drain is electrically connected to the output terminal of the 2N-th stage scanning signal;
  • the second pull-down sustain unit includes a 61st thin film transistor, a 62nd thin film transistor, a 63rd thin film transistor, a 64th thin film transistor, a 43rd thin film transistor, a 33rd thin film transistor, And at least one seventy-third thin film transistor;
  • the gate and drain of the sixty-first thin film transistor are connected to a second square wave signal, and the source is electrically connected to the drain of the sixty-second thin film transistor and the gate of the sixty-third thin film transistor ;
  • the gate of the 62nd thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the drain of the 63rd thin film transistor is connected to the second square wave signal, and the source is electrically connected to the drain of the 64th thin film transistor, the gate of the 43rd thin film transistor and the The gate of the thirty-third thin film transistor;
  • the gate of the 64th thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the source of the forty-third thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module;
  • the source of the thirty-third thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the scan signal of the 2N-1 stage;
  • the source of the seventy-third thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the 2N-th stage scanning signal.
  • the GOA unit includes at least a first bootstrap capacitor and a second bootstrap capacitor, and the number of the bootstrap capacitors is equal to the number of the pull-up modules.
  • the first bootstrap capacitor is arranged between the output terminal of the pull-up control module and the output terminal of the scan signal of the 2N-1 stage
  • the second bootstrap capacitor is arranged between the output terminal of the pull-up control module and the output terminal of the 2N-th stage scan signal.
  • the pull-up control module includes an eleventh thin film transistor, and the gate and drain of the eleventh thin film transistor are electrically connected to the scan signal G(2N-5 ), the source is electrically connected to the output terminal of the pull-up control module.
  • This application also proposes a display panel including a gate driving circuit, wherein the gate driving circuit includes:
  • At least a first clock signal source where the first clock signal source is used to provide a 2N-1 level clock signal;
  • At least a second clock signal source where the second clock signal source is used to provide a 2N-th level clock signal
  • Constant voltage low level source used to provide constant voltage low level
  • the GOA device includes at least two GOA units, and the GOA units include:
  • the pull-up control module is configured to receive the first scan signal, and generate at least a 2N-1 level scan level signal and a 2N level scan level signal according to the control of the first scan signal;
  • At least one first pull-up module the first pull-up module is configured to receive the scan level signal of the 2N-1 level and the clock signal of the 2N-1 level provided by the first clock signal source, and Used to pull up the scan signal of the 2N-1 level according to the scan level signal of the 2N-1 level and the clock signal of the 2N-1 level;
  • At least one second pull-up module is configured to receive the scan level signal of the 2N level and the clock signal of the 2N level provided by the second clock signal source, and is used to The scan level signal of the 2N stage and the clock signal of the 2N stage raise the scan signal of the 2N stage;
  • a pull-down module for receiving a second scan signal and a constant voltage low level provided by a constant voltage low level source, and for outputting the constant voltage low level to the GOA unit according to the second scan signal
  • the output terminal
  • the pull-down sustaining module is used to maintain the scan level signal of the 2N-1 stage and the low level of the scan signal of the 2N-1 stage, the scan level signal of the 2N stage and the second Low level of 2N level scanning signal;
  • At least one first bootstrap capacitor where the first bootstrap capacitor is used to generate a high level of the scan level signal of the 2N-1th stage;
  • At least one second bootstrap capacitor where the second bootstrap capacitor is used to generate the high level of the 2Nth level scan level signal
  • the constant voltage low-level source is electrically connected to the pull-down maintaining module and the pull-down module
  • the first clock signal source is electrically connected to the first pull-up module
  • the second clock signal source is electrically connected to the pull-down module.
  • the second pull-up module is electrically connected;
  • N is a positive integer.
  • the GOA unit includes a first pull-up module and a second pull-up module
  • the first pull-up module includes a twenty-first thin film transistor, the gate of the twenty-first thin film transistor is electrically connected to the output terminal of the pull-up control module, the drain is electrically connected to the first clock signal source, and the source The pole is electrically connected to the output terminal of the scan signal of the 2N-1th stage;
  • the second pull-up module includes a seventieth thin film transistor, the gate of the seventieth thin film transistor is electrically connected to the output terminal of the pull-up control module, the drain is electrically connected to the second clock signal source, and the source is It is electrically connected to the output terminal of the scan signal of the 2Nth stage.
  • the pull-down module includes a thirty-first thin film transistor, a forty-first thin film transistor, and at least one seventy-first thin film transistor;
  • the gate of the thirty-first thin film transistor is electrically connected to the output terminal of the second scan signal, the source is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the 2N-1 stage The output terminal of the scanning signal;
  • the gate of the forty-first thin film transistor is electrically connected to the output terminal of the second scan signal, the source is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module ;
  • the gate of the seventy-first thin film transistor is electrically connected to the output terminal of the second scan signal, the source is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module .
  • the pull-down maintenance module includes a first pull-down maintenance unit and a second pull-down maintenance unit;
  • the first pull-down sustaining unit includes a fifty-first thin film transistor, a fifty-second thin film transistor, a fifty-third thin film transistor, a fifty-fourth thin film transistor, a forty-second thin film transistor, and a thirty-second thin film transistor , And at least one seventy-second thin film transistor;
  • the gate and drain of the fifty-first thin film transistor are connected to a first square wave signal, and the source is electrically connected to the drain of the fifty-second thin film transistor and the gate of the fifty-third thin film transistor ;
  • the gate of the fifty-second thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the drain of the fifty-third thin film transistor is connected to the first square wave signal, and the source is electrically connected to the drain of the fifty-fourth thin film transistor, the gate of the forty-second thin film transistor, and the The gate of the thirty-second thin film transistor;
  • the gate of the fifty-fourth thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the source of the forty-second thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module;
  • the source of the thirty-second thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the 2N-1th stage scanning signal;
  • the source of the seventy-second thin film transistor is electrically connected to the constant-voltage low-level source, and the drain is electrically connected to the output terminal of the 2N-th stage scanning signal;
  • the second pull-down sustain unit includes a 61st thin film transistor, a 62nd thin film transistor, a 63rd thin film transistor, a 64th thin film transistor, a 43rd thin film transistor, a 33rd thin film transistor, And at least one seventy-third thin film transistor;
  • the gate and drain of the sixty-first thin film transistor are connected to a second square wave signal, and the source is electrically connected to the drain of the sixty-second thin film transistor and the gate of the sixty-third thin film transistor ;
  • the gate of the 62nd thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the drain of the 63rd thin film transistor is connected to the second square wave signal, and the source is electrically connected to the drain of the 64th thin film transistor, the gate of the 43rd thin film transistor and the The gate of the thirty-third thin film transistor;
  • the gate of the 64th thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant voltage low level source;
  • the source of the forty-third thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the pull-up control module;
  • the source of the thirty-third thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the scan signal of the 2N-1 stage;
  • the source of the seventy-third thin film transistor is electrically connected to the constant voltage low-level source, and the drain is electrically connected to the output terminal of the 2N-th stage scanning signal.
  • the GOA unit includes at least a first bootstrap capacitor and a second bootstrap capacitor, and the number of the bootstrap capacitors is equal to the number of the pull-up modules.
  • the first bootstrap capacitor is arranged between the output terminal of the pull-up control module and the output terminal of the scan signal of the 2N-1 stage
  • the second bootstrap capacitor is arranged between the output terminal of the pull-up control module and the output terminal of the 2N-th stage scan signal.
  • the pull-up control module includes an eleventh thin film transistor, and the gate and drain of the eleventh thin film transistor are electrically connected to the scan signal G(2N-5 ), the source is electrically connected to the output terminal of the pull-up control module.
  • each pull-up module corresponds to a clock signal source, and the pull-up control module and the pull-down module And the pull-down maintenance module, so that two adjacent rows of pixel units share a gate drive circuit, shorten the layout of the GOA circuit in the frame area, and realize the design of an ultra-narrow frame.
  • FIG. 1 is a circuit structure diagram of a GOA unit of this application.
  • the GOA device includes N cascaded GOA units.
  • Each GOA unit a pull-up control module, at least two pull-up modules, a pull-down module, a pull-down maintenance module, and at least two A bootstrap capacitor.
  • the output end of the pull-up control module is electrically connected to at least two pull-up modules, the pull-down module, the pull-down maintenance module, and at least one bootstrap capacitor.
  • the pull-up module includes at least a first pull-up module and a second pull-up module.
  • the bootstrap capacitor includes at least a first bootstrap capacitor and a second bootstrap capacitor.
  • FIG. 1 is a schematic circuit diagram of a GOA unit of this application.
  • the GOA unit 100 includes: a pull-up control module 10; a first pull-up module 20, a second pull-up module 30, a pull-down module 40, a pull-down maintenance module 50, a first bootstrap capacitor Cb_1, The second bootstrap capacitor Cb_2.
  • the output terminal of the pull-up control module 10 is connected to the first pull-up module 20, the second pull-up module 30, the pull-down module 40, the pull-down maintenance module 50, and the first bootstrap capacitor Cb_1 , And the second bootstrap capacitor Cb_2 are electrically connected.
  • the GOA unit 100 is electrically connected to a constant voltage low level source and at least one clock signal source.
  • the number of the clock signal sources may be less than the number of the pull-up modules.
  • One said clock signal source corresponds to at least two said pull-up modules.
  • the number of the clock signal sources may be equal to the number of the pull-up modules.
  • Each of the clock signal sources corresponds to a pull-up module.
  • the clock signal source includes a first clock signal source CK1 and a second clock signal source CK2.
  • the constant voltage low-level source Vss is electrically connected to the pull-down maintaining module 50 and the pull-down module 40.
  • the first clock signal source CK1 is electrically connected to the first pull-up module 20, and the second clock signal source CK2 is electrically connected to the second pull-up module 30.
  • the first clock signal source CK1 is used to provide a 2N-1 level clock signal.
  • the first clock signal CK1 includes a first high level and a first low level.
  • the second clock signal source CK2 is used to provide a 2N-level clock signal.
  • the second clock signal CK2 includes a second high level and a second low level.
  • Constant voltage low level source Vss used to provide constant voltage low level.
  • the pull-up control module 10 is configured to receive the first scan signal, and generate the scan level signal Q(2N) of the 2N-1 stage and the scan level signal Q(2N) of the 2N stage according to the control of the first scan signal. 2N).
  • the first pull-up module 20 is used to pull up the scan signal of the 2N-1 stage according to the scan level signal Q(2N) of the 2N-1 stage and the first clock signal CK1 of the 2N-1 stage.
  • the second pull-up module 30 is configured to pull up the scan signal of the 2N level according to the scan level signal Q(2N) of the 2N level and the second clock signal CK2 of the 2N level.
  • the pull-down module 40 is configured to output the constant voltage low level provided by the constant voltage low level source Vss to the output terminal of the scan signal of the corresponding stage according to the second scan signal.
  • the pull-down maintaining module 50 is used to maintain the scan level signal of the corresponding level and the low level of the scan signal.
  • the first bootstrap capacitor Cb_1 is used to generate the high level of the scan level signal of the 2N-1th stage.
  • the second bootstrap capacitor Cb_2 is used to generate the high level of the 2Nth stage scan level signal.
  • N is a positive integer.
  • the first pull-up module 20 includes a twenty-first thin film transistor T21, and the gate of the twenty-first thin film transistor T21 is electrically connected to the pull-up control module 10, the drain is electrically connected to the first clock signal source, and the source is electrically connected to the output end of the scan signal G(2N-1) of the 2N-1 stage.
  • the gate of the twenty-first thin film transistor T21 is electrically connected to the output terminal of the pull-up control module 10.
  • the second pull-up module 30 includes a seventieth thin film transistor T70, the gate of the seventieth thin film transistor T70 is electrically connected to the output terminal of the pull-up control module 10, and the drain is electrically connected to the second The source of the clock signal is electrically connected to the output terminal of the scanning signal G(2N) of the 2Nth stage.
  • the gate of the seventieth thin film transistor T70 is electrically connected to the output terminal of the pull-up control module 10.
  • the pull-down module 40 includes a thirty-first thin film transistor T31, a forty-first thin film transistor T41, and at least one seventy-first thin film transistor T71.
  • the number of the seventy-first thin film transistor T71 is not specifically limited.
  • the pull-down module 40 in this embodiment includes one the seventy-first thin film transistor T71.
  • the gate of the thirty-first thin film transistor T31 is electrically connected to the output terminal of the 2N+4 level scanning signal G (2N+4), the source is electrically connected to the constant voltage low-level source Vss, and the drain is electrically connected Connected to the output terminal of the scan signal G(2N-1) of the 2N-1 stage.
  • the gate of the seventy-first thin film transistor T71 is electrically connected to the output terminal of the 2N+4 level scanning signal G (2N+4), the source is electrically connected to the constant voltage low level source Vss, and the drain is electrically connected Connected to the output terminal of the scan signal G(2N) of the 2Nth stage.
  • the gate of the forty-first thin film transistor T41 is electrically connected to the output terminal of the 2N+4 level scanning signal G (2N+4), the source is electrically connected to the constant voltage low-level source Vss, and the drain is electrically connected Connected to the output terminal of the pull-up control module 10.
  • the pull-up control module 10 includes an eleventh thin film transistor T11, the gate and drain of the eleventh thin film transistor T11 are electrically connected to the output terminal of the scan signal G(2N-5) of the 2N-5th stage, The source is electrically connected to the output terminal of the pull-up control module 10.
  • the pull-down maintenance module 50 includes a first pull-down maintenance unit 501 and a second pull-down maintenance unit 502.
  • the first pull-down sustain unit 501 includes a fifty-first thin film transistor T51, a fifty-second thin film transistor T52, a fifty-third thin film transistor T53, a fifty-fourth thin film transistor T54, and a forty-second thin film transistor T42, The thirty-second thin film transistor T32, and at least one seventy-second thin film transistor T72.
  • the number of the seventy-second thin film transistor T72 is not specifically limited.
  • the first pull-down sustaining unit 501 in this embodiment includes one the seventy-second thin film transistor T72.
  • the gate and drain of the fifty-first thin film transistor T51 are connected to the first square wave signal LC1, and the source is electrically connected to the drain of the fifty-second thin film transistor T52 and the fifty-third thin film transistor The gate of T53.
  • the gate of the fifty-second thin film transistor T52 is electrically connected to the output terminal of the pull-up control module 10, and the source is electrically connected to the constant voltage low level source Vss.
  • the drain of the fifty-third thin film transistor T53 is connected to the first square wave signal LC1, and the source is electrically connected to the drain of the fifty-fourth thin film transistor T54 and the gate of the forty-second thin film transistor T42. And the gate of the thirty-second thin film transistor T32.
  • the gate of the fifty-fourth thin film transistor T54 is electrically connected to the output terminal of the pull-up control module 10, and the source is electrically connected to the constant voltage low level source Vss.
  • the source of the forty-second thin film transistor T42 is electrically connected to the constant voltage low-level source Vss, and the drain is electrically connected to the output terminal of the pull-up control module 10.
  • the source of the thirty-second thin film transistor T32 is electrically connected to the constant voltage low-level source Vss, and the drain is electrically connected to the output end of the scan signal G(2N-1) of the 2N-1 stage.
  • the source of the seventy-second thin film transistor T72 is electrically connected to the constant voltage low-level source Vss, and the drain is electrically connected to the output end of the 2N-th stage scanning signal G(2N).
  • the second pull-down sustain unit 502 includes the sixty-first thin film transistor T61, the sixty-second thin film transistor T62, the sixty-third thin film transistor T63, the sixty-fourth thin film transistor T64, the forty-third thin film transistor T43, and the Thirty-three thin film transistors T33, and at least one seventy-third thin film transistor T73.
  • the number of the seventy-third thin film transistor T73 is not specifically limited.
  • the second pull-down sustain unit 502 in this embodiment includes one the seventy-third thin film transistor T73.
  • the gate and drain of the 61st thin film transistor T61 are connected to a second square wave signal LC2, and the source is electrically connected to the drain of the 62nd thin film transistor T62 and the 63rd thin film transistor The gate of T63.
  • the gate of the 62nd thin film transistor T62 is electrically connected to the output terminal of the pull-up control module 10, and the source is electrically connected to the constant voltage low-level source Vss.
  • the drain of the 63rd thin film transistor T63 is connected to the second square wave signal LC2, and the source is electrically connected to the drain of the 64th thin film transistor T64 and the gate of the 43rd thin film transistor T43. And the gate of the thirty-third thin film transistor T33.
  • the gate of the sixty-fourth thin film transistor T64 is electrically connected to the output terminal of the pull-up control module 10, and the source is electrically connected to the constant voltage low level source VSS;
  • the source of the forty-third thin film transistor T43 is electrically connected to the constant voltage low-level source VSS, and the drain is electrically connected to the output terminal of the pull-up control module 10.
  • the source of the thirty-third thin film transistor T33 is electrically connected to the constant voltage low-level source VSS, and the drain is electrically connected to the output terminal of the scan signal G(2N) of the 2N-1 stage.
  • the source of the seventy-third thin film transistor T73 is electrically connected to the constant voltage low-level source VSS, and the drain is electrically connected to the output end of the 2N-th stage scanning signal G(2N).
  • the first bootstrap capacitor Cb_1 is arranged between the output terminal of the pull-up control module 10 and the output terminal of the scan signal G(2N-1) of the 2N-1 stage.
  • the second bootstrap capacitor Cb_2 is arranged between the output terminal of the pull-up control module 10 and the output terminal of the 2N-th stage scanning signal G(2N).
  • the number of the seventieth thin film transistor T70 in the second pull-up module 30, the number of the seventy-first thin film transistor T71 in the pull-down module 40, the number of the first pull-up module 40 The number of the seventy-second thin film transistor T72 in the pull-down maintaining module 501 and the number of the seventy-third thin film transistor T73 in the second pull-down maintaining module 502 are equal.
  • the number of bootstrap capacitors may be equal to the number of pull-up modules.
  • Each of the bootstrap capacitors corresponds to a pull-up module.
  • the first square wave signal LC1 and the second square wave signal LC2 are both square waves with a duty cycle of 1/2, and the phase difference is 1/2 period, and the first pull-down maintains The unit and the second pull-down sustain unit work alternately, making the entire circuit more stable.
  • the driving circuit when the GOA device is used, the driving circuit is activated by the activation signal STV.
  • the eleventh thin film transistor T11 When the 2N-5 level scan signal G (2N-5) is high, the eleventh thin film transistor T11 is turned on, and the high level of the 2N-5 level scan signal G (2N-5) passes through the eleventh film
  • the transistor T11 charges the first bootstrap capacitor Cb_1 and the second bootstrap capacitor Cb_2, so that the reference point Q(2N) rises to a higher level.
  • the eleventh thin film transistor T11 When the scan signal G (2N-5) of the 2N-5 level is low, the eleventh thin film transistor T11 is turned on. The reference point Q(2N) is maintained at a higher level through the bootstrap capacitor Cb_1. The twenty-first thin film transistor T21 is turned on, and the first clock signal is output to the output terminal of the scan signal G(2N-1) of the 2N-1 stage via the first pull-up module 20.
  • the reference point Q(2N) maintains a higher level through the bootstrap capacitor Cb_2.
  • the seventy thin film transistor T70 is turned on, and the second clock signal is output to the output terminal of the scan signal G(2N) of the 2Nth stage via the second pull-up module 30.
  • the thirty-first thin film transistor T31, the forty-first thin film transistor T41, and the seventy-first thin film transistor T71 are turned on.
  • the constant voltage low level source Vss sets the corresponding scan signal G(2N-1) to a constant voltage low level. Since the first low level is smaller than the constant voltage low level, it compensates for the feedthrough voltage generated by the corresponding parasitic capacitance .
  • the constant voltage low level source Vss places the corresponding scan signal G(2N) at a constant voltage low level. Since the second low level is less than the constant voltage low level, it compensates for the feedthrough voltage generated by the corresponding parasitic capacitance.
  • the alternate action of the first pull-down maintenance module 501 and the second pull-down maintenance module 502 on the pull-down maintenance module 50 is used to ensure that the low potential of the reference point Q(2N) is at a constant voltage low level.
  • the corresponding scan signal or G(2N-1) or G(2N) plays a maintenance role.
  • the frequencies of the first clock signal source CK1 and the second clock signal source CK2 may be the same or different, and there is no specific limitation.
  • This application is provided with at least two pull-up modules and at least two bootstrap capacitors.
  • Each pull-up module corresponds to one clock signal source, and is maintained by sharing the pull-up control module, pull-down module and pull-down module.
  • the module enables two adjacent rows of pixel units to be driven by the same GOA device, which shortens the arrangement of GOA circuits in the frame area and realizes the design of an ultra-narrow frame.
  • the present application provides a gate driving circuit.
  • the gate driving circuit includes: at least a first clock signal source, and the first clock signal source is used to provide a clock signal of the 2N-1 level. At least a second clock signal source, and the second clock signal source is used to provide a 2N-th level clock signal. Constant voltage low level source, used to provide the corresponding level of constant voltage low level.
  • the GOA device includes at least two GOA units, each of the GOA units: a pull-up control module, at least one first pull-up module, at least one second pull-up module, a pull-down module, and a pull-down maintenance module , At least one first bootstrap capacitor, and at least one second bootstrap capacitor.
  • the output terminal of the pull-up control module and at least one of the first pull-up module, at least one of the second pull-up module, the pull-down module, the pull-down maintenance module, and at least one of the first bootstrap capacitor And electrically connected to at least one of the second bootstrap capacitors.
  • the constant voltage low level source is electrically connected with the pull-down maintaining module and the pull-down module.
  • the first clock signal source is electrically connected with the first pull-up module, and the second clock signal source is electrically connected with the second pull-up module.
  • N is a positive integer.
  • the specific working principle of the gate driving circuit in this embodiment is the same as that of the GOA device, and will not be repeated here.
  • This application also proposes a display panel including the above-mentioned gate driving circuit.
  • the working principle of the display panel is the same as the above-mentioned gate driving circuit, and will not be repeated here.
  • the gate drive circuit includes: at least one clock signal source; a constant voltage low-level source; a GOA device, including N cascaded GOA units, Each GOA unit includes: a pull-up control module, at least two pull-up modules, a pull-down module, a pull-down maintenance module, and at least two bootstrap capacitors.
  • each pull-up module corresponds to a clock signal source, and the pull-up control module and the pull-down module And the pull-down maintenance module, so that two adjacent rows of pixel units share a gate drive circuit, shorten the layout of the GOA circuit in the frame area, and realize the design of an ultra-narrow frame.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA器件及栅极驱动电路、显示面板，栅极驱动电路包括：至少一时钟信号源；恒压低电平源（Vss）；GOA器件，包括至少两个的GOA单元（100），GOA单元（100）包括：上拉控制模块（10）、至少一第一上拉模块（20）、至少一第二上拉模块（30）、下拉模块（40）、下拉维持模块（50）、至少一第一自举电容（Cb_1）、及至少一第二自举电容（Cb_2）。

Description

GOA器件及栅极驱动电路、显示面板 技术领域
本申请涉及显示领域，尤其涉及一种GOA器件及栅极驱动电路、显示面板。
 背景技术
阵列基板行驱动(Gate Drive ON Array，GOA)技术，为将扫描线驱动电路集成在液晶面板的阵列基板上，从而在材料成本和制作工艺方面上降低产品成本。
随着显示行业技术的发展，用户对显示面板的外观设计要求越来越高，比如窄边框的设计。显示面板边框区域设置有大量的GOA走线，使得边框区域无法进一步减小。
因此，本申请基于此技术问题提出了下列技术方案。
 技术问题
本申请提供一种GOA器件及栅极驱动电路、显示面板，以实现显示面板窄边框的设计。
 技术解决方案
本申请提出了一种GOA器件，其中，所述GOA器件包括至少两个GOA单元，所述GOA单元包括：
上拉控制模块，用于接收第一扫描信号，并根据所述第一扫描信号的控制至少生成第2N-1级的扫描电平信号和第2N级的扫描电平信号；
至少一第一上拉模块，所述第一上拉模块用于接收所述第2N-1级的扫描电平信号和由时钟信号源提供的第2N-1级的时钟信号，以及用于根据所述第2N-1级的扫描电平信号以及所述第2N-1级的时钟信号拉升第2N-1级的扫描信号；
至少一第二上拉模块，所述第二上拉模块用于接收所述第2N级的扫描电平信号和由所述时钟信号源提供的第2N级的时钟信号，以及用于根据所述第2N级的扫描电平信号以及所述第2N级的时钟信号拉升第2N级的扫描信号；
下拉模块，用于接收第二扫描信号和由恒压低电平源提供的恒压低电平，以及用于根据所述第二扫描信号将所述恒压低电平输出至所述GOA单元的输出端；
下拉维持模块，用于维持所述第2N-1级的扫描电平信号及所述第2N-1级的扫描信号的低电平、及所述第2N级的扫描电平信号及所述第2N级的扫描信号的低电平；
至少一第一自举电容，所述第一自举电容用于生成所述第2N-1级的扫描电平信号的高电平；
至少一第二自举电容，所述第二自举电容用于生成所述第2N级的扫描电平信号的高电平；
所述上拉控制模块的输出端与至少一所述第一上拉模块、至少一所述第二上拉模块、所述下拉模块、所述下拉维持模块、至少一所述第一自举电容、及至少一所述第二自举电容电连接；
其中，N为正整数。
在本申请的GOA器件中，所述GOA单元包括第一上拉模块和第二上拉模块；
所述第一上拉模块包括第二十一薄膜晶体管，所述二十一薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第一时钟信号源，源极电连接至所述第2N-1级的扫描信号的输出端；
所述第二上拉模块包括第七十薄膜晶体管，所述第七十薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第二时钟信号源，源极电连接至所述第2N级的扫描信号的输出端。
在本申请的GOA器件中，所述下拉模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、及至少一第七十一薄膜晶体管；
所述第三十一薄膜晶体管的栅极电连接至所述第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
所述第四十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
所述第七十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端。
在本申请的GOA器件中，所述下拉维持模块包括第一下拉维持单元及第二下拉维持单元；
所述第一下拉维持单元包括第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、第五十四薄膜晶体管、第四十二薄膜晶体管、第三十二薄膜晶体管、及至少一第七十二薄膜晶体管；
所述第五十一薄膜晶体管的栅极以及漏极接入第一方波信号，源极电连接于所述第五十二薄膜晶体管的漏极以及所述第五十三薄膜晶体管的栅极；
所述第五十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
所述第五十三薄膜晶体管的漏极接入第一方波信号，源极电连接至所述第五十四薄膜晶体管的漏极、所述第四十二薄膜晶体管的栅极以及所述第三十二薄膜晶体管的栅极；
所述第五十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
所述第四十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
所述第三十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
所述第七十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N级的扫描信号的输出端；
所述第二下拉维持单元包括第六十一薄膜晶体管、第六十二薄膜晶体管、第六十三薄膜晶体管、第六十四薄膜晶体管、第四十三薄膜晶体管、第三十三薄膜晶体管、及至少一第七十三薄膜晶体管；
所述第六十一薄膜晶体管的栅极以及漏极接入第二方波信号，源极电连接于所述第六十二薄膜晶体管的漏极以及所述第六十三薄膜晶体管的栅极；
所述第六十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接至所述恒压低电平源；
所述第六十三薄膜晶体管的漏极接入第二方波信号，源极电连接于所述第六十四薄膜晶体管的漏极、所述第四十三薄膜晶体管的栅极以及所述第三十三薄膜晶体管的栅极；
所述第六十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
所述第四十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述上拉控制模块的输出端；
所述第三十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N-1级的扫描信号的输出端；
所述第七十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N级的扫描信号的输出端。
在本申请的GOA器件中，所述GOA单元至少包括第一自举电容和第二自举电容，所述自举电容的数量与所述上拉模块的数量相等。
在本申请的GOA器件中，所述第一自举电容设置在所述上拉控制模块的输出端及所述第2N-1级的扫描信号的输出端之间
所述第二自举电容设置在所述上拉控制模块的输出端及所述第2N级的扫描信号的输出端之间。
在本申请的GOA器件中，所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极和漏极电连接至第2N-5级的扫描信号G(2N-5)的输出端，源极电连接至所述上拉控制模块的输出端。
本申请还提出了一种栅极驱动电路，其包括：
至少第一时钟信号源，所述第一时钟信号源用于提供第2N-1级的时钟信号；
至少第二时钟信号源，所述第二时钟信号源用于提供第2N级的时钟信号；
恒压低电平源，用于提供恒压低电平；
GOA器件，包括至少两个GOA单元，所述GOA单元包括：
上拉控制模块，用于接收第一扫描信号，并根据所述第一扫描信号的控制至少生成第2N-1级的扫描电平信号和第2N级的扫描电平信号；
至少一第一上拉模块，所述第一上拉模块用于接收所述第2N-1级的扫描电平信号和所述第一时钟信号源提供的第2N-1级的时钟信号，以及用于根据所述第2N-1级的扫描电平信号以及所述第2N-1级的时钟信号拉升第2N-1级的扫描信号；
至少一第二上拉模块，所述第二上拉模块用于接收所述第2N级的扫描电平信号和由所述第二时钟信号源提供的第2N级的时钟信号，以及用于根据所述第2N级的扫描电平信号以及所述第2N级的时钟信号拉升第2N级的扫描信号；
下拉模块，用于接收第二扫描信号和由恒压低电平源提供的恒压低电平，以及用于根据所述第二扫描信号将所述恒压低电平输出至所述GOA单元的输出端；
下拉维持模块，用于维持所述第2N-1级的扫描电平信号及所述第2N-1级的扫描信号的低电平、及所述第2N级的扫描电平信号及所述第2N级的扫描信号的低电平；
至少一第一自举电容，所述第一自举电容用于生成所述第2N-1级的扫描电平信号的高电平；
至少一第二自举电容，所述第二自举电容用于生成所述第2N级的扫描电平信号的高电平；
所述上拉控制模块的输出端与至少一所述第一上拉模块、至少一所述第二上拉模块、所述下拉模块、所述下拉维持模块、至少一所述第一自举电容、及至少一所述第二自举电容电连接；
所述恒压低电平源与所述下拉维持模块、及所述下拉模块电连接，所述第一时钟信号源与所述第一上拉模块电连接，所述第二时钟信号源与所述第二上拉模块电连接；
其中，N为正整数。
在本申请的栅极驱动电路中，所述GOA单元包括第一上拉模块和第二上拉模块；
所述第一上拉模块包括第二十一薄膜晶体管，所述二十一薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第一时钟信号源，源极电连接至所述第2N-1级的扫描信号的输出端；
所述第二上拉模块包括第七十薄膜晶体管，所述第七十薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第二时钟信号源，源极电连接至所述第2N级的扫描信号的输出端。
在本申请的栅极驱动电路中，所述下拉模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、及至少一第七十一薄膜晶体管；
所述第三十一薄膜晶体管的栅极电连接至所述第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
所述第四十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
所述第七十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端。
在本申请的栅极驱动电路中，所述下拉维持模块包括第一下拉维持单元及第二下拉维持单元；
所述第一下拉维持单元包括第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、第五十四薄膜晶体管、第四十二薄膜晶体管、第三十二薄膜晶体管、及至少一第七十二薄膜晶体管；
所述第五十一薄膜晶体管的栅极以及漏极接入第一方波信号，源极电连接于所述第五十二薄膜晶体管的漏极以及所述第五十三薄膜晶体管的栅极；
所述第五十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
所述第五十三薄膜晶体管的漏极接入第一方波信号，源极电连接至所述第五十四薄膜晶体管的漏极、所述第四十二薄膜晶体管的栅极以及所述第三十二薄膜晶体管的栅极；
所述第五十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
所述第四十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
所述第三十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
所述第七十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N级的扫描信号的输出端；
所述第二下拉维持单元包括第六十一薄膜晶体管、第六十二薄膜晶体管、第六十三薄膜晶体管、第六十四薄膜晶体管、第四十三薄膜晶体管、第三十三薄膜晶体管、及至少一第七十三薄膜晶体管；
所述第六十一薄膜晶体管的栅极以及漏极接入第二方波信号，源极电连接于所述第六十二薄膜晶体管的漏极以及所述第六十三薄膜晶体管的栅极；
所述第六十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接至所述恒压低电平源；
所述第六十三薄膜晶体管的漏极接入第二方波信号，源极电连接于所述第六十四薄膜晶体管的漏极、所述第四十三薄膜晶体管的栅极以及所述第三十三薄膜晶体管的栅极；
所述第六十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
所述第四十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述上拉控制模块的输出端；
所述第三十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N-1级的扫描信号的输出端；
所述第七十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N级的扫描信号的输出端。
在本申请的栅极驱动电路中，所述GOA单元至少包括第一自举电容和第二自举电容，所述自举电容的数量与所述上拉模块的数量相等。
在本申请的栅极驱动电路中，所述第一自举电容设置在所述上拉控制模块的输出端及所述第2N-1级的扫描信号的输出端之间
所述第二自举电容设置在所述上拉控制模块的输出端及所述第2N级的扫描信号的输出端之间。
在本申请的GOA器件中，所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极和漏极电连接至第2N-5级的扫描信号G(2N-5)的输出端，源极电连接至所述上拉控制模块的输出端。
本申请还提出了一种显示面板，包括栅极驱动电路，其中，所述栅极驱动电路包括：
至少第一时钟信号源，所述第一时钟信号源用于提供第2N-1级的时钟信号；
至少第二时钟信号源，所述第二时钟信号源用于提供第2N级的时钟信号；
恒压低电平源，用于提供恒压低电平；
GOA器件，包括至少两个GOA单元，所述GOA单元包括：
上拉控制模块，用于接收第一扫描信号，并根据所述第一扫描信号的控制至少生成第2N-1级的扫描电平信号和第2N级的扫描电平信号；
至少一第一上拉模块，所述第一上拉模块用于接收所述第2N-1级的扫描电平信号和所述第一时钟信号源提供的第2N-1级的时钟信号，以及用于根据所述第2N-1级的扫描电平信号以及所述第2N-1级的时钟信号拉升第2N-1级的扫描信号；
至少一第二上拉模块，所述第二上拉模块用于接收所述第2N级的扫描电平信号和由所述第二时钟信号源提供的第2N级的时钟信号，以及用于根据所述第2N级的扫描电平信号以及所述第2N级的时钟信号拉升第2N级的扫描信号；
下拉模块，用于接收第二扫描信号和由恒压低电平源提供的恒压低电平，以及用于根据所述第二扫描信号将所述恒压低电平输出至所述GOA单元的输出端；
下拉维持模块，用于维持所述第2N-1级的扫描电平信号及所述第2N-1级的扫描信号的低电平、及所述第2N级的扫描电平信号及所述第2N级的扫描信号的低电平；
至少一第一自举电容，所述第一自举电容用于生成所述第2N-1级的扫描电平信号的高电平；
至少一第二自举电容，所述第二自举电容用于生成所述第2N级的扫描电平信号的高电平；
所述上拉控制模块的输出端与至少一所述第一上拉模块、至少一所述第二上拉模块、所述下拉模块、所述下拉维持模块、至少一所述第一自举电容、及至少一所述第二自举电容电连接；
所述恒压低电平源与所述下拉维持模块、及所述下拉模块电连接，所述第一时钟信号源与所述第一上拉模块电连接，所述第二时钟信号源与所述第二上拉模块电连接；
其中，N为正整数。
在本申请的显示面板中，所述GOA单元包括第一上拉模块和第二上拉模块；
所述第一上拉模块包括第二十一薄膜晶体管，所述二十一薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第一时钟信号源，源极电连接至所述第2N-1级的扫描信号的输出端；
所述第二上拉模块包括第七十薄膜晶体管，所述第七十薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第二时钟信号源，源极电连接至所述第2N级的扫描信号的输出端。
在本申请的栅极驱动电路中，所述下拉模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、及至少一第七十一薄膜晶体管；
所述第三十一薄膜晶体管的栅极电连接至所述第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
所述第四十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
所述第七十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端。
在本申请的显示面板中，所述下拉维持模块包括第一下拉维持单元及第二下拉维持单元；
所述第一下拉维持单元包括第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、第五十四薄膜晶体管、第四十二薄膜晶体管、第三十二薄膜晶体管、及至少一第七十二薄膜晶体管；
所述第五十一薄膜晶体管的栅极以及漏极接入第一方波信号，源极电连接于所述第五十二薄膜晶体管的漏极以及所述第五十三薄膜晶体管的栅极；
所述第五十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
所述第五十三薄膜晶体管的漏极接入第一方波信号，源极电连接至所述第五十四薄膜晶体管的漏极、所述第四十二薄膜晶体管的栅极以及所述第三十二薄膜晶体管的栅极；
所述第五十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
所述第四十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
所述第三十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
所述第七十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N级的扫描信号的输出端；
所述第二下拉维持单元包括第六十一薄膜晶体管、第六十二薄膜晶体管、第六十三薄膜晶体管、第六十四薄膜晶体管、第四十三薄膜晶体管、第三十三薄膜晶体管、及至少一第七十三薄膜晶体管；
所述第六十一薄膜晶体管的栅极以及漏极接入第二方波信号，源极电连接于所述第六十二薄膜晶体管的漏极以及所述第六十三薄膜晶体管的栅极；
所述第六十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接至所述恒压低电平源；
所述第六十三薄膜晶体管的漏极接入第二方波信号，源极电连接于所述第六十四薄膜晶体管的漏极、所述第四十三薄膜晶体管的栅极以及所述第三十三薄膜晶体管的栅极；
所述第六十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
所述第四十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述上拉控制模块的输出端；
所述第三十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N-1级的扫描信号的输出端；
所述第七十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N级的扫描信号的输出端。
在本申请的显示面板中，所述GOA单元至少包括第一自举电容和第二自举电容，所述自举电容的数量与所述上拉模块的数量相等。
在本申请的显示面板中，所述第一自举电容设置在所述上拉控制模块的输出端及所述第2N-1级的扫描信号的输出端之间
所述第二自举电容设置在所述上拉控制模块的输出端及所述第2N级的扫描信号的输出端之间。
在本申请的显示面板中，所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极和漏极电连接至第2N-5级的扫描信号G(2N-5)的输出端，源极电连接至所述上拉控制模块的输出端。
 有益效果
本申请在GOA单元中设置有至少两个所述上拉模块及至少两个所述自举电容，每一所述上拉模块对应一所述时钟信号源，并通过上拉控制模块、下拉模块及下拉维持模块，使得相邻两行像素单元共用一个栅极驱动电路，缩短了边框区域GOA电路的排布，实现了超窄边框的设计。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一种GOA单元的电路结构图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请提出了一种GOA器件，所述GOA器件包括N个级联的GOA单元，每一所述GOA单元：上拉控制模块、至少两个上拉模块、下拉模块、下拉维持模块、至少两个自举电容。所述上拉控制模块的输出端与至少两个所述上拉模块、所述下拉模块、所述下拉维持模块、至少一个自举电容电连接。
所述上拉模块至少包括第一上拉模块和第二上拉模块。所述自举电容至少包括第一自举电容和第二自举电容。
请参阅图1，图1为本申请一种GOA单元的电路原理图。
在一种实施例中，所述GOA单元100包括：上拉控制模块10；第一上拉模块20、第二上拉模块30、下拉模块40、下拉维持模块50、第一自举电容Cb_1、第二自举电容Cb_2。
所述上拉控制模块10的输出端与所述第一上拉模块20、所述第二上拉模块30、所述下拉模块40、所述下拉维持模块50、所述第一自举电容Cb_1、及所述第二自举电容Cb_2电连接。
所述GOA单元100与恒压低电平源及至少一时钟信号源电连接。
在一种实施例中，所述时钟信号源的数量可以小于所述上拉模块的数量。一所述时钟信号源对应至少两个所述上拉模块。
在一种实施例中，所述时钟信号源的数量可以与所述上拉模块的数量相等。每一所述时钟信号源对应一所述上拉模块。
在一种实施例中，所述时钟信号源包括第一时钟信号源CK1和第二时钟信号源CK2。
所述恒压低电平源Vss与所述下拉维持模块50、及所述下拉模块40电连接。所述第一时钟信号源CK1与所述第一上拉模块20电连接，所述第二时钟信号源CK2与所述第二上拉模块30电连接。
所述第一时钟信号源CK1，用于提供第2N-1级的时钟信号。所述第一时钟信号CK1包括第一高电平及第一低电平。
所述第二时钟信号源CK2，用于提供第2N级的时钟信号。所述第二时钟信号CK2包括第二高电平及第二低电平。
恒压低电平源Vss，用于提供恒压低电平。
上拉控制模块10，用于接收第一扫描信号，并根据所述第一扫描信号的控制生成第2N-1级的扫描电平信号Q(2N)与第2N级的扫描电平信号Q(2N)。
第一上拉模块20，用于根据第2N-1级的扫描电平信号Q(2N)、及第2N-1级的第一时钟信号CK1拉升第2N-1级的扫描信号。
第二上拉模块30，用于根据第2N级的扫描电平信号Q(2N)、及第2N级的第二时钟信号CK2拉升第2N级的扫描信号。
下拉模块40，用于根据第二扫描信号，将恒压低电平源Vss所提供的恒压低电平输出至对应级的扫描信号的输出端。
下拉维持模块50，用于维持对应级的扫描电平信号及扫描信号的低电平。
第一自举电容Cb_1，用于生成第2N-1级的的扫描电平信号的高电平。
第二自举电容Cb_2，用于生成第2N级的的扫描电平信号的高电平。
在一种实施例中，N为正整数。
在一种实施例中，请参阅图1，所述第一上拉模块20包括第二十一薄膜晶体管T21，所述第二十一薄膜晶体管T21的栅极电连接至所述上拉控制模块10的输出端，漏极电连接至所述第一时钟信号源，源极电连接至所述第2N-1级的扫描信号G(2N-1)的输出端。所述第二十一薄膜晶体管T21的栅极电连接至所述上拉控制模块10的输出端。
所述第二上拉模块30包括第七十薄膜晶体管T70，所述第七十薄膜晶体管T70的栅极电连接至所述上拉控制模块10的输出端，漏极电连接至所述第二时钟信号源，源极电连接至所述第2N级的扫描信号G(2N)的输出端。所述第七十薄膜晶体管T70的栅极电连接至所述上拉控制模块10的输出端。
所述下拉模块40包括第三十一薄膜晶体管T31、第四十一薄膜晶体管T41及至少一第七十一薄膜晶体管T71。
在一种实施例中，所述第七十一薄膜晶体管T71的数量没有具体的限制，本实施例所述下拉模块40包括一个所述第七十一薄膜晶体管T71。
所述第三十一薄膜晶体管T31的栅极电连接至第2N+4级扫描信号G(2N+4)的输出端，源极电连接至所述恒压低电平源Vss，漏极电连接至所述第2N-1级的扫描信号G(2N-1)的输出端。
所述第七十一薄膜晶体管T71的栅极电连接至第2N+4级扫描信号G(2N+4)的输出端，源极电连接至所述恒压低电平源Vss，漏极电连接至所述第2N级的扫描信号G(2N)的输出端。
所述第四十一薄膜晶体管T41的栅极电连接至第2N+4级扫描信号G(2N+4)的输出端，源极电连接至所述恒压低电平源Vss，漏极电连接至所述上拉控制模块10的输出端。
所述上拉控制模块10包括第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极和漏极电连接至第2N-5级的扫描信号G(2N-5)的输出端，源极电连接至所述上拉控制模块10的输出端。
所述下拉维持模块50包括第一下拉维持单元501及第二下拉维持单元502。
所述第一下拉维持单元501包括第五十一薄膜晶体管T51、第五十二薄膜晶体管T52、第五十三薄膜晶体管T53、第五十四薄膜晶体管T54、第四十二薄膜晶体管T42、第三十二薄膜晶体管T32、及至少一第七十二薄膜晶体管T72。
在一种实施例中，所述第七十二薄膜晶体管T72的数量没有具体的限制，本实施例所述第一下拉维持单元501包括一个所述第七十二薄膜晶体管T72。
所述第五十一薄膜晶体管T51的栅极以及漏极接入第一方波信号LC1，源极电连接于所述第五十二薄膜晶体管T52的漏极以及所述第五十三薄膜晶体管T53的栅极。
所述第五十二薄膜晶体管T52的栅极电连接至所述上拉控制模块10的输出端，源极电连接于所述恒压低电平源Vss。
所述第五十三薄膜晶体管T53的漏极接入第一方波信号LC1，源极电连接至所述第五十四薄膜晶体管T54的漏极、所述第四十二薄膜晶体管T42的栅极以及所述第三十二薄膜晶体管T32的栅极。
所述第五十四薄膜晶体管T54的栅极电连接至所述上拉控制模块10的输出端，源极电连接于所述恒压低电平源Vss。
所述第四十二薄膜晶体管T42的源极电连接于所述恒压低电平源Vss，漏极电连接至所述上拉控制模块10的输出端。
所述第三十二薄膜晶体管T32的源极电连接于所述恒压低电平源Vss，漏极电连接至第2N-1级的扫描信号G(2N-1)的输出端。
所述第七十二薄膜晶体管T72的源极电连接于所述恒压低电平源Vss，漏极电连接至第2N级的扫描信号G(2N)的输出端。
所述第二下拉维持单元502包括第六十一薄膜晶体管T61、第六十二薄膜晶体管T62、第六十三薄膜晶体管T63、第六十四薄膜晶体管T64、第四十三薄膜晶体管T43、第三十三薄膜晶体管T33、及至少一第七十三薄膜晶体管T73。
在一种实施例中，所述第七十三薄膜晶体管T73的数量没有具体的限制，本实施例所述第二下拉维持单元502包括一个所述第七十三薄膜晶体管T73。
所述第六十一薄膜晶体管T61的栅极以及漏极接入第二方波信号LC2，源极电连接于所述第六十二薄膜晶体管T62的漏极以及所述第六十三薄膜晶体管T63的栅极。
所述第六十二薄膜晶体管T62的栅极电连接至所述上拉控制模块10的输出端，源极电连接至所述恒压低电平源Vss。
所述第六十三薄膜晶体管T63的漏极接入第二方波信号LC2，源极电连接于所述第六十四薄膜晶体管T64的漏极、所述第四十三薄膜晶体管T43的栅极以及所述第三十三薄膜晶体管T33的栅极。
所述第六十四薄膜晶体管T64的栅极电连接至所述上拉控制模块10的输出端，源极电连接于所述恒压低电平源VSS；
所述第四十三薄膜晶体管T43的源极电连接于所述恒压低电平源VSS，漏极电连接于所述上拉控制模块10的输出端。
所述第三十三薄膜晶体管T33的源极电连接于所述恒压低电平源VSS，漏极电连接于第2N-1级的扫描信号G(2N)的输出端。
所述第七十三薄膜晶体管T73的源极电连接于所述恒压低电平源VSS，漏极电连接于第2N级的扫描信号G(2N)的输出端。
所述第一自举电容Cb_1设置在所述上拉控制模块10的输出端及第2N-1级的扫描信号G(2N-1)的输出端之间。
所述第二自举电容Cb_2设置在所述上拉控制模块10的输出端及第2N级的扫描信号G(2N)的输出端之间。
在一种实施例中，所述第二上拉模块30中所述第七十薄膜晶体管T70的数量、所述下拉模块40中所述第七十一薄膜晶体管T71的数量、所述第一下拉维持模块501中所述第七十二薄膜晶体管T72的数量、及所述第二下拉维持模块502中所述第七十三薄膜晶体管T73的数量相等。
在一种实施例中，所述自举电容的数量可以与所述上拉模块的数量相等。每一所述自举电容与一所述上拉模块对应。
在一种实施例中，所述第一方波信号LC1和所述第二方波信号LC2均为占空比为1/2的方波，相位相差1/2个周期，第一下拉维持单元和第二下拉维持单元交替工作，使得整个电路更加稳定。
在一种实施例中，当使用所述GOA器件时，由启动信号STV启动驱动电路。当第2N-5级扫描信号G(2N-5)为高电平时，第十一薄膜晶体管T11导通，第2N-5级扫描信号G(2N-5)的高电平通过第十一薄膜晶体管T11给所述第一自举电容Cb_1和所述第二自举电容Cb_2充电，使得参考点Q(2N)上升到一较高电平。
当第2N-5级扫描信号G(2N-5)为低电平时，第十一薄膜晶体管T11闭合。参考点Q(2N)通过自举电容Cb_1维持一较高的电平。第二十一薄膜晶体管T21导通，所述第一时钟信号经由所述第一上拉模块20输出至第2N-1级的扫描信号G(2N-1)的输出端。
另外，参考点Q(2N)通过自举电容Cb_2维持一较高的电平。七十薄膜晶体管T70导通，所述第二时钟信号经由所述第二上拉模块30输出至第2N级的扫描信号G(2N)的输出端。
当第2N+4级的扫描信号G(2N+4)为高电平时，第三十一薄膜晶体管T31、第四十一薄膜晶体管T41、及第七十一薄膜晶体管T71导通。
恒压低电平源Vss将对应的扫描信号G(2N-1)置于恒压低电平，由于第一低电平小于恒压低电平，从而弥补对应的寄生电容产生的馈通电压。
恒压低电平源Vss将对应的扫描信号G(2N)置于恒压低电平，由于第二低电平小于恒压低电平，从而弥补对应的寄生电容产生的馈通电压。
在一种实施例中，通过下拉维持模块50上的第一下拉维持模块501和第二下拉维持模块502的交替作用，保证参考点Q(2N)的低电位，对处于恒压低电平的对应的扫描信号或G(2N-1)或G(2N)起到维持作用。
在一种实施例中，所述第一时钟信号源CK1和所述第二时钟信号源CK2的频率可以相同或不同，具体不做限制。
本申请设置有至少两个所述上拉模块及至少两个所述自举电容，每一所述上拉模块对应一所述时钟信号源，并通过共用上拉控制模块、下拉模块及下拉维持模块，使得相邻两行像素单元同一GOA器件所驱动，缩短了边框区域GOA电路的排布，实现了超窄边框的设计。
本申请提供一种栅极驱动电路，所述栅极驱动电路包括：至少第一时钟信号源，所述第一时钟信号源用于提供第2N-1级的时钟信号。至少第二时钟信号源，所述第二时钟信号源用于提供第2N级的时钟信号。恒压低电平源，用于提供对应级的恒压低电平。以及GOA器件，所述GOA器件包括至少两个的GOA单元，每一所述GOA单元：上拉控制模块、至少一第一上拉模块、至少一第二上拉模块、下拉模块、下拉维持模块、至少一第一自举电容、及至少一第二自举电容。
所述上拉控制模块的输出端与至少一所述第一上拉模块、至少一所述第二上拉模块、所述下拉模块、所述下拉维持模块、至少一所述第一自举电容、及至少一所述第二自举电容电连接。所述恒压低电平源与所述下拉维持模块、及所述下拉模块电连接。所述第一时钟信号源与所述第一上拉模块电连接，所述第二时钟信号源与所述第二上拉模块电连接。
在一种实施例中，N为正整数。
本实施例中的所述栅极驱动电路的具体工作原理与所述GOA器件相同，此处不再一一赘述。
本申请还提出了一种显示面板，所述显示面板包括上述栅极驱动电路。所述显示面板的工作原理与上述栅极驱动电路相同，此处不再一一赘述。
本申请提出了一种GOA器件及栅极驱动电路、显示面板，所述栅极驱动电路包括：至少一时钟信号源；恒压低电平源；GOA器件，包括N个级联的GOA单元，每一所述GOA单元包括：上拉控制模块、至少两个上拉模块、下拉模块、下拉维持模块、至少两个自举电容。本申请在GOA单元中设置有至少两个所述上拉模块及至少两个所述自举电容，每一所述上拉模块对应一所述时钟信号源，并通过上拉控制模块、下拉模块及下拉维持模块，使得相邻两行像素单元共用一个栅极驱动电路，缩短了边框区域GOA电路的排布，实现了超窄边框的设计。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种GOA器件，其特征在于，所述GOA器件包括至少两个GOA单元，所述GOA单元包括：
    上拉控制模块，用于接收第一扫描信号，并根据所述第一扫描信号的控制至少生成第2N-1级的扫描电平信号、及第2N级的扫描电平信号；
    至少一第一上拉模块，所述第一上拉模块用于接收所述第2N-1级的扫描电平信号和由时钟信号源提供的第2N-1级的时钟信号，以及用于根据所述第2N-1级的扫描电平信号以及所述第2N-1级的时钟信号拉升第2N-1级的扫描信号；
    至少一第二上拉模块，所述第二上拉模块用于接收所述第2N级的扫描电平信号和由所述时钟信号源提供的第2N级的时钟信号，以及用于根据所述第2N级的扫描电平信号以及所述第2N级的时钟信号拉升第2N级的扫描信号；
    下拉模块，用于接收第二扫描信号和由恒压低电平源提供的恒压低电平，以及用于根据所述第二扫描信号将所述恒压低电平输出至所述GOA单元的输出端；
    下拉维持模块，用于维持所述第2N-1级的扫描电平信号及所述第2N-1级的扫描信号的低电平、及所述第2N级的扫描电平信号及所述第2N级的扫描信号的低电平；
    至少一第一自举电容，所述第一自举电容用于生成所述第2N-1级的扫描电平信号的高电平；
    至少一第二自举电容，所述第二自举电容用于生成所述第2N级的扫描电平信号的高电平；
    所述上拉控制模块的输出端与至少一所述第一上拉模块、至少一所述第二上拉模块、所述下拉模块、所述下拉维持模块、至少一所述第一自举电容、及至少一所述第二自举电容电连接；
    其中，N为正整数。
  2. 根据权利要求1所述的GOA器件，其特征在于，所述GOA单元包括第一上拉模块和第二上拉模块；
    所述第一上拉模块包括第二十一薄膜晶体管，所述二十一薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第一时钟信号源，源极电连接至所述第2N-1级的扫描信号的输出端；
    所述第二上拉模块包括第七十薄膜晶体管，所述第七十薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第二时钟信号源，源极电连接至所述第2N级的扫描信号的输出端。
  3. 根据权利要求1所述的GOA器件，其特征在于，所述下拉模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、及至少一第七十一薄膜晶体管；
    所述第三十一薄膜晶体管的栅极电连接至所述第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
    所述第四十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
    所述第七十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端。
  4. 根据权利要求1所述的GOA器件，其特征在于，所述下拉维持模块包括第一下拉维持单元及第二下拉维持单元；
    所述第一下拉维持单元包括第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、第五十四薄膜晶体管、第四十二薄膜晶体管、第三十二薄膜晶体管、及至少一第七十二薄膜晶体管；
    所述第五十一薄膜晶体管的栅极以及漏极接入第一方波信号，源极电连接于所述第五十二薄膜晶体管的漏极以及所述第五十三薄膜晶体管的栅极；
    所述第五十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
    所述第五十三薄膜晶体管的漏极接入第一方波信号，源极电连接至所述第五十四薄膜晶体管的漏极、所述第四十二薄膜晶体管的栅极以及所述第三十二薄膜晶体管的栅极；
    所述第五十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
    所述第四十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
    所述第三十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
    所述第七十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N级的扫描信号的输出端；
    所述第二下拉维持单元包括第六十一薄膜晶体管、第六十二薄膜晶体管、第六十三薄膜晶体管、第六十四薄膜晶体管、第四十三薄膜晶体管、第三十三薄膜晶体管、及至少一第七十三薄膜晶体管；
    所述第六十一薄膜晶体管的栅极以及漏极接入第二方波信号，源极电连接于所述第六十二薄膜晶体管的漏极以及所述第六十三薄膜晶体管的栅极；
    所述第六十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接至所述恒压低电平源；
    所述第六十三薄膜晶体管的漏极接入第二方波信号，源极电连接于所述第六十四薄膜晶体管的漏极、所述第四十三薄膜晶体管的栅极以及所述第三十三薄膜晶体管的栅极；
    所述第六十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
    所述第四十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述上拉控制模块的输出端；
    所述第三十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N-1级的扫描信号的输出端；
    所述第七十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N级的扫描信号的输出端。
  5. 根据权利要求1所述的GOA器件，其特征在于，所述GOA单元至少包括第一自举电容和第二自举电容，所述自举电容的数量与所述上拉模块的数量相等。
  6. 根据权利要求5所述的GOA器件，其特征在于，所述第一自举电容设置在所述上拉控制模块的输出端及所述第2N-1级的扫描信号的输出端之间；
    所述第二自举电容设置在所述上拉控制模块的输出端及所述第2N级的扫描信号的输出端之间。
  7. 根据权利要求1所述的GOA器件，其特征在于，所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极和漏极电连接至第2N-5级的扫描信号G(2N-5)的输出端，源极电连接至所述上拉控制模块的输出端。
  8. 一种栅极驱动电路，其特征在于，包括：
    至少第一时钟信号源，所述第一时钟信号源用于提供第2N-1级的时钟信号；
    至少第二时钟信号源，所述第二时钟信号源用于提供第2N级的时钟信号；
    恒压低电平源，用于提供恒压低电平；
    GOA器件，包括至少两个GOA单元，所述GOA单元包括：
    上拉控制模块，用于接收第一扫描信号，并根据所述第一扫描信号的控制至少生成第2N-1级的扫描电平信号、及第2N级的扫描电平信号；
    至少一第一上拉模块，所述第一上拉模块用于接收所述第2N-1级的扫描电平信号和所述第一时钟信号源提供的第2N-1级的时钟信号，以及用于根据所述第2N-1级的扫描电平信号以及所述第2N-1级的时钟信号拉升第2N-1级的扫描信号；
    至少一第二上拉模块，所述第二上拉模块用于接收所述第2N级的扫描电平信号和由所述第二时钟信号源提供的第2N级的时钟信号，以及用于根据所述第2N级的扫描电平信号以及所述第2N级的时钟信号拉升第2N级的扫描信号；
    下拉模块，用于接收第二扫描信号和由恒压低电平源提供的恒压低电平，以及用于根据所述第二扫描信号将所述恒压低电平输出至所述GOA单元的输出端；
    下拉维持模块，用于维持所述第2N-1级的扫描电平信号及所述第2N-1级的扫描信号的低电平、及所述第2N级的扫描电平信号及所述第2N级的扫描信号的低电平；
    至少一第一自举电容，所述第一自举电容用于生成所述第2N-1级的扫描电平信号的高电平；
    至少一第二自举电容，所述第二自举电容用于生成所述第2N级的扫描电平信号的高电平；
    所述上拉控制模块的输出端与至少一所述第一上拉模块、至少一所述第二上拉模块、所述下拉模块、所述下拉维持模块、至少一所述第一自举电容、及至少一所述第二自举电容电连接；
    所述恒压低电平源与所述下拉维持模块、及所述下拉模块电连接，所述第一时钟信号源与所述第一上拉模块电连接，所述第二时钟信号源与所述第二上拉模块电连接；
    其中，N为正整数。
  9. 根据权利要求8所述的栅极驱动电路，其特征在于，所述GOA单元包括第一上拉模块和第二上拉模块；
    所述第一上拉模块包括第二十一薄膜晶体管，所述二十一薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第一时钟信号源，源极电连接至所述第2N-1级的扫描信号的输出端；
    所述第二上拉模块包括第七十薄膜晶体管，所述第七十薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第二时钟信号源，源极电连接至所述第2N级的扫描信号的输出端。
  10. 根据权利要求8所述的栅极驱动电路，其特征在于，所述下拉模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、及至少一第七十一薄膜晶体管；
    所述第三十一薄膜晶体管的栅极电连接至所述第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
    所述第四十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
    所述第七十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端。
  11. 根据权利要求8所述的栅极驱动电路，其特征在于，所述下拉维持模块包括第一下拉维持单元及第二下拉维持单元；
    所述第一下拉维持单元包括第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、第五十四薄膜晶体管、第四十二薄膜晶体管、第三十二薄膜晶体管、及至少一第七十二薄膜晶体管；
    所述第五十一薄膜晶体管的栅极以及漏极接入第一方波信号，源极电连接于所述第五十二薄膜晶体管的漏极以及所述第五十三薄膜晶体管的栅极；
    所述第五十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
    所述第五十三薄膜晶体管的漏极接入第一方波信号，源极电连接至所述第五十四薄膜晶体管的漏极、所述第四十二薄膜晶体管的栅极以及所述第三十二薄膜晶体管的栅极；
    所述第五十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
    所述第四十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
    所述第三十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
    所述第七十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N级的扫描信号的输出端；
    所述第二下拉维持单元包括第六十一薄膜晶体管、第六十二薄膜晶体管、第六十三薄膜晶体管、第六十四薄膜晶体管、第四十三薄膜晶体管、第三十三薄膜晶体管、及至少一第七十三薄膜晶体管；
    所述第六十一薄膜晶体管的栅极以及漏极接入第二方波信号，源极电连接于所述第六十二薄膜晶体管的漏极以及所述第六十三薄膜晶体管的栅极；
    所述第六十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接至所述恒压低电平源；
    所述第六十三薄膜晶体管的漏极接入第二方波信号，源极电连接于所述第六十四薄膜晶体管的漏极、所述第四十三薄膜晶体管的栅极以及所述第三十三薄膜晶体管的栅极；
    所述第六十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
    所述第四十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述上拉控制模块的输出端；
    所述第三十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N-1级的扫描信号的输出端；
    所述第七十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N级的扫描信号的输出端。
  12. 根据权利要求8所述的栅极驱动电路，其特征在于，所述GOA单元至少包括第一自举电容和第二自举电容，所述自举电容的数量与所述上拉模块的数量相等。
  13. 根据权利要求8所述的栅极驱动电路，其特征在于，所述第一自举电容设置在所述上拉控制模块的输出端及所述第2N-1级的扫描信号的输出端之间；
    所述第二自举电容设置在所述上拉控制模块的输出端及所述第2N级的扫描信号的输出端之间。
  14. 根据权利要求8所述的栅极驱动电路，其特征在于，所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极和漏极电连接至第2N-5级的扫描信号G(2N-5)的输出端，源极电连接至所述上拉控制模块的输出端。
  15. 一种显示面板，包括栅极驱动电路，其特征在于，所述栅极驱动电路包括：
    至少第一时钟信号源，所述第一时钟信号源用于提供第2N-1级的时钟信号；
    至少第二时钟信号源，所述第二时钟信号源用于提供第2N级的时钟信号；
    恒压低电平源，用于提供恒压低电平；
    GOA器件，包括至少两个GOA单元，所述GOA单元包括：
    上拉控制模块，用于接收第一扫描信号，并根据所述第一扫描信号的控制至少生成第2N-1级的扫描电平信号、及第2N级的扫描电平信号；
    至少一第一上拉模块，所述第一上拉模块用于接收所述第2N-1级的扫描电平信号和所述第一时钟信号源提供的第2N-1级的时钟信号，以及用于根据所述第2N-1级的扫描电平信号以及所述第2N-1级的时钟信号拉升第2N-1级的扫描信号；
    至少一第二上拉模块，所述第二上拉模块用于接收所述第2N级的扫描电平信号和由所述第二时钟信号源提供的第2N级的时钟信号，以及用于根据所述第2N级的扫描电平信号以及所述第2N级的时钟信号拉升第2N级的扫描信号；
    下拉模块，用于接收第二扫描信号和由恒压低电平源提供的恒压低电平，以及用于根据所述第二扫描信号将所述恒压低电平输出至所述GOA单元的输出端；
    下拉维持模块，用于维持所述第2N-1级的扫描电平信号及所述第2N-1级的扫描信号的低电平、及所述第2N级的扫描电平信号及所述第2N级的扫描信号的低电平；
    至少一第一自举电容，所述第一自举电容用于生成所述第2N-1级的扫描电平信号的高电平；
    至少一第二自举电容，所述第二自举电容用于生成所述第2N级的扫描电平信号的高电平；
    所述上拉控制模块的输出端与至少一所述第一上拉模块、至少一所述第二上拉模块、所述下拉模块、所述下拉维持模块、至少一所述第一自举电容、及至少一所述第二自举电容电连接；
    所述恒压低电平源与所述下拉维持模块、及所述下拉模块电连接，所述第一时钟信号源与所述第一上拉模块电连接，所述第二时钟信号源与所述第二上拉模块电连接；
    其中，N为正整数。
  16. 根据权利要求15所述的显示面板，其特征在于，所述GOA单元包括第一上拉模块和第二上拉模块；
    所述第一上拉模块包括第二十一薄膜晶体管，所述二十一薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第一时钟信号源，源极电连接至所述第2N-1级的扫描信号的输出端；
    所述第二上拉模块包括第七十薄膜晶体管，所述第七十薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，漏极电连接至第二时钟信号源，源极电连接至所述第2N级的扫描信号的输出端。
  17. 根据权利要求15所述的显示面板，其特征在于，所述下拉模块包括第三十一薄膜晶体管、第四十一薄膜晶体管、及至少一第七十一薄膜晶体管；
    所述第三十一薄膜晶体管的栅极电连接至所述第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
    所述第四十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
    所述第七十一薄膜晶体管的栅极电连接至第二扫描信号的输出端，源极电连接至所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端。
  18. 根据权利要求15所述的显示面板，其特征在于，所述下拉维持模块包括第一下拉维持单元及第二下拉维持单元；
    所述第一下拉维持单元包括第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、第五十四薄膜晶体管、第四十二薄膜晶体管、第三十二薄膜晶体管、及至少一第七十二薄膜晶体管；
    所述第五十一薄膜晶体管的栅极以及漏极接入第一方波信号，源极电连接于所述第五十二薄膜晶体管的漏极以及所述第五十三薄膜晶体管的栅极；
    所述第五十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
    所述第五十三薄膜晶体管的漏极接入第一方波信号，源极电连接至所述第五十四薄膜晶体管的漏极、所述第四十二薄膜晶体管的栅极以及所述第三十二薄膜晶体管的栅极；
    所述第五十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
    所述第四十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述上拉控制模块的输出端；
    所述第三十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N-1级的扫描信号的输出端；
    所述第七十二薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接至所述第2N级的扫描信号的输出端；
    所述第二下拉维持单元包括第六十一薄膜晶体管、第六十二薄膜晶体管、第六十三薄膜晶体管、第六十四薄膜晶体管、第四十三薄膜晶体管、第三十三薄膜晶体管、及至少一第七十三薄膜晶体管；
    所述第六十一薄膜晶体管的栅极以及漏极接入第二方波信号，源极电连接于所述第六十二薄膜晶体管的漏极以及所述第六十三薄膜晶体管的栅极；
    所述第六十二薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接至所述恒压低电平源；
    所述第六十三薄膜晶体管的漏极接入第二方波信号，源极电连接于所述第六十四薄膜晶体管的漏极、所述第四十三薄膜晶体管的栅极以及所述第三十三薄膜晶体管的栅极；
    所述第六十四薄膜晶体管的栅极电连接至所述上拉控制模块的输出端，源极电连接于所述恒压低电平源；
    所述第四十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述上拉控制模块的输出端；
    所述第三十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N-1级的扫描信号的输出端；
    所述第七十三薄膜晶体管的源极电连接于所述恒压低电平源，漏极电连接于所述第2N级的扫描信号的输出端。
  19. 根据权利要求15所述的显示面板，其特征在于，所述GOA单元至少包括第一自举电容和第二自举电容，所述自举电容的数量与所述上拉模块的数量相等；
    所述第一自举电容设置在所述上拉控制模块的输出端及所述第2N-1级的扫描信号的输出端之间；
    所述第二自举电容设置在所述上拉控制模块的输出端及所述第2N级的扫描信号的输出端之间。
  20. 根据权利要求15所述的显示面板，其特征在于，所述上拉控制模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极和漏极电连接至第2N-5级的扫描信号G(2N-5)的输出端，源极电连接至所述上拉控制模块的输出端。
PCT/CN2019/078191 2019-01-21 2019-03-14 Goa器件及栅极驱动电路、显示面板 WO2020151065A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910054413.0A CN109637423A (zh) 2019-01-21 2019-01-21 Goa器件及栅极驱动电路
CN201910054413.0 2019-01-21

Publications (1)

Publication Number Publication Date
WO2020151065A1 true WO2020151065A1 (zh) 2020-07-30

Family

ID=66061477

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/078191 WO2020151065A1 (zh) 2019-01-21 2019-03-14 Goa器件及栅极驱动电路、显示面板

Country Status (2)

Country Link
CN (1) CN109637423A (zh)
WO (1) WO2020151065A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113793563A (zh) * 2021-10-27 2021-12-14 京东方科技集团股份有限公司 驱动电路、驱动模组、驱动方法和显示装置
CN115862511A (zh) * 2022-11-30 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109637421A (zh) * 2019-01-14 2019-04-16 京东方科技集团股份有限公司 栅极驱动电路以及显示基板
CN110223648B (zh) * 2019-05-09 2020-07-10 深圳市华星光电半导体显示技术有限公司 用于显示屏的驱动电路
TWI699744B (zh) * 2019-07-16 2020-07-21 友達光電股份有限公司 驅動方法、移位暫存器、以及相關的顯示裝置
CN110969977A (zh) * 2019-12-02 2020-04-07 深圳市华星光电半导体显示技术有限公司 一种栅极驱动电路、其控制方法及显示装置
CN111145680B (zh) * 2020-02-24 2021-07-27 苏州华星光电技术有限公司 驱动电路及显示面板
CN111292699B (zh) * 2020-03-31 2021-03-16 Tcl华星光电技术有限公司 双向输出goa电路及无缝拼接屏
CN111445880B (zh) * 2020-04-30 2022-04-05 深圳市华星光电半导体显示技术有限公司 Goa器件及栅极驱动电路
CN111477190A (zh) * 2020-05-13 2020-07-31 深圳市华星光电半导体显示技术有限公司 Goa器件及栅极驱动电路
CN113189806B (zh) * 2021-05-10 2023-08-01 深圳市华星光电半导体显示技术有限公司 Goa电路、液晶面板及其驱动方法、显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100150303A1 (en) * 2008-12-12 2010-06-17 Au Optronics Corp. Shift register with pre-pull-down module to suppress a spike
CN101976580A (zh) * 2010-10-12 2011-02-16 友达光电股份有限公司 可增加驱动能力的第n级移位寄存器及其方法
CN103325354A (zh) * 2013-02-25 2013-09-25 友达光电股份有限公司 栅极驱动电路
CN103345941A (zh) * 2013-07-03 2013-10-09 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、移位寄存器电路及显示装置
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
CN107507556A (zh) * 2017-09-30 2017-12-22 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路以及显示装置
CN107633833A (zh) * 2017-10-31 2018-01-26 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101661798B (zh) * 2009-09-24 2012-08-29 友达光电股份有限公司 移位寄存器电路与其栅极信号产生方法
TWI414152B (zh) * 2010-12-08 2013-11-01 Au Optronics Corp 移位暫存器電路
TWI426486B (zh) * 2010-12-16 2014-02-11 Au Optronics Corp 運用於電荷分享畫素的整合面板型閘極驅動電路
CN102651207B (zh) * 2011-02-22 2014-09-24 乐金显示有限公司 栅极驱动电路
CN103730094B (zh) * 2013-12-30 2016-02-24 深圳市华星光电技术有限公司 Goa电路结构
CN106448606A (zh) * 2016-11-23 2017-02-22 深圳市华星光电技术有限公司 一种goa驱动电路
CN107909980B (zh) * 2017-12-27 2020-08-04 深圳市华星光电技术有限公司 Goa电路及具有该goa电路的液晶显示装置
CN107919100B (zh) * 2018-01-04 2020-10-13 深圳市华星光电技术有限公司 一种栅极驱动电路及液晶显示器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100150303A1 (en) * 2008-12-12 2010-06-17 Au Optronics Corp. Shift register with pre-pull-down module to suppress a spike
CN101976580A (zh) * 2010-10-12 2011-02-16 友达光电股份有限公司 可增加驱动能力的第n级移位寄存器及其方法
CN103325354A (zh) * 2013-02-25 2013-09-25 友达光电股份有限公司 栅极驱动电路
CN103345941A (zh) * 2013-07-03 2013-10-09 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、移位寄存器电路及显示装置
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
CN107507556A (zh) * 2017-09-30 2017-12-22 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路以及显示装置
CN107633833A (zh) * 2017-10-31 2018-01-26 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113793563A (zh) * 2021-10-27 2021-12-14 京东方科技集团股份有限公司 驱动电路、驱动模组、驱动方法和显示装置
CN113793563B (zh) * 2021-10-27 2023-12-05 京东方科技集团股份有限公司 驱动电路、驱动模组、驱动方法和显示装置
CN115862511A (zh) * 2022-11-30 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN115862511B (zh) * 2022-11-30 2024-04-12 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

Also Published As

Publication number Publication date
CN109637423A (zh) 2019-04-16

Similar Documents

Publication Publication Date Title
WO2020151065A1 (zh) Goa器件及栅极驱动电路、显示面板
US9966025B1 (en) Gate driving circuit
JP6208872B2 (ja) 液晶表示に用いられるｇｏａ回路及び表示装置
WO2016173017A1 (zh) 具有正反向扫描功能的goa电路
JP6405056B2 (ja) Ｐｍｏｓゲート電極駆動回路
US9818363B2 (en) Charging scan and charge sharing scan double output GOA circuit
WO2017012160A1 (zh) 降低功耗的goa电路
WO2021007932A1 (zh) Goa电路
CN107909971B (zh) Goa电路
US20150187312A1 (en) GOA Circuit Structure
TWI438763B (zh) 顯示面板及其閘極驅動電路
WO2019024324A1 (zh) Goa驱动电路及液晶面板
JP2007034305A (ja) 表示装置
CN110068970B (zh) Tft阵列基板及显示面板
JP2020516960A (ja) Ｇｏａ回路駆動アーキテクチャ
WO2019200820A1 (zh) 液晶显示装置及其驱动方法
CN107340657A (zh) 阵列基板
WO2021007931A1 (zh) Tft阵列基板及显示面板
US10692454B2 (en) Gate driver on array having a circuit start signal applied to a pull-down maintenance module
WO2021072948A1 (zh) Goa器件及栅极驱动电路
WO2019000517A1 (zh) 基于goa电路的hva接线方法
CN106683624A (zh) Goa电路及液晶显示装置
US20190049768A1 (en) Goa circuit and liquid crystal display device
US10002560B2 (en) Gate drive on array unit, gate drive on array circuit and display apparatus
WO2020029377A1 (zh) 液晶显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19911248

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19911248

Country of ref document: EP

Kind code of ref document: A1