WO2019071702A1 - Cmos反相器及阵列基板 - Google Patents

Cmos反相器及阵列基板 Download PDF

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WO2019071702A1
WO2019071702A1 PCT/CN2017/110989 CN2017110989W WO2019071702A1 WO 2019071702 A1 WO2019071702 A1 WO 2019071702A1 CN 2017110989 W CN2017110989 W CN 2017110989W WO 2019071702 A1 WO2019071702 A1 WO 2019071702A1
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thin film
film transistor
semiconductor layer
gate insulating
metal oxide
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French (fr)
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周星宇
徐源竣
任章淳
吴元均
吕伯彦
杨伯儒
陈昌东
刘川
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a CMOS inverter and an array substrate.
  • LCD liquid crystal display
  • OLED organic light emitting display
  • CMOS Complementary Metal Oxide Semiconductor
  • inverter is a device often used in a flat display device, and mainly functions to receive an input signal and output an output signal that is logically opposite to the input signal.
  • the existing CMOS inverter usually includes an N-type thin film transistor (TFT) and a P-type thin film transistor.
  • TFT N-type thin film transistor
  • P-type thin film transistor P-type thin film transistor
  • the N-type thin film transistor and the P-type thin film transistor are both metal oxide thin film transistors, for example, Indium gallium zinc oxide (IGZO) TFTs, however, IGZO TFTs only appear as N-type unipolar semiconductors, and the lack of P-type semiconductors makes logic circuit design based on IGZO TFTs difficult.
  • IGZO TFTs Indium gallium zinc oxide
  • IGZO TFT logic circuits can be roughly divided into two categories: the first type is the use of IGZO TFTs to form pseudo-CMOS (Pseduo-CMOS) implementation of non-gates (ie, inverters), in pseudo CMOS design, Two IGZO TFTs have different threshold voltages, which requires simultaneous preparation of Depletion mode and Enhancement mode IGZO TFTs on the same sample. Then in pseudo CMOS fabrication, methods such as double-gate structure, double-layer active layer structure, and additional illumination to IGZO TFTs were invented. However, even in these improved inverters, the static power consumption of pseudo-CMOS is large. The problem of small noise margin has still not been solved.
  • the second type is the hybrid CMOS design, that is, the P-type thin film transistor is realized by other semiconductor materials different from metal oxide.
  • a P-type thin film transistor uses a two-dimensional carbon nanotube (CNT) material or an organic semiconductor material.
  • CNT carbon nanotube
  • the preparation of CNT materials is always partially metallized, and the mobility of organic semiconductor TFTs is low, and it is sensitive to water and oxygen in the environment, making the stability of P-type thin film transistors in existing hybrid CMOS very stable. difference.
  • CMOS inverter comprising: an electrically connected P-type low temperature polysilicon thin film transistor and an N-type metal oxide thin film transistor;
  • the P-type low temperature polysilicon thin film transistor and the N-type metal oxide thin film transistor satisfy the following formula:
  • C n and C P are respectively a gate insulating layer capacitance of the N-type metal oxide thin film transistor and a gate insulating layer capacitance of the P-type low temperature polysilicon thin film transistor, with
  • ⁇ n and ⁇ P are the mobility of the N-type metal oxide thin film transistor and the P-type low temperature, respectively.
  • the mobility of polysilicon thin film transistors are respectively a gate insulating layer capacitance of the N-type metal oxide thin film transistor and a gate insulating layer capacitance of the P-type low temperature polysilicon thin film transistor, with
  • ⁇ n and ⁇ P are the mobility of the N-type metal oxide thin film transistor and the P-type low temperature, respectively.
  • the mobility of polysilicon thin film transistors are respectively a gate insulating layer capacitance of the N-
  • the gate of the P-type low temperature polysilicon thin film transistor and the gate of the N-type metal oxide thin film transistor are all connected to the input signal;
  • One of a source of the P-type low temperature polysilicon thin film transistor and a source of the N-type metal oxide thin film transistor is grounded, a source of the P-type low temperature polysilicon thin film transistor, and a source of the N-type metal oxide thin film transistor Another access to the power supply voltage;
  • the drain of the P-type low temperature polysilicon thin film transistor and the drain of the N-type metal oxide thin film transistor each output an output signal.
  • the CMOS inverter includes: a substrate, a first semiconductor layer formed on the substrate, a first gate insulating layer covering the first semiconductor layer and the substrate, and a first electrode insulating layer disposed on the first gate insulating layer a metal layer, a second gate insulating layer covering the first metal layer and the first gate insulating layer, a second semiconductor layer formed on the second gate insulating layer, formed on the second semiconductor layer, and a second metal layer on the second gate insulating layer.
  • the first semiconductor layer is a semiconductor layer of the P-type low temperature polysilicon thin film transistor
  • the second semiconductor layer is a semiconductor layer of the N-type metal oxide thin film transistor.
  • the first metal layer includes: a first gate and a second gate which are spaced apart, the first gate is disposed opposite to the first semiconductor layer, and the second gate is opposite to the second semiconductor Layer setting
  • the first gate is a gate of a P-type low temperature polysilicon thin film transistor
  • the second gate is The gate of an N-type metal oxide thin film transistor.
  • a first via hole and a second via hole penetrating the first gate insulating layer and the second gate insulating layer are formed on the second gate insulating layer, and the first via hole and the second via hole are respectively exposed Illustrating both ends of the first semiconductor layer;
  • the second metal layer includes: a first source and a second source spaced apart from each other, and a first drain and a second drain between the first source and the second source; the first source a pole and a first drain are respectively in contact with both ends of the first semiconductor layer through the first via and the second via, and the second source and the second drain are respectively opposite to the second semiconductor layer Contacting at both ends, the first drain and the second drain are in contact;
  • the first source and the first drain are a source and a drain of a P-type low temperature polysilicon thin film transistor
  • the second source and the second drain are a source and a drain of an N-type metal oxide thin film transistor.
  • a buffer layer is further disposed between the first semiconductor layer and the substrate and between the first gate insulating layer and the substrate, and is further disposed on the second semiconductor layer between the second source and the second drain Etching the barrier layer.
  • the materials of the first gate insulating layer and the second gate insulating layer are each one of silicon oxide or silicon nitride or a combination of the two, and the materials of the first metal layer and the second metal layer are molybdenum, A combination of one or more of aluminum, copper, and titanium.
  • the material of the semiconductor layer of the N-type metal oxide thin film transistor is IGZO or IZO.
  • the present invention also provides an array substrate comprising the above-described CMOS inverter.
  • the present invention also provides a CMOS inverter comprising: an electrically connected P-type low temperature polysilicon thin film transistor and an N-type metal oxide thin film transistor;
  • the P-type low temperature polysilicon thin film transistor and the N-type metal oxide thin film transistor satisfy the following formula:
  • C n and C P are respectively a gate insulating layer capacitance of the N-type metal oxide thin film transistor and a gate insulating layer capacitance of the P-type low temperature polysilicon thin film transistor, with
  • the channel width-to-length ratio of the N-type metal oxide thin film transistor and the channel width-to-length ratio of the P-type low-temperature polysilicon thin film transistor, respectively, ⁇ n and ⁇ P are the mobility of the N-type metal oxide thin film transistor and the P-type low temperature, respectively. Mobility of polysilicon thin film transistors;
  • the gate of the P-type low temperature polysilicon thin film transistor and the gate of the N-type metal oxide thin film transistor are all connected to the input signal;
  • the source of the P-type low-temperature polysilicon thin film transistor is connected to a power supply voltage, and the N-type metal is oxidized.
  • the source of the thin film transistor is grounded, and the drain of the P-type low temperature polysilicon thin film transistor and the drain of the N-type metal oxide thin film transistor output an output signal;
  • the method further includes: a substrate, a first semiconductor layer formed on the substrate, a first gate insulating layer covering the first semiconductor layer and the substrate, a first metal layer disposed on the first gate insulating layer, and a cover a second gate insulating layer of the first metal layer and the first gate insulating layer, a second semiconductor layer formed on the second gate insulating layer, formed on the second semiconductor layer and the second gate insulating layer Second metal layer;
  • the first semiconductor layer is a semiconductor layer of the P-type low temperature polysilicon thin film transistor
  • the second semiconductor layer is a semiconductor layer of the N-type metal oxide thin film transistor
  • the first metal layer includes: a first gate and a second gate which are spaced apart, the first gate is disposed opposite to the first semiconductor layer, and the second gate is opposite to the first Two semiconductor layer settings;
  • the first gate is a gate of a P-type low temperature polysilicon thin film transistor
  • the second gate is a gate of an N-type metal oxide thin film transistor.
  • the present invention provides a CMOS inverter comprising: an electrically connected P-type low temperature polysilicon thin film transistor and an N-type metal oxide thin film transistor; the P-type low temperature polysilicon thin film transistor and N-type metal oxide
  • the thin film transistor satisfies the following formula: Wherein C n and C P are respectively a gate insulating layer capacitance of the N-type metal oxide thin film transistor and a gate insulating layer capacitance of the P-type low temperature polysilicon thin film transistor, with The channel width-to-length ratio of the N-type metal oxide thin film transistor and the channel width-to-length ratio of the P-type low-temperature polysilicon thin film transistor, respectively, ⁇ n and ⁇ P are the mobility of the N-type metal oxide thin film transistor and the P-type low temperature, respectively.
  • the mobility of the polysilicon thin film transistor can improve the performance of the CMOS inverter and reduce the manufacturing difficulty and production cost of the CMOS inverter by making the P-type low temperature polysilicon thin film transistor and the N-type metal oxide thin film transistor satisfy the above formula.
  • the invention also provides an array substrate, which can improve the performance of the CMOS inverter and reduce the manufacturing difficulty and production cost of the CMOS inverter.
  • FIG. 1 is a structural diagram of a CMOS inverter of the present invention
  • FIG. 2 is an equivalent circuit diagram of a CMOS inverter of the present invention.
  • the present invention provides a CMOS inverter comprising: an electrically connected P-type low temperature polysilicon thin film transistor 10 and an N-type metal oxide thin film transistor 20;
  • the P-type low temperature polysilicon thin film transistor 10 and the N-type metal oxide thin film transistor 20 satisfy the following formula:
  • C n and C P are the gate insulating layer capacitance of the N-type metal oxide thin film transistor 20 and the gate insulating layer capacitance of the P-type low temperature polysilicon thin film transistor 10, respectively.
  • ⁇ n and ⁇ P are the mobility of the N-type metal oxide thin film transistor 20, respectively.
  • the gate of the P-type low temperature polysilicon thin film transistor 10 and the gate of the N-type metal oxide thin film transistor 20 are both connected to the input signal Vin;
  • the source of the P-type low temperature polysilicon thin film transistor 10 is connected to a power supply voltage Vdd, the source of the N-type metal oxide thin film transistor 20 is grounded;
  • the drain of the P-type low temperature polysilicon thin film transistor 10 and an N-type metal oxide The drains of the thin film transistors 20 each output an output signal Vout.
  • the N-type metal oxide thin film transistor 20 In operation, when the input signal Vin is at a high potential, the N-type metal oxide thin film transistor 20 is turned on, the output signal Vout is grounded through the N-type metal oxide thin film transistor 20, and the output signal Vout is low.
  • the P-type low temperature polysilicon thin film transistor 10 When the input signal Vin is at a low potential, the P-type low temperature polysilicon thin film transistor 10 is turned on, the output signal Vout outputs a power supply voltage Vdd, and the output signal Vout is at a high potential.
  • the detailed structure of the CMOS inverter is as follows, the CMOS inverter includes: a substrate 30, a first semiconductor layer 11 formed on the substrate 30, and a cover a first gate insulating layer 12 of the first semiconductor layer 11 and the substrate 30, a first metal layer 13 disposed on the first gate insulating layer 12, covering the first metal layer 13 and the first gate insulating layer 12 a second gate insulating layer 18, a second semiconductor formed on the second gate insulating layer 18
  • the bulk layer 14 is formed on the second semiconductor layer 14 and the second metal layer 15 on the second gate insulating layer 18.
  • the first semiconductor layer 11 is a semiconductor layer of the P-type low temperature polysilicon thin film transistor 10
  • the second semiconductor layer 14 is a semiconductor of the N-type metal oxide thin film transistor 20. Floor.
  • the first metal layer 13 includes: a first gate 131 and a second gate 132 which are spaced apart, and the first gate 131 is disposed opposite to the first semiconductor layer 11
  • the electrode 132 is disposed opposite to the second semiconductor layer 14; wherein the first gate 131 is a gate of the P-type low temperature polysilicon thin film transistor 10, and the second gate 132 is an N-type metal oxide thin film transistor 20 The gate.
  • a first via 141 and a second via 142 penetrating the first gate insulating layer 12 and the second gate insulating layer 18 are formed on the second gate insulating layer 18, and the first via 141 And the second via 142 respectively expose both ends of the first semiconductor layer 11;
  • the second metal layer 14 includes: a first source 151 and a second source 152 spaced apart from each other, and the first source a first drain 153 and a second drain 154 between the 151 and the second source 152; the first source 151 and the first drain 153 pass through the first via 141 and the second via 142, respectively In contact with both ends of the first semiconductor layer 11, the second source 152 and the second drain 154 are respectively in contact with both ends of the second semiconductor layer 14, the first drain 153 and the second The drain 154 is in contact; wherein the first source 151 and the first drain 153 are the source and the drain of the P-type low temperature polysilicon thin film transistor 10, and the second source 152 and the second drain 154 are N The source and drain of
  • the CMOS inverter is further provided with a buffer layer 16 between the first semiconductor layer 11 and the substrate 30 and between the first gate insulating layer 12 and the substrate 30, in the second source.
  • An etch stop layer 17 is further disposed on the second semiconductor layer 14 between the pole 152 and the second drain 154.
  • the materials of the first gate insulating layer 12 and the second gate insulating layer 14 are each one of silicon oxide or silicon nitride or a combination of the two, the first metal layer 13 and the second metal layer
  • the material of 15 is a combination of one or more of molybdenum, aluminum, copper, and titanium.
  • the material of the semiconductor layer of the N-type metal oxide thin film transistor 20 is IGZO or IZO.
  • CMOS inverter using a P-type low temperature polysilicon thin film transistor 10 and an N-type metal oxide thin film transistor 20:
  • CMOS inverter By designing a CMOS inverter according to this formula, the characteristics of the P-type thin film transistor and the N-type thin film transistor can be more matched, and the P-type thin film transistor and the N-type thin film transistor can both operate at fullness. And zone to achieve better CMOS inverter effects.
  • the CMOS inverter of the present invention uses a low-temperature polysilicon thin film transistor as a P-type thin film transistor, a metal oxide thin film transistor as an N-type thin film transistor, and two thin film transistors are mixed to form a CMOS inverter, compared to only using A CMOS inverter of a rigid low-temperature polysilicon thin film transistor, the present invention can improve the ductility of a CMOS inverter by using a metal oxide thin film transistor as an N-type thin film transistor, thereby making the CMOS inverter more suitable for flexible electronic products.
  • the present invention can reduce the number of photolithography and doping times and simplify the fabrication process as compared with a CMOS inverter using only a low-temperature polysilicon thin film transistor. Compared with the conventional pseudo CMOS inverter using only the metal oxide thin film transistor, the present invention can reduce the static power consumption, increase the noise margin, and ensure the fabrication quality of the CMOS inverter.
  • the present invention further provides an array substrate including the above-described CMOS inverter, and the specific technical features of the CMOS inverter are the same as those of the above CMOS inverter, and are not described herein again.
  • the array substrate of the present invention simultaneously forms a low-temperature polysilicon thin film transistor and a metal oxide thin film transistor on the same substrate, and the two are mixed to form a CMOS inverter, wherein the low-temperature polysilicon thin film transistor is used as a P-type thin film transistor.
  • Metal Oxide Thin Film Transistor As an N-type thin film transistor, the present invention can make a CMOS inverter by using a metal oxide thin film transistor as an N-type thin film transistor as compared with a CMOS inverter using only a rigid low-temperature polysilicon thin film transistor.
  • the ductility is improved, making CMOS inverters more suitable for flexible electronic products, and existing CMOS inverters using only low-temperature polysilicon thin film transistors require complex fabrication processes of at least 9 lithography and 4 doping.
  • the CMOS inverter of the present invention can be fabricated only by using 6 lithography and 1 doping.
  • the metal oxide thin film transistor of the CMOS inverter can be used with the metal in the pixel array in the array substrate when the array substrate is fabricated.
  • the oxide thin film transistor is simultaneously fabricated, so the array substrate of the present invention can enhance CMOS inversion The performance and reduce the CMOS inverter production difficulty and cost of production.
  • the present invention provides a CMOS inverter comprising: an electrically connected P-type low temperature polysilicon thin film transistor and an N-type metal oxide thin film transistor; the P-type low temperature polysilicon thin film transistor and an N-type metal oxide
  • the thin film transistor satisfies the following formula: Wherein C n and C P are respectively a gate insulating layer capacitance of the N-type metal oxide thin film transistor and a gate insulating layer capacitance of the P-type low temperature polysilicon thin film transistor, with The channel width-to-length ratio of the N-type metal oxide thin film transistor and the channel width-to-length ratio of the P-type low-temperature polysilicon thin film transistor, respectively, ⁇ n and ⁇ P are the mobility of the N-type metal oxide thin film transistor and the P-type low temperature, respectively.
  • the mobility of the polysilicon thin film transistor can improve the performance of the CMOS inverter and reduce the manufacturing difficulty and production cost of the CMOS inverter by making the P-type low temperature polysilicon thin film transistor and the N-type metal oxide thin film transistor satisfy the above formula.
  • the invention also provides an array substrate, which can improve the performance of the CMOS inverter and reduce the manufacturing difficulty and production cost of the CMOS inverter.

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  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种CMOS反相器及阵列基板。该CMOS反相器包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足公式（I）；其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，（II）和（III）分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。

Description

CMOS反相器及阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种CMOS反相器及阵列基板。
背景技术
随着显示技术的发展，包括液晶显示装置(Liquid Crystal Display，LCD)及有机发光二极管显示装置(Organic Light Emitting Display，OLED)在内的平面显示装置已经成为最为常见的显示装置，被广泛地应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品之中。
CMOS(Complementary Metal Oxide Semiconductor，互补式金属氧化物半导体)反相器是平面显示装置中经常使用的一器件，主要作用为接收一输入信号，并输出与输入信号逻辑相反的一输出信号。
现有的CMOS反相器通常包括一个N型薄膜晶体管(Thin Film Transistor，TFT)和一个P型薄膜晶体管，理想情况希望该N型薄膜晶体管和P型薄膜晶体管均为金属氧化物薄膜晶体管，例如铟镓锌氧化物(IGZO)TFT，然而，IGZO TFT只表现为N型单极性半导体，P型半导体的缺失使得基于IGZO TFT的逻辑电路设计面临难题。
现有技术关于IGZO TFT逻辑电路设计的研究可大体分为两类：第一类是仅使用IGZO TFT组成伪CMOS(Pseduo-CMOS)实现非门(即反相器)，在伪CMOS设计时，两个IGZO TFT要有不同的阈值电压，这就要求在同一块样品上同时制备出耗尽型(Depletion mode)和增强型(Enhancement mode)IGZO TFT。那么在伪CMOS制备时，诸如双栅结构、双层主动层结构和对IGZO TFT额外光照等方法就被发明出来，然而即使在这些工艺改进过的反相器中，伪CMOS的静态功耗大和噪声容限小的问题依旧未能解决。第二类就是采用混合型CMOS设计，也即P型薄膜晶体管由不同于金属氧化物的其他半导体材料来实现。在以往的混合CMOS设计中，P型薄膜晶体管使用的是二维碳纳米管(CNT)材料或有机半导体材料。然而CNT材料的制备中总是会有部分被金属化，而有机半导体TFT的迁移率又很低，且对环境中水氧敏感，使得现有的混合型CMOS中P型薄膜晶体管的稳定性很差。
发明内容
本发明的目的在于提供一种CMOS反相器，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
本发明的目的还在于提供一种阵列基板，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
为实现上述目的，本发明提供了一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；
所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：
Figure PCTCN2017110989-appb-000001
其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，
Figure PCTCN2017110989-appb-000002
和
Figure PCTCN2017110989-appb-000003
分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率。
所述P型低温多晶硅薄膜晶体管的栅极和N型金属氧化物薄膜晶体管的栅极均接入输入信号；
所述P型低温多晶硅薄膜晶体管的源极和N型金属氧化物薄膜晶体管的源极中的一个接地，所述P型低温多晶硅薄膜晶体管的源极和N型金属氧化物薄膜晶体管的源极中的另一个接入电源电压；
所述P型低温多晶硅薄膜晶体管的漏极和N型金属氧化物薄膜晶体管的漏极均输出输出信号。
所述CMOS反相器包括：基板、形成于所述基板上的第一半导体层、覆盖所述第一半导体层和基板的第一栅绝缘层、设于所述第一栅绝缘层上的第一金属层、覆盖所述第一金属层和第一栅绝缘层的第二栅绝缘层、形成于所述第二栅绝缘层上的第二半导体层、形成于所述第二半导体层和第二栅绝缘层上的第二金属层。
所述第一半导体层为所述P型低温多晶硅薄膜晶体管的半导体层，所述第二半导体层为所述N型金属氧化物薄膜晶体管的半导体层。
所述第一金属层包括：间隔分布的第一栅极和第二栅极，所述第一栅极正对所述第一半导体层设置，所述第二栅极正对所述第二半导体层设置；
所述第一栅极为P型低温多晶硅薄膜晶体管的栅极，所述第二栅极为 N型金属氧化物薄膜晶体管的栅极。
所述第二栅绝缘层上形成有贯穿所述第一栅绝缘层和第二栅绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述第一半导体层的两端；
所述第二金属层包括：间隔分布的第一源极和第二源极、以及位于第一源极和第二源极之间的第一漏极和第二漏极；所述第一源极和第一漏极分别通过所述第一过孔和第二过孔与所述第一半导体层的两端接触，所述第二源极和第二漏极分别与所述第二半导体层的两端接触，所述第一漏极和第二漏极接触；
所述第一源极和第一漏极为P型低温多晶硅薄膜晶体管的源极和漏极，所述第二源极和第二漏极为N型金属氧化物薄膜晶体管的源极和漏极。
在所述第一半导体层与基板之间以及第一栅绝缘层与基板之间还设有缓冲层，在所述第二源极和第二漏极之间的第二半导体层上还设有刻蚀阻挡层。
所述第一栅绝缘层和第二栅绝缘层的材料均为氧化硅或氮化硅中的一种或二者的组合，所述第一金属层和第二金属层的材料均为钼、铝、铜、及钛中的一种或多种的组合。
所述N型金属氧化物薄膜晶体管的半导体层的材料为IGZO或IZO。
本发明还提供一种阵列基板，包括上述的CMOS反相器。
本发明还提供一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；
所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：
Figure PCTCN2017110989-appb-000004
其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，
Figure PCTCN2017110989-appb-000005
和
Figure PCTCN2017110989-appb-000006
分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率；
其中，所述P型低温多晶硅薄膜晶体管的栅极和N型金属氧化物薄膜晶体管的栅极均接入输入信号；
所述P型低温多晶硅薄膜晶体管的源极接入电源电压，N型金属氧化 物薄膜晶体管的源极接地，所述P型低温多晶硅薄膜晶体管的漏极和N型金属氧化物薄膜晶体管的漏极均输出输出信号；
还包括：基板、形成于所述基板上的第一半导体层、覆盖所述第一半导体层和基板的第一栅绝缘层、设于所述第一栅绝缘层上的第一金属层、覆盖所述第一金属层和第一栅绝缘层的第二栅绝缘层、形成于所述第二栅绝缘层上的第二半导体层、形成于所述第二半导体层和第二栅绝缘层上的第二金属层；
其中，所述第一半导体层为所述P型低温多晶硅薄膜晶体管的半导体层，所述第二半导体层为所述N型金属氧化物薄膜晶体管的半导体层；
其中，所述第一金属层包括：间隔分布的第一栅极和第二栅极，所述第一栅极正对所述第一半导体层设置，所述第二栅极正对所述第二半导体层设置；
所述第一栅极为P型低温多晶硅薄膜晶体管的栅极，所述第二栅极为N型金属氧化物薄膜晶体管的栅极。
本发明的有益效果：本发明提供一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：
Figure PCTCN2017110989-appb-000007
Figure PCTCN2017110989-appb-000008
其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，
Figure PCTCN2017110989-appb-000009
和
Figure PCTCN2017110989-appb-000010
分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率，通过使得P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足上述公式，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。本发明还提供一种阵列基板，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的CMOS反相器的结构图；
图2为本发明的CMOS反相器的等效电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管10和N型金属氧化物薄膜晶体管20；
所述P型低温多晶硅薄膜晶体管10和N型金属氧化物薄膜晶体管20满足以下公式：
Figure PCTCN2017110989-appb-000011
其中，Cn和CP分别为N型金属氧化物薄膜晶体管20的栅绝缘层电容和P型低温多晶硅薄膜晶体管10的栅绝缘层电容，
Figure PCTCN2017110989-appb-000012
和
Figure PCTCN2017110989-appb-000013
分别为N型金属氧化物薄膜晶体管20的沟道宽长比和P型低温多晶硅薄膜晶体管10的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管20的迁移率和P型低温多晶硅薄膜晶体管10的迁移率。
具体地，如图2所示，本发明的CMOS反相器中，所述P型低温多晶硅薄膜晶体管10的栅极和N型金属氧化物薄膜晶体管20的栅极均接入输入信号Vin；所述P型低温多晶硅薄膜晶体管10的源极接入电源电压Vdd，所述N型金属氧化物薄膜晶体管20的源极接地；所述P型低温多晶硅薄膜晶体管10的漏极和N型金属氧化物薄膜晶体管20的漏极均输出输出信号Vout。
工作时，当所述输入信号Vin为高电位时，所述N型金属氧化物薄膜晶体管20打开，所述输出信号Vout通过所述N型金属氧化物薄膜晶体管20接地，输出信号Vout为低电位，当所述输入信号Vin为低电位时，所述P型低温多晶硅薄膜晶体管10打开，所述输出信号Vout输出电源电压Vdd，输出信号Vout为高电位。
详细地，在本发明的优选实施例中，所述CMOS反相器的详细结构如下，所述CMOS反相器包括：基板30、形成于所述基板30上的第一半导体层11、覆盖所述第一半导体层11和基板30的第一栅绝缘层12、设于所述第一栅绝缘层12上的第一金属层13、覆盖所述第一金属层13和第一栅绝缘层12的第二栅绝缘层18、形成于所述第二栅绝缘层18上的第二半导 体层14、形成于所述第二半导体层14和第二栅绝缘层18上的第二金属层15。
进一步地，在上述实施例中，所述第一半导体层11为所述P型低温多晶硅薄膜晶体管10的半导体层，所述第二半导体层14为所述N型金属氧化物薄膜晶体管20的半导体层。
进一步地，所述第一金属层13包括：间隔分布的第一栅极131和第二栅极132，所述第一栅极131正对所述第一半导体层11设置，所述第二栅极132正对所述第二半导体层14设置；其中，所述第一栅极131为P型低温多晶硅薄膜晶体管10的栅极，所述第二栅极132为N型金属氧化物薄膜晶体管20的栅极。
进一步地，所述第二栅绝缘层18上形成有贯穿所述第一栅绝缘层12和第二栅绝缘层18的第一过孔141和第二过孔142，所述第一过孔141和第二过孔142分别暴露出所述第一半导体层11的两端；所述第二金属层14包括：间隔分布的第一源极151和第二源极152、以及位于第一源极151和第二源极152之间的第一漏极153和第二漏极154；所述第一源极151和第一漏极153分别通过所述第一过孔141和第二过孔142与所述第一半导体层11的两端接触，所述第二源极152和第二漏极154分别与所述第二半导体层14的两端接触，所述第一漏极153和第二漏极154接触；其中，所述第一源极151和第一漏极153为P型低温多晶硅薄膜晶体管10的源极和漏极，所述第二源极152和第二漏极154为N型金属氧化物薄膜晶体管20的源极和漏极。
值得一提的是，所述CMOS反相器在所述第一半导体层11与基板30之间以及第一栅绝缘层12与基板30之间还设有缓冲层16，在所述第二源极152和第二漏极154之间的第二半导体层14上还设有刻蚀阻挡层17。
优选地，所述第一栅绝缘层12和第二栅绝缘层14的材料均为氧化硅或氮化硅中的一种或二者的组合，所述第一金属层13和第二金属层15的材料均为钼、铝、铜、及钛中的一种或多种的组合。所述N型金属氧化物薄膜晶体管20的半导体层的材料为IGZO或IZO。
进一步地，本发明针对采用P型低温多晶硅薄膜晶体管10和N型金属氧化物薄膜晶体管20的CMOS反相器，提出了具体的设计准则：
Figure PCTCN2017110989-appb-000014
按照此公式设计CMOS反相器，可以使P型薄膜晶体管和N型薄膜晶体管的特性更加匹配，保证P型薄膜晶体管和N型薄膜晶体管均工作于饱 和区，达到更好的CMOS反相器效果。
需要说明的是，本发明的CMOS反相器采用低温多晶硅薄膜晶体管作为P型薄膜晶体管，金属氧化物薄膜晶体管作为N型薄膜晶体管，两种薄膜晶体管混合组成CMOS反相器，相比于仅采用刚性的低温多晶硅薄膜晶体管的CMOS反相器，本发明通过采用金属氧化物薄膜晶体管作为N型薄膜晶体管，能够使得CMOS反相器的延展性得到提升，从而使得CMOS反相器更胜任柔性电子产品的要求，且现有的仅采用低温多晶硅薄膜晶体管的CMOS反相器需要至少9次光刻和4次掺杂的复杂制作工艺，而本发明的CMOS反相器只用到6次光刻和1次掺杂即可完成制作，因此本发明相比仅采用低温多晶硅薄膜晶体管的CMOS反相器，还能够减少光刻和掺杂次数，简化制作工艺。而相比于传统的仅采用金属氧化物薄膜晶体管的伪CMOS反相器，本发明又可以减小静态功耗，增大噪声容限，保证CMOS反相器的制作品质。
基于上述的CMOS反相器，本发明还提供一种阵列基板，其包括上述的CMOS反相器，所述CMOS反相器的具体技术特征与上述CMOS反相器相同，在此不再赘述。
需要说明的是，本发明的阵列基板通过在同一基板同时制备了低温多晶硅薄膜晶体管以及金属氧化物薄膜晶体管，两者混合组成了CMOS反相器，其中，低温多晶硅薄膜晶体管作为P型薄膜晶体管，金属氧化物薄膜晶体管作为N型薄膜晶体管，相比于仅采用刚性的低温多晶硅薄膜晶体管的CMOS反相器，本发明通过采用金属氧化物薄膜晶体管作为N型薄膜晶体管，能够使得CMOS反相器的延展性得到提升，从而使得CMOS反相器更胜任柔性电子产品的要求，且现有的仅采用低温多晶硅薄膜晶体管的CMOS反相器需要至少9次光刻和4次掺杂的复杂制作工艺，而本发明的CMOS反相器只用到6次光刻和1次掺杂即可完成制作，在制作阵列基板时CMOS反相器的金属氧化物薄膜晶体管可以与阵列基板中像素阵列内的金属氧化物薄膜晶体管同时制作，因此本发明的阵列基板能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
综上所述，本发明提供一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：
Figure PCTCN2017110989-appb-000015
Figure PCTCN2017110989-appb-000016
其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，
Figure PCTCN2017110989-appb-000017
和
Figure PCTCN2017110989-appb-000018
分别为N型金属氧 化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率，通过使得P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足上述公式，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。本发明还提供一种阵列基板，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (15)

  1. 一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；
    所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：
    Figure PCTCN2017110989-appb-100001
    其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，
    Figure PCTCN2017110989-appb-100002
    和
    Figure PCTCN2017110989-appb-100003
    分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率。
  2. 如权利要求1所述的CMOS反相器，其中，所述P型低温多晶硅薄膜晶体管的栅极和N型金属氧化物薄膜晶体管的栅极均接入输入信号；
    所述P型低温多晶硅薄膜晶体管的源极接入电源电压，N型金属氧化物薄膜晶体管的源极接地，所述P型低温多晶硅薄膜晶体管的漏极和N型金属氧化物薄膜晶体管的漏极均输出输出信号。
  3. 如权利要求1所述的CMOS反相器，还包括：基板、形成于所述基板上的第一半导体层、覆盖所述第一半导体层和基板的第一栅绝缘层、设于所述第一栅绝缘层上的第一金属层、覆盖所述第一金属层和第一栅绝缘层的第二栅绝缘层、形成于所述第二栅绝缘层上的第二半导体层、形成于所述第二半导体层和第二栅绝缘层上的第二金属层。
  4. 如权利要求3所述的CMOS反相器，其中，所述第一半导体层为所述P型低温多晶硅薄膜晶体管的半导体层，所述第二半导体层为所述N型金属氧化物薄膜晶体管的半导体层。
  5. 如权利要求4所述的CMOS反相器，其中，所述第一金属层包括：间隔分布的第一栅极和第二栅极，所述第一栅极正对所述第一半导体层设置，所述第二栅极正对所述第二半导体层设置；
    所述第一栅极为P型低温多晶硅薄膜晶体管的栅极，所述第二栅极为N型金属氧化物薄膜晶体管的栅极。
  6. 如权利要求5所述的CMOS反相器，其中，所述第二栅绝缘层上形 成有贯穿所述第一栅绝缘层和第二栅绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述第一半导体层的两端；
    所述第二金属层包括：间隔分布的第一源极和第二源极、以及位于第一源极和第二源极之间的第一漏极和第二漏极；所述第一源极和第一漏极分别通过所述第一过孔和第二过孔与所述第一半导体层的两端接触，所述第二源极和第二漏极分别与所述第二半导体层的两端接触，所述第一漏极和第二漏极接触；
    所述第一源极和第一漏极为P型低温多晶硅薄膜晶体管的源极和漏极，所述第二源极和第二漏极为N型金属氧化物薄膜晶体管的源极和漏极。
  7. 如权利要求3所述的CMOS反相器，其中，在所述第一半导体层与基板之间以及第一栅绝缘层与基板之间还设有缓冲层，在所述第二源极和第二漏极之间的第二半导体层上还设有刻蚀阻挡层。
  8. 如权利要求3所述的CMOS反相器，其中，所述第一栅绝缘层和第二栅绝缘层的材料均为氧化硅或氮化硅中的一种或二者的组合，所述第一金属层和第二金属层的材料均为钼、铝、铜、及钛中的一种或多种的组合。
  9. 如权利要求1所述的CMOS反相器，其中，所述N型金属氧化物薄膜晶体管的半导体层的材料为IGZO或IZO。
  10. 一种阵列基板，包括如权利要求1所述的CMOS反相器。
  11. 一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；
    所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：
    Figure PCTCN2017110989-appb-100004
    其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，
    Figure PCTCN2017110989-appb-100005
    和
    Figure PCTCN2017110989-appb-100006
    分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率；
    其中，所述P型低温多晶硅薄膜晶体管的栅极和N型金属氧化物薄膜晶体管的栅极均接入输入信号；
    所述P型低温多晶硅薄膜晶体管的源极接入电源电压，N型金属氧化物薄膜晶体管的源极接地，所述P型低温多晶硅薄膜晶体管的漏极和N型 金属氧化物薄膜晶体管的漏极均输出输出信号；
    还包括：基板、形成于所述基板上的第一半导体层、覆盖所述第一半导体层和基板的第一栅绝缘层、设于所述第一栅绝缘层上的第一金属层、覆盖所述第一金属层和第一栅绝缘层的第二栅绝缘层、形成于所述第二栅绝缘层上的第二半导体层、形成于所述第二半导体层和第二栅绝缘层上的第二金属层；
    其中，所述第一半导体层为所述P型低温多晶硅薄膜晶体管的半导体层，所述第二半导体层为所述N型金属氧化物薄膜晶体管的半导体层；
    其中，所述第一金属层包括：间隔分布的第一栅极和第二栅极，所述第一栅极正对所述第一半导体层设置，所述第二栅极正对所述第二半导体层设置；
    所述第一栅极为P型低温多晶硅薄膜晶体管的栅极，所述第二栅极为N型金属氧化物薄膜晶体管的栅极。
  12. 如权利要求11所述的CMOS反相器，其中，所述第二栅绝缘层上形成有贯穿所述第一栅绝缘层和第二栅绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述第一半导体层的两端；
    所述第二金属层包括：间隔分布的第一源极和第二源极、以及位于第一源极和第二源极之间的第一漏极和第二漏极；所述第一源极和第一漏极分别通过所述第一过孔和第二过孔与所述第一半导体层的两端接触，所述第二源极和第二漏极分别与所述第二半导体层的两端接触，所述第一漏极和第二漏极接触；
    所述第一源极和第一漏极为P型低温多晶硅薄膜晶体管的源极和漏极，所述第二源极和第二漏极为N型金属氧化物薄膜晶体管的源极和漏极。
  13. 如权利要求11所述的CMOS反相器，其中，在所述第一半导体层与基板之间以及第一栅绝缘层与基板之间还设有缓冲层，在所述第二源极和第二漏极之间的第二半导体层上还设有刻蚀阻挡层。
  14. 如权利要求11所述的CMOS反相器，其中，所述第一栅绝缘层和第二栅绝缘层的材料均为氧化硅或氮化硅中的一种或二者的组合，所述第一金属层和第二金属层的材料均为钼、铝、铜、及钛中的一种或多种的组合。
  15. 如权利要求11所述的CMOS反相器，其中，所述N型金属氧化物薄膜晶体管的半导体层的材料为IGZO或IZO。
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