Classifications

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  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/425—Barrier, adhesion or liner layers
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/04—Coating on selected surface areas, e.g. using masks
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  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
  • C23C16/16—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal carbonyl compounds
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  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
  • C23C16/45523—Pulsed gas flow or change of composition over time
  • C23C16/45525—Atomic layer deposition [ALD]
  • C23C16/45553—Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
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  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/56—After-treatment
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  • H10D64/01—Manufacture or treatment
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  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
  • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
  • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition
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  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
  • H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
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  • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
  • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
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  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6326—Deposition processes
  • H10P14/6328—Deposition from the gas or vapour phase
  • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
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  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
  • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
  • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
  • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
  • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
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  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
  • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
  • H10W20/045—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]
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  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
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  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
  • H10W20/059—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by reflowing or applying pressure
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  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
  • H10W20/0595—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by using multiple deposition steps separated by etching steps
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  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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  • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
  • H10P52/40—Chemomechanical polishing [CMP]
  • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
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  • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
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  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/42—Vias, e.g. via plugs
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  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/44—Conductive materials thereof
  • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
  • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
  • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal

Definitions

• the present invention relates to methods for void-free filling of features such as vias and trenches for microelectronic devices with low resistivity ruthenium (Ru) metal.
• An integrated circuit contains various semiconductor devices and a plurality of conducting metal paths that provide electrical power to the semiconductor devices and allow these semiconductor devices to share and exchange information.
• metal layers are stacked on top of one another using intermetal and interlayer dielectric layers that insulate the metal layers from each other.
• each metal layer must form an electrical contact to at least one additional metal layer.
• Such electrical contact is achieved by etching a feature (i.e., a via) in the interlayer dielectric that separates the metal layers, and filling the resulting via with a metal to create an interconnect.
• Metal layers typically occupy etched pathways in the interlayer dielectric.
• a "via” normally refers to any feature such as a hole, line or other similar feature formed within a dielectric layer that provides an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer.
• metal layers connecting two or more vias are normally referred to as trenches.
• Cu metal layers, Cu filled trenches, and Cu filled vias are normally encapsulated with a barrier material to prevent Cu atoms from diffusing into the dielectrics and Si.
• Barrier layers are normally deposited on trench and via sidewalls and bottoms prior to Cu seed deposition, and may include materials that are preferably non-reactive and immiscible in Cu, provide good adhesion to the dielectrics and can offer low electrical resistivity.
• An increase in device performance is normally accompanied by a decrease in device area or an increase in device density.
• An increase in device density requires a decrease in via dimensions used to form interconnects, including a larger aspect ratio (i.e., depth to width ratio).
• via dimensions decrease and aspect ratios increase it becomes increasingly more challenging to form diffusion barrier layers with adequate thickness on the sidewalls of the vias, while also providing enough volume for the metal layer in the via.
• the material properties of the layers and the layer interfaces become increasingly more important. In particular, the processes forming those layers need to be carefully integrated into a
• a method for Ru metal filling of features in a substrate includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal. [0009] According another embodiment, the method includes providing a substrate containing features, depositing a Ru metal layer in the features, where depositing the Ru metal layer pinches off the feature openings before the features is filled with the Ru metal layer, thereby forming a void inside the feature.
• the method further includes removing excess Ru metal that caused the pinch-off, where the removing removes the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the feature, where the additional Ru metal is deposited in the features at a higher rate than on the field area.
• the additional Ru metal is deposited until the features are fully filled with Ru metal.
• FIGS. 1A - ID schematically show cross-sectional Ru metal filling of features according to an embodiment of the invention.
• FIGS. 2A - 2C show cross-sectional scanning electron microscopy (SEM) images of Ru metal filling of features according to an embodiment of the invention.
• Ru metal with its short effective electron mean free path, is an excellent candidate to meet International Technology Roadmap for Semiconductors (ITRS) resistance requirements as a Cu metal replacement at about lOnm (5nm node) minimum feature sizes. Due to many material and electrical properties of Ru metal, it is less affected by downward scaling of feature sizes than Cu metal.
• IRS International Technology Roadmap for Semiconductors
• the method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the feature at a higher rate than on the field area.
• the method includes providing a substrate containing features, depositing a Ru metal layer in the features, where depositing the Ru metal layer pinches off feature openings before the features are filled with the Ru metal layer, thereby forming a void inside the features.
• the method further includes removing excess Ru metal that caused the pinch-off, where the removing removes the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area.
• Embodiments of the invention may be applied to a variety of recessed features of different physical shapes found in semiconductor devices, including square features with vertical sidewalls, bowed features with convex sidewalls, and features with a sidewall having an area of retrograde profile relative to a direction extending from a top of the feature to the bottom of the features.
• the features can, for example, include a trench or a via.
• a feature diameter can be less than 30nm, less than 20nm, less than lOnm, or less than 5nm.
• a feature diameter can be between 20nm and 30nm, between lOnm and 20nm, between 5nm and l Onm, or between 3nm and 5nm.
• a depth of the features can, for example be greater 20nm, greater than 50nm, greater than lOOnm, or greater than 200nm.
• the features can, for example, have an aspect ratio (AR, depth:width) between 2: 1 and 20: 1 , between 2: 1 and 10: 1, or between 2: 1 and 5: 1.
• the substrate e.g., Si
• the substrate includes a dielectric layer and the feature is formed in the dielectric layer.
• FIGS. 1 A - ID schematically show cross-sectional Ru metal filling of features according to an embodiment of the invention.
• the substrate 10 contains features 104 in a film 102, where the features 104 include a sidewall 108 having an area of retrograde profile relative to a direction extending from a top of the features 104 to the bottom of the features 104 above a film 100.
• the substrate 10 further contains a field area 106 near the openings of the features 104.
• the films 100 and 102 may contain the same material.
• the material may be selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal-containing material.
• the dielectric material may selected from the group consisting of SiC , SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.
• the films 100 and 102 may contain different materials.
• the different materials may be selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal-containing material.
• the dielectric material may be selected from the group consisting of SiCh, SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.
• FIG. IB show a conformal Ru metal layer 110 deposited with a substantially uniform thickness on the substrate 10, including on the field area 106 and in the features 104.
• the conformal Ru metal layer 110 pinches off the feature openings before the features 104 are filled with the Ru metal, thereby blocking further Ru metal deposition in the features 104 and forming voids (keyholes) 112 inside the features 104.
• the Ru metal layer 110 consists of pure Ru metal or substantially pure Ru metal containing a small amount of impurities (e.g., carbon and oxygen).
• the Ru metal layer 110 may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), plating, or sputtering. In one example, the Ru metal layer may be deposited by CVD using Ru3(CO)i2 and CO carrier gas at a substrate temperature of about 200°C.
• Ru metal precursors may be used by CVD to deposit the Ru metal layer 110.
• a nucleation layer may be deposited on the substrate 10, including in the features 104, by ALD or CVD prior to the Ru metal deposition.
• the nucleation layer may be selected from the group consisting of Mo, MoN, Ta, TaN, TaAIN, W, WN, Ti, TiN, and TiAlN.
• a role of the nucleation layer is to provide a good nucleation surface and an adhesion surface in the features 104 to ensure conformal deposition of the Ru metal layer 110 with a short incubation time. Unlike when using a Cu metal fill, a good diffusion barrier layer is not required between the dielectric material and the Ru metal in the features.
• the nucleation layer in the case of a Ru metal fill, can be very thin and may be non-continuous or incomplete with gaps that expose a dielectric material in the features. This allows for increasing the amount of Ru metal in a feature fill compared to a Cu metal feature fill.
• a thickness of the nucleation layer can be 20 A or less, 15A or less, lOA or less, or 5 A or less.
• a TaN nucleation layer may be deposited using atomic layer deposition (ALD) with alternating exposures of tert-butylimido-tris- ethylmethylamido-tantalum (TBTEMT, Ta(NCMe3)(NEtMe)3) and ammonia (Nft) at a substrate temperature of about 350°C.
• ALD atomic layer deposition
• FIG. 1C shows the substrate 10 following removal of the Ru metal layer 110 from the field area 106 around the openings of the features 104 and removal of the Ru metal layer 110 that caused the pinch-off of the feature openings.
• the removal of the Ru metal layer 110 can include exposing the substrate 10 to a plasma-excited dry etching process.
• the plasma-excited dry etching process can include a chemical reaction between a plasma-excited etching gas and the Ru metal layer 110, physical removal of the Ru metal layer 110 by a non-reactive gas, or a combination thereof.
• the plasma-excited dry etching process includes exposing the substrate 10 to a plasma- excited etching gas containing an oxygen-containing gas and optionally a halogen-containing gas.
• the removing can include sputter removal or redistribution of the Ru metal layer 110 using a plasma- excited Ar gas.
• the removal of the Ru metal layer 110 may include a chemical mechanical polishing (CMP) process.
• CMP chemical mechanical polishing
• the removal of the Ru metal layer 110 can include heat-treating the Ru metal layer 110 to reflow the Ru metal layer 110 in the features 104.
• the removal of the Ru metal layer 110 can include a combination of a plasma-excited dry etching process and heat-treating.
• Exemplary processing conditions for a plasma-excited dry etching process include a gas pressure between about 5mTorr and about 760mTorr, substrate temperature between about 40°C about 370°C.
• a capacitively coupled plasma (CCP) processing system containing a top electrode plate and a bottom electrode plate supporting a substrate may be used.
• CCP capacitively coupled plasma
• RF radio frequency
• the plasma excited etching gas can contain an oxygen- containing gas and optionally a halogen-containing gas to enhance the Ru metal removal.
• the oxygen-containing gas can include O2, H2O, CO, CO2, and a combination thereof.
• the halogen-containing gas can, for example, include Cb, BCh, CF 4 , and a combination thereof.
• the plasma excited etching gas can include O2 and Cb.
• the plasma excited etching gas can further include Ar gas.
• the plasma excited etching gas can consist of O2 gas and optionally Ar gas. In some embodiments, one or more of the gases in the plasma excited etching gas may be cycled.
• FIG. ID shows the substrate 10 following depositing of additional Ru metal 114 in the features 104 that results in void-free Ru metal filling of the features 104.
• the inventors have discovered that the additional Ru metal 114 is deposited on the Ru metal layer 110 in the features 104 at a higher rate than on the field area 106 of the film 102, thereby enabling complete Ru metal filling of the features 104 and preventing pinch-off of the feature openings before the features 104 are filled with the additional Ru metal 114. Together, the Ru metal layer 110 and the additional Ru metal 114 fully fill the features 104 with Ru metal, with excess Ru metal present on the field area 106. According to some embodiments, the steps of Ru metal deposition and the Ru metal removal may be repeated at least once if needed to provide void-free Ru metal filling of the features 104.
• the substrate 10 may be heat-treated in order to minimize impurities in the Ru metal and to increase Ru metal grain size. This results in lowering the electrical resistance of the Ru metal.
• the substrate following the removal of the Ru metal layer 110 from the field area 106 around the openings of the features 104, the substrate may be heat-treated in order to minimize impurities in the Ru metal and provide improved Ru metal deposition selectivity in the features 104 relative to on the field area 106.
• the heat-treating may be performed at a substrate temperature between 200°C and 600°C, between 300°C and 400°C, between 500°C and 600°C, between 400°C and 450°C, or between 450°C and 500°C.
• the heat-treating may be performed at below atmospheric pressure in the presence of Ar gas, H2 gas, or both Ar gas and H2 gas.
• the heat-treating may be performed at below atmospheric pressure in the presence of forming gas.
• Forming gas is a mixture of H2 and N2.
• the heat-treating may be performed under high-vacuum conditions without flowing a gas into a process chamber used for the heat-treating.
• FIGS. 2A - 2C show cross-sectional SEM images of Ru metal filling of features according to an embodiment of the invention.
• FIG. 2A shows a conformal Ru metal layer 202 deposited on a substrate containing features etched in a film 200. The features had an opening diameter of about 19nm, a bottom diameter of about 40nm, and a height of about 83nm.
• the conformal Ru metal layer 202 was deposited by CVD using Ru3(CO)i2 and CO carrier gas at a substrate temperature of about 200°C.
• the conformal Ru metal layer 202 layer in FIG. 2A pinched-off the feature openings before the features were filled with Ru metal, thereby forming voids 212 inside the features.
• FIG. 2A shows a conformal Ru metal layer 202 deposited on a substrate containing features etched in a film 200. The features had an opening diameter of about 19nm, a bottom diameter of about 40nm, and a height of about 83nm.
• FIG. 2B shows the substrate following removal of the conformal Ru metal layer 202 from the field area 206 around the openings of the features and removal of a portion of the Ru metal layer 202 that caused the pinch-off of the feature openings.
• the Ru metal removal was performed using a plasma-excited dry etching process that included exposing the substrate to a plasma-excited etching gas containing an O2 gas, Cb gas, and Ar gas.
• FIG. 2C shows the substrate following deposition of additional Ru metal 214 in the features that results in void-free Ru metal filling of the features.
• the additional Ru metal 214 was deposited in the features at a higher rate than on the field area 206, thereby enabling the complete Ru metal filling of the features and preventing pinching-off the feature openings before features were filled with the Ru metal.

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