WO2019061926A1 - Procédé d'interconnexion verticale de trou traversant de silicium tridimensionnel à base de structure composite de nanomatériau de carbone - Google Patents

Procédé d'interconnexion verticale de trou traversant de silicium tridimensionnel à base de structure composite de nanomatériau de carbone Download PDF

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Publication number
WO2019061926A1
WO2019061926A1 PCT/CN2018/000016 CN2018000016W WO2019061926A1 WO 2019061926 A1 WO2019061926 A1 WO 2019061926A1 CN 2018000016 W CN2018000016 W CN 2018000016W WO 2019061926 A1 WO2019061926 A1 WO 2019061926A1
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WIPO (PCT)
Prior art keywords
layer
silicon
composite structure
depositing
dry film
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PCT/CN2018/000016
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English (en)
Chinese (zh)
Inventor
陆向宁
何贞志
韩继光
宿磊
樊梦莹
刘凡
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江苏师范大学
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Publication of WO2019061926A1 publication Critical patent/WO2019061926A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Definitions

  • the invention relates to a method for vertical interconnection of through-silicon vias, in particular to a three-dimensional through-silicon via vertical interconnection method based on a composite structure of carbon nano materials, belonging to the technical field of microelectronic packaging.
  • Microelectronic packaging technology faces new challenges as integrated circuit (IC) integrated circuit functions, size reduction, energy consumption and cost reduction.
  • IC integrated circuit
  • three-dimensional packaging technology came into being.
  • TSV Through Silicon Via
  • TSV technology directly bonds two or more layers of device die or the entire silicon wafer through a number of vertically through electrodes to achieve the shortest and most abundant z-directional interconnection. This not only improves device integration, but also reduces interconnect latency, increases device speed and reduces power consumption. Therefore, TSV technology is regarded as one of the mainstream processes for the development of future packaging technologies.
  • the TSV interconnect channel will become a highly dense and very complex three-dimensional microstructure group.
  • the increase in package density causes the power density of the stacked chip to rise sharply due to the significant difference between the thermal expansion coefficients of the package material.
  • the 3D TSV structure faces serious heat dissipation problems, and the silicon/copper thermal stress mismatch problem is also more prominent. This results in a large thermal stress in the TSV structure at both process and service temperatures.
  • the stress migration occurring under the residual stress of the process causes the vacancies in the metal to move and accumulate in the direction of the stress gradient to form voids, which eventually leads to the disconnection of the interconnect; the residual stress accumulated in the process and the thermal stress in the TSV structure at the service temperature are superimposed, The stress situation in the TSV structure is more complicated, and severe thermal stress mismatch will lead to the failure of the TSV interconnect structure.
  • the present invention provides a three-dimensional through-silicon via vertical interconnection method based on a carbon nanomaterial composite structure, which solves the heat dissipation problem of the TSV package structure caused by the increase in power density and the thermal stress loss between the package materials. Match the problem.
  • the technical solution adopted by the present invention is: a three-dimensional through-silicon via vertical interconnection method based on a carbon nano material composite structure, comprising the following steps:
  • the catalytic metal layer is formed by ion beam sputtering or physical vapor deposition, and the catalytic metal layer material is cobalt or iron.
  • the nano catalytic particles are formed by plasma etching, and the etching gas is hydrogen or argon.
  • the carbon nanomaterial composite structure layer in the step e is prepared by a thermal chemical vapor deposition method, the carbon source gas is methane, and hydrogen is used as a shielding gas, and the total gas pressure is stabilized at 1 kPa.
  • the structure of the carbon nanomaterial composite structure layer in the step e is divided into two layers, the upper layer is a horizontal multilayer graphene, and the lower layer is a vertical carbon nanotube array.
  • the diameter of the dry film layer is smaller than the diameter of the silicon hole and the hole of the dry film layer is coaxial with the silicon hole.
  • the silicon hole is plated with a conductive material by using the seed layer as a guide.
  • the present invention opens a hole in a silicon substrate and then deposits an insulating layer, a barrier layer, a carbon nano material composite structure layer, a dry film, a seed layer and a conductive material, and a good thermal energy using the carbon nanotube bundle.
  • mechanical properties to solve the heat dissipation problem of the TSV package structure caused by the increase in power density and the thermal stress mismatch between the package materials, improve the thermal conductivity and package reliability of the 3D-TSV structure.
  • FIG. 1 is a schematic view showing the structure of a silicon hole according to the present invention.
  • FIG. 2 is a schematic view showing the structure of depositing an insulating layer, a barrier layer and a catalytic metal layer in this invention
  • FIG. 3 is a schematic view showing the structure of etching a catalytic metal layer of the present invention to form nano catalytic metal particles;
  • FIG. 4 is a schematic structural view of a composite carbon nanomaterial composite structure layer of the present invention.
  • FIG. 5 is a schematic structural view of a carbon nanomaterial composite structural layer
  • Figure 6 is a schematic view showing the structure of the dry film layer of the present invention.
  • FIG. 7 is a schematic structural view of depositing a seed layer and filling a conductive material according to the present invention.
  • FIG. 8 is a schematic diagram of thermal stress buffering of a carbon nanomaterial composite structure layer of the present invention.
  • silicon substrate 2, insulating layer, 3, barrier layer, 4, catalytic metal layer, 5, carbon nano material composite structural layer, 6, dry film layer, 7, seed layer, 8, conductive material, 9, silicon holes.
  • the present invention includes the following steps:
  • a silicon hole 9 is formed on the silicon substrate 1;
  • the surface of the carbon nanomaterial composite structure layer 5 on the silicon substrate 1 is coated with a dry film, exposed and developed to form a dry film layer 6;
  • the conductive material 8 is filled in the silicon hole 9.
  • a silicon hole 9 is formed on the silicon substrate 1 by deep reaction etching, laser etching or wet etching; the diameter of the silicon hole 9 is 1-100 ⁇ m, and the silicon hole 9 is The cross section is generally circular, and the aspect ratio of the silicon holes 9 is generally from 1 to 30.
  • an insulating layer 2 is grown on the surface of the silicon substrate 1 and the inner walls (circumferential surface and bottom surface) of the silicon via 9, and the deposition of the insulating layer 2 is performed by thermal oxidation, chemical vapor deposition or physical vapor deposition, and the insulating layer is formed.
  • the material of 2 may be selected from inorganic materials such as silicon dioxide, aluminum oxide or silicon nitride, the thickness of the insulating layer 2 is 0.5-1 micrometer; the barrier layer 3 is deposited on the insulating layer 2, and the deposition of the barrier layer 3 is performed by physical vapor deposition or
  • the material of the barrier layer 3 may be selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, etc., and the thickness of the barrier layer 3 is 50-100 nm; the catalytic metal layer 4 is deposited on the barrier layer 3, and the catalytic metal is The layer 4 is formed by ion beam sputtering or physical vapor deposition.
  • the material is generally cobalt or iron, and the thickness of the catalytic metal layer 4 is 2-5 nm.
  • the catalytic metal layer 4 is etched by plasma etching to form nano-catalytic particles; the etching gas is hydrogen or argon, and the plasma power density is 0.1-0.5 (W/cm2), time 0.5- 3 minutes.
  • a carbon nanomaterial composite structure layer 5 is grown on the surface of the catalytic metal layer 4; the growth process is performed by a thermal chemical vapor deposition method, the carbon source gas is methane, and hydrogen gas is used as a shielding gas, and the total gas pressure is stabilized at 1 kPa.
  • the growth temperature is 450-600 ° C; the growth of the carbon nanomaterial composite structure layer 5 firstly precipitates the graphene layer from the catalytic metal cobalt, and then synthesizes the carbon nano material composite structural layer 5 from the cobalt nanoparticles according to the tip growth mode, as shown in FIG. 5 . It is shown that the structure of the carbon nanomaterial composite structure layer 5 after growth is that the upper layer is a graphene layer and the lower layer is a carbon nanotube bundle array.
  • the surface of the carbon nanomaterial composite structure layer 5 on the silicon substrate 1 is coated with a dry film, and the structure of the silicon hole 9 is exposed by exposure and development, and then the multilayer dry film is attached to the silicon substrate by hot pressing.
  • the surface of the sheet 1 is exposed by a photolithography machine, and the exposed silicon substrate 1 is placed in a developing solution to remove a part of the dry film to form a dry film layer 6 requiring a pattern.
  • the diameter of the dry film layer 6 is smaller than that of the silicon hole 9.
  • the diameter of the dry film layer 6 is coaxial with the silicon hole 9.
  • a seed layer 7 is deposited on the bottom surface of the silicon hole 9 and the surface of the dry film layer 6.
  • the seed layer 7 is deposited on the silicon hole by electron beam evaporation or magnetron sputtering using the dry film layer 6 as a mask.
  • the material of the seed layer 7 is generally selected from gold or copper; the conductive material 8 is filled by electroplating in the silicon hole 9 with the seed layer 7 as a guide, and the conductive material 8 is filled by electroplating, and the conductive material is used.
  • 8 is generally copper; an inhibitor and an accelerator are added to the plating solution to achieve high-speed, high-quality filling of the conductive material 8 "bottom up".
  • the bottom of the TSV channel is removed by chemical mechanical polishing techniques and planarization is achieved.
  • the heat in the TSV channel can be rapidly transferred up and down and left and right through the carbon nanomaterial composite structure layer 5 to accelerate thermal diffusion, regardless of process conditions or service conditions. Meanwhile, the thermal stress of the carbon nanomaterial composite structural layer 5 as the filling material 8
  • the release and buffer layers avoid severe thermal stress mismatch between the fill material 8 and the insulating layer 2/silicon substrate 1 causing TSV interconnect defects or even failure.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un procédé d'interconnexion verticale de trou traversant de silicium tridimensionnel à base de structure composite de nanomatériau de carbone : fabriquer des trous de silicium sur un substrat de silicium ; déposer une couche isolante sur une surface du substrat de silicium et une paroi interne des trous de silicium ; déposer une couche de blocage sur la couche isolante, et déposer une couche métallique catalytique sur la couche de blocage ; graver la couche métallique catalytique pour former des nanoparticules catalytiques ; utiliser les nanoparticules catalytiques pour faire croître une couche composite de nanomatériau de carbone ; fixer un film sec sur une surface de la couche composite de nanomatériau de carbone sur le substrat de silicium, exposer et développer pour former une couche de film sec ; déposer une couche de germe sur une surface inférieure des trous de silicium et une surface de la couche de film sec ; remplir un matériau conducteur dans les trous de silicium. La présente invention utilise les excellentes performances thermiques et mécaniques d'un nanomatériau de carbone pour résoudre le problème de dissipation de chaleur d'une structure d'encapsulation de trou d'interconnexion traversant le silicium (TSV)) qui est provoquée par une densité de puissance accrue ainsi que le problème de désadaptation de contrainte thermique entre des matériaux d'encapsulation, améliorant ainsi la conductivité thermique et la fiabilité d'encapsulation d'une structure de TSV 3D.
PCT/CN2018/000016 2017-09-28 2018-01-15 Procédé d'interconnexion verticale de trou traversant de silicium tridimensionnel à base de structure composite de nanomatériau de carbone WO2019061926A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710900247.2 2017-09-28
CN201710900247.2A CN107658263B (zh) 2017-09-28 2017-09-28 一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法

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CN109524513A (zh) * 2018-11-23 2019-03-26 江苏新广联半导体有限公司 一种硅基倒装led芯片及其制作方法
CN116435290B (zh) * 2023-06-13 2023-08-22 中诚华隆计算机技术有限公司 一种芯片的三维堆叠结构和堆叠方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010025962A1 (en) * 2000-03-31 2001-10-04 Masayuki Nakamoto Field emmision type cold cathode device, manufacturing method thereof and vacuum micro device
US20020163079A1 (en) * 2001-05-02 2002-11-07 Fujitsu Limited Integrated circuit device and method of producing the same
CN102569181A (zh) * 2011-12-15 2012-07-11 中国科学院微电子研究所 一种碳纳米管束垂直互连的制作方法
CN103258789A (zh) * 2013-04-17 2013-08-21 华中科技大学 一种通孔互联结构的制作方法及其产品

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102530931B (zh) * 2011-12-14 2014-04-02 天津大学 基于石墨烯的纳米复合材料及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010025962A1 (en) * 2000-03-31 2001-10-04 Masayuki Nakamoto Field emmision type cold cathode device, manufacturing method thereof and vacuum micro device
US20020163079A1 (en) * 2001-05-02 2002-11-07 Fujitsu Limited Integrated circuit device and method of producing the same
CN102569181A (zh) * 2011-12-15 2012-07-11 中国科学院微电子研究所 一种碳纳米管束垂直互连的制作方法
CN103258789A (zh) * 2013-04-17 2013-08-21 华中科技大学 一种通孔互联结构的制作方法及其产品

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CN107658263B (zh) 2021-01-22

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