WO2019052233A1 - 二极管、功率器件、电力电子设备及二极管制作方法 - Google Patents

二极管、功率器件、电力电子设备及二极管制作方法 Download PDF

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Publication number
WO2019052233A1
WO2019052233A1 PCT/CN2018/089781 CN2018089781W WO2019052233A1 WO 2019052233 A1 WO2019052233 A1 WO 2019052233A1 CN 2018089781 W CN2018089781 W CN 2018089781W WO 2019052233 A1 WO2019052233 A1 WO 2019052233A1
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Prior art keywords
type semiconductor
conductive type
semiconductor substrate
layer
diode
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PCT/CN2018/089781
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English (en)
French (fr)
Inventor
曾丹
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格力电器（武汉）有限公司
珠海格力电器股份有限公司
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Publication of WO2019052233A1 publication Critical patent/WO2019052233A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a diode, a power device, a power electronic device, and a method of fabricating a diode.
  • power devices also known as power electronics devices
  • power electronics devices have gradually shifted from single discrete devices to high-current power modules and smart power modules.
  • High-current power modules In high-power applications such as power grids and locomotives, high-current power modules are mainly used.
  • High-current power modules generally include two types of chips: insulated gate bipolar transistors (IGBT) and fast recovery diodes (FRD).
  • IGBT insulated gate bipolar transistors
  • FRD fast recovery diodes
  • a combination of several IGBTs and FRDs is typically packaged in one module depending on the power level.
  • Intelligent power modules In low-power applications such as inverter household appliances and small-scale inverter industrial equipment, intelligent power modules are mainly used. Intelligent power modules generally include four types of chips: IGBT, FRD, power control circuit (MIC) and bootstrap diode (BDI). Some smart power modules may also not include a BDI chip, which is disposed on the main circuit board of the electronic power device.
  • IGBT IGBT
  • FRD power control circuit
  • BDI bootstrap diode
  • Some smart power modules may also not include a BDI chip, which is disposed on the main circuit board of the electronic power device.
  • Embodiments of the present invention provide a diode, including:
  • a second conductive type semiconductor located on a side of the first conductive type semiconductor epitaxial layer away from the first conductive type semiconductor substrate;
  • a first metal layer located on a side of the resistance layer away from the first conductive type semiconductor substrate.
  • the resistance layer covers a second side surface of the first conductive type semiconductor substrate.
  • the resistance layer covers a partial region of the second side surface of the first conductive type semiconductor substrate.
  • the resistance layer comprises a plurality of resistor units arranged in an array.
  • the shape of the orthographic projection of the resistor unit on the first conductive type semiconductor substrate comprises a circle, a square or a polygon.
  • the resistance layer is located in the same physical structure layer as the first conductive type semiconductor substrate.
  • the resistance layer and the first conductive type semiconductor substrate are located in different physical structure layers.
  • the resistive layer is at least two layers.
  • the material type of the resistance layer comprises an amorphous silicon layer, an oxide semiconductor layer or a doped polysilicon layer.
  • the first conductive semiconductor substrate is an N-type semiconductor substrate
  • the first conductive semiconductor epitaxial layer is an N-type semiconductor epitaxial layer
  • the second conductive semiconductor is a P-type semiconductor.
  • the diode further includes a voltage resistant terminal structure, the voltage resistant terminal structure is located on a side of the first conductive semiconductor epitaxial layer away from the first conductive type semiconductor substrate, and surrounds the second conductive type Semiconductor setup.
  • a resistor layer is integrated in the diode of the embodiment of the invention, and the power device including the diode is applied to the power electronic device, and the circuit board of the power electronic device does not need to be separately provided with a resistor, thereby simplifying the circuit board structure and reducing the circuit board area. To enable power electronics to achieve a compact design.
  • An embodiment of the present invention further provides a power device, including the diode of any of the foregoing technical solutions. Since the resistor layer is integrated in the diode of the power device, the power device is applied to the power electronic device, and the circuit board of the power electronic device does not need to be separately provided with a resistor, thereby simplifying the circuit board structure and reducing the board area. Enables power electronics to achieve a compact design.
  • An embodiment of the present invention further provides a power electronic device, including the power device described in the foregoing technical solution.
  • the power electronic device can be provided with no resistor on the circuit board, so the circuit board has a simplified structure and a small area, and the power electronic device is easy to realize a compact design.
  • the embodiment of the invention further provides a diode manufacturing method, including:
  • a first metal layer is formed on a side of the resistance layer away from the first conductive type semiconductor substrate.
  • the forming a resistance layer on the second side of the first conductive type semiconductor substrate comprises: performing a second conductive type doping on the entire surface of the second side surface of the first conductive type semiconductor substrate Miscellaneous injection treatment.
  • the forming a resistance layer on the second side of the first conductive type semiconductor substrate comprises: performing a partial region of the second side surface of the first conductive type semiconductor substrate by a mask patterning process The second conductivity type doping implantation process.
  • the forming a resistance layer on the second side of the first conductive type semiconductor substrate comprises: forming an amorphous silicon layer and an oxide semiconductor layer on a second side of the first conductive type semiconductor substrate Or doped polysilicon layer.
  • the method further comprises: performing a thinning treatment and a stress release etching treatment on the second side surface of the first conductive type semiconductor substrate in sequence.
  • the method further comprises: performing an activation process of doping the resistive layer.
  • the diode fabricated by the above method has a resistor layer integrated in the diode, so that the power device including the diode is applied to the power electronic device, and the circuit board of the power electronic device does not need to be separately provided with a resistor, thereby simplifying the circuit board structure and reducing The small board area enables power electronics to be miniaturized.
  • 1a is a schematic cross-sectional view showing the structure of a diode according to a first embodiment of the present invention
  • 1b is a schematic view showing the fabrication of a resistor layer of a diode according to a first embodiment of the present invention
  • FIG. 2a is a schematic cross-sectional view showing the structure of a diode according to a second embodiment of the present invention
  • FIG. 2b is a top plan view of a resistive layer in a diode according to a second embodiment of the present invention.
  • 2c is a schematic view showing the fabrication of a resistor layer of a diode according to a second embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing the structure of a diode according to a third embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method for fabricating a diode according to a sixth embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a method for fabricating a diode according to a seventh embodiment of the present invention.
  • FIG. 6 is a schematic flow chart of a method for fabricating a diode according to an eighth embodiment of the present invention.
  • a diode provided in Embodiment 1 of the present invention includes:
  • a first conductive type semiconductor epitaxial layer 2 located on a first side of the first conductive type semiconductor substrate 1;
  • a second conductive type semiconductor 3 located on the side of the first conductive type semiconductor epitaxial layer 2 away from the first conductive type semiconductor substrate 1;
  • the first metal layer 6 is located on the side of the resistance layer 5 away from the first conductive type semiconductor substrate 1.
  • diodes in the embodiments of the present invention are not limited, including but not limited to rectifier diodes, Zener diodes, switching diodes or bootstrap diodes, and the like.
  • the first conductive semiconductor substrate 1 may be an N-type semiconductor substrate, the first conductive semiconductor epitaxial layer 2 is an N-type semiconductor epitaxial layer, and the second conductive semiconductor 3 is a P-type semiconductor. Further, the first conductive type semiconductor substrate 1 may be a P type semiconductor substrate, and the first conductive type semiconductor epitaxial layer 2 is a P type semiconductor epitaxial layer; and the second conductive type semiconductor 3 is an N type semiconductor.
  • the chip fab production line mostly uses an N-type semiconductor material as a chip substrate. Therefore, the first conductive type semiconductor substrate 1 in the embodiment of the present invention preferably adopts an N-type semiconductor substrate, which is convenient for collinear production and saves cost.
  • the second conductive type semiconductor 3 and the first conductive type semiconductor epitaxial layer 2 may be located in different physical structural layers or in the same physical structural layer.
  • the second conductive semiconductor 3 and the first conductive semiconductor epitaxial layer 2 are located in the same physical structure layer, and the second conductive type is implanted in the set region of the first conductive semiconductor epitaxial layer 2 Doping forms a second conductivity type semiconductor 3, and a junction of the second conductivity type semiconductor 3 and the first conductivity type semiconductor epitaxial layer 2 forms a semiconductor junction.
  • the structure of the diode may further include a withstand voltage terminal structure 4, and the voltage-resistant terminal structure 4 is located at the first conductive type semiconductor.
  • the epitaxial layer 2 is apart from one side of the first conductive type semiconductor substrate 1 and disposed around the second conductive type semiconductor 3.
  • the pressure-resistant terminal structure 4 may include a pressure-resistant ring 41, a dielectric layer 42 and a pressure-resistant terminal metal 43 disposed in a direction away from the first conductive type semiconductor substrate 1, wherein the pressure-resistant ring 41 may be
  • the one-conductivity-type semiconductor epitaxial layer 2 is located in the same physical structure layer, and the pressure-resistant ring 41 is formed by implanting a doping of the second conductivity type in the peripheral region of the first-conductivity-type semiconductor epitaxial layer 2.
  • the second metal layer 8 is located inside the annular shape of the withstand voltage terminal structure and is in contact with the second conductive type semiconductor 3, and the passivation layer 9 exposes a portion of the second metal layer 8.
  • the portion of the second metal layer 8 exposed by the passivation layer 9, and the aforementioned first metal layer 6 serve as two electrodes of the diode, respectively.
  • a protective film 10 may be integrally attached to the surface of the passivation layer 9 away from the first conductive type semiconductor substrate 1 , and the protective film 10 can effectively protect the second metal layer 8 .
  • the portion exposed by the passivation layer 9 is prevented from being contaminated and damaged during subsequent fabrication processes.
  • the protective film 10 is removed.
  • the resistive layer 5 covers the second side surface of the first conductive type semiconductor substrate 1, and the resistive layer 5 is located on the same physical structure layer as the first conductive type semiconductor substrate 1.
  • FIG. 1b by performing a second conductivity type doping implantation process on the entire surface of the second side surface of the first conductive type semiconductor substrate 1, the first conductive type semiconductor substrate 1 can be neutralized in the second The first conductive type particles on the side surface are such that the partial resistivity is increased to form the resistive layer 5 shown in Fig. 1a.
  • the relevant process conditions such as gas atmosphere, gas flow rate, device power, etc.
  • the circuit board of the prior art power electronic device is generally provided with a resistor element for reducing the peak current when the diode is being charged in the forward direction, thereby reducing interference to other circuits, but on the other hand, the circuit board structure is complicated. This hinders the development of equipment in the direction of miniaturization.
  • the diode is integrated with a resistance layer, and the power device including the diode is applied to the power electronic device, and the circuit board of the power electronic device does not need to be separately provided with a resistor, thereby simplifying the circuit board structure and reducing the circuit board.
  • the area enables power electronics to be miniaturized.
  • the resistive layer 5 is in the form of a resistive layer 5 covering the first conductive type semiconductor substrate 1.
  • the resistance layer 5 includes a plurality of resistor units 5a arranged in an array.
  • the specific shape of the resistance unit 5a is not limited, and for example, the shape of the orthographic projection on the first conductive type semiconductor substrate 1 may be a circle, a square or a polygon, or the like.
  • the resistive layer 5 is located in the same physical structural layer as the first conductive type semiconductor substrate 1.
  • a partial region of the second side surface of the first conductive type semiconductor substrate 1 i.e., a region corresponding to the resistor unit 5a
  • the impurity implantation process can form the resistive layer 5 of a certain thickness in the partial region.
  • the injection depth of the second conductivity type doping can be adjusted by controlling relevant process conditions such as gas atmosphere, gas flow rate, device power, etc., thereby forming the resistance layer 5 of a desired thickness.
  • the diode of the second embodiment of the present invention integrates a resistance layer, and the power device including the diode is applied to the power electronic device, and the circuit board of the power electronic device does not need to be separately provided with a resistor, thereby simplifying the circuit board structure.
  • the board area is reduced, enabling power electronics to be miniaturized.
  • the resistive layer 5 is configured in such a manner that the resistive layer 5 covers the second side of the first conductive type semiconductor substrate 1.
  • the surface, and the resistive layer 5 and the first conductive type semiconductor substrate 1 are located in different physical structural layers.
  • the resistive layer 5 of this embodiment has a single layer structure.
  • the resistive layer may also be at least two layers.
  • the specific material type of the resistance layer is not limited, and may be, for example, an amorphous silicon layer, an oxide semiconductor layer, or a doped polysilicon layer.
  • the resistance layer is at least two layers, the material types of the resistance layers of the respective layers may be the same or different.
  • the diode of the third embodiment of the present invention integrates a resistance layer, and the power device including the diode is applied to the power electronic device, and the circuit board of the power electronic device does not need to be separately provided with a resistor, thereby simplifying the circuit board structure and reducing The board area enables power electronics to be miniaturized.
  • Embodiment 4 of the present invention provides a power device including the diode of any of the foregoing embodiments. Since the resistor layer is integrated in the diode of the power device, the power device is applied to the power electronic device, and the circuit board of the power electronic device does not need to be separately provided with a resistor, thereby simplifying the circuit board structure and reducing the board area. Enables power electronics to achieve a compact design.
  • the specific type of power device is not limited, and may be an intelligent power module (IPM) or other small power module.
  • Embodiment 5 of the present invention provides a power electronic device, including the power device of any of the foregoing technical solutions.
  • the power electronic device can be provided with no resistor on the circuit board, so the circuit board has a simplified structure and a small area, and the power electronic device is easy to realize a compact design.
  • the specific type of power electronic equipment is not limited, and may be, for example, a frequency conversion household appliance or a small frequency conversion industrial equipment.
  • the sixth embodiment of the present invention provides a diode manufacturing method, which can be used to fabricate the diode of the first embodiment. As shown in FIG. 1a, FIG. 1b and FIG. 4, the method specifically includes the following steps:
  • Step 601 forming a first conductive type semiconductor epitaxial layer 2 on the first side of the first conductive type semiconductor substrate 1.
  • the type of the first conductive type semiconductor substrate 1 is not limited and may be an N type semiconductor substrate or a P type semiconductor substrate.
  • the N-type semiconductor substrate is used to facilitate co-production with the existing fab production line, and the cost is saved.
  • the first conductive semiconductor epitaxial layer 2 is an N-type semiconductor epitaxial layer, which is usually formed by a vapor phase epitaxy process.
  • Step 602 forming a second conductive type semiconductor 3 on a side of the first conductive type semiconductor epitaxial layer 2 away from the first conductive type semiconductor substrate 1.
  • the second conductive type doping is implanted in an intermediate portion of the first conductive type semiconductor epitaxial layer 2 away from the side surface of the first conductive type semiconductor substrate 1 to form the second conductive type semiconductor 3, and the second conductive type A junction of the semiconductor 3 and the first conductive type semiconductor epitaxial layer 2 forms a semiconductor junction.
  • Step 603 forming a withstand voltage terminal structure 4 surrounding the second conductive type semiconductor 3 on a side of the first conductive type semiconductor epitaxial layer 2 away from the first conductive type semiconductor substrate 1.
  • the pressure-resistant terminal structure 4 may include a pressure-resistant ring 41, a dielectric layer 42 and a pressure-resistant terminal metal 43 which are sequentially formed in a direction away from the first conductive type semiconductor substrate 1, wherein the pressure-resistant ring 41 and the first conductive type
  • the semiconductor epitaxial layer 2 is located in the same physical structure layer, and a pressure-resistant ring 41 is formed by implanting a doping of a second conductivity type in a peripheral region of the first-conductivity-type semiconductor epitaxial layer 2.
  • Step 604 forming a second metal layer 8 in contact with the second conductive type semiconductor 3 inside the annular end of the withstand voltage terminal structure 4.
  • Step 605 forming a passivation layer 9 on the side of the withstand voltage termination structure 4 and the second metal layer 8 away from the first conductive type semiconductor substrate 1, and the passivation layer 9 exposing a portion of the second metal layer 8.
  • Step 606 a protective film 10 is attached to the entire surface of the passivation layer 9 away from the first conductive type semiconductor substrate 1.
  • Step 607 performing a thinning treatment on the second side surface of the first conductive type semiconductor substrate 1, specifically by mechanical grinding or deep reactive ion etching.
  • the first conductive type semiconductor substrate 1 may first adopt a raw material having a relatively large thickness, and after finishing the first surface process, the second surface is thinned to satisfy the thickness. Demand, to avoid the heat dissipation and performance of the diode due to excessive thickness.
  • Step 608 performing stress relief etching treatment on the second side surface of the first conductive type semiconductor substrate 1.
  • the second side surface of the thinned first conductive type semiconductor substrate 1 is subjected to stress release etching treatment using an etching solution or an etching gas to release stress generated by mechanical grinding, thereby reducing stress due to subsequent process fabrication.
  • the resulting debris and subsequent doping implants are easier and more uniform.
  • Step 609 forming a resistive layer 5 on the second side of the first conductive type semiconductor substrate 1.
  • a second conductive type doping implantation process is performed on the second side surface of the first conductive type semiconductor substrate 1 to neutralize the first conductive type by the second conductive type doping.
  • the first conductive type particles in the semiconductor substrate are adjacent to the second side surface, thereby increasing the resistivity of the portion to form the resistive layer 5.
  • the implantation depth of the second conductivity type doping can be adjusted to form a resistance layer of a desired thickness.
  • Step 610 performing an activation process of doping the resistive layer 5 to activate the doping ions and repair the surface defects.
  • the specific manner of the activation process is not limited, and for example, annealing activation or laser scanning activation or the like may be employed.
  • Step 611 forming a first metal layer 6 on a side of the resistive layer 5 remote from the first conductive type semiconductor substrate 1. Specifically, it can be formed by an evaporation process or a sputtering process.
  • the diode fabricated by the above method has a structure as shown in FIG. 1. Since the resistor layer 5 is integrated in the diode, the power device including the diode is applied to the power electronic device, and no circuit is required on the circuit board of the power electronic device. This simplifies the board structure, reduces the board area, and enables power electronics to achieve a compact design.
  • a seventh embodiment of the present invention provides a diode manufacturing method, which can be used to fabricate the diode of the foregoing second embodiment. As shown in FIG. 2a, FIG. 2b, FIG. 2c and FIG. 5, the method specifically includes the following steps:
  • Step 701 forming a first conductive type semiconductor epitaxial layer 2 on the first side of the first conductive type semiconductor substrate 1.
  • Step 702 forming a second conductive type semiconductor 3 on a side of the first conductive type semiconductor epitaxial layer 2 away from the first conductive type semiconductor substrate 1.
  • Step 703 forming a withstand voltage terminal structure 4 surrounding the second conductive type semiconductor 3 on a side of the first conductive type semiconductor epitaxial layer 2 away from the first conductive type semiconductor substrate 1.
  • Step 704 forming a second metal layer 8 in contact with the second conductive semiconductor 3 on the inner side of the annular structure of the withstand voltage terminal structure 4.
  • Step 705 forming a passivation layer 9 on the side of the withstand voltage termination structure 4 and the second metal layer 8 away from the first conductive type semiconductor substrate 1, and the passivation layer 9 exposing a portion of the second metal layer 8.
  • Step 706 a protective film 10 is attached to the entire surface of the passivation layer 9 away from the first conductive type semiconductor substrate 1.
  • Step 707 performing a thinning process on the second side surface of the first conductive type semiconductor substrate 1.
  • Step 708 performing stress relief etching treatment on the second side surface of the first conductive type semiconductor substrate 1.
  • Step 709 as shown in FIG. 2c, a second conductive type doping implantation process is performed on a partial region of the second side surface of the first conductive type semiconductor substrate 1 by a mask patterning process to form the resistive layer 5.
  • This step specifically includes the following sub-steps:
  • Sub-step 1 applying a photoresist layer on the second side surface of the first conductive type semiconductor substrate;
  • Sub-step 2 using a mask to expose the photoresist layer that completes the above steps, so that the photoresist layer is completely exposed to the area of the resistive unit, and the remaining areas are not exposed;
  • Sub-step 3 developing the photoresist layer completing the above steps to remove the fully exposed photoresist;
  • Sub-step 4 using the developed photoresist layer as a protective mask, performing a second conductivity type doping implantation process on the second side surface of the first conductive type semiconductor substrate to make the first conductive type semiconductor substrate a portion of the surface of the two sides exposed by the photoresist layer is increased in resistivity to form a resistive layer;
  • Sub-step 5 removing the residual photoresist.
  • Step 710 performing an activation process of doping the resistive layer 5.
  • Step 711 forming a first metal layer 6 on a side of the resistive layer 5 remote from the first conductive type semiconductor substrate 1.
  • the diode fabricated by the above method has a structure as shown in FIG. 2a, and the diode is applied to the power device, and then applied to the power electronic device.
  • the circuit board of the power electronic device does not need to be separately provided with a resistor, thereby simplifying the circuit board structure and reducing The board area enables power electronics to be miniaturized.
  • the eighth embodiment of the present invention provides a diode manufacturing method, which can be used to fabricate the diode of the foregoing third embodiment. As shown in FIG. 3 and FIG. 6, the method specifically includes the following steps:
  • Step 801 forming a first conductive type semiconductor epitaxial layer 2 on the first side of the first conductive type semiconductor substrate 1.
  • Step 802 forming a second conductive type semiconductor 3 on a side of the first conductive type semiconductor epitaxial layer 2 away from the first conductive type semiconductor substrate 1.
  • Step 803 forming a withstand voltage terminal structure 4 surrounding the second conductive type semiconductor 3 on a side of the first conductive type semiconductor epitaxial layer 2 away from the first conductive type semiconductor substrate 1.
  • Step 804 forming a second metal layer 8 in contact with the second conductive semiconductor 3 on the inner side of the annular structure of the withstand voltage terminal structure 4.
  • Step 805 forming a passivation layer 9 on the side of the withstand voltage termination structure 4 and the second metal layer 8 away from the first conductive type semiconductor substrate 1, and the passivation layer 9 exposing a portion of the second metal layer 8.
  • Step 806 a protective film 10 is attached to the entire surface of the passivation layer 9 away from the first conductive type semiconductor substrate 1.
  • Step 807 performing a thinning process on the second side surface of the first conductive type semiconductor substrate 1.
  • Step 808 performing stress relief etching treatment on the second side surface of the first conductive type semiconductor substrate 1.
  • Step 809 forming an amorphous silicon layer, an oxide semiconductor layer or a doped polysilicon layer on the second side of the first conductive type semiconductor substrate 1 as the resistive layer 5.
  • the doped polysilicon layer is formed on the second side of the first conductive type semiconductor substrate, and specifically includes the following substeps:
  • Sub-step 1 forming a pure polysilicon layer on the second side of the first conductive type semiconductor substrate; the pure polysilicon layer may be formed by epitaxial growth or chemical vapor deposition;
  • Sub-step 2 Doping the pure polysilicon layer so that the resistivity reaches a certain resistivity requirement, and finally forming a resistive layer that meets the requirements. Doping can be performed by an implantation process or a diffusion process.
  • a doped polysilicon layer may be directly formed on the second side of the first conductive type semiconductor substrate by an epitaxial growth or chemical vapor deposition process.
  • Step 810 performing an activation process of doping the resistive layer 5. If step 87 is to form a pure polysilicon layer and then perform a diffusion doping process on the pure polysilicon layer, the doping is activated by the diffusion doping process, so step 88 can be omitted.
  • Step 811 forming a first metal layer 6 on a side of the resistive layer 5 remote from the first conductive type semiconductor substrate.
  • the diode fabricated by the above method has the structure shown in FIG. 3. Similarly, the diode is applied to the power device and applied to the power electronic device, and the circuit board of the power electronic device does not need to be separately provided with a resistor, thereby simplifying the circuit board structure. , reducing the board area, enabling power electronics to achieve a compact design.

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Abstract

本发明公开了一种二极管、功率器件、电力电子设备及二极管制作方法，以简化电力电子设备的电路板结构，使设备易于实现小型化设计。二极管包括第一导电型半导体衬底；位于所述第一导电型半导体衬底第一侧的第一导电型半导体外延层；位于所述第一导电型半导体外延层远离所述第一导电型半导体衬底一侧的第二导电型半导体；位于所述第一导电型半导体衬底第二侧的电阻层；位于所述电阻层远离所述第一导电型半导体衬底一侧的第一金属层。本发明实施例的二极管中集成有电阻层，包含该二极管的功率器件应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备易于实现小型化设计。

Description

二极管、功率器件、电力电子设备及二极管制作方法 技术领域
本发明涉及半导体技术领域，特别是涉及一种二极管、功率器件、电力电子设备及二极管制作方法。
背景技术
随着时代的发展和技术的进步，功率器件(又称电力电子器件)也逐渐由单一的分立器件向大电流功率模块和智能功率模块转变。
在电网、机车等大功率应用场景中，主要使用大电流功率模块。大电流功率模块一般包括绝缘栅双极型晶体管(IGBT)和快恢复二极管(FRD)两类芯片。一般根据功率大小将数个IGBT和FRD的组合封装在一个模块中。
在变频家用电器、小型变频工业设备等小功率应用场景中，主要使用智能功率模块。智能功率模块一般包括IGBT、FRD、功率控制电路(MIC)和自举二极管(BDI)四类芯片。有些智能功率模块也可以不包括BDI芯片，BDI芯片设置在电子电力设备的主电路板上。
当前，终端产品都在朝着小型化趋势发展，如何简化电力电子设备的电路板结构，使设备易于实现小型化是目前亟待解决的技术问题。
发明内容
本发明实施例的目的是提供一种二极管、功率器件、电力电子设备及二极管制作方法，以简化电力电子设备的电路板结构，使设备易于实现小型化设计。
本发明实施例提供了一种二极管，包括：
第一导电型半导体衬底；
位于所述第一导电型半导体衬底第一侧的第一导电型半导体外延层；
位于所述第一导电型半导体外延层远离所述第一导电型半导体衬底一侧的第二导电型半导体；
位于所述第一导电型半导体衬底第二侧的电阻层；
位于所述电阻层远离所述第一导电型半导体衬底一侧的第一金属层。
可选的，所述电阻层覆盖所述第一导电型半导体衬底的第二侧表面。
可选的，所述电阻层覆盖所述第一导电型半导体衬底的第二侧表面的部分区域。
可选的，所述电阻层包括阵列排布的多个电阻单元。
可选的，所述电阻单元在所述第一导电型半导体衬底上的正投影的形状包括圆形、方形或多边形。
可选的，所述电阻层与所述第一导电型半导体衬底位于同一物理结构层。
可选的，所述电阻层与所述第一导电型半导体衬底位于不同物理结构层。
可选的，所述电阻层至少为两层。
可选的，所述电阻层的材质类型包括非晶硅层、氧化物半导体层或掺杂多晶硅层。
较佳的，所述第一导电型半导体衬底为N型半导体衬底，所述第一导电型半导体外延层为N型半导体外延层；所述第二导电型半导体为P型半导体。
可选的，二极管还包括耐压终端结构，所述耐压终端结构位于所述第一导电型半导体外延层远离所述第一导电型半导体衬底的一侧，且环绕所述第二导电型半导体设置。
本发明实施例的二极管中集成有电阻层，包含该二极管的功率器件应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。
本发明实施例还提供一种功率器件，包括前述任一技术方案所述的二极管。由于该功率器件的二极管中集成有电阻层，因此，该功率器件应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。
本发明实施例还提供一种电力电子设备，包括前述技术方案所述的功率器件。该电力电子设备的电路板上可以不设置电阻，因此电路板结构简化，面积较小，电力电子设备易于实现小型化设计。
本发明实施例还提供一种二极管制作方法，包括：
在第一导电型半导体衬底的第一侧形成第一导电型半导体外延层；
在所述第一导电型半导体外延层远离所述第一导电型半导体衬底的一侧形成第二导电型半导体；
在所述第一导电型半导体衬底的第二侧形成电阻层；
在所述电阻层远离所述第一导电型半导体衬底的一侧形成第一金属层。
可选的，所述在所述第一导电型半导体衬底的第二侧形成电阻层，包括：对所述第一导电型半导体衬底的第二侧表面进行整面的第二导电型掺杂注入处理。
可选的，所述在所述第一导电型半导体衬底的第二侧形成电阻层，包括：通过掩模构图工艺对所述第一导电型半导体衬底的第二侧表面的部分区域进行第二导电型掺杂注入处理。
可选的，所述在所述第一导电型半导体衬底的第二侧形成电阻层，包括：在所述第一导电型半导体衬底的第二侧形成非晶硅层、氧化物半导体层或掺杂多晶硅层。
较佳的，在形成所述电阻层之前，所述方法还包括：依次对所述第一导电型半导体衬底的第二侧表面进行减薄处理和应力释放腐蚀处理。
较佳的，在形成所述电阻层之后，在形成所述第一金属层之前，所述方法还包括：对所述电阻层进行掺杂的激活处理。
采用上述方法制作的二极管，由于二极管中集成有电阻层，因此，包含该二极管的功率器件应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。
附图说明
构成本申请的一部分的说明书附图用来提供对本发明的进一步理解，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1a为本发明第一实施例二极管的结构截面示意图；
图1b为本发明第一实施例二极管的电阻层制作示意图；
图2a为本发明第二实施例二极管的结构截面示意图；
图2b为本发明第二实施例二极管中的电阻层俯视示意图；
图2c为本发明第二实施例二极管的电阻层制作示意图；
图3为本发明第三实施例二极管的结构截面示意图；
图4为本发明第六实施例二极管制作方法流程示意图；
图5为本发明第七实施例二极管制作方法流程示意图；
图6为本发明第八实施例二极管制作方法流程示意图。
其中，上述附图包括以下附图标记：
1、第一导电型半导体衬底；
2、第一导电型半导体外延层；
3、第二导电型半导体；
4、耐压终端结构；
41、耐压环；
42、介质层；
43、耐压终端金属；
5、电阻层；
6、金属层；
5a、电阻单元；
8、第二金属层；
9、钝化层；
10、保护膜；
100、掩模板。
具体实施方式
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本发明。
实施例一
如图1a所示，本发明实施例一提供的二极管，包括：
第一导电型半导体衬底1；
位于第一导电型半导体衬底1第一侧的第一导电型半导体外延层2；
位于第一导电型半导体外延层2远离第一导电型半导体衬底1一侧的第二导电型半导体3；
位于第一导电型半导体衬底1第二侧的电阻层5；
位于电阻层5远离第一导电型半导体衬底1一侧的第一金属层6。
本发明实施例二极管的具体类型不限，包括但不限整流二极管、稳压二极管、开关二极管或自举二极管等等。
其中，第一导电型半导体衬底1可以为N型半导体衬底，则第一导电型半导体外延层2为N型半导体外延层；第二导电型半导体3为P型半导体。此外，第一导电型半导体衬底1也可以为P型半导体衬底，则第一导电型半导体外延层2为P型半导体外延层；第二导电型半导体3为N型半导体。目前，芯片晶圆厂生产线多采用N型半导体材料作为芯片衬底，因 此，本发明实施例中的第一导电型半导体衬底1优选采用N型半导体衬底，便于共线生产，节约成本。
第二导电型半导体3和第一导电型半导体外延层2可以位于不同物理结构层或位于同一物理结构层。在本发明一个优选实施方式中，第二导电型半导体3和第一导电型半导体外延层2位于同一物理结构层，通过在第一导电型半导体外延层2的设定区域注入第二导电型的掺杂形成第二导电型半导体3，第二导电型半导体3和第一导电型半导体外延层2的结合处形成了半导体结。
请继续参照图1a所示，对于上百伏的高压功率器件，为使二极管具有良好的耐压性能，二极管的结构还可包括耐压终端结构4，耐压终端结构4位于第一导电型半导体外延层2远离第一导电型半导体衬底1的一侧，且环绕第二导电型半导体3设置。具体的，耐压终端结构4可包括：沿远离第一导电型半导体衬底1的方向依次设置的耐压环41、介质层42和耐压终端金属43，其中，耐压环41可以与第一导电型半导体外延层2位于同一物理结构层，通过在第一导电型半导体外延层2的周边区域注入第二导电型的掺杂形成耐压环41。
在形成第二导电型半导体3和耐压终端结构4之后，通常还需要在该结构侧继续并依次形成第二金属层8和钝化层9。第二金属层8位于耐压终端结构的环形内侧并与第二导电型半导体3接触，钝化层9曝露出部分第二金属层8。第二金属层8被钝化层9曝露出的部分，以及前述的第一金属层6分别作为二极管的两个电极。
在完成钝化层9的制作后，可以在钝化层9远离第一导电型半导体衬底1的一侧表面整体贴附一层保护膜10，该保护膜10可以有效保护第二金属层8被钝化层9曝露出的部分，防止其在后续制作工艺过程中受到污染和损伤。在二极管制作完成后，将保护膜10揭去即可。
如图1a所示，该可选实施例中，电阻层5覆盖第一导电型半导体衬底1的第二侧表面，电阻层5与第一导电型半导体衬底1位于同一物理结构层。如图1b所示，通过对第一导电型半导体衬底1的第二侧表面进行整面的第二导电型掺杂注入处理，可以中和掉第一导电型半导体衬底1中靠近第二侧表面的第一导电型粒子，从而使该部分电阻率增大，形成图1a所示的电阻层5。通过控制相关工艺条件，如气体氛围、气体流速、设备功率等，可以调整第二导电型掺杂的注入深度，从而形成所需厚度的电阻层5，工艺简单可行，易于管控。
现有技术电力电子设备的电路板上一般都设有电阻元件，用于降低二极管正向充电时的峰值电流，从而减少对其它电路造成的干扰，但另一方面也使电路板结构较为复杂，从而阻碍了设备向小型化方向发展。在本发明实施例中，二极管集成有电阻层，包含该二极管的功率器件应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。
实施例二
基于与实施例一相同的发明构思，如图2a和图2b所示，本发明实施例二提供的二极管中，电阻层5的结构形式为：电阻层5覆盖第一导电型半导体衬底1的第二侧表面的部分区域。具体的，在该实施例中，电阻层5包括阵列排布的多个电阻单元5a。电阻单元5a的具体形状不限，例如，在第一导电型半导体衬底1上的正投影的形状可以为圆形、方形或多边形，等等。
该实施例中，电阻层5与第一导电型半导体衬底1位于同一物理结构层。如图2c所示，使用掩模板100，通过掩模构图工艺，对第一导电型半导体衬底1的第二侧表面的部分区域(即对应形成电阻单元5a的区域)进行第二导电型掺杂注入处理，可以使该部分区域形成一定厚度的电阻层5。通过控制相关工艺条件，如气体氛围、气体流速、设备功率等，可以调整第二导电型掺杂的注入深度，从而形成所需厚度的电阻层5。
有益效果同理，本发明实施例二的二极管中集成有电阻层，包含该二极管的功率器件应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。
实施例三
基于与实施例一相同的发明构思，如图3所示，本发明实施例三提供的二极管中，电阻层5的结构形式为：电阻层5覆盖第一导电型半导体衬底1的第二侧表面，且电阻层5与第一导电型半导体衬底1位于不同物理结构层。
如图3所示，该实施例电阻层5为单层结构。在本发明的可选实施例中，电阻层也可以至少为两层。电阻层的具体材质类型不限，例如可以为非晶硅层、氧化物半导体层或掺杂多晶硅层。当电阻层至少为两层时，各层电阻层的材质类型可以相同，也可以不相同。
同理，本发明实施例三的二极管中集成有电阻层，包含该二极管的功率器件应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。
实施例四
本发明实施例四提供了一种功率器件，包括前述任一实施例的二极管。由于该功率器件的二极管中集成有电阻层，因此，该功率器件应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。功率器件的具体类型不限，可以为智能功率模块(IPM)或其它小型功率模块等。
实施例五
本发明实施例五提供了一种电力电子设备，包括前述任一技术方案的功率器件。该电力电子设备的电路板上可以不设置电阻，因此电路板结构简化，面积较小，电力电子设备易于实现小型化设计。电力电子设备的具体类型不限，例如可以为变频家用电器或小型变频工业设备等。
实施例六
本发明实施例六提供了一种二极管制作方法，可用于制作前述实施例一的二极管，如图1a、图1b和图4所示，该方法具体包括以下步骤：
步骤601、在第一导电型半导体衬底1的第一侧形成第一导电型半导体外延层2。第一导电型半导体衬底1的类型不限，可以为N型半导体衬底或P型半导体衬底。优选采用N型半导体衬底，便于与现有晶圆厂生产线共线生产，节约成本，第一导电型半导体外延层2则为N型半导体外延层，通常采用气相外延工艺形成。
步骤602、在第一导电型半导体外延层2远离第一导电型半导体衬底1的一侧形成第二导电型半导体3。具体的，在第一导电型半导体外延层2远离第一导电型半导体衬底1的一侧表面的中间区域进行第二导电型掺杂的注入，形成第二导电型半导体3，第二导电型半导体3和第一导电型半导体外延层2的结合处就形成了半导体结。
步骤603、在第一导电型半导体外延层2远离第一导电型半导体衬底1的一侧形成环绕第二导电型半导体3的耐压终端结构4。耐压终端结构4可包括：沿远离第一导电型半导体衬底1的方向依次形成的耐压环41、介质层42和耐压终端金属43，其中，耐压环41可以与第一导电型半导体外延层2位于同一物理结构层，通过在第一导电型半导体外延层2的周边区域注入第二导电型的掺杂形成耐压环41。
步骤604、在耐压终端结构4的环形内侧形成与第二导电型半导体3接触的第二金属层8。
步骤605、在耐压终端结构4和第二金属层8远离第一导电型半导体衬底1的一侧形成钝化层9，钝化层9曝露出部分第二金属层8。
步骤606、在钝化层9远离第一导电型半导体衬底1的一侧表面整体贴附一层保护膜10。
步骤607、对第一导电型半导体衬底1的第二侧表面进行减薄处理，具体可以采用机械研磨或者深反应离子刻蚀工艺进行。为便于加工，避免加工中碎片，第一导电型半导体衬底1可以先采用厚度较大的原材料，在完成第一面的工艺制作后，再对第二面进行减薄处理，使其满足厚度需求，避免因厚度过大而影响到二极管的散热和性能。
步骤608、对第一导电型半导体衬底1的第二侧表面进行应力释放腐蚀处理。使用腐蚀液或腐蚀气体对减薄处理后的第一导电型半导体衬底1的第二侧表面进行应力释放腐蚀处理，释放掉由于机械研磨产生的应力，这样，可以减少后续工艺制作时因应力造成的碎片，并使后续的掺杂注入更易进行，也更加均匀。
步骤609、在第一导电型半导体衬底1的第二侧形成电阻层5。具体的，如图1b所示，对第一导电型半导体衬底1的第二侧表面进行整面的第二导电型掺杂注入处理，使第二导电型掺杂中和掉第一导电型半导体衬底中靠近第二侧表面的第一导电型粒子，从而使该部分电阻率增大，形成电阻层5。通过控制相关工艺条件，如气体氛围、气体流速、设备功率等，可以调整第二导电型掺杂的注入深度，从而形成所需厚度的电阻层。
步骤610、对电阻层5进行掺杂的激活处理，以激活掺杂离子和修复表面缺陷。激活处理的具体方式不限，例如，可以采用退火激活或激光扫描激活等。
步骤611、在电阻层5远离第一导电型半导体衬底1的一侧形成第一金属层6。具体可以采用蒸镀工艺或者溅射工艺形成。
采用上述方法制作的二极管，其结构如图1所示，由于二极管中集成有电阻层5，因此，包含该二极管的功率器件应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。
实施例七
本发明实施例七提供了一种二极管制作方法，可用于制作前述实施例二的二极管，如图2a、图2b、图2c和图5所示，该方法具体包括以下步骤：
步骤701、在第一导电型半导体衬底1的第一侧形成第一导电型半导体外延层2。
步骤702、在第一导电型半导体外延层2远离第一导电型半导体衬底1的一侧形成第二导电型半导体3。
步骤703、在第一导电型半导体外延层2远离第一导电型半导体衬底1的一侧形成环绕第二导电型半导体3的耐压终端结构4。
步骤704、在耐压终端结构4的环形内侧形成与第二导电型半导体3接触的第二金属层8。
步骤705、在耐压终端结构4和第二金属层8远离第一导电型半导体衬底1的一侧形成钝化层9，钝化层9曝露出部分第二金属层8。
步骤706、在钝化层9远离第一导电型半导体衬底1的一侧表面整体贴附一层保护膜10。
步骤707、对第一导电型半导体衬底1的第二侧表面进行减薄处理。
步骤708、对第一导电型半导体衬底1的第二侧表面进行应力释放腐蚀处理。
步骤709、如图2c所示，通过掩模构图工艺对第一导电型半导体衬底1的第二侧表面的部分区域进行第二导电型掺杂注入处理，形成电阻层5。该步骤具体包括以下子步骤：
子步骤一、在第一导电型半导体衬底的第二侧表面涂覆光刻胶层；
子步骤二、使用掩模板对完成上述步骤的光刻胶层进行曝光，使光刻胶层对应电阻单元的区域完全曝光，其余区域不被曝光；
子步骤三、对完成上述步骤的光刻胶层进行显影，去除完全曝光的光刻胶；
子步骤四、以显影后的光刻胶层为保护掩模，对第一导电型半导体衬底的第二侧表面进行第二导电型掺杂注入处理，使第一导电型半导体衬底的第二侧表面被光刻胶层暴露的部分电阻率增大，形成电阻层；
子步骤五、去除残余的光刻胶。
步骤710、对电阻层5进行掺杂的激活处理。
步骤711、在电阻层5远离第一导电型半导体衬底1的一侧形成第一金属层6。
采用上述方法制作的二极管，其结构如图2a所示，二极管应用到功率器件，进而应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。
实施例八
本发明实施例八提供了一种二极管制作方法，可用于制作前述实施例三的二极管，如图3和图6所示，该方法具体包括以下步骤：
步骤801、在第一导电型半导体衬底1的第一侧形成第一导电型半导体外延层2。
步骤802、在第一导电型半导体外延层2远离第一导电型半导体衬底1的一侧形成第二导电型半导体3。
步骤803、在第一导电型半导体外延层2远离第一导电型半导体衬底1的一侧形成环绕第二导电型半导体3的耐压终端结构4。
步骤804、在耐压终端结构4的环形内侧形成与第二导电型半导体3接触的第二金属层8。
步骤805、在耐压终端结构4和第二金属层8远离第一导电型半导体衬底1的一侧形成钝化层9，钝化层9曝露出部分第二金属层8。
步骤806、在钝化层9远离第一导电型半导体衬底1的一侧表面整体贴附一层保护膜10。
步骤807、对第一导电型半导体衬底1的第二侧表面进行减薄处理。
步骤808、对第一导电型半导体衬底1的第二侧表面进行应力释放腐蚀处理。
步骤809、在第一导电型半导体衬底1的第二侧形成非晶硅层、氧化物半导体层或掺杂多晶硅层，作为电阻层5。
以在第一导电型半导体衬底的第二侧形成掺杂多晶硅层为例，具体可以包括以下子步骤：
子步骤一、在第一导电型半导体衬底的第二侧形成纯多晶硅层；纯多晶硅层可以采用外延生长或者化学气相沉积工艺形成；
子步骤二、对纯多晶硅层进行掺杂处理，以使其电阻率达到一定的电阻率要求，最终形成符合需求的电阻层。掺杂可以采用注入工艺或者扩散工艺进行。
此外，也可以采用外延生长或者化学气相沉积工艺直接在第一导电型半导体衬底的第二侧形成掺杂多晶硅层。
步骤810、对电阻层5进行掺杂的激活处理。如果步骤87是先形成纯多晶硅层，再对纯多晶硅层进行扩散掺杂工艺处理，由于扩散掺杂工艺处理的同时也激活了掺杂，因此步骤88可以省略。
步骤811、在电阻层5远离第一导电型半导体衬底的一侧形成第一金属层6。
采用上述方法制作的二极管，其结构如图3所示，同理，二极管应用到功率器件，进而应用到电力电子设备中，电力电子设备的电路板上无需另外设置电阻，从而简化了电路板结构，减小了电路板面积，使电力电子设备能够实现小型化设计。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (19)

  1. 一种二极管，其特征在于，包括：
    第一导电型半导体衬底；
    位于所述第一导电型半导体衬底第一侧的第一导电型半导体外延层；
    位于所述第一导电型半导体外延层远离所述第一导电型半导体衬底一侧的第二导电型半导体；
    位于所述第一导电型半导体衬底第二侧的电阻层；
    位于所述电阻层远离所述第一导电型半导体衬底一侧的第一金属层。
  2. 如权利要求1所述的二极管，其特征在于，所述电阻层覆盖所述第一导电型半导体衬底的第二侧表面。
  3. 如权利要求1所述的二极管，其特征在于，所述电阻层覆盖所述第一导电型半导体衬底的第二侧表面的部分区域。
  4. 如权利要求3所述的二极管，其特征在于，所述电阻层包括阵列排布的多个电阻单元。
  5. 如权利要求4所述的二极管，其特征在于，所述电阻单元在所述第一导电型半导体衬底上的正投影的形状包括圆形、方形或多边形。
  6. 如权利要求1所述的二极管，其特征在于，所述电阻层与所述第一导电型半导体衬底位于同一物理结构层。
  7. 如权利要求1所述的二极管，其特征在于，所述电阻层与所述第一导电型半导体衬底位于不同物理结构层。
  8. 如权利要求7所述的二极管，其特征在于，所述电阻层至少为两层。
  9. 如权利要求7或8所述的二极管，其特征在于，所述电阻层的材质类型包括非晶硅层、氧化物半导体层或掺杂多晶硅层。
  10. 如权利要求1所述的二极管，其特征在于，
    所述第一导电型半导体衬底为N型半导体衬底，所述第一导电型半导体外延层为N型半导体外延层；
    所述第二导电型半导体为P型半导体。
  11. 如权利要求1所述的二极管，其特征在于，还包括耐压终端结构，所述耐压终端结构位于所述第一导电型半导体外延层远离所述第一导电型半导体衬底的一侧，且环绕所述第二导电型半导体设置。
  12. 一种功率器件，其特征在于，包括如权利要求1～11任一项所述的二极管。
  13. 一种电力电子设备，其特征在于，包括如权利要求12所述的功率器件。
  14. 一种二极管制作方法，其特征在于，包括：
    在第一导电型半导体衬底的第一侧形成第一导电型半导体外延层；
    在所述第一导电型半导体外延层远离所述第一导电型半导体衬底的一侧形成第二导电型半导体；
    在所述第一导电型半导体衬底的第二侧形成电阻层；
    在所述电阻层远离所述第一导电型半导体衬底的一侧形成第一金属层。
  15. 如权利要求14所述的方法，其特征在于，所述在所述第一导电型半导体衬底的第二侧形成电阻层，包括：
    对所述第一导电型半导体衬底的第二侧表面进行整面的第二导电型掺杂注入处理。
  16. 如权利要求14所述的方法，其特征在于，所述在所述第一导电型半导体衬底的第二侧形成电阻层，包括：
    通过掩模构图工艺对所述第一导电型半导体衬底的第二侧表面的部分区域进行第二导电型掺杂注入处理。
  17. 如权利要求14所述的方法，其特征在于，所述在所述第一导电型半导体衬底的第二侧形成电阻层，包括：
    在所述第一导电型半导体衬底的第二侧形成非晶硅层、氧化物半导体层或掺杂多晶硅层。
  18. 如权利要求14～17任一项所述的方法，其特征在于，在形成所述电阻层之前，所述方法还包括：
    依次对所述第一导电型半导体衬底的第二侧表面进行减薄处理和应力释放腐蚀处理。
  19. 如权利要求14～17任一项所述的方法，其特征在于，在形成所述电阻层之后，在形成所述第一金属层之前，所述方法还包括：
    对所述电阻层进行掺杂的激活处理。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104576763A (zh) * 2014-12-31 2015-04-29 杭州士兰集成电路有限公司 一种二极管结构及其制造方法
WO2017073264A1 (ja) * 2015-10-30 2017-05-04 三菱電機株式会社 炭化珪素半導体装置
CN107564968A (zh) * 2017-09-15 2018-01-09 珠海格力电器股份有限公司 二极管、功率器件、电力电子设备及二极管制作方法
CN207303113U (zh) * 2017-09-15 2018-05-01 珠海格力电器股份有限公司 二极管、功率器件及电力电子设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060037062A (ko) * 2004-10-27 2006-05-03 주식회사 케이이씨 저항과 캐패시터가 내장된 바렉터 다이오드 및 그 제조 방법
US20100117725A1 (en) * 2008-11-12 2010-05-13 Infineon Technologies Austria Ag Semiconductor diode
JP2012186353A (ja) * 2011-03-07 2012-09-27 Fuji Electric Co Ltd 複合半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104576763A (zh) * 2014-12-31 2015-04-29 杭州士兰集成电路有限公司 一种二极管结构及其制造方法
WO2017073264A1 (ja) * 2015-10-30 2017-05-04 三菱電機株式会社 炭化珪素半導体装置
CN107564968A (zh) * 2017-09-15 2018-01-09 珠海格力电器股份有限公司 二极管、功率器件、电力电子设备及二极管制作方法
CN207303113U (zh) * 2017-09-15 2018-05-01 珠海格力电器股份有限公司 二极管、功率器件及电力电子设备

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