WO2019041606A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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WO2019041606A1
WO2019041606A1 PCT/CN2017/114018 CN2017114018W WO2019041606A1 WO 2019041606 A1 WO2019041606 A1 WO 2019041606A1 CN 2017114018 W CN2017114018 W CN 2017114018W WO 2019041606 A1 WO2019041606 A1 WO 2019041606A1
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layer
substrate
array substrate
protection structure
transparent conductive
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PCT/CN2017/114018
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English (en)
French (fr)
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刘元甫
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武汉华星光电技术有限公司
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Priority to US15/916,435 priority Critical patent/US10345659B2/en
Publication of WO2019041606A1 publication Critical patent/WO2019041606A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a liquid crystal display panel.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the display panel of a TFT-LCD is usually made by cutting a large glass into a small display screen. Static electricity is easily generated during the cutting, thinning and handling of the panel. Static electricity is easily introduced into the liquid crystal panel and causes electrostatic damage to the internal components of the panel, which affects the display effect and greatly affects the product yield.
  • the present invention provides an array substrate and a liquid crystal display panel having an electrostatic protection structure for effectively shielding external static electricity and improving the antistatic capability of the array substrate and the panel.
  • a first aspect of the present invention provides an array substrate having an electrostatic protection structure, the array substrate Included in a plurality of spaced array blocks, each array block includes a plurality of spaced sub-array substrates, a periphery of the array substrate, a periphery of the array block, and a periphery of a display area of the sub-array substrate At least one of the places is provided with an electrostatic protection structure, which is a transparent metal oxide trace, or a metal trace and a transparent conductive metal oxide trace disposed in a stack.
  • the static electricity protection structure is surrounded on the periphery of the array substrate, the periphery of each array block, and the periphery of the display area of each sub-array substrate.
  • static electricity can be prevented from entering the signal line and the display region, and the substrate can be better protected against static electricity.
  • the electrostatic protection structure has a closed annular or intermittent ring shape.
  • the material of the transparent conductive metal oxide trace is selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), fluorine-doped tin dioxide (FTO), and phosphorus-doped dioxide.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum-doped zinc oxide
  • FTO fluorine-doped tin dioxide
  • PTO phosphorus-doped dioxide
  • the array substrate includes a substrate substrate, and a buffer layer, a gate insulating layer, an interlayer insulating layer, and a protective layer disposed on the substrate substrate in sequence, wherein the electrostatic protection structure is disposed on the protective layer
  • the electrostatic protection structure is a transparent metal oxide trace.
  • the annular transparent conductive metal oxide trace is used as the electrostatic protection structure, and at least one of the periphery of the array substrate, the periphery of each array block, and the periphery of the display area of each sub-array substrate may be surrounded.
  • the transparent conductive metal material has high conductivity and good electrical conductivity, so that the static electricity can be well shielded during the handling, cutting and thinning of the substrate and the panel containing the substrate, and the static electricity enters the signal line and In the display area, electrostatic protection is better achieved.
  • the thickness of the static electricity protection structure is Preferred More preferably
  • the array substrate includes a substrate substrate, and a buffer layer, a gate insulating layer, an interlayer insulating layer, and a protective layer disposed on the substrate substrate in sequence, wherein the interlayer insulating layer and the protective layer A metal layer is further disposed, and the protective layer is further provided with a transparent conductive layer, the protective layer has a via hole, and the transparent conductive layer and the metal layer are electrically connected through the via hole, the transparent conductive layer and the metal
  • the layer constitutes the static electricity protection structure; the static electricity protection structure is a metal trace and a transparent conductive metal oxide trace disposed in a stack; the transparent conductive metal oxide trace is the same material as the transparent conductive layer.
  • the transparent conductive layer and the metal layer are electrically connected in the up and down direction through the via holes on the protective layer to form an electrostatic protection structure.
  • the electrostatic protection structure is equivalent to the parallel transparent conductive layer and the metal layer. It has better conductivity than the use of the annular transparent conductive layer alone, and has a good antistatic effect.
  • the electrostatic protection structure is disposed at at least one of the periphery of the array substrate, the periphery of each array block, and the periphery of the display area of each sub-array substrate, so that the substrate can be better prevented from being electrostatically damaged.
  • the metal layer is in a closed loop or a discontinuous ring shape; and the transparent conductive layer is in a closed loop or a discontinuous loop.
  • the metal layer is one or more layers of at least one of Mo, Ti, Cu, Cr and Al.
  • a second aspect of the invention provides a liquid crystal display panel comprising the array substrate according to the first aspect of the invention.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate having an electrostatic protection structure according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of an array substrate having an electrostatic protection structure according to a first embodiment of the present invention
  • FIG. 3 is a schematic top plan view of an array substrate having an electrostatic protection structure according to a first embodiment of the present invention
  • FIG. 4 is a schematic top plan view of an array substrate having an electrostatic protection structure according to a second embodiment of the present invention.
  • FIG. 5 is a schematic top plan view of an array substrate having an electrostatic protection structure according to a third embodiment of the present invention.
  • FIG. 6 is a flow chart of a method for fabricating an array substrate having an electrostatic protection structure according to a fourth embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of an array substrate having an electrostatic protection structure according to a fourth embodiment of the present invention.
  • Embodiments of the present invention provide a method for fabricating an array substrate having an electrostatic protection structure.
  • the method please refer to FIG. 1 and FIG. 2 together, including the following steps:
  • the array substrate is divided into a plurality of spaced array blocks, each display block includes a plurality of spaced sub-array substrates; and the electrostatic protection structure is arranged At least one of the periphery of the array substrate, the periphery of each array block, and the periphery of the display area of each sub-array substrate; the ESD protection structure 6 is a transparent conductive layer, specifically a transparent metal oxide trace.
  • the material of the substrate substrate 1 is glass or plastic.
  • a buffer layer 2 covering the substrate 1 is formed on the substrate 1 by a coating process such as plasma enhanced chemical vapor deposition (PECVD), and the buffer layer 2 can shield the influence of defects on the substrate 1.
  • PECVD plasma enhanced chemical vapor deposition
  • the material of the buffer layer 2 includes at least one of silicon nitride and silicon oxide.
  • the buffer layer 2 may be a single-layer silicon oxide (SiOx) film layer or a silicon nitride (SiNx) film layer, or a composite film layer of silicon oxide (SiOx) and silicon nitride (SiNx).
  • the buffer layer 2 is a silicon nitride film layer or a silicon oxide film layer which is sequentially deposited.
  • the thickness of the buffer layer 2 is For example, 2000, 3000, 4000 or
  • the patterned gate insulating layer 3 may be formed on the buffer layer 2 by a patterning process, wherein the patterning process includes a process of coating film formation, masking, exposure, development, etching, etc. (also referred to as Lithography process).
  • the material of the gate insulating layer 3 includes at least one of silicon nitride and silicon oxide.
  • the material of the gate insulating layer 3 may be a single layer of silicon nitride (SiNx) or a single layer of silicon oxide (SiOx), or a stack of silicon oxide (SiOx) and silicon nitride (SiNx).
  • the material of the gate insulating layer 3 is silicon oxide.
  • the thickness of the gate insulating layer 3 is Preferred
  • the thickness of the gate insulating layer 3 may be or
  • a patterned interlayer insulating layer 4 may be formed on the gate insulating layer 3 by a patterning process including a process of coating film formation, masking, exposure, development, etching, and the like.
  • the material of the interlayer insulating layer 4 includes at least one of silicon nitride and silicon oxide.
  • the material of the interlayer insulating layer 4 may be a single layer of silicon nitride (SiNx) or a single layer of silicon oxide (SiOx), or a silicon oxide (SiOx) and silicon nitride (SiNx). The stack.
  • the material of the interlayer insulating layer 4 may be a laminate of silicon oxide (SiOx) and silicon nitride (SiNx).
  • the thickness of the interlayer insulating layer 4 is Preferred
  • the thickness of the interlayer insulating layer 4 may be
  • a patterned protective layer 5 may be formed on the interlayer insulating layer 4 by a patterning process including a process of coating film formation, masking, exposure, development, etching, and the like.
  • the thickness of the protective layer 5 is The material of the protective layer 5 may be silicon nitride, silicon dioxide or the like.
  • the electrostatic protection structure 6 may be formed on the protective layer 5 by a patterning process, and the patterning process includes a process of coating film formation, masking, exposure, development, etching, and the like.
  • the electrostatic protection structure 6 is a transparent conductive layer.
  • the material of the transparent conductive layer is selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), fluorine-doped tin dioxide (FTO), and phosphorus-doped tin dioxide (PTO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum-doped zinc oxide
  • FTO fluorine-doped tin dioxide
  • PTO phosphorus-doped tin dioxide
  • the material of the static electricity protection structure 6 is preferably ITO.
  • the ITO material has good electrical conductivity and light transmittance due to its high electrical conductivity, and can effectively shield external static electricity.
  • FIG. 2 is a cross-sectional view of an array substrate having an electrostatic protection structure according to a first embodiment of the present invention, which is fabricated by the method shown in FIG. 2 is a cross-sectional view of an array substrate on the periphery of a substrate, instead of showing an array substrate including a display region.
  • the buffer layer 2, the gate insulating layer 3, the interlayer insulating layer 4, and the protective layer 5 are disposed in the display area of the array substrate, but the generally patterned transparent conductive layer 6 is disposed only in the display area of the array substrate to serve as a pixel electrode.
  • the transparent conductive layer 6 is usually not present on the periphery of the array substrate, the periphery of the array block, etc., but in the embodiment of the present invention, when the transparent conductive layer such as ITO is patterned on the array substrate, the array substrate is The peripheral portion, the periphery of the array block, and the like retain a portion of the ITO layer and have a ring structure, so that the annular transparent conductive layer 6 having a high conductivity can provide a good electrostatic shielding effect. It can be seen that the process of the electrostatic protection structure 6 provided in the embodiment of the present invention does not add a new process based on the preparation process of the existing array substrate.
  • the electrostatic protection structure 6 (ie, the transparent conductive layer 6) has a ring shape, preferably a rectangular shape.
  • the electrostatic protection structure 6 has a closed annular or intermittent ring shape. It is preferably a closed loop structure.
  • FIG. 3 is a schematic top plan view of an array substrate having an electrostatic protection structure according to a first embodiment of the present invention.
  • the array substrate 9 is divided into a plurality of spaced array blocks 90, each of the display blocks 90 includes a plurality of spaced sub-array substrates 900, wherein the plurality of sub-array substrates 900 are generally cut in a ring shape.
  • the lines are spaced apart so that the late large array substrate 9 and the color film substrate are bonded to each other, and then cut along the cutting line to form a plurality of liquid crystal display sub-panels.
  • the electrostatic protection structure 6 encloses a periphery of a plurality of array blocks 90, and the electrostatic protection structure 6 is a closed loop.
  • the thickness of the electrostatic protection structure 6 ie, the transparent conductive layer 6) may be Its inner diameter (or "width") can be from 2 to 100 ⁇ m.
  • FIG. 4 is a plan view showing the structure of an array substrate 9 having an electrostatic protection structure in a second embodiment of the present invention.
  • the electrostatic protection structure 6 is disposed around the periphery (or edge, periphery) of the entire array substrate 9, and the electrostatic protection structure 6 is a closed loop.
  • the thickness of the electrostatic protection structure 6 ie, the transparent conductive layer 6) may be Its inner diameter (or "width") can be from 2 to 100 ⁇ m.
  • Fig. 5 is a plan view showing the structure of an array substrate 9 having an electrostatic protection structure in a third embodiment of the present invention.
  • the electrostatic protection structure 6 surrounds the periphery (or edge, periphery) of the display area 901 of the sub-array substrate, and the electrostatic protection structure 6 is a discontinuous ring shape.
  • the thickness of the electrostatic protection structure 6 ie, the transparent conductive layer 6) is Its inner diameter (or "width") is 2-100 ⁇ m.
  • the plurality of sub-array substrates are usually spaced apart by a circular cutting line 902, so that the late large-sized array substrate and the color film substrate are bonded to each other and cut along the cutting line to form a plurality of liquid crystal display sub-panels.
  • the periphery of the display area of each array sub-substrate 900 may be surrounded by the electrostatic protection structure 6. In this way, in the process of transporting, cutting, and thinning the substrate and the panel including the substrate in the later stage, the static electricity can be prevented from entering the signal line and the display area of the substrate, and the electrostatic protection of the substrate can be achieved.
  • the second aspect of the present invention provides an array substrate having an electrostatic protection structure, and the array substrate having the electrostatic protection structure is prepared by the method for preparing an array substrate having an electrostatic protection structure according to the first aspect.
  • the structure of the obtained array substrate can be referred to both FIG. 2 and FIG. 6.
  • the third aspect further provides a method for preparing an array substrate having an electrostatic protection structure. Please refer to FIG. 6 and FIG. 7 together, including the following steps:
  • a transparent conductive layer 62 is formed on the protective layer 5', and the transparent conductive layer 62 is electrically connected to the metal layer 61 through the via hole.
  • the transparent conductive layer 62 and the metal layer 61 constitute an electrostatic protection structure, and the array base is completed.
  • step S21 in this embodiment is similar to the above step S11, and details are not described herein again.
  • the metal layer 61 may be formed by a patterning process including a process of film formation, masking, exposure, development, etching, and the like.
  • the thickness of the metal layer 61 is The metal layer 61 may have a one-layer or multi-layer structure.
  • the material thereof may be metal Mo, Ti, Cu, Cr or Al.
  • the metal layer 61 may be a multilayer metal layer composed of at least two of Mo, Ti, Cu, Cr, and Al.
  • it may be a copper film layer and a Ti layer which are laminated.
  • the protective layer 5' having via holes in S23 can be realized by forming a protective film by a patterning process on the substrate substrate on which the metal layer 61 is formed, and then forming a via hole penetrating the protective film by a photolithography process. To expose the metal layer 61.
  • the etching gas used in the dry etching includes a fluorine-containing gas and hydrogen.
  • the flow ratio of the fluorine-containing gas to the hydrogen gas is 5-15:1. Further optionally, the flow ratio of the fluorine-containing gas to the hydrogen gas is 10:1.
  • the flow rate of the fluorine-containing gas is from 100 sccm to 500 sccm.
  • the thickness of the protective layer 5' is The material of the protective layer 5' may be silicon nitride, silicon dioxide or the like.
  • the material of the transparent conductive layer 62 in step S24 in this embodiment is similar to the above step S12.
  • the material of the transparent conductive layer 62 is selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), fluorine-doped tin dioxide (FTO), and phosphorus-doped tin dioxide (PTO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum-doped zinc oxide
  • FTO fluorine-doped tin dioxide
  • PTO phosphorus-doped tin dioxide
  • the material of the electrostatic protection structure 62 is preferably ITO.
  • the ITO material has high electrical conductivity and good electrical conductivity and light transmittance.
  • the thickness of the transparent conductive layer 62 is
  • FIG. 7 is a cross-sectional view of an array substrate having an electrostatic protection structure according to a fourth embodiment of the present invention, which is fabricated by the method shown in FIG. 6 above.
  • the structure described in FIG. 7 refers to a cross-sectional view of the array substrate on the periphery of the substrate, instead of the schematic view of the array substrate including the display region.
  • the buffer layer 2, the gate insulating layer 3, the interlayer insulating layer 4, the protective layer 5', the metal layer 61, and the transparent conductive layer 62 are disposed in the display region of the array substrate, but the patterned transparent conductive layer 62 and metal are usually patterned.
  • the layer 61 is disposed only in the display region of the array substrate and functions as a pixel electrode.
  • the array substrate of the display region generally includes a substrate substrate 1, a buffer layer 2, a low temperature polysilicon layer (providing a source contact region and a drain contact region at opposite ends thereof), a gate insulating layer 3, a gate layer, and a layer Inter-insulating layer 4, first metal layer, source and drain, planarization insulating layer, second metal layer, patterned transparent conductive layer 62, etc., wherein the first metal layer is disposed between the gate insulating layer and the interlayer Between the insulating layers, the role is to conduct the gate voltage; the second metal layer is disposed between the interlayer insulating layer and the planar layer to conduct the pixel voltage. At this time, the second metal layer of the display region corresponds to the metal layer 61 in FIG. It can be seen that the process of the electrostatic protection structure 6 provided in
  • the transparent conductive layer 62 and the metal layer 61 are electrically connected in the up and down direction through the via holes on the protective layer 5' to form the electrostatic protection structure 6.
  • the electrostatic protection structure 6 is equivalent to the transparent conductive in parallel.
  • the layer 62 and the metal layer 61 have a lower electrical resistance than the resistance of the individual transparent conductive layer 62, which makes the electrostatic protection structure 6 have a better antistatic effect.
  • the static electricity protection structure 6 is disposed around at least one of the periphery of the array substrate, the periphery of each array block, and the periphery of the display area of each sub-array substrate (refer to FIGS. 3-5, respectively), which can be preferably avoided. The substrate was damaged by static electricity.
  • the metal layer 61 is in a closed loop or a discontinuous ring shape, and the transparent conductive layer 62 is in a closed loop or between Broken ring.
  • a fourth aspect of the embodiments of the present invention provides an array substrate having an electrostatic protection structure.
  • the array substrate having the electrostatic protection structure is prepared by the method for preparing an array substrate having an electrostatic protection structure according to the second aspect.
  • the structure of the obtained array substrate can be referred to FIG. 7 and FIG. 3 to FIG. 5 together.
  • a fourth aspect of the embodiments of the present invention further provides a liquid crystal display panel to which the array substrate shown in FIG. 1 to FIG. 7 is applied.
  • the liquid crystal display panel includes a color filter substrate and a liquid crystal layer and a sealant sandwiched between the array substrate and the color filter substrate, and the sealant surrounds the liquid crystal layer. Since the array substrate has an electrostatic protection structure, the static electricity can be well shielded during the handling, cutting, and thinning of the liquid crystal display panel, and the static electricity is prevented from entering the signal line and the display area, thereby achieving electrostatic protection.

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Abstract

一种阵列基板（9）及液晶显示面板，该阵列基板（9）包括多个间隔设置的阵列区块（90），每个阵列区块（90）包括多个间隔设置的子阵列基板（900），阵列基板（9）的外围、阵列区块（90）的外围和子阵列基板（900）的显示区外围中的至少一处设置有静电防护结构（6），静电防护结构（6）为透明金属氧化物走线，或者为层叠设置的金属走线和透明导电金属氧化物走线。该静电防护结构（6）的存在，能有效屏蔽外界静电。

Description

一种阵列基板及液晶显示面板
本申请要求于2017年08月31日提交中国专利局、申请号为201710771654.8、发明名称为“阵列基板和液晶显示面板”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种阵列基板和液晶显示面板。
背景技术
近年来，随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)以其高画质、低功耗、机身轻薄的独特优势迅速得到普及。其中，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)是目前最常用的主流液晶显示器，广泛应用于手机、掌上电脑等电子设置中。
TFT-LCD的显示面板通常是由大的玻璃切割成小的显示屏幕而制成。在面板的切割，薄化以及搬运过程中极易产生静电，静电很容易导入液晶面板内而对面板内部器件造成静电击伤，影响显示效果，极大地影响了产品良品率。
发明内容
有鉴于此，本发明提供了一种具有静电防护结构的阵列基板和液晶显示面板，用于有效屏蔽外界静电，提高阵列基板和面板的抗静电能力。
本发明第一方面提供了一种具有静电防护结构的阵列基板，所述阵列基板 包括多个间隔设置的阵列区块，每个阵列区块包括多个间隔设置的子阵列基板，所述阵列基板的外围、所述阵列区块的外围和所述子阵列基板的显示区外围中的至少一处设置有静电防护结构，所述静电防护结构为透明金属氧化物走线，或者为层叠设置的金属走线和透明导电金属氧化物走线。
优选地，在所述阵列基板外围、每个阵列区块外围和每个子阵列基板的显示区外围均围设有所述静电防护结构。这样在该基板及包含该基板的面板的搬运、切割、薄化过程中，都能很好地防止静电进入信号线以及显示区域内，可以对基板实现更好的静电防护。
其中，所述静电防护结构呈闭合式环状或间断式环状。
其中，所述透明导电金属氧化物走线的材质选自氧化铟锡(ITO)、氧化铟锌(IZO)、掺铝氧化锌(AZO)、掺氟二氧化锡(FTO)和掺磷二氧化锡(PTO)中的一种。
其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保护层，其中，所述静电防护结构设置在所述保护层上；所述静电防护结构为透明金属氧化物走线。
此时，采用环状透明导电金属氧化物走线作为静电防护结构，可将所述阵列基板外围、每个阵列区块外围和每个子阵列基板的显示区外围中的至少一处包围起来，该透明导电金属材料的导电率较高，具有良好的导电特性，这样在该基板及包含该基板的面板的搬运、切割、薄化过程中，都能很好地屏蔽静电，防止静电进入信号线以及显示区域内，较好地实现静电防护。
进一步地，所述静电防护结构的厚度为
Figure PCTCN2017114018-appb-000001
优选为
Figure PCTCN2017114018-appb-000002
更优选为
Figure PCTCN2017114018-appb-000003
其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保护层，其中，所述层间绝缘层和所述保护层之间还设置金属层，所述保护层上还设置有透明导电层，所述保护层具有过孔，所述透明导电层和金属层通过所述过孔电连接，所述透明导电层和金属层构成所述静电防护结构；所述静电防护结构为层叠设置的金属走线和透明导电金属氧化物走线；所述透明导电金属氧化物走线与透明导电层的材质相同。
此时，所述透明导电层和金属层通过保护层上的过孔在上下方向上实现电连接，共同构成静电防护结构，此时，静电防护结构相当于并连的透明导电层和金属层，比单独采用环状透明导电层时的导电性还好，具有较好的抗静电击伤效果。而且，所述静电防护结构围设在所述阵列基板外围、每个阵列区块外围和每个子阵列基板的显示区外围中的至少一处，可以较好地避免基板被静电击伤。
具体地，所述金属层呈闭合式环状或间断式环状；所述透明导电层呈闭合式环状或间断式环状。
其中，所述金属层的厚度为
Figure PCTCN2017114018-appb-000004
其中，所述金属层为Mo，Ti，Cu，Cr和Al中的至少一种构成的一层或多层涂层。
本发明第二方面提供了一种液晶显示面板，包括如本发明第一方面所述的阵列基板。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作简单的介绍。
图1为本发明一实施例提供的具有静电防护结构的阵列基板的制备方法流程图；
图2为本发明第一实施例提供的具有静电防护结构的阵列基板的剖视示意图；
图3为本发明第一实施例中具有静电防护结构的阵列基板的俯视结构示意图；
图4为本发明第二实施例中具有静电防护结构的阵列基板的俯视结构示意图；
图5为本发明第三实施例中具有静电防护结构的阵列基板的俯视结构示意图；
图6为本发明第四实施例提供的具有静电防护结构的阵列基板的制备方法流程图；
图7为本发明第四实施例提供的具有静电防护结构的阵列基板的剖视示意图。
具体实施方式
下面结合附图及实施例，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。应当指出，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明实施例，第一方面提供了一种具有静电防护结构的阵列基板的制备 方法，请一并参阅图1和图2，包括如下步骤：
S11，提供基板衬底1，在基板衬底1依次形成缓冲层2、栅绝缘层3、层间绝缘层4、保护层5；
S12，在保护层5上形成静电防护结构6，得到阵列基板；阵列基板分为多个间隔设置的阵列区块，每个陈列区块包括多个间隔设置的子阵列基板；静电防护结构围设在阵列基板外围、每个阵列区块外围和每个子阵列基板的显示区外围中的至少一处；静电防护结构6为透明导电层，具体为透明金属氧化物走线。
本实施例的S11中，基板衬底1的材质为玻璃或塑料。通过镀膜工艺如等离子体增强化学的气相沉积法(PECVD)在基板衬底1上形成一层覆盖基板衬底1的缓冲层(Buffer)2，缓冲层2可以屏蔽基板衬底1上缺陷的影响，避免引起的器件或涂层不良。可选地，缓冲层2的材料包括氮化硅和氧化硅中的至少一种。进一步可选地，缓冲层2可以为单层的氧化硅(SiOx)膜层或氮化硅(SiNx)膜层，或者为氧化硅(SiOx)和氮化硅(SiNx)的复合膜层。优选地，缓冲层2为依次沉积成的氮化硅膜层、氧化硅膜层。可选地，缓冲层2的厚度为
Figure PCTCN2017114018-appb-000005
例如为2000、3000、4000或
Figure PCTCN2017114018-appb-000006
本实施例中，在缓冲层2上可以通过构图工艺形成图案化的栅绝缘层3，其中，构图工艺包括涂覆成膜、掩膜、曝光、显影、刻蚀等工艺(也可称之为光刻工艺)。可选地，栅绝缘层3的材料包括氮化硅和氧化硅中的至少一种。进一步可选地，栅绝缘层3的材料可以为单层的氮化硅(SiNx)或者单层的氧化硅(SiOx)，或者为氧化硅(SiOx)和氮化硅(SiNx)形成的叠层。优选地，栅绝缘层3的材料为氧化硅。可选地，所述栅绝缘层3的厚度为
Figure PCTCN2017114018-appb-000007
优选为
Figure PCTCN2017114018-appb-000008
例如，所述栅绝缘层3的厚度可以为
Figure PCTCN2017114018-appb-000009
Figure PCTCN2017114018-appb-000010
或
Figure PCTCN2017114018-appb-000011
在栅绝缘层3上可以通过构图工艺形成图案化的层间绝缘层4，构图工艺包括涂覆成膜、掩膜、曝光、显影、刻蚀等工艺。可选地，所述层间绝缘层4的材料包括氮化硅和氧化硅中的至少一种。进一步可选地，所述层间绝缘层4的材料可以为单层的氮化硅(SiNx)或者单层的氧化硅(SiOx)，或者为氧化硅(SiOx)和氮化硅(SiNx)形成的叠层。优选地，所述层间绝缘层4的材料可以为氧化硅(SiOx)和氮化硅(SiNx)形成的叠层材料。可选地，所述层间绝缘层4的厚度为
Figure PCTCN2017114018-appb-000012
优选为
Figure PCTCN2017114018-appb-000013
例如，所述层间绝缘层4的厚度可以为
Figure PCTCN2017114018-appb-000014
在层间绝缘层4上可以通过构图工艺形成图案化的保护层5，构图工艺包括涂覆成膜、掩膜、曝光、显影、刻蚀等工艺。可选地，保护层5的厚度为
Figure PCTCN2017114018-appb-000015
保护层5的材质可以为氮化硅、二氧化硅等。
步骤S12中，在保护层5上可以通过构图工艺形成静电防护结构6，构图工艺包括涂覆成膜、掩膜、曝光、显影、刻蚀等工艺。其中，静电防护结构6为透明导电层。可选地，透明导电层的材质选自氧化铟锡(ITO)、氧化铟锌(IZO)、掺铝氧化锌(AZO)、掺氟二氧化锡(FTO)和掺磷二氧化锡(PTO)中的一种。静电防护结构6的材质优选为ITO。ITO材料因其高导电率而具有良好的导电特性和光透过率，可以将外来静电有效屏蔽。
图2为本发明第一实施例提供的具有静电防护结构的阵列基板的剖视示意图，该阵列基板采用上述图1示出的方法所制得。图2所述的结构，均是指在基板外围的阵列基板剖视截面图，而非示出了包含显示区的阵列基板的示意 图。上述缓冲层2、栅绝缘层3、层间绝缘层4、保护层5在阵列基板的显示区均有设置，但通常图案化的透明导电层6只是设置在阵列基板的显示区，充当像素电极，从纵向上看，在阵列基板的外围、阵列区块的外围等通常不存在透明导电层6，但本发明实施例在图案化处理阵列基板上的ITO等透明导电层时，在阵列基板的外围、阵列区块的外围等保留部分ITO层，并使其呈环形结构，这样导电率高的环状透明导电层6能起到较好的静电屏蔽作用。可见，本发明实施例中提供的静电防护结构6的制程，并没有在现有的阵列基板的制备工艺基础上增加新制程。
其中，静电防护结构6(即透明导电层6)的形状为环形，优选为矩形。静电防护结构6呈闭合式环状或间断式环状。优选为闭合式环状结构。
图3为本发明第一实施例中具有静电防护结构的阵列基板的俯视结构示意图。如图3所示，阵列基板9分为多个间隔设置的阵列区块90，每个陈列区块90包括多个间隔设置的子阵列基板900，其中，多个子阵列基板900通常是以环形切割线间隔开，以便后期大块的阵列基板9与彩膜基板上下贴合后，沿着切割线切割开来，形成多个液晶显示子面板。
图3中，静电防护结构6围设多个阵列区块90的外围，静电防护结构6为闭合式环状。此时，静电防护结构6(即透明导电层6)的厚度可以为
Figure PCTCN2017114018-appb-000016
其内径(或称为“宽度”)可以为2-100μm。
图4为本发明第二实施例中具有静电防护结构的阵列基板9的俯视结构。图4中，静电防护结构6围设在整个阵列基板9的外围(或称为边缘、周边)，静电防护结构6为闭合式环状。此时，静电防护结构6(即透明导电层6)的厚度可以为
Figure PCTCN2017114018-appb-000017
其内径(或称为“宽度”)可以为2-100μm。
图5为本发明第三实施例中具有静电防护结构的阵列基板9的俯视结构。图5中，静电防护结构6围设子阵列基板的显示区901的外围(或称为边缘、周边)，静电防护结构6为间断式环状。此时，静电防护结构6(即透明导电层6)的厚度为
Figure PCTCN2017114018-appb-000018
其内径(或称为“宽度”)为2-100μm。多个子阵列基板通常是以环形切割线902间隔开，以便后期大块的阵列基板与彩膜基板上下贴合后沿着切割线切割开来，形成多个液晶显示子面板。
在本发明的其他实施例中，在阵列基板9的外围、每个阵列区块90的外围，每个阵列子基板900的显示区的外围，均可同时围设有所述静电防护结构6。这样在该基板，以及后期包含该基板的面板的搬运、切割、薄化过程中，都能很好地防止静电进入基板的信号线以及显示区域内，可以对基板实现更好的静电防护。
本发明实施例第二方面提供了一种具有静电防护结构的阵列基板，所述具有静电防护结构的阵列基板采用上述第一方面所述的具有静电防护结构的阵列基板的制备方法制备得到。所得阵列基板的结构可一并参阅图2-图6。
本发明实施例，第三方面还提供了一种具有静电防护结构的阵列基板的制备方法，请一并参阅图6和图7，包括如下步骤：
S21，提供基板衬底1，在基板衬底1依次形成缓冲层2、栅绝缘层3、层间绝缘层4；
S22，在层间绝缘层4上形成金属层61；
S23，在金属层61上形成具有过孔的保护层5’，以从过孔露出金属层61；
S24，在保护层5’上形成透明导电层62，使透明导电层62通过过孔与金属层61电连接，透明导电层62和金属层61构成静电防护结构，完成阵列基 板的制备；其中，阵列基板分为多个间隔设置的阵列区块，每个陈列区块包括多个间隔设置的子阵列基板，静电防护结构围设在阵列基板外围、每个阵列区块外围和每个子阵列基板的显示区外围中的至少一处。更具体地说，所述静电防护结构为层叠设置的金属走线和透明导电金属氧化物走线。
本实施例中步骤S21的操作类似上述步骤S11，这里不再赘述。
S22中，金属层61可以通过构图工艺来形成，构图工艺包括涂覆成膜、掩膜、曝光、显影、刻蚀等工艺。金属层61的厚度为
Figure PCTCN2017114018-appb-000019
金属层61可以为一层或多层结构。当金属层61为一层结构时，其材质可以为金属Mo，Ti，Cu，Cr或Al。当金属层61为多层结构时，其可以为Mo，Ti，Cu，Cr和Al中的至少2种构成的多层金属层。例如，可以是层叠设置的铜膜层和Ti层。
S23中具有过孔的保护层5’可以通过以下过程实现：在形成有金属层61的基板衬底上，通过一次构图工艺形成保护膜，再通过光刻工艺干刻形成贯穿保护膜的过孔，以使金属层61暴露。其中，所述干法刻蚀采用的刻蚀气体包括含氟气体和氢气。可选地，所述含氟气体与所述氢气的流量比为5-15:1。进一步可选地，所述含氟气体与所述氢气的流量比为10:1。可选地，所述含氟气体的流量为100sccm-500sccm。保护层5’的厚度为
Figure PCTCN2017114018-appb-000020
保护层5’的材质可以为氮化硅、二氧化硅等。
本实施例中步骤S24中透明导电层62的形成过程类似上述步骤S12。可选地，透明导电层62的材质选自氧化铟锡(ITO)、氧化铟锌(IZO)、掺铝氧化锌(AZO)、掺氟二氧化锡(FTO)和掺磷二氧化锡(PTO)中的一种。静电防护结构62的材质优选为ITO。ITO材料具有较高的导电率而具有良好的 导电特性和光透过率。透明导电层62的厚度为
Figure PCTCN2017114018-appb-000021
图7为本发明第四实施例提供的具有静电防护结构的阵列基板的剖视示意图，该阵列基板采用上述图6示出的方法所制得。图7所述的结构均是指在基板外围的阵列基板剖视截面图，而非示出了包含显示区的阵列基板的示意图。上述缓冲层2、栅绝缘层3、层间绝缘层4、保护层5’、金属层61和透明导电层62在阵列基板的显示区均有设置，但通常图案化的透明导电层62和金属层61只是设置在阵列基板的显示区，充当像素电极，从纵向上看，在阵列基板的外围、阵列区块的外围等通常不存在金属层61和透明导电层62。显示区的阵列基板通常会包括基板衬底1、缓冲层2、低温多晶硅层(在其相对的两端设置有源极接触区和漏极接触区)、栅绝缘层3、栅极层、层间绝缘层4、第一金属层、源极和漏极、平坦化绝缘层、第二金属层、图案化的透明导电层62等，其中，第一金属层是设置在栅绝缘层和层间绝缘层之间，作用是传导栅极电压；第二金属层是设置在层间绝缘层和平坦层之间，作用是传导像素电压。此时，显示区的第二金属层就相当于图7中的金属层61。由此可见，本发明实施例中提供的静电防护结构6的制程，并没有在现有的阵列基板的制备工艺基础上增加新制程。
本实施例中，透明导电层62和金属层61通过保护层5’上的过孔在上下方向上实现电连接，共同构成静电防护结构6，此时，静电防护结构6相当于并联的透明导电层62和金属层61，其电阻小于单独的透明导电层62的电阻，这使静电防护结构6得具有较好的抗静电击伤效果。而且，静电防护结构6围设在阵列基板的外围、每个阵列区块的外围和每个子阵列基板的显示区外围中的至少一处(可分别参考图3-5)，可以较好地避免基板被静电击伤。其中，所述金属层61呈闭合式环状或间断式环状，透明导电层62呈闭合式环状或间 断式环状。
本发明实施例第四方面提供了一种具有静电防护结构的阵列基板，所述具有静电防护结构的阵列基板采用上述第二方面所述的具有静电防护结构的阵列基板的制备方法制备得到。所得阵列基板的结构可一并参阅图7及图3-图5。
本发明实施例第四方面还提供一种应用上述图1至图7所示的阵列基板的液晶显示面板。关于阵列基板，请参看上述对图1-图7的描述，在此不再赘述。此时，液晶显示面板除了包括上述的阵列基板外，还包括彩膜基板和夹持于所述阵列基板与彩膜基板之间的液晶层和框胶，框胶环绕着液晶层。由于上述阵列基板上具有静电防护结构，这样在液晶显示面板的搬运、切割、薄化过程中，都能很好地屏蔽静电，防止静电进入信号线以及显示区域内，较好地实现静电防护。
需要说明的是，根据上述说明书的揭示和和阐述，本发明所属领域的技术人员还可以对上述实施方式进行变更和修改。因此，本发明并不局限于上面揭示和描述的具体实施方式，对本发明的一些等同修改和变更也应当在本发明的权利要求的保护范围之内。此外，尽管本说明书中使用了一些特定的术语，但这些术语只是为了方便说明，并不对本发明构成任何限制。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括多个间隔设置的阵列区块，每个阵列区块包括多个间隔设置的子阵列基板，所述阵列基板的外围、所述阵列区块的外围和所述子阵列基板的显示区外围中的至少一处设置有静电防护结构，所述静电防护结构为透明金属氧化物走线，或者为层叠设置的金属走线和透明导电金属氧化物走线。
  2. 如权利要求1所述的阵列基板，其中，所述静电防护结构呈闭合式环状或间断式环状。
  3. 如权利要求1所述的阵列基板，其中，所述透明导电金属氧化物走线的材质选自氧化铟锡、氧化铟锌、掺铝氧化锌、掺氟二氧化锡和掺磷二氧化锡中的一种。
  4. 如权利要求1所述的阵列基板，其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保护层，其中，所述静电防护结构设置在所述保护层上；所述静电防护结构为透明导电金属氧化物走线。
  5. 如权利要求2所述的阵列基板，其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保护层，其中，所述静电防护结构设置在所述保护层上；所述静电防护结构为透明导电金属氧化物走线。
  6. 如权利要求3所述的阵列基板，其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保护层，其中，所述静电防护结构设置在所述保护层上；所述静电防护结构为透明导电 金属氧化物走线。
  7. 如权利要求4所述的阵列基板，其中，所述静电防护结构的厚度为
    Figure PCTCN2017114018-appb-100001
  8. 如权利要求1所述的阵列基板，其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保护层，其中，所述层间绝缘层和所述保护层之间还设置金属层，所述保护层上还设置有透明导电层，所述保护层具有过孔，所述透明导电层和金属层通过所述过孔电连接，所述透明导电层和金属层构成所述静电防护结构；所述静电防护结构为层叠设置的金属走线和透明导电金属氧化物走线。
  9. 如权利要求2所述的阵列基板，其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保护层，其中，所述层间绝缘层和所述保护层之间还设置金属层，所述保护层上还设置有透明导电层，所述保护层具有过孔，所述透明导电层和金属层通过所述过孔电连接，所述透明导电层和金属层构成所述静电防护结构；所述静电防护结构为层叠设置的金属走线和透明导电金属氧化物走线。
  10. 如权利要求3所述的阵列基板，其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保护层，其中，所述层间绝缘层和所述保护层之间还设置金属层，所述保护层上还设置有透明导电层，所述保护层具有过孔，所述透明导电层和金属层通过所述过孔电连接，所述透明导电层和金属层构成所述静电防护结构；所述静电防护结构为层叠设置的金属走线和透明导电金属氧化物走线。
  11. 如权利要求8所述的阵列基板，其中，所述金属层的厚度为
    Figure PCTCN2017114018-appb-100002
    Figure PCTCN2017114018-appb-100003
  12. 如权利要求9所述的阵列基板，其中，所述金属层的厚度为
    Figure PCTCN2017114018-appb-100004
    Figure PCTCN2017114018-appb-100005
  13. 如权利要求10所述的阵列基板，其中，所述金属层的厚度为
    Figure PCTCN2017114018-appb-100006
    Figure PCTCN2017114018-appb-100007
  14. 如权利要求8所述的阵列基板，其中，所述金属层为Mo，Ti，Cu，Cr和Al中的至少一种构成的一层或多层涂层。
  15. 如权利要求9所述的阵列基板，其中，所述金属层为Mo，Ti，Cu，Cr和Al中的至少一种构成的一层或多层涂层。
  16. 一种液晶显示面板，包括阵列基板，其中，所述阵列基板包括多个间隔设置的阵列区块，每个阵列区块包括多个间隔设置的子阵列基板，所述阵列基板的外围、所述阵列区块的外围和所述子阵列基板的显示区外围中的至少一处设置有静电防护结构，所述静电防护结构为透明金属氧化物走线，或者为层叠设置的金属走线和透明导电金属氧化物走线。
  17. 如权利要求16所述的液晶显示面板，其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保护层，其中，所述静电防护结构设置在所述保护层上；所述静电防护结构为透明导电金属氧化物走线。
  18. 如权利要求17所述的液晶显示面板，其中，所述静电防护结构的厚度为
    Figure PCTCN2017114018-appb-100008
  19. 如权利要求16所述的液晶显示面板，其中，所述阵列基板包括基板衬底，以及依次设置在所述基板衬底上的缓冲层、栅绝缘层、层间绝缘层、保 护层，其中，所述层间绝缘层和所述保护层之间还设置金属层，所述保护层上还设置有透明导电层，所述保护层具有过孔，所述透明导电层和金属层通过所述过孔电连接，所述透明导电层和金属层构成所述静电防护结构；所述静电防护结构为层叠设置的金属走线和透明导电金属氧化物走线。
  20. 如权利要求19所述的液晶显示面板，其中，所述金属层为Mo，Ti，Cu，Cr和Al中的至少一种构成的一层或多层涂层。
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