WO2019037475A1 - 源极驱动增强电路、源极驱动增强方法、源极驱动电路和显示设备 - Google Patents

源极驱动增强电路、源极驱动增强方法、源极驱动电路和显示设备 Download PDF

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Publication number
WO2019037475A1
WO2019037475A1 PCT/CN2018/086523 CN2018086523W WO2019037475A1 WO 2019037475 A1 WO2019037475 A1 WO 2019037475A1 CN 2018086523 W CN2018086523 W CN 2018086523W WO 2019037475 A1 WO2019037475 A1 WO 2019037475A1
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Prior art keywords
circuit
sub
control signal
enhancement
transistor
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PCT/CN2018/086523
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English (en)
French (fr)
Inventor
张媛
刘磊
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to EP18845460.7A priority Critical patent/EP3489942A4/en
Priority to US16/327,783 priority patent/US20210335315A1/en
Publication of WO2019037475A1 publication Critical patent/WO2019037475A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation

Definitions

  • the present disclosure relates to the field of display driving, and in particular to a source driving enhancement circuit, a source driving enhancement method, a source driving circuit, and a display device.
  • the source-driven output is directly connected to the display of a thin film transistor liquid crystal display (TFT-LCD).
  • TFT-LCD thin film transistor liquid crystal display
  • RC delays are likely to occur at the far end of the source COF (Chip on Flex) package. This delay becomes more serious as the screen gets bigger and bigger.
  • the source data line may not be able to charge the pixel cell to a predetermined voltage before the gate drive is turned off.
  • the present disclosure proposes a source driving enhancement circuit, a source driving enhancement method, a source driving circuit, and a display device.
  • a source drive enhancement circuit includes a switch subcircuit, a charge subcircuit, an enhancement subcircuit, and an energy storage subcircuit.
  • the control end of the switch sub-circuit is connected to the switch control signal line, the input end is connected to the source drive signal line, and the output end is connected to the data line.
  • the control end of the charging sub-circuit is connected to the charging control signal line, the first input end is connected to the first voltage, the second input end is connected to the charging voltage, and the first output end and the second output end are respectively connected to the energy storage sub-circuit First end and second end.
  • the control end of the enhancer circuit is connected to the enhancement control signal line, the input end of the enhancement sub-circuit is connected to the source drive signal line, the output end of the enhancement sub-circuit is connected to the data line, the first discharge end and the second discharge end Connected to the first end and the second end of the energy storage unit, respectively.
  • the switch subcircuit includes a first transistor, a control terminal of the switch subcircuit is a gate of the first transistor, and an input terminal is in a source and a drain of the first transistor One, the output is the other of the source and the drain of the first transistor.
  • the charging sub-circuit includes a second transistor and a third transistor, a control terminal of the charging sub-circuit is connected to a gate of the second transistor and a gate of the third transistor, a first input The terminal is one of a source and a drain of the second transistor, the second input is one of a source and a drain of the third transistor, and the first output is a source of the second transistor And the other of the drains, the second output being the other of the source and the drain of the third transistor.
  • the enhancement sub-circuit includes a fourth transistor and a fifth transistor, and a control terminal of the enhancement sub-circuit is connected to a gate of the fourth transistor and a gate of the fifth transistor, and the input terminal is One of a source and a drain of the fourth transistor, an output end being one of a source and a drain of the fifth transistor, and a first discharge end being a source and a drain of the fourth transistor The other, the second discharge end is the other of the source and the drain of the fifth transistor.
  • the energy storage subcircuit includes a capacitor, the first end and the second end of the energy storage subcircuit being a first end and a second end of the capacitor, respectively.
  • the switch subcircuit in response to not enhancing the source drive signal, under control of the switch control signal on the switch control signal line, the charge control signal on the charge control signal line, and the enhanced control signal on the enhanced control signal line, The switch subcircuit is turned on.
  • the switch sub-circuit in response to enhancing the source drive signal, under control of the switch control signal on the switch control signal line, the charge control signal on the charge control signal line, and the enhanced control signal on the enhanced control signal line, In a first period of time, the switch sub-circuit is turned on, the charging sub-circuit is turned on, and the enhancement sub-circuit is turned off to charge the energy storage sub-circuit with the charging voltage; and in the second period, the switching sub-circuit is turned off.
  • the off, charging sub-circuit is turned off and the enhancement sub-circuit is turned on to provide an enhanced source driving voltage to the data line, the magnitude of the enhanced source driving voltage being equal to the magnitude of the source driving voltage and the amplitude of the charging voltage
  • the sum of the values is subtracted from the first voltage.
  • the source driving enhancement method includes: determining whether to enhance the source driving; when determining that no enhancement is performed, providing a switch control signal for turning the switch sub-circuit on the switch control signal line, providing the charging control signal line a charging control signal that is turned off by the charging sub-circuit, an enhanced control signal that causes the enhancement sub-circuit to be turned off on the enhanced control signal line to provide the source driving voltage to the data line; and when it is determined that the enhancement is performed, charging a period of time, a switch control signal for turning on the switch sub-circuit is provided on the switch control signal line, a charge control signal for turning on the charge sub-circuit is provided on the charge control signal line, and an enhancement sub-circuit is provided on the enhanced control signal line.
  • the source drive circuit includes a source drive enhancement circuit in accordance with the various embodiments described above.
  • a display device includes the source drive circuit described above.
  • FIG. 1 is a block diagram showing the structure of a source driving enhancement circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic circuit diagram of the source driving enhancement circuit shown in FIG. 1;
  • Figure 3 shows a timing diagram of the circuit shown in Figure 2;
  • FIG. 4 illustrates a flow chart of a source drive enhancement method in accordance with an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics.
  • the thin film transistor used in the embodiment of the present disclosure may be an oxide semiconductor transistor.
  • the source and drain of the transistor used here are symmetrical, the source and drain thereof can be interchanged.
  • an N-type transistor is taken as an example, that is, when the gate voltage of the transistor is at a high level, the transistor is turned on, and when the gate voltage is at a low level, the transistor is turned off.
  • a P-type transistor can be used, that is, when the gate voltage of the transistor is low, the transistor is turned on and the gate voltage is high, the transistor is turned off, and the corresponding modification of the circuit structure is It will be apparent to those skilled in the art.
  • FIG. 1 shows a block diagram of a structure of a source drive enhancement circuit 100 in accordance with an embodiment of the present disclosure.
  • the source drive enhancement circuit 100 includes a switch sub-circuit 110, a charge sub-circuit 120, an enhancement sub-circuit 130, and an energy storage sub-circuit 140.
  • the output of the source drive enhancement circuit 100 is schematically illustrated in FIG. 1 as being connected to a data line and charging the corresponding pixel unit via the data line.
  • the control terminal of the switch sub-circuit 110 is connected to a switch control signal line that provides a switch control signal EN, the input terminal is connected to a source drive signal line that provides a source drive signal Vs1, and the output terminal is connected to the data line.
  • the control terminal of the charging sub-circuit 120 is connected to a charging control signal line for providing a charging control signal TP, the first input terminal is connected to the first voltage V1, the second input terminal is connected to the charging voltage VREF, and the first output terminal and the second output terminal are respectively connected.
  • the first and second ends of the energy storage sub-circuit 140 are coupled to enable charging of the energy storage sub-circuit 140.
  • the first voltage V1 is shown to be low, such as ground potential.
  • the voltage polarity of VREF coincides with the voltage polarity of Vs1.
  • Vs1 is a positive voltage
  • VREF is also a positive voltage
  • the source driving signal reversely charges (ie, discharges) the pixel unit
  • Vs1 is a negative voltage
  • VREF is also a negative voltage.
  • the control end of the enhancer circuit 130 is connected to an enhanced control signal line for providing an enhanced control signal TP_D, the input end is connected to the source drive signal line, the output end is connected to the data line, and the first discharge end and the second discharge end are respectively connected to the energy storage unit The first end and the second end of 140.
  • the energy storage sub-circuit 140 can enable the voltage received by the data line to be the enhanced source drive voltage Vs2 by means of the enhancement sub-circuit 130.
  • FIG. 2 shows a schematic circuit diagram of the source drive enhancement circuit 100 shown in FIG. 1.
  • the switch sub-circuit 110 can include a first transistor S1.
  • the control terminal of the switch sub-circuit 110 is the gate of the first transistor S1, the input terminal is one of the source and the drain of the first transistor S1, and the output terminal is the other of the source and the drain of the first transistor.
  • the charging sub-circuit 120 includes a second transistor S2 and a third transistor S3.
  • the control terminal of the charging sub-circuit 120 is connected to the gate of the second transistor S2 and the gate of the third transistor S3 to respectively provide a charging control signal TP to the two.
  • the first input of the charging sub-circuit 120 is one of the source and the drain of the second transistor S2, and the second input is one of the source and the drain of the third transistor S3.
  • the first output of the charging sub-circuit 120 is the other of the source and the drain of the second transistor S2, and the second output is the other of the source and the drain of the third transistor S3.
  • the second transistor S2 and the third transistor S3 may be set to satisfy a condition that the first input terminal of the charging sub-circuit 120 is the source and drain of the third transistor S3.
  • One of the poles, the second input terminal is one of the source and the drain of the second transistor S2, and the remaining connection relationship remains unchanged.
  • VREF and V1 are interchanged.
  • V1 is a relatively low level (such as ground potential)
  • V1 is a relatively low level (such as ground potential)
  • the enhancer circuit 130 may include a fourth transistor S4 and a fifth transistor S5.
  • the control terminal of the enhancement sub-circuit 130 is connected to the gate of the fourth transistor S4 and the gate of the fifth transistor S5 to respectively provide an enhancement control signal TP_D to the two.
  • the input terminal of the enhancement sub-circuit 130 is one of the source and the drain of the fourth transistor S4, and the output terminal is one of the source and the drain of the fifth transistor S5.
  • the first discharge end of the enhancer circuit 130 is the other of the source and the drain of the fourth transistor S4, and the second discharge end is the other of the source and the drain of the fifth transistor S5.
  • the energy storage subcircuit 140 includes a capacitor C.
  • the first end and the second end of the energy storage sub-circuit 140 are a first end and a second end of the capacitor C, respectively.
  • the pixel capacitance is charged using the output of the source drive enhancement circuit 100.
  • the switching sub-circuit 110 In response to the enhancement of the source driving signal voltage Vs1, under the control of the switching control signal, the charging control signal, and the enhanced control signal, the switching sub-circuit 110 is turned on, the charging sub-circuit 120 is turned off, and the enhancement sub-circuit 130 is turned off. At this time, the source driving signal voltage Vs1 is directly output to the data line through the switching sub-circuit 110, and the outputted voltage is the source driving voltage Vs1.
  • the source drive signal voltage Vs1 is boosted in response to the source.
  • the switch sub-circuit 110 is turned on, the charge sub-circuit 120 is turned on, and the enhancement sub-circuit 130 is turned off to provide the source drive signal Vs1 to
  • the energy storage sub-circuit 140 is charged while the data line is simultaneously charged with the charging voltage VREF.
  • the second transistor S2 and the third transistor S3 are turned on, and the charging voltage VREF charges the capacitor C.
  • the switch sub-circuit 110 is turned off, the charge sub-circuit 120 is turned off, and the enhancement sub-circuit 130 is turned on to supply the enhanced source drive voltage Vs2 to the data line.
  • the first transistor S1, the second transistor S2, and the third transistor S3 are turned off, the fourth transistor S4 and the fifth transistor S4 are turned on, the capacitor C is discharged, and the input source driving voltage Vs1 is passed through the fourth transistor S4 and the capacitor C.
  • the enhancement is to enhance the source driving voltage Vs2 and is applied to the data line via the fifth transistor S5.
  • the magnitude of the enhanced source drive voltage Vs2 is equal to the sum of the magnitude of the source drive voltage Vs1 and the magnitude of the charge voltage VREF minus the first voltage V1, ie,
  • Vs1 is a positive voltage
  • VREF is a positive voltage
  • FIG. 2 only shows a schematic circuit diagram of the source drive enhancement circuit 100 in accordance with an embodiment of the present disclosure.
  • the energy storage sub-circuit 140 may be implemented by a plurality of capacitors connected in parallel or in series, whereby the capacity of the energy storage sub-circuit can be flexibly designed according to an application environment.
  • switch sub-circuit 110, charge sub-circuit 120, and/or enhancer circuit 130 in accordance with embodiments of the present disclosure may be implemented using other combinations of transistors. For the sake of brevity, this description will not be repeated.
  • FIG. 3 shows an exemplary timing diagram of the circuit shown in FIG. 2. It should be noted that the amplitudes of the various signals in FIG. 3 are merely exemplary and are only used to reflect the trend of amplitude variation within a single signal and do not represent specific values. Different signals, even if shown as having the same signal amplitude in the figures, do not imply that the two actually have the same magnitude. Similarly, different signals, even if shown as having different signal amplitudes in the figures, do not imply that the two actually have different amplitudes.
  • Switch Control Signal EN (only shows the EN timing for enhancement, EN keeps low for no enhancement), charge control signal TP, enhancement
  • the control signal TP_D the level applied to the pixel unit when no enhancement is performed (the signal corresponding to "unenhanced” in FIG. 3), and the level applied to the pixel unit when performing enhancement (corresponding to "enhancement” in FIG. 3) signal of).
  • the switching sub-circuit 110 is turned on under the control of the switching control signal, the charging control signal, and the enhanced control signal, and the charging sub-circuit 120 is turned off.
  • the enhancement sub-circuit 130 is turned off such that the voltage output to the data line is the source driving voltage Vs1, at which time the level of the pixel unit corresponds to the "unenhanced" signal in FIG. At this point, just consider this one signal in Figure 3.
  • the solid line portion of the "unenhanced" signal corresponds to the case where there is no RC delay
  • the dotted line portion corresponds to the case where there is an RC delay. It can be seen that when there is no RC delay, the pixel unit is quickly charged to a predetermined level (as shown in Figure 3, elapsed time T1). When the RC delay occurs, this charging time is greatly lengthened to (T1+T2+T3). This can cause an undercharge condition to occur. Need to consider the enhancement of the source drive voltage.
  • the switch sub-circuit 110 Under the control of the switch control signal, the charge control signal and the enhanced control signal, during the charging period, the switch sub-circuit 110 is turned on, the charge sub-circuit 120 is turned on, and the enhancement sub-circuit 130 is turned off, so that the charge sub-circuit 120 pairs the energy storage device. Circuit 140 is charged. At this time, the charging rate of the pixel unit is the same as that of the "unenhanced" case (see the dotted line portion (or the solid line portion) of the T1 segment "unenhanced" signal and the "enhancement" signal in FIG.
  • the switch sub-circuit 110 is turned off, the charging sub-circuit 120 is turned off, and the enhancement sub-circuit 130 is turned on, so that the enhancement sub-circuit 130 appends the potential of the energy storage sub-circuit 140 to the source driving voltage Vs1 to the pixel unit.
  • Charging is performed, that is, charging is performed using the enhanced source driving voltage Vs2.
  • the solid line portion of the "enhancement" signal corresponds to the case where there is no RC delay, and the dotted line portion corresponds to the case where there is an RC delay. It can be seen that after the enhancement, when there is an RC delay, the charging time is shortened from the original T1+T2+T3 to T1+T2. This improves the effect of the RC delay and suppresses the occurrence of undercharging.
  • FIG. 4 illustrates a flow diagram of a source drive enhancement method 400 in accordance with an embodiment of the present disclosure.
  • the source drive enhancement method 400 begins in step S410, where it is determined whether the source drive voltage Vs1 is boosted.
  • step S420 a switch control signal for turning on the switch sub-circuit 110 is provided to supply the source drive voltage Vs1 to the data line.
  • step S430 the charging phase is started.
  • the switch control signal line provides a switch control signal EN for turning on the switch sub-circuit 110
  • the charge control signal line provides a charge control signal TP for turning on the charge sub-circuit 120
  • the enhancement control signal line is provided to turn off the enhancement sub-circuit 130.
  • the enhancement control signal TP_D charges the energy storage sub-circuit 140 with the charging voltage VREF while supplying the source driving voltage Vs1 to the data line.
  • step S440 the enhancement phase is entered.
  • a switch control signal EN for turning off the switch sub-circuit 110 a charge control signal TP for turning off the charge sub-circuit 120, and an enhancement control signal TP_D for turning on the enhancement sub-circuit 130 are provided to provide enhancement to the data line.
  • the source driving voltage Vs2, the magnitude of the enhanced source driving voltage Vs2 is equal to the sum of the magnitude of the source driving voltage Vs1 and the magnitude of the charging voltage minus the first voltage.
  • the present disclosure also proposes a source driving circuit.
  • the source drive circuit includes a source drive enhancement circuit 100 as shown in FIGS. 1 and/or 2.
  • the present disclosure also proposes a display device.
  • the display device includes a source drive circuit as described above.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
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Abstract

一种源极驱动增强电路，包括开关子电路（110）、充电子电路（120）、增强子电路（130）和储能子电路（140）。开关子电路（110）的控制端连接开关控制信号线，输入端连接源极驱动信号线，输出端连接数据线。充电子电路（120）的控制端连接充电控制信号线，第一输入端连接第一电压（V1），第二输入端连接充电电压（VREF），第一输出端和第二输出端分别连接到储能子电路（140）的第一端和第二端。增强子电路（130）的控制端连接增强控制信号线，第一输入端连接源极驱动信号线，第一输出端连接数据线，第一放电端和第二放电端分别连接到储能子电路（140）的第一端和第二端。

Description

源极驱动增强电路、源极驱动增强方法、源极驱动电路和显示设备
本申请要求于2017年8月22日提交的、申请号为201710726894.6的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示驱动领域，具体地涉及一种源极驱动增强电路、源极驱动增强方法、源极驱动电路和显示设备。
背景技术
目前，源极驱动的输出直接接入到薄膜晶体管液晶显示器(TFT-LCD)的显示屏内。然而，由于屏内存在诸多等效电阻和电容，导致在源极COF(Chip on Flex，覆晶薄膜)封装结合的远端很可能会出现RC延迟。当屏幕变得越来越大时，这一延迟越发严重。当延迟大到一定程度时，或当刷新率提高而需要缩短充电周期时，源极数据线可能无法在栅极驱动关闭之前将像素单元充电到预定电压。
发明内容
本公开提出了一种源极驱动增强电路、源极驱动增强方法、源极驱动电路和显示设备。
根据本公开的一个方面，提出了一种源极驱动增强电路。该源极驱动增强电路包括开关子电路、充电子电路、增强子电路和储能子电路。所述开关子电路的控制端连接开关控制信号线，输入端连接源极驱动信号线，输出端连接数据线。所述充电子电路的控制端连接充电控制信号线，第一输入端连接第一电压，第二输入端连接充电电压，第一输出端和第二输出端分别连接到所述储能子电路的第一端和第二端。所述增强子电路的控制端连接增强控制信号线，增强子电路的输入端连接所述源极驱动信号线，增强子电路的输出端连接所述数据线，第一放电端和第二放电端分别连接到所述储能单元的第一端和第二端。
在一个实施例中，所述开关子电路包括第一晶体管，所述开关子电路的控制端是所述第一晶体管的栅极，输入端是所述第一晶体管的源极和漏极中的一个，输出端是所述 第一晶体管的源极和漏极中的另一个。
在一个实施例中，所述充电子电路包括第二晶体管和第三晶体管，所述充电子电路的控制端连接所述第二晶体管的栅极和所述第三晶体管的栅极，第一输入端是所述第二晶体管的源极和漏极中的一个，第二输入端是所述第三晶体管的源极和漏极中的一个，第一输出端是所述第二晶体管的源极和漏极中的另一个，第二输出端是所述第三晶体管的源极和漏极中的另一个。
在一个实施例中，所述增强子电路包括第四晶体管和第五晶体管，所述增强子电路的控制端连接所述第四晶体管的栅极和所述第五晶体管的栅极，输入端是所述第四晶体管的源极和漏极中的一个，输出端是所述第五晶体管的源极和漏极中的一个，第一放电端是所述第四晶体管的源极和漏极中的另一个，第二放电端是所述第五晶体管的源极和漏极中的另一个。
在一个实施例中，所述储能子电路包括电容器，所述储能子电路的第一端和第二端分别是所述电容器的第一端和第二端。
在一个实施例中，响应于不对源极驱动信号进行增强，在开关控制信号线上的开关控制信号、充电控制信号线上的充电控制信号以及增强控制信号线上的增强控制信号的控制下，开关子电路接通。
在一个实施例中，响应于对源极驱动信号进行增强，在开关控制信号线上的开关控制信号、充电控制信号线上的充电控制信号以及增强控制信号线上的增强控制信号的控制下，使得在第一时段，开关子电路接通、充电子电路接通和增强子电路关断，以利用所述充电电压向所述储能子电路充电；以及使得在第二时段，开关子电路关断、充电子电路关断和增强子电路接通，以向所述数据线提供增强源极驱动电压，所述增强源极驱动电压的幅值等于源极驱动电压的幅值与充电电压的幅值之和减去第一电压。
根据本公开的另一方面，提出了一种使用根据上述各实施例的源极驱动增强电路的源极驱动增强方法。该源极驱动增强方法包括：确定是否对源极驱动进行增强；当确定不进行增强时，在开关控制信号线上提供使开关子电路接通的开关控制信号、在充电控制信号线上提供使充电子电路关断的充电控制信号、在增强控制信号线上提供使增强子电路关断的增强控制信号，以将所述源极驱动电压提供给数据线；以及当确定进行增强时，在充电时段，在开关控制信号线上提供使开关子电路接通的开关控制信号、在充电控制信号线上提供使充电子电路接通的充电控制信号以及在增强控制信号线上提供使 增强子电路关断的增强控制信号，以在将源极驱动电压提供给数据线的同时利用所述充电电压向所述储能子电路充电；在增强时段，在开关控制信号线上提供使开关子电路关断的开关控制信号、在充电控制信号线上提供使充电子电路关断的充电控制信号以及在增强控制信号线上提供使增强子电路接通的增强控制信号，以向所述数据线提供增强源极驱动电压，所述增强源极驱动电压的幅值等于源极驱动电压的幅值与充电电压的幅值之和减去第一电压。
根据本公开的又一方面，提出了一种源极驱动电路。该源极驱动电路包括根据上述各实施例的源极驱动增强电路。
根据本公开的又一方面，提出了一种显示设备。该显示设备包括上述源极驱动电路。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出了根据本公开实施例的源极驱动增强电路的结构框图；
图2示出了图1所示的源极驱动增强电路的一种示意电路图；
图3示出了图2所示的电路的时序图；以及
图4示出了根据本公开实施例的源极驱动增强方法的流程图。
具体实施方式
以下参照附图，对本公开的示例实施例进行详细描述。贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本公开至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。
还应注意的是，本领域技术人员可以理解，本文中的术语“A与B相连”和“A连接到B”可以是A与B直接相连，也可以是A经由一个或多个其他组件与B相连。此外，本文中的“相连”和“连接到”可以是物理电连接，也可以是电耦接或电耦合等。
本领域技术人员可以理解，本公开所有实施例中采用的晶体管均可以是薄膜晶体管或场效应管或其他特性相同的器件。可选地，本公开实施例中使用的薄膜晶体管可以是氧化物半导体晶体管。此外，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。
此外，在以下实施例中均以N型晶体管为例进行描述，即，当晶体管的栅极电压为高电平时晶体管导通，当栅极电压为低电平时晶体管断开。本领域技术人员可以理解，可以使用P型晶体管，即，当晶体管的栅极电压为低电平时晶体管导通且栅极电压为高电平时晶体管断开，此时对电路结构的相应修改是本领域技术人员显而易见的。
以下参考附图对本公开进行具体描述。
图1示出了根据本公开实施例的源极驱动增强电路100的结构框图。如图1所示，源极驱动增强电路100包括开关子电路110、充电子电路120、增强子电路130和储能子电路140。图1中示意性地示出了源极驱动增强电路100的输出连接到数据线，并经由数据线对相应的像素单元进行充电。
开关子电路110的控制端连接至提供开关控制信号EN的开关控制信号线，输入端连接至提供源极驱动信号Vs1的源极驱动信号线，输出端连接数据线。
充电子电路120的控制端连接至提供充电控制信号TP的充电控制信号线，第一输入端连接第一电压V1，第二输入端连接充电电压VREF，第一输出端和第二输出端分别连接到储能子电路140的第一端和第二端，以能够对储能子电路140进行充电。在一个实施例中，所示第一电压V1可以为低电平，例如地电势。
在本申请中，需要利用VREF对源极驱动电压Vs1起到增强作用。因此，VREF的电压极性与Vs1的电压极性一致。当源极驱动信号对像素单元进行充电时，Vs1为正电压，此时，VREF也为正电压。类似地，当源极驱动信号对像素单元进行反充(即，放电)时，Vs1为负电压，此时，VREF也为为负电压。
增强子电路130的控制端连接至提供增强控制信号TP_D的增强控制信号线，输入端连接源极驱动信号线，输出端连接数据线，第一放电端和第二放电端分别连接到储能单 元140的第一端和第二端。储能子电路140能够借助增强子电路130使数据线接收的电压为增强源极驱动电压Vs2。
图2示出了图1所示的源极驱动增强电路100的一种示意电路图。
从图2可见，开关子电路110可以包括第一晶体管S1。其中，开关子电路110的控制端是第一晶体管S1的栅极，输入端是第一晶体管S1的源极和漏极中的一个，输出端是第一晶体管的源极和漏极中的另一个。
充电子电路120包括第二晶体管S2和第三晶体管S3。充电子电路120的控制端连接第二晶体管S2的栅极和第三晶体管S3的栅极，以向二者分别提供充电控制信号TP。充电子电路120的第一输入端是第二晶体管S2的源极和漏极中的一个，第二输入端是第三晶体管S3的源极和漏极中的一个。充电子电路120的第一输出端是第二晶体管S2的源极和漏极中的另一个，第二输出端是第三晶体管S3的源极和漏极中的另一个。
应该理解的是，在备选实施例中，可以将第二晶体管S2和第三晶体管S3设置成满足以下条件，即，充电子电路120的第一输入端是第三晶体管S3的源极和漏极中的一个，第二输入端是第二晶体管S2的源极和漏极中的一个，其余连接关系保持不变。此时，相当于将图2中充电子电路120的第一输入端和第二输入端互换位置，即VREF与V1互换。为了保证增强作用的实现，只需相应改变VREF和V1的电压极性即可。考虑到V1是相对低得多的电平(比如地电势)，可以只改变VREF的电压极性即可。例如，如果第二晶体管S2连接充电电压VREF且第三晶体管S3连接第一电压V1，则充电电压VREF的电压极性与源极驱动信号的电压极性应相反。
增强子电路130可以包括第四晶体管S4和第五晶体管S5。增强子电路130的控制端连接第四晶体管S4的栅极和第五晶体管S5的栅极，以向二者分别提供增强控制信号TP_D。增强子电路130的输入端是第四晶体管S4的源极和漏极中的一个，输出端是第五晶体管S5的源极和漏极中的一个。增强子电路130的第一放电端是第四晶体管S4的源极和漏极中的另一个，第二放电端是第五晶体管S5的源极和漏极中的另一个。
储能子电路140包括电容器C。储能子电路140的第一端和第二端分别是电容器C的第一端和第二端。
需要指出的是，在图2中为了便于描述，只将各个像素单元简化地示为单个的像素电容。本领域技术人员能够理解本发明技术方案所使用的范围不限于此。在一个实施例中，利用源极驱动增强电路100的输出对像素电容进行充电。
响应于不对源极驱动信号电压Vs1进行增强，在开关控制信号、充电控制信号和增强控制信号的控制下，开关子电路110接通，充电子电路120关断，增强子电路130关断。此时，源极驱动信号电压Vs1直接通过开关子电路110输出到数据线，输出的电压为源极驱动电压Vs1。
响应于对源极驱动信号电压Vs1进行增强。在开关控制信号、充电控制信号和增强控制信号的控制下，首先，使得开关子电路110接通，充电子电路120接通，增强子电路130关断，以在将源极驱动信号Vs1提供给数据线的同时利用充电电压VREF对储能子电路140充电。例如，第二晶体管S2和第三晶体管S3导通，充电电压VREF对电容器C进行充电。
接下来，使得开关子电路110关断，充电子电路120关断，增强子电路130接通，以向数据线提供增强源极驱动电压Vs2。例如，第一晶体管S1、第二晶体管S2和第三晶体管S3关断，第四晶体管S4和第五晶体管S4导通，电容器C放电，输入的源极驱动电压Vs1经由第四晶体管S4和电容器C增强为增强源极驱动电压Vs2，并经由第五晶体管S5施加到数据线。增强源极驱动电压Vs2的幅值等于源极驱动电压Vs1的幅值与充电电压VREF的幅值之和减去第一电压V1，即，|Vs2|＝|Vs1|+|VREF|-V1。由于V1接近于零电势，此时，数据线接收到的驱动电压在增强子电路的作用下得以增强，输出到数据线的电压为增强源极驱动电压Vs2。
本领域技术人员可以理解，当源极驱动信号对像素单元进行充电时，Vs1为正电压，此时VREF为正电压，由此施加到第五晶体管S5的输入端的电压Vs2为(Vs1+VREF-V1)＝|Vs1|+|VREF|-V1。由于V1可以忽略不计，即|Vs2|＝|Vs1|+|VREF|，因此与源极驱动电压Vs1相比较，增强源极驱动电压Vs2的电压幅值增大。当源极驱动信号对像素单元进行反充(即，放电)时，Vs1为负电压，此时，VREF为负电压，由此施加到第五晶体管S5的输入端的电压Vs2为(Vs1+VREF-V1)＝-(|Vs1|+|VREF|-V1)。由于V1可以忽略不计，|Vs2|＝|Vs1|+|VREF|，因此与源极驱动电压Vs1相比较，增强源极驱动电压Vs2的电压幅值增大。
此外，图2仅示出了根据本公开实施例的源极驱动增强电路100的一种示意电路图。本领域技术人员可以理解，可以基于图2所示的示例实现各种变体。例如，可以通过并联或串联的多个电容器来实现根据本公开实施例的储能子电路140，由此能够根据应用环境灵活地设计储能子电路的容量。此外，可以使用晶体管的其他组合方式来实现根据 本公开实施例的开关子电路110、充电子电路120和/或增强子电路130。为了简明，本说明书中将不对此进行赘述。
图3示出了图2所示的电路的示例性时序图。应该指出的是，图3中各个信号的幅度只是示例性的，只用于体现单个信号内的幅值变化趋势，并不表示具体数值。不同的信号即使在图中示为具有相同的信号幅度，也并不意味着二者实际上具有相同的幅值。同样，不同的信号即使在图中示为具有不同的信号幅度，也并不意味着二者实际上具有不同的幅值。
图3中共示出了以下几种信号的时序图：开关控制信号EN(只示出了进行增强时的EN时序，不进行增强时EN一直保持低电平即可)、充电控制信号TP、增强控制信号TP_D、不进行增强时施加到像素单元的电平(图3中的“未增强”所对应的信号)、进行增强时施加到像素单元的电平(图3中的“增强”所对应的信号)。
首先，如上文所述，如果确定不对源极驱动电压Vs1进行增强，则在开关控制信号、充电控制信号和增强控制信号的控制下，使开关子电路110接通，充电子电路120关断，增强子电路130关断，使得输出到数据线的电压为源极驱动电压Vs1，此时像素单元的电平对应于图3中的“未增强”信号。此时，只需考虑图3中的这一个信号。
“未增强”信号的实线部分对应于没有RC延迟的情况，虚线部分则对应于存在RC延迟的情况。可以看出，当不存在RC延迟时，像素单元很快便被充电到预定电平(如图3所示，经过时间T1)。而当RC延迟出现时，这一充电时间被大大拉长，达到(T1+T2+T3)。这可能会导致充电不足的情况发生。需要考虑对源极驱动电压进行增强。
如上文所述，如果确定对源极驱动电压Vs1进行增强，则进入包括充电阶段和增强阶段的增强操作过程。
在开关控制信号、充电控制信号和增强控制信号的控制下，在充电时段，开关子电路110接通，充电子电路120接通，增强子电路130关断，使得充电子电路120对储能子电路140进行充电。此时，像素单元的充电速率与“未增强”情况相同(参见图3中的T1段“未增强”信号和“增强”信号的虚线部分(或实线部分))。在增强阶段，开关子电路110关断，充电子电路120关断，增强子电路130接通，以使得增强子电路130将储能子电路140的电势附加在源极驱动电压Vs1上对像素单元进行充电，即使用增强源极驱动电压Vs2进行充电。
“增强”信号的实线部分对应于没有RC延迟的情况，虚线部分则对应于存在RC延 迟的情况。可以看出，在进行增强后，当存在RC延迟时，充电时间从原来的T1+T2+T3缩短为T1+T2。这改善了RC延迟的影响，抑制了充电不足情况的发生。
如图3所示，在下一个周期中，针对反充的情况，也能实现类似的效果，只不过如前文所述，与正充的情况相比，需要改变VREF的电压极性(考虑到V1是低电平(比如地电势)，可以选择改变或不改变其电压极性)。
图4示出了根据本公开实施例的源极驱动增强方法400的流程图。
所述源极驱动增强方法400开始于步骤S410，其中，确定是否对源极驱动电压Vs1进行增强。
如果为“否”，则在步骤S420中，提供使开关子电路110接通的开关控制信号，以将所述源极驱动电压Vs1提供给数据线。
如果为“是”，则在步骤S430中，开始充电阶段。其中，开关控制信号线提供使开关子电路110接通的开关控制信号EN、充电控制信号线提供使充电子电路120接通的充电控制信号TP以及增强控制信号线提供使增强子电路130关断的增强控制信号TP_D，以在将源极驱动电压Vs1提供给数据线的同时利用充电电压VREF对所述储能子电路140充电。
然后，在步骤S440中，进入增强阶段。其中，提供使开关子电路110关断的开关控制信号EN、使充电子电路120关断的充电控制信号TP以及使增强子电路130接通的增强控制信号TP_D，以向所述数据线提供增强源极驱动电压Vs2，所述增强源极驱动电压Vs2幅值等于源极驱动电压Vs1的幅值与充电电压的幅值之和减去第一电压。
本公开还提出了一种源极驱动电路。该源极驱动电路包括如图1和/或图2中所示的源极驱动增强电路100。
本公开还提出了一种显示设备。该显示设备包括如上所述的源极驱动电路。
以上的详细描述通过使用示意图、流程图和/或示例，已经阐述了众多实施例。在这种示意图、流程图和/或示例包含一个或多个功能和/或操作的情况下，本领域技术人员应理解，这种示意图、流程图或示例中的每一功能和/或操作可以通过各种结构、硬件、软件、固件或实质上它们的任意组合来单独和/或共同实现。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的 精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (10)

  1. 一种源极驱动增强电路，包括：
    开关子电路，所述开关子电路的控制端连接开关控制信号线，输入端连接源极驱动信号线，输出端连接数据线；
    储能子电路，具有第一端和第二端；
    充电子电路，所述充电子电路的控制端连接充电控制信号线，第一输入端连接第一电压，第二输入端连接充电电压，第一输出端和第二输出端分别连接到所述储能子电路的第一端和第二端；以及
    增强子电路，所述增强子电路的控制端连接增强控制信号线，所述增强子电路的输入端连接所述源极驱动信号线，所述增强子电路的输出端连接所述数据线，第一放电端和第二放电端分别连接到所述储能单元的第一端和第二端。
  2. 根据权利要求1所述的源极驱动增强电路，其中，所述开关子电路包括第一晶体管，所述开关子电路的控制端是所述第一晶体管的栅极，输入端是所述第一晶体管的源极和漏极中的一个，输出端是所述第一晶体管的源极和漏极中的另一个。
  3. 根据权利要求1所述的源极驱动增强电路，其中，所述充电子电路包括第二晶体管和第三晶体管，所述充电子电路的控制端连接所述第二晶体管的栅极和所述第三晶体管的栅极，第一输入端是所述第二晶体管的源极和漏极中的一个，第二输入端是所述第三晶体管的源极和漏极中的一个，第一输出端是所述第二晶体管的源极和漏极中的另一个，第二输出端是所述第三晶体管的源极和漏极中的另一个。
  4. 根据权利要求1所述的源极驱动增强电路，其中，所述增强子电路包括第四晶体管和第五晶体管，所述增强子电路的控制端连接所述第四晶体管的栅极和所述第五晶体管的栅极，所述增强子电路的输入端是所述第四晶体管的源极和漏极中的一个，所述增强子电路的输出端是所述第五晶体管的源极和漏极中的一个，第一放电端是所述第四晶体管的源极和漏极中的另一个，第二放电端是所述第五晶体管的源极和漏极中的另一个。
  5. 根据权利要求1所述的源极驱动增强电路，其中，所述储能子电路包括电容器，所述储能子电路的第一端和第二端分别是所述电容器的第一端和第二端。
  6. 根据权利要求1所述的源极驱动增强电路，其中，响应于不对源极驱动信号进行增强，在开关控制信号线上的开关控制信号、充电控制信号线上的充电控制信号以及增 强控制信号线上的增强控制信号的控制下，开关子电路接通。
  7. 根据权利要求1所述的源极驱动增强电路，其中，响应于对源极驱动进行增强，在开关控制信号线上的开关控制信号、充电控制信号线上的充电控制信号以及增强控制信号线上的增强控制信号的控制下，
    使得开关子电路接通、充电子电路接通以及增强子电路关断，以在将源极驱动电压提供给数据线的同时利用所述充电电压向所述储能子电路充电，以及
    使得开关子电路关断、充电子电路关断以及增强子电路接通，以向所述数据线提供增强源极驱动电压，所述增强源极驱动电压的幅值等于源极驱动电压的幅值与充电电压的幅值之和减去第一电压。
  8. 一种使用根据权利要求1-7中的任一项所述的源极驱动增强电路的源极驱动增强方法，包括：
    确定是否对源极驱动进行增强；
    当确定不进行增强时，在开关控制信号线上提供使开关子电路接通的开关控制信号，以将所述源极驱动电压提供给数据线，以及
    当确定进行增强时，
    在充电时段，在开关控制信号线上提供使开关子电路接通的开关控制信号、在充电控制信号线上提供使充电子电路接通的充电控制信号以及在增强控制信号线上提供使增强子电路关断的增强控制信号，以在将源极驱动电压提供给数据线的同时利用所述充电电压对所述储能子电路充电；
    在增强时段，在开关控制信号线上提供使开关子电路关断的开关控制信号、在充电控制信号线上提供使充电子电路关断的充电控制信号以及在增强控制信号线上提供使增强子电路接通的增强控制信号，以向所述数据线提供增强源极驱动电压，所述增强源极驱动电压的幅值等于源极驱动电压的幅值与充电电压的幅值之和减去第一电压。
  9. 一种源极驱动电路，包括根据权利要求1-7所述的源极驱动增强电路。
  10. 一种显示设备，包括根据权利要求9所述的源极驱动电路。
PCT/CN2018/086523 2017-08-22 2018-05-11 源极驱动增强电路、源极驱动增强方法、源极驱动电路和显示设备 WO2019037475A1 (zh)

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