WO2019033340A1 - 一种可输出正负电压的电平转换器 - Google Patents

一种可输出正负电压的电平转换器 Download PDF

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Publication number
WO2019033340A1
WO2019033340A1 PCT/CN2017/097857 CN2017097857W WO2019033340A1 WO 2019033340 A1 WO2019033340 A1 WO 2019033340A1 CN 2017097857 W CN2017097857 W CN 2017097857W WO 2019033340 A1 WO2019033340 A1 WO 2019033340A1
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Prior art keywords
voltage
coupled
transistor
type transistor
type
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PCT/CN2017/097857
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English (en)
French (fr)
Inventor
黄慕理
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深圳市汇顶科技股份有限公司
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Priority to CN201780000992.XA priority Critical patent/CN109417606B/zh
Priority to EP17911395.6A priority patent/EP3462617A4/en
Priority to PCT/CN2017/097857 priority patent/WO2019033340A1/zh
Priority to US16/197,255 priority patent/US10924115B2/en
Publication of WO2019033340A1 publication Critical patent/WO2019033340A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356086—Bistable circuits with additional means for controlling the main nodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present application relates to a level shifter, and more particularly to a level shifter that can output positive and negative voltages.
  • Image sensors have been widely used in electronic devices with photography functions as well as digital photography devices.
  • the image sensor includes a pixel sensing array, and a row/column of the pixel sensing array can be coupled to a row of level shifters to convert the level of the output thereof.
  • part of the circuit operates between a high voltage and a low voltage
  • the low voltage is a negative voltage lower than the ground voltage
  • the amplitude between the high voltage and the low voltage is greater than that in the circuit system.
  • the prior art requires a special high-voltage process to produce circuit components having high withstand voltages to achieve the level shifters required by the system, resulting in an increase in production cost.
  • the embodiment of the present application provides a level shifter including a first P-type transistor, a second P-type transistor, and a third P-type transistor coupled to the second P-type transistor.
  • a fourth P-type transistor coupled to the first P-type transistor; a first N-type transistor coupled to the third P-type transistor; and a second N-type transistor coupled to the fourth P-type transistor; a third N-type transistor coupled to the first N-type transistor; a fourth N-type transistor coupled to the second N-type transistor; and an inverter coupled to the third N-type transistor and Between the fourth N-type transistors, an input end of the inverter receives an input signal of the level shifter; wherein a source of the first P-type transistor is coupled to the second P-type a source of the transistor forms a first node, a gate of the third P-type transistor is coupled to a gate of the fourth P-type transistor to form a second node, and a gate of the first N-type transistor is coupled
  • the first N-type transistor, the second N-type transistor, the third N-type transistor, and the fourth N-type transistor are all N-type transistors having deep N-type wells.
  • the first node receives a first voltage
  • the second node receives a second voltage or a fifth voltage
  • the third node receives a third voltage
  • the fourth node receives a fourth voltage
  • the fourth The voltage is a negative voltage
  • the voltage difference between the fourth voltage and the first voltage is greater than the specific withstand voltage of the level shifter.
  • the gate of the third P-type transistor and the gate of the fourth P-type transistor receive the second voltage; when the first voltage ( VPH) is less than The second specific value, the gate of the third P-type transistor and the gate of the fourth P-type transistor receive the fifth voltage; the fifth voltage is less than the second voltage.
  • the level shifter further includes a first voltage supply unit for providing the second voltage, a second voltage supply unit for providing the fifth voltage, and a switching unit coupled to one end thereof a second node, the other end is coupled to the first voltage supply unit, and the other end is coupled to the second voltage supply unit; wherein, when the first voltage is greater than the first specific value, the switching unit is Passing a link between the second node and the first voltage supply unit; wherein, when the first voltage is less than a second specific value, the switching unit turns on the second node and the second A link between voltage supply units.
  • the inverter outputs a first high potential and a first low potential, wherein the first high potential is the third voltage and the first low potential is a fourth voltage.
  • the output of the level shifter is located between the fourth P-type transistor and the second N-type transistor.
  • the level shifter further includes an output circuit including a first P-type output transistor coupled to the first P-type transistor, and a second P-type output transistor coupled to the first P-type output a transistor and the second node; a first N-type output transistor coupled to the second P-type output transistor and the third node; and a second N-type output transistor coupled to the first N-type An output transistor and the fourth N-type transistor.
  • the level shifter further includes a first voltage supply unit for providing the second voltage, a second voltage supply unit for providing the fifth voltage, and a switching unit coupled at one end thereof
  • the second node is coupled to the first voltage supply unit, and the other end is coupled to the second voltage supply unit; wherein, when the first voltage is greater than the first specific value, the switching unit Transmitting a link between the second node and the first voltage supply unit; wherein, when the first voltage is less than a second specific value, the switching unit turns on the second node and the A link between two voltage supply units.
  • the inverter outputs a first high potential and a first low potential, wherein the first high potential is the third voltage and the first low potential is a fourth voltage.
  • the output of the level shifter is located between the fourth P-type transistor and the second N-type transistor.
  • the level shifter further includes an output circuit including a first P-type output transistor coupled to the first P-type transistor, and a second P-type output transistor coupled to the first P-type output a transistor and the second node; a first N-type output transistor coupled to the second P-type output transistor and the third node; and a second N-type output transistor coupled to the first N-type An output transistor and the fourth N-type transistor.
  • the level shifter further includes a first buffer circuit including a first buffer inverter having an input coupled to the fourth P-type transistor and an output coupled to the first P-type An output transistor having a high DC bias terminal coupled to the first node and a low DC bias terminal coupled to the second node; a second buffer inverter having an input coupled to the fourth An N-type transistor has an output coupled to the second N-type output transistor, a high DC bias terminal coupled to the third node, and a low DC bias terminal coupled to the fourth node.
  • the first buffer circuit further includes a pull-down transistor coupled between the input end of the first buffer inverter and the second node, controlled by a pull-down signal to be open or turned on;
  • the pull transistor is coupled between the input end of the second buffer inverter and the third node, and is controlled to be open or turned on by the pull-up signal.
  • the pull down signal is related to a first output signal of the first buffer inverter
  • the pull up signal is related to a second output signal of the second buffer inverter
  • the first buffer circuit further includes a plurality of first auxiliary inverters coupled between the output of the first buffer inverter and the first P-type output transistor; and a plurality of second An auxiliary inverter coupled between the output of the second buffer inverter and the second N-type output transistor.
  • the pull-down signal is related to the first buffering inverter and the plurality of output signals of the plurality of first auxiliary inverters
  • the pull-up signal is related to the second buffering inverter and the A plurality of output signals of the plurality of second auxiliary inverters are described.
  • the pull-down transistor when the output signal of the first buffer inverter is high, the pull-down transistor is turned on; when the output signal of the second buffer inverter is high, the pull-up transistor is turned on.
  • the level shifter further includes a second buffer circuit coupled to the first P-type transistor, the third P-type transistor, the first N-type transistor, and the third N-type transistor Wherein the second buffer circuit has the same circuit structure as the first buffer circuit.
  • the output of the level shifter is located between the second P-type output transistor and the first N-type output transistor.
  • the level shifter further includes a first capacitor, one end of which is coupled between the first P-type transistor and the third P-type transistor, and the other end of which is coupled to the inverter And an output terminal; and a second capacitor, one end of which is coupled between the second P-type transistor and the fourth P-type transistor, and the other end of which is coupled to the input end of the inverter.
  • the level shifter is applied to a row/column decoder of an image sensor.
  • the voltage difference of the amplitude of the output signal is shared by using the transistors formed by the cascade; the output signal of the low potential is outputted by the N-type transistor having the deep N-type well; and the output circuit is used to provide sufficient and stable output.
  • the capacitance of the device shortens the instantaneous time of potential flipping.
  • the embodiment of the present application can output a large amplitude output signal without using a high voltage process to produce its components, which has the advantage of reducing production cost.
  • FIG. 1 is a schematic diagram of a level shifter according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a level shifter according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a level shifter according to an embodiment of the present application.
  • Coupled is used to mean any direct or indirect electrical connection, and the term “electrical connection” refers to a direct electrical connection.
  • FIG. 1 is a schematic diagram of a level shifter 10 according to an embodiment of the present application.
  • the level shifter 10 is a circuit produced by a specific process having a specific breakdown voltage BV, in other words, when the component across the level shifter 10 exceeds a specific withstand voltage BV, The semiconductor element inside the level shifter circuit 10 is broken down, causing the level shifter 10 to be damaged.
  • the level shifter 10 is used to convert a signal having a small amplitude into a signal having a large amplitude, and the amplitude of the output signal of the level shifter 10 is greater than a specific withstand voltage BV.
  • the level shifter 10 includes P-type transistors MP1, MP2, MP3, MP4, N-type transistors MN1, MN2, MN3, MN4 and an inverter INV, P-type transistors MP1, MP2, MP3, MP4,
  • the N-type transistors MN1, MN2, MN3, and MN4 are connected to each other in a Cascode manner.
  • the sources of the P-type transistors MP3 and MP4 are respectively coupled to the drains of the P-type transistors MP1 and MP2.
  • the drains of the N-type transistors MN1 and MN2 are respectively coupled to the drains of the P-type transistors MP3 and MP4, and the drains of the N-type transistors MN3 and MN4 are respectively coupled to the sources of the N-type transistors MN1 and MN2.
  • the source of the P-type transistors MP1 and MP2 receives the voltage VPH, and the gates of the P-type transistors MP3 and MP4 (Gate, which are recorded as nodes) N2)
  • the receivable voltage VPL is received, the gates of the N-type transistors MN1, MN2 (denoted as node N3) receive the voltage VPM, and the sources of the N-type transistors MN3, MN4 (denoted as the node N4) receive the voltage VPN.
  • the input terminal IN of the inverter INV is coupled to the gate of the N-type transistor MN3, and the output terminal OUT of the inverter INV is coupled to the gate of the N-type transistor MN4.
  • the high DC bias terminal of the inverter INV receives the voltage VPM (ie, the DC bias received by the source of the P-type transistor in the inverter INV is the voltage VPM), and the low DC bias terminal of the inverter INV receives the voltage VPN. (ie, the DC bias received by the source of the N-type transistor in the inverter INV is the voltage VPN).
  • the high potential of the inverter INV output is the voltage VPM
  • the low potential of the inverter INV output is Voltage VPN.
  • the voltage VPN is a negative voltage (for example, the voltage VPN can be -1 V). Therefore, the N-type transistors in the N-type transistors MN1, MN2, MN3, MN4 and the inverter INV are all deep N. N-type transistor of the type well (Deep N Well). The structure of an N-type transistor having a deep N-well is well known to those skilled in the art and will not be described herein.
  • the P-type transistors MP1, MP2, MP3, and MP4 form a positive feedback loop.
  • the source of the P-type transistor MP3 is coupled to the gate of the P-type transistor MP2, and the source of the P-type transistor MP4.
  • the pole is coupled to the gate of the P-type transistor MP1.
  • the input terminal IN of the inverter INV receives the input signal LS_IN of the level shifter 10, and the drains of the P-type transistor MP4 and the N-type transistor MN2 output the output signal LS_OUT of the level shifter 10.
  • the amplitude of the input signal LS_IN is between the voltage VPN and the voltage VPM
  • the amplitude of the output signal LS_OUT is between the voltage VPN and the voltage VPH.
  • a waveform diagram of the input signal LS_IN and the output signal LS_OUT can be referred to FIG.
  • the voltage VPN is -1V
  • the voltage VPM is 2.6V
  • the voltage VPL is 1V
  • the voltage VPH is 4.6V
  • the withstand voltage BV of the level shifter 10 is 3.6V.
  • the level shifter 10 uses P-type transistors MP3, MP4 and N-type transistors MN1, MN2 to cascade to share the voltage difference between the voltage VPN and the voltage VPH, so that the level The component across voltage of converter 10 (whether V GD /V DG , V GS /V SG , V DS /V SD or even V BD ) does not exceed the withstand voltage BV. Therefore, in the case where the output signal LS_OUT has an amplitude of 5.6 V, the level shifter 10 can still operate normally without being damaged.
  • the level shifter 10 of the present application can be composed of circuit components produced by a low voltage process without causing breakdown/crash of circuit components, which can reduce production costs.
  • the voltage VPH may be lower than 4.6V, for example, the voltage VPH may be 3.1V.
  • the level shifter 10 can adjust the voltage of the node N2 to be low, so that the P-type transistors MP1, MP2, MP3, and MP4 can be normally turned on during the turn-on to maintain the level shifter 10 in normal operation.
  • the level shifter 10 can include a switching unit 16, and the switching unit 16 can have three end points. The three end points of the switching unit 16 are respectively coupled to the node N2, the voltage supply unit 12, and the voltage supply unit 14, and the voltage supply.
  • the unit 12 can provide a voltage VPL
  • the voltage supply unit 14 can provide a voltage VPL' (VPL' ⁇ VPL) whose potential is less than the voltage VPL.
  • VPL' VPL' ⁇ VPL
  • the switching unit 16 turns on the link between the node N2 and the voltage supply unit 12, at which time the node N2 can receive the voltage VPL; when the voltage VPH is less than the second specific value, the switching unit 16 A link between the node N2 and the voltage supply unit 14, at which point the node N2 can receive the voltage VPL'.
  • the first specific value and the second specific value may be adjusted according to actual needs, as long as the P-type transistors MP1, MP2, MP3, and MP4 are normally turned on when the conduction is performed, and all meet the requirements of the present invention.
  • the voltage supply unit 14 can be simply a ground terminal, that is, the voltage VPL' is 0V.
  • the switching unit 16 can include a transmission/pass gate TG and a transistor TN. When the voltage VPH is greater than the first specific value, the transmission gate TG is turned on and the transistor TN is turned off; When VPH is less than the second specific value, the transfer gate TG is open and the transistor TN is turned on.
  • the level shifter can include an output circuit and a buffer circuit.
  • FIG. 2 is a schematic diagram of a level shifter 20 according to an embodiment of the present application.
  • the level shifter 20 is similar to the level shifter 10, so the same elements follow the same symbols.
  • the level shifter 20 further includes a buffer circuit 22 and an output circuit 24.
  • the snubber circuit 22 serves to block/block the effects of transient voltage changes on the output circuit 24, and the output circuit 24 is used to provide a sufficient and stable output current to smoothly drive the back-end/stage circuit.
  • the buffer circuit 22 includes buffer inverters IVB_1, IVB_2, and the high DC bias terminal of the buffer inverter IVB_1 (ie, the source of the P-type transistor in the buffer inverter IVB_1) is coupled to the node receiving the voltage VPH.
  • N1 the low DC bias end of the buffer inverter IVB_1 (ie, the source of the N-type transistor in the buffer inverter IVB_1) is coupled to the node N2 of the receiving voltage VPL or VPL', in other words, the buffer inversion
  • the high potential of the output of the IVB_1 is the voltage VPH
  • the low potential of the buffer inverter IVB_1 is the voltage VPL or VPL'.
  • the high DC bias terminal of the buffer inverter IVB_2 (ie, the source of the P-type transistor in the buffer inverter IVB_2) is coupled to the node N3 that can receive the voltage VPM
  • the low DC bias terminal of the buffer inverter IVB_2 (ie, The source of the N-type transistor in the buffer inverter IVB_2 is coupled to the node N4 that can receive the voltage VPN.
  • the high potential of the buffer inverter IVB_2 is the voltage VPM
  • the output of the buffer inverter IVB_2 is low.
  • the potential is a voltage VPN.
  • the output circuit 24 includes P-type output transistors MPA, MPB and N-type output transistors MNA, MNB, P-type output transistors MPA, MPB and N-type output transistors MNA, MNB are connected in series, and the connections between the transistors are connected. Similar to the P-type transistors MP2, MP4 and N-type transistors MN2, MN4, that is, the source of the P-type output transistor MPB is coupled to the P-type output crystal The drain of the body transistor MPA, the drain of the N-type output transistor MNA is coupled to the drain of the P-type output transistor MPB, and the drain of the N-type output transistor MNB is coupled to the source of the N-type output transistor MNA.
  • the gate of the P-type output transistor MPB is coupled to the node N2
  • the gate of the N-type output transistor MNA is coupled to the node N3
  • the source of the P-type output transistor MPA is coupled to the node N1, and the output of the N-type output transistor MNB.
  • the source is coupled to the node N4.
  • the input end of the buffer inverter IVB_1 is coupled between the P-type transistors MP2 and MP4, and the output end of the buffer inverter IVB_1 is coupled to the gate of the P-type output transistor MPA; the input end of the buffer inverter IVB_2
  • the output of the buffer inverter IVB_2 is coupled to the gate of the N-type output transistor MNB.
  • the drains of the P-type output transistor MPB and the N-type output transistor MNA output the output signal LS_OUT of the level shifter 20.
  • the N-type transistors of the N-type output transistors MNA and MNB and the buffer inverters IVB_1 and IVB_2 are N-type transistors having deep N-type wells.
  • level shifter 20 The operation of level shifter 20 is described below.
  • the buffer inverter IVB_1 regards the voltage of the node N5 as a high potential, and at this time, the buffer inverter IVB_1 outputs a low potential to the voltage VPL or VPL', thereby accelerating P.
  • the output transistors MPA and MPB are turned on, and the output current when the P-type output transistors MPA and MPB are turned on is improved.
  • the buffer inverter IVB_2 regards the voltage of the node N6 as a low potential, and at this time, the buffer inverter IVB_2 outputs a high potential as the voltage VPM, thereby accelerating N.
  • the output transistors MNA and MNB are turned on, and the output current when the N-type output transistors MNA and MNB are turned on is improved.
  • the N-type transistor in the buffer inverter IVB_1 when the voltage of node N5 in Figure 2 drops to near (but slightly larger than) voltage VPL (or VPL') At this time, the N-type transistor in the buffer inverter IVB_1 generates a leakage current.
  • the buffer inverter IVB_1 when the voltage of the node N5 in FIG. 3 is close but slightly larger than the voltage VPL (or VPL'), the buffer inverter IVB_1 should consider the voltage of the node N5 to be low, and the buffer type IVB_1 is N-type. The crystal management should be open, but the voltage at node N5 is greater than the voltage VPL (or VPL'), causing the N-type transistor in the buffer inverter IVB_1 to be open to be slightly turned on, resulting in leakage current.
  • the P-type transistor in the buffer inverter IVB_2 when the voltage of the node N6 in FIG. 2 rises to be close to (but slightly smaller than) the voltage VPM
  • a pull-down transistor can be added between the input of the buffer inverter IVB_1 and the low DC bias terminal (ie, the source of the N-type transistor in the buffer inverter IVB_1).
  • a pull-up transistor can also be added between the input of the buffer inverter IVB_2 and the high DC bias terminal (ie, the source of the P-type transistor in the buffer inverter IVB_2).
  • FIG. 3 is a schematic diagram of a level shifter 30 according to an embodiment of the present application.
  • the level shifter 30 is similar to the level shifter 20, so the same elements follow the same symbols.
  • the level shifter 30 includes buffer circuits 32_a, 32_b, and the buffer circuit 32_b is coupled to the transistors MP1, MP3, MN1, and MN3 for transposing the potential and the transistor MP2 on the other side.
  • MP4, MN2, and MN4 have the same load, that is, the transistors MP1 to MP4 and MN1 to MN4 in the level shifter 30 are turned from low potential to high potential or from high potential to low potential. Can withstand the same / symmetrical load.
  • the buffer circuit 32_b may have the same circuit structure as the buffer circuit 32_a.
  • the buffer circuit 32_b can be regarded as providing the same load as the buffer circuit 32_a without generating signals for the transistors MP1, MP3, MN1, MN3 /
  • the voltage is operated in the field, and the following description will be based on the buffer circuit 32_a.
  • the buffer circuit 32_a includes a pull-down transistor LVMN, a pull-up transistor LVMP, and inverters IVB_11 to IVB_13, IVB_21 to IVB_23 (wherein the inverters IVB_11, IVB_21 can be regarded as a buffer inverter, and the inverters IVB_12, IVB_13, IVB_22, IVB_23 can be Considered as an auxiliary inverter).
  • the high DC bias terminals of the inverters IVB_11 to IVB_13 are coupled to the node N1, and the low DC bias terminals of the inverters IVB_11 to IVB_13 are coupled to the node N2; the high DC bias terminals of the inverters IVB_21 to IVB_23 The low DC bias terminals of the inverters IVB_21 to IVB_23 are coupled to the node N4.
  • the high potential of the inverters IVB_11 to IVB_13 is the voltage VPH
  • the low potentials of the inverters IVB_11 to IVB_13 are the voltages VPL or VPL'
  • the high potentials of the inverters IVB_21 to IVB_23 are the voltages VPM.
  • the low potential output by the inverters IVB_21 to IVB_23 is the voltage VPN.
  • the N-type transistors of the pull-down transistor LVMN and the inverters IVB_11 to IVB_13 and IVB_21 to IVB_23 are all N-type transistors having deep N-type wells.
  • the pull-down transistor LVMN is controlled by the pull-down signal PD and coupled between the input of the buffer inverter IVB_11 and the low DC bias terminal; the pull-up transistor LVMP is controlled by a pull-up signal PU coupled to the buffer reverse
  • the input of the IVB_21 is between the input terminal and the high DC bias terminal.
  • the pull-down transistor LVMN is turned on, which can pull down the voltage of the node N5 to the voltage VPL (or VPL'); when the buffer inverter IVB_21 outputs a low potential, the pull-up transistor LVMP leads Pass, which pulls up the voltage of node N6 to voltage VPM.
  • the buffer circuit 32_a may include a pull-down signal generator 34_PD and a pull-up signal generation
  • the 34_PU, pull-down signal generator 34_PD and pull-up signal generator 34_PU may be composed of transmission brake(s).
  • the pull-down signal PD can be the voltage VPM
  • the pull-down transistor LVMN is turned on, and the voltage of the node N5 can be pulled down to the voltage VPL (or VPL'); when the buffer is reversed
  • the pull-down signal PD can be the voltage VPL, and the pull-down transistor LVMN is open.
  • the pull-up signal PU When the output signal VOUTNB of the buffer inverter IVB_21 is low, the pull-up signal PU can be the voltage VPL, the pull-up transistor LVMP is turned on, and the voltage of the node N6 can be pulled up to the voltage VPM; when the buffer inverter IVB_21 When the output signal VOUTNB is at a high potential, the pull-down signal PD can be the voltage VPM, and the pull-up transistor LVMP is open.
  • the pull-down signal generator 34_PD and the pull-up signal generator 34_PU may also receive the output signal VOUTP of the inverter IVB_12 and the output signal VOUTN of the inverter IVB_22 to control the conduction state of its transmission gate. In short, the pull-down transistor LVMN and the pull-up transistor LVMP can be used to eliminate the leakage current of the buffer inverter.
  • the buffer circuit 32_a further includes a capacitor C1 and a capacitor C2.
  • One end of the capacitor C1 is coupled between the P-type transistors MP1 and MP3, and the other end of the capacitor C1 is coupled to the output terminal OUT of the inverter INV.
  • One end of the capacitor C2 is coupled between the P-type transistors MP2 and MP4. The other end of C2 is coupled to the input terminal IN of the inverter INV.
  • the capacitor C1 and the capacitor C2 are used to enhance the flipping force when the level shifter 30 is switched (turned from a low potential to a high potential or turned from a high potential to a low potential), and the potential transition time of the flat converter 30 is shortened (Transition Interval). To improve the system performance of the overall circuit.
  • level shifter of the present application is not limited to application to a specific circuit system, for example, the present application
  • the level shifter can be applied to the Image Sensor's Row Decoder without this limitation.
  • the embodiment of the present application utilizes a series of transistors to share the voltage difference of the output signal amplitude; using an N-type transistor having a deep N-type well, outputting an output signal with a low potential as a negative voltage; using an output circuit, Provide sufficient and stable output current to smoothly push the back-end/stage circuit; use the buffer circuit to block/block the influence of the instantaneous voltage change on the output circuit; use the lower/up-pull transistor to eliminate the leakage current of the buffer inverter; The capacitor coupled to the inverter shortens the instantaneous time of the potential flip.
  • the embodiment of the present application can output a large amplitude output signal without using a high voltage process to produce its components, which has the advantage of reducing production cost.

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Abstract

一种电平转换器（10）包括第一P型晶体管（MP2）；第二P型晶体管（MP1）；第三P型晶体管（MP3），耦接于第二P型晶体管（MP1）；第四P型晶体管（MP4），耦接于第一P型晶体管（MP2）；第一N型晶体管（MN1），耦接于第三P型晶体管（MP3）；第二N型晶体管（MN2），耦接于第四P型晶体管（MP4）；第三N型晶体管（MN3），耦接于第一N型晶体管（MN1）；第四N型晶体管（MN4），耦接于所述第二N型晶体管（MN2）；以及反向器（INN），耦接于第三N型晶体管与第四N型晶体管之间，反向器的输入端接收电平转换器的输入信号（LS_IN）。

Description

一种可输出正负电压的电平转换器 技术领域
本申请涉及一种电平转换器，尤其涉及一种可输出正负电压的电平转换器。
背景技术
图像传感器(Image Sensor)已广泛的应用于具有摄影功能的电子装置以及数字摄影装置中。一般而言，图像传感器包括一像素传感阵列，像素传感阵列的一行/列可耦接一排电平转换器，以转换其所输出的电平。
然而，对特定需求的电路系统，其部份电路运作于一高电压与一低电压之间，其低电压为低于接地电压的负电压，且高电压与低电压之间幅度大于电路系统中一般元件可承受的耐压。现有技术需特别另外利用高压制程来生产具有高耐压的电路元件，以实现系统所需的电平转换器，而导致生产成本的增加。
因此，现有技术实有改进的必要。
发明内容
因此，本申请部分实施例的目的即在于提供一种可输出正负电压且具有大输出振幅的电平转换器，以改善现有技术的缺点。
为了解决上述技术问题，本申请实施例提供了一种电平转换器，包括第一P型晶体管；第二P型晶体管；第三P型晶体管，耦接于所述第二P型晶体管；第四P型晶体管，耦接于所述第一P型晶体管；第一N型晶体管，耦接于所述第三P型晶体管；第二N型晶体管，耦接于所述第四P型晶体管；第三N型晶体管，耦接于所述第一N型晶体管；第四N型晶体管，耦接于所述第二N型晶体管；以及反向器，耦接于所述第三N型晶体管与所述第四N型晶体管之间，所述反向器的输入端接收所述电平转换器的输入信号；其中，所述第一P型晶体管的源极耦接于所述第二P型晶体管的源极而形成第一节点，所述第三P型晶体管的栅极耦接于所述第四P型晶体管的栅极而形成第二节点，所述第一N型晶体管的栅极耦接与所述第二N型晶体管的栅极而形成第三节点，所述第三N型晶体管的源极耦接于所述第四N型晶体管的源极而形成第四节点。
例如，所述第一N型晶体管、所述第二N型晶体管、所述第三N型晶体管以及所述第四N型晶体管皆为具有深N型井的N型晶体管。
例如，所述第一节点接收第一电压，所述第二节点接收第二电压或第五电压，所述第三节点接收第三电压，所述第四节点接收第四电压，所述第四电压为负电压。
例如，第四电压与第一电压的电压差大于所述电平转换器的特定耐压。
例如，当所述第一电压大于第一特定值时，所述第三P型晶体管的栅极及所述第四P型晶体管的栅极接收所述第二电压；当所述第一电压(VPH)小于 第二特定值时，所述第三P型晶体管的栅极及所述第四P型晶体管的栅极接收所述第五电压；所述第五电压小于所述第二电压。
例如，所述的电平转换器还包括第一电压供应单元，用来提供所述第二电压；第二电压供应单元，用来提供所述第五电压；以及切换单元，其一端耦接于第二节点，另一端耦接于所述第一电压供应单元，又一端耦接于所述第二电压供应单元；其中，当所述第一电压大于第一特定值时，所述切换单元导通所述第二节点与所述第一电压供应单元之间的链接；其中，当所述第一电压小于第二特定值时，所述切换单元导通所述第二节点与所述第二电压供应单元之间的链接。
例如，所述反向器输出第一高电位以及第一低电位，其中所述第一高电位为所述第三电压，所述第一低电位为第四电压。
例如，所述电平转换器的输出端位于所述第四P型晶体管与所述第二N型晶体管之间。
例如，所述的电平转换器还包括输出电路，包括第一P型输出晶体管，耦接于所述第一P型晶体管；第二P型输出晶体管，耦接于所述第一P型输出晶体管以及所述第二节点；第一N型输出晶体管，耦接于所述第二P型输出晶体管以及所述第三节点；以及第二N型输出晶体管，耦接于所述第一N型输出晶体管以及所述第四N型晶体管。
例如，所述的电平转换器还包括第一电压供应单元，用来提供所述第二电压；第二电压供应单元，用来提供所述第五电压；以及切换单元，其一端耦接 于第二节点，另一端耦接于所述第一电压供应单元，又一端耦接于所述第二电压供应单元；其中，当所述第一电压大于第一特定值时，所述切换单元导通所述第二节点与所述第一电压供应单元之间的链接；其中，当所述第一电压小于第二特定值时，所述切换单元导通所述第二节点与所述第二电压供应单元之间的链接。
例如，所述反向器输出第一高电位以及第一低电位，其中所述第一高电位为所述第三电压，所述第一低电位为第四电压。
例如，所述电平转换器的输出端位于所述第四P型晶体管与所述第二N型晶体管之间。
例如，所述的电平转换器还包括输出电路，包括第一P型输出晶体管，耦接于所述第一P型晶体管；第二P型输出晶体管，耦接于所述第一P型输出晶体管以及所述第二节点；第一N型输出晶体管，耦接于所述第二P型输出晶体管以及所述第三节点；以及第二N型输出晶体管，耦接于所述第一N型输出晶体管以及所述第四N型晶体管。
例如，所述的电平转换器还包括第一缓冲电路，包括第一缓冲反向器，其输入端耦接于所述第四P型晶体管，其输出端耦接于所述第一P型输出晶体管，其高直流偏压端耦接于所述第一节点，其低直流偏压端耦接于所述第二节点；第二缓冲反向器，其输入端耦接于所述第四N型晶体管，其输出端耦接于所述第二N型输出晶体管，其高直流偏压端耦接于所述第三节点，其低直流偏压端耦接于所述第四节点。
例如，所述第一缓冲电路还包括下拉晶体管，耦接于所述第一缓冲反向器的输入端与所述第二节点之间，受控于下拉信号而为断路或导通；以及上拉晶体管，耦接于所述第二缓冲反向器的输入端与所述第三节点之间，受控于上拉信号而为断路或导通。
例如，所述下拉信号相关于所述第一缓冲反向器的第一输出信号，所述上拉信号相关于所述第二缓冲反向器的第二输出信号。
例如，所述第一缓冲电路还包括多个第一辅助反向器，耦接与所述第一缓冲反向器的输出端与所述第一P型输出晶体管之间；以及多个第二辅助反向器，耦接与所述第二缓冲反向器的输出端与所述第二N型输出晶体管之间。
例如，所述下拉信号相关于所述第一缓冲反向器以及所述多个第一辅助反向器的多个输出信号，所述上拉信号相关于所述第二缓冲反向器以及所述多个第二辅助反向器的多个输出信号。
例如，当第一缓冲反向器的输出信号为高电位时，所述下拉晶体管导通；当第二缓冲反向器的输出信号为高电位时，所述上拉晶体管导通。
例如，所述的电平转换器还包括第二缓冲电路，耦接于所述第一P型晶体管、所述第三P型晶体管、所述第一N型晶体管以及所述第三N型晶体管；其中，所述第二缓冲电路与所述第一缓冲电路具有相同的电路结构。
例如，所述电平转换器的输出端位于所述第二P型输出晶体管与所述第一N型输出晶体管之间。
例如，所述的电平转换器还包括一第一电容，其一端耦接于所述第一P型晶体管与所述第三P型晶体管之间，另一端耦接于所述反向器的输出端；以及一第二电容，其一端耦接于所述第二P型晶体管与所述第四P型晶体管之间，另一端耦接于所述反向器的输入端。
例如，所述的电平转换器应用于图像传感器的行/列译码器。
本申请实施例利用串迭而成的晶体管，分摊输出信号振幅的电压差；利用具有深N型井的N型晶体管，输出低电位为负电压的输出信号；利用输出电路，提供充分且稳定的输出电流，以顺利推动后端/级电路；利用缓冲电路阻确/阻挡瞬时电压变化对输出电路的影响；利用下/上拉晶体管，消除缓冲反向器的漏电流；利用耦接于反向器的电容，缩短电位翻转的瞬时时间。本申请实施例可输出大振幅的输出信号，而不需利用高压制程来生产其元件，具有降低生产成本的优点。
附图说明
图1为本申请实施例一电平转换器的示意图；
图2为本申请实施例一电平转换器的示意图；
图3为本申请实施例一电平转换器的示意图；
图4为本申请实施例多个信号波形图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实 施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
在说明书以及权利要求中，「耦接」一词是指包含任何直接或间接的电气连接手段，「电性连接」一词是指直接电性连接。
请参考图1，图1为本申请实施例一电平转换器(Level Shifter)10的示意图。电平转换器10为利用一特定制程所生产的电路，其具有一特定耐压(Breakdown Voltage)BV，换句话说，当电平转换器10的元件跨压超过特定耐压BV时，将导致电平转换器电路10内部的半导体元件击穿/崩溃(Breakdown)，而导致电平转换器10损坏。电平转换器10用来将振幅较小的信号转换成振幅较大的信号，且电平转换器10输出信号的振幅大于特定耐压BV。
如图1所示，电平转换器10包括P型晶体管MP1、MP2、MP3、MP4、N型晶体管MN1、MN2、MN3、MN4以及反向器INV，P型晶体管MP1、MP2、MP3、MP4、N型晶体管MN1、MN2、MN3、MN4以串迭(Cascode)的方式相互连接，详细来说，P型晶体管MP3、MP4的源极(Source)分别耦接于P型晶体管MP1、MP2的漏极(Drain)，N型晶体管MN1、MN2的漏极分别耦接于P型晶体管MP3、MP4的漏极，N型晶体管MN3、MN4的漏极分别耦接于N型晶体管MN1、MN2的源极。其中，P型晶体管MP1、MP2的源极(记为节点N1)接收电压VPH，P型晶体管MP3、MP4的栅极(Gate，记为节点 N2)可接收电压VPL，N型晶体管MN1、MN2的栅极(记为节点N3)接收电压VPM，N型晶体管MN3、MN4的源极(记为节点N4)接收电压VPN。
反向器INV的输入端IN耦接于N型晶体管MN3的栅极，反向器INV的输出端OUT耦接于N型晶体管MN4的栅极。反向器INV的高直流偏压端接收电压VPM(即反向器INV中P型晶体管的源极所接收的直流偏压为电压VPM)，反向器INV的低直流偏压端接收电压VPN(即反向器INV中N型晶体管的源极所接收的直流偏压为电压VPN)，换句话说，反向器INV输出的高电位为电压VPM，而反向器INV输出的低电位为电压VPN。于一实施例中，电压VPN为一负电压(例如，电压VPN可为－1V)，因此，N型晶体管MN1、MN2、MN3、MN4以及反向器INV中的N型晶体管皆为具有深N型井(Deep N Well)的N型晶体管。具有深N型井的N型晶体管的结构为本领域据通常知识者所公知，故于此不再赘述。
除此之外，P型晶体管MP1、MP2、MP3、MP4形成一正回授回路，详细来说，P型晶体管MP3的源极耦接于P型晶体管MP2的栅极，P型晶体管MP4的源极耦接于P型晶体管MP1的栅极。反向器INV的输入端IN接收电平转换器10的输入信号LS_IN，而P型晶体管MP4及N型晶体管MN2的漏极输出电平转换器10的输出信号LS_OUT。输入信号LS_IN的振幅介于电压VPN与电压VPM之间，输出信号LS_OUT的振幅介于电压VPN与电压VPH之间。输入信号LS_IN与输出信号LS_OUT的波形图可参考图4。
电平转换器10的工作原理简述如下。于一实施例中，电压VPN为－1V，电压VPM为2.6V，电压VPL为1V，电压VPH为4.6V，电平转换器10的耐压BV为3.6V。当输入信号LS_IN为低电位(即电压VPN＝－1V)时，反向器INV的输出端OUT为高电位(即电压VPM＝2.6V)，此时N型晶体管MN2、MN4以及P型晶体管MP1、MP3为导通(Conducted)，N型晶体管MN1、MN3以及P型晶体管MP2、MP4为断路(Cutoff)，N型晶体管MN2的漏极电压被下拉至电压VPN(即－1V)，因此，此时电平转换器10输出输出信号LS_OUT为电压VPN(即－1V)。另一方面，当输入信号LS_IN为高电位(即电压VPM＝2.6V)时，反向器INV的输出端OUT为低电位(即电压VPN＝－1V)，此时N型晶体管MN1、MN3以及P型晶体管MP2、MP4为导通，N型晶体管MN2、MN4以及P型晶体管MP1、MP3为断路，P型晶体管MP1的漏极电压被上拉至电压VPH(即4.6V)，因此，此时电平转换器10输出输出信号LS_OUT为电压VPH。
由上述可知，当电平转换器10操作时，电平转换器10利用P型晶体管MP3、MP4以及N型晶体管MN1、MN2串迭以分摊电压VPN与电压VPH之间的电压差，使得电平转换器10的元件跨压(不论是VGD/VDG、VGS/VSG、VDS/VSD甚至是VBD)皆不会超过耐压BV。因此，在输出信号LS_OUT具有振幅为5.6V的情况下，电平转换器10仍可正常运作而不会损坏。
从另一角度来说，在系统需求需要电平转换器输出大振幅信号时，现有技术需利用高压制程来生产电平转换器所需的电路元件，以避免使电路元件击穿/ 崩溃。相较之下，本申请的电平转换器10可由低压制程所生产的电路元件所组成，而不会造成电路元件击穿/崩溃，其可降低生产成本。
更进一步地，于某些实施例/应用中，电压VPH可能会低于4.6V，举例来说，电压VPH可为3.1V。在此情形下，电平转换器10可调低节点N2的电压，使得P型晶体管MP1、MP2、MP3、MP4可于该导通的时候正常地导通，以维持电平转换器10正常运作。举例来说，电平转换器10可包括切换单元16，切换单元16可具有三个端点，切换单元16的三个端点分别耦接于节点N2、电压供应单元12以及电压供应单元14，电压供应单元12可提供电压VPL，电压供应单元14可提供其电位小于电压VPL的电压VPL’(VPL’<VPL)。当电压VPH大于第一特定值时，切换单元16导通节点N2与电压供应单元12之间的链接，此时节点N2可接收电压VPL；当电压VPH小于第二特定值时，切换单元16导通节点N2与电压供应单元14之间的链接，此时节点N2可接收电压VPL’。其中，第一特定值及第二特定值可视实际需要而有所调整，只要确保P型晶体管MP1、MP2、MP3、MP4于该导通的时候可正常地导通，皆满足本发明的要求。于一实施例中，电压供应单元14可单纯地为一接地端，即电压VPL’为0V。于一实施例中，切换单元16可包括一传输闸(Transmission/Pass Gate)TG以及一晶体管TN，当电压VPH大于第一特定值时，传输闸TG为导通且晶体管TN为断路；当电压VPH小于第二特定值时，传输闸TG为断路且晶体管TN为导通。
除此之外，为了使电平转换器具有更好的后端/级电路驱动能力，本申请的 电平转换器可包括输出电路以及缓冲电路。具体来说，请参考图2，图2为本申请实施例一电平转换器20的示意图。电平转换器20与电平转换器10类似，故相同元件沿用相同符号。与电平转换器10不同的是，电平转换器20还包括缓冲电路22以及输出电路24。缓冲电路22用来阻确/阻挡瞬时电压变化对输出电路24的影响，输出电路24用来提供充分且稳定的输出电流，以顺利推动后端/级电路。
详细来说，缓冲电路22包括缓冲反向器IVB_1、IVB_2，缓冲反向器IVB_1的高直流偏压端(即缓冲反向器IVB_1中P型晶体管的源极)耦接于接收电压VPH的节点N1，缓冲反向器IVB_1的低直流偏压端(即缓冲反向器IVB_1中N型晶体管的源极)耦接于所述接收电压VPL或VPL’的节点N2，换句话说，缓冲反向器IVB_1输出的高电位为电压VPH，而缓冲反向器IVB_1输出的低电位为电压VPL或VPL’。缓冲反向器IVB_2的高直流偏压端(即缓冲反向器IVB_2中P型晶体管的源极)耦接于可接收电压VPM的节点N3，缓冲反向器IVB_2的低直流偏压端(即缓冲反向器IVB_2中N型晶体管的源极)耦接于可接收电压VPN的节点N4，换句话说，缓冲反向器IVB_2输出的高电位为电压VPM，而缓冲反向器IVB_2输出的低电位为电压VPN。
输出电路24包括P型输出晶体管MPA、MPB以及N型输出晶体管MNA、MNB，P型输出晶体管MPA、MPB以及N型输出晶体管MNA、MNB以串迭的方式相互连接，其晶体管之间的连接方式与P型晶体管MP2、MP4以及N型晶体管MN2、MN4类似，即P型输出晶体管MPB的源极耦接于P型输出晶 体管MPA的漏极，N型输出晶体管MNA的漏极耦接于P型输出晶体管MPB的漏极，N型输出晶体管MNB的漏极耦接于N型输出晶体管MNA的源极。另外，P型输出晶体管MPB的栅极耦接于节点N2，N型输出晶体管MNA的栅极耦接于节点N3，P型输出晶体管MPA的源极耦接于节点N1，N型输出晶体管MNB的源极耦接于节点N4。另外，缓冲反向器IVB_1的输入端耦接于P型晶体管MP2与MP4之间，缓冲反向器IVB_1的输出端耦接于P型输出晶体管MPA的栅极；缓冲反向器IVB_2的输入端耦接于N型晶体管MN2与MN4之间，缓冲反向器IVB_2的输出端耦接于N型输出晶体管MNB的栅极。在此情形下，P型输出晶体管MPB及N型输出晶体管MNA的漏极输出电平转换器20的输出信号LS_OUT。另外，N型输出晶体管MNA、MNB以及缓冲反向器IVB_1、IVB_2中的N型晶体管皆为具有深N型井的N型晶体管。
电平转换器20的工作原理叙述如下。当图2中节点N5的电压上升至接近电压VPH时，缓冲反向器IVB_1将节点N5的电压视为高电位，此时缓冲反向器IVB_1输出低电位为电压VPL或VPL’，进而加速P型输出晶体管MPA、MPB导通，且增进P型输出晶体管MPA、MPB导通时的输出电流。同样地，当图2中节点N6的电压下降至接近电压VPN时，缓冲反向器IVB_2将节点N6的电压视为低电位，此时缓冲反向器IVB_2输出高电位为电压VPM，进而加速N型输出晶体管MNA、MNB导通，且增进N型输出晶体管MNA、MNB导通时的输出电流。
然而，当图2中节点N5的电压下降至接近(但略大于)电压VPL(或VPL’) 时，缓冲反向器IVB_1中的N型晶体管会产生漏电流。详细来说，当图3中节点N5的电压接近但略大于电压VPL(或VPL’)时，缓冲反向器IVB_1应视节点N5的电压为低电位，而缓冲反向器IVB_1中的N型晶体管理应为断路，但节点N5的电压又大于电压VPL(或VPL’)，导致缓冲反向器IVB_1中应为断路的N型晶体管略为导通，而导致漏电流。同样地，当图2中节点N6的电压上升至接近(但略小于)电压VPM时，缓冲反向器IVB_2中的P型晶体管亦会产生漏电流。
为了消除缓冲反向器IVB_1、IVB_2的漏电流，可于缓冲反向器IVB_1的输入端与低直流偏压端(即缓冲反向器IVB_1中N型晶体管的源极)之间加入一下拉晶体管，亦可于缓冲反向器IVB_2的输入端与高直流偏压端(即缓冲反向器IVB_2中P型晶体管的源极)之间加入一上拉晶体管。
具体来说，请参考图3，图3为本申请实施例一电平转换器30的示意图。电平转换器30与电平转换器20类似，故相同元件沿用相同符号。与电平转换器20不同的是，电平转换器30包括缓冲电路32_a、32_b，缓冲电路32_b耦接于晶体管MP1、MP3、MN1、MN3，用来于电位翻转时与另一侧的晶体管MP2、MP4、MN2、MN4具有相同的负载(Loading)，即不论是由低电位翻转为高电位或是由高电位翻转为低电位，电平转换器30中的晶体管MP1～MP4、MN1～MN4皆可承受相同/对称的负载。于一实施例中，缓冲电路32_b可与缓冲电路32_a具有相同的电路结构。缓冲电路32_b可视为提供与缓冲电路32_a相同的负载，而不对晶体管MP1、MP3、MN1、MN3所产生的信号/ 电压进行实地的运作，以下说明将以缓冲电路32_a为主。
缓冲电路32_a包括下拉晶体管LVMN、上拉晶体管LVMP以及反向器IVB_11～IVB_13、IVB_21～IVB_23(其中反向器IVB_11、IVB_21可视为缓冲反向器，反向器IVB_12、IVB_13、IVB_22、IVB_23可视为辅助反向器)。反向器IVB_11～IVB_13的高直流偏压端皆耦接于节点N1，反向器IVB_11～IVB_13的低直流偏压端皆耦接于节点N2；反向器IVB_21～IVB_23的高直流偏压端皆耦接于节点N3，反向器IVB_21～IVB_23的低直流偏压端皆耦接于节点N4。换句话说，反向器IVB_11～IVB_13输出的高电位为电压VPH，反向器IVB_11～IVB_13输出的低电位为电压VPL或VPL’，反向器IVB_21～IVB_23输出的高电位为电压VPM，而反向器IVB_21～IVB_23输出的低电位为电压VPN。另外，下拉晶体管LVMN以及反向器IVB_11～IVB_13、IVB_21～IVB_23中的N型晶体管皆为具有深N型井的N型晶体管。
下拉晶体管LVMN受控于一下拉信号PD而耦接于缓冲反向器IVB_11的输入端与低直流偏压端之间；上拉晶体管LVMP受控于一上拉信号PU而耦接于缓冲反向器IVB_21的输入端与高直流偏压端之间。当缓冲反向器IVB_11输出高电位时，下拉晶体管LVMN导通，其可将节点N5的电压下拉至电压VPL(或VPL’)；当缓冲反向器IVB_21输出低电位时，上拉晶体管LVMP导通，其可将节点N6的电压上拉至电压VPM。
具体来说，缓冲电路32_a可包括下拉信号产生器34_PD及上拉信号产生 器34_PU，下拉信号产生器34_PD及上拉信号产生器34_PU可由(多个)传输闸组成。当缓冲反向器IVB_11的输出信号VOUTPB为高电位时，下拉信号PD可为电压VPM，下拉晶体管LVMN导通，而可将节点N5的电压下拉至电压VPL(或VPL’)；当缓冲反向器IVB_11的输出信号VOUTPB为低电位时，下拉信号PD可为电压VPL，下拉晶体管LVMN为断路。当缓冲反向器IVB_21的输出信号VOUTNB为低电位时，上拉信号PU可为电压VPL，上拉晶体管LVMP导通，而可将节点N6的电压上拉至电压VPM；当缓冲反向器IVB_21的输出信号VOUTNB为高电位时，下拉信号PD可为电压VPM，上拉晶体管LVMP为断路。另外，下拉信号产生器34_PD及上拉信号产生器34_PU还可接收反向器IVB_12的输出信号VOUTP及反向器IVB_22的输出信号VOUTN，以控制其传输闸的导通状态。简言之，下拉晶体管LVMN及上拉晶体管LVMP可用来消除缓冲反向器的漏电流。
除此之外，缓冲电路32_a还包括电容C1及电容C2。电容C1的一端耦接于P型晶体管MP1、MP3之间，电容C1的另一端耦接于反向器INV的输出端OUT；电容C2的一端耦接于P型晶体管MP2、MP4之间，电容C2的另一端耦接于反向器INV的输入端IN。电容C1及电容C2用来增强电平转换器30电位转换(由低电位翻转成为高电位或由高电位翻转成为低电位)时的翻转力道，缩短平转换器30的电位转换时间(Transition Interval)，以提高整体电路的系统性能。
另外，本申请的电平转换器不限于应用于特定电路系统，举例来说，本申 请的电平转换器可应用于图像传感器(Image Sensor)的行/列译码器(Row Decoder)，而不在此限。
综上所述，本申请实施例利用串迭而成的晶体管，分摊输出信号振幅的电压差；利用具有深N型井的N型晶体管，输出低电位为负电压的输出信号；利用输出电路，提供充分且稳定的输出电流，以顺利推动后端/级电路；利用缓冲电路阻确/阻挡瞬时电压变化对输出电路的影响；利用下/上拉晶体管，消除缓冲反向器的漏电流；利用耦接于反向器的电容，缩短电位翻转的瞬时时间。本申请实施例可输出大振幅的输出信号，而不需利用高压制程来生产其元件，具有降低生产成本的优点。
以上所述仅为本申请的部分实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种电平转换器，其特征在于，包括：
    第一P型晶体管；
    第二P型晶体管；
    第三P型晶体管，耦接于所述第二P型晶体管；
    第四P型晶体管，耦接于所述第一P型晶体管；
    第一N型晶体管，耦接于所述第三P型晶体管；
    第二N型晶体管，耦接于所述第四P型晶体管；
    第三N型晶体管，耦接于所述第一N型晶体管；
    第四N型晶体管，耦接于所述第二N型晶体管；以及
    反向器，耦接于所述第三N型晶体管与所述第四N型晶体管之间，所述反向器的输入端接收所述电平转换器的输入信号；
    其中，所述第一P型晶体管的源极耦接于所述第二P型晶体管的源极而形成第一节点，所述第三P型晶体管的栅极耦接于所述第四P型晶体管的栅极而形成第二节点，所述第一N型晶体管的栅极耦接与所述第二N型晶体管的栅极而形成第三节点，所述第三N型晶体管的源极耦接于所述第四N型晶体管的源极而形成第四节点。
  2. 如权利要求1所述的电平转换器，其特征在于，所述第一N型晶体管、所述第二N型晶体管、所述第三N型晶体管以及所述第四N型晶体管皆为具有深N型井的N型晶体管。
  3. 如权利要求1所述的电平转换器，其特征在于，所述第一节点接收第一电压，所述第二节点接收第二电压或第五电压，所述第三节点接收第三电压，所述第四节点接收第四电压，所述第四电压为负电压。
  4. 如权利要求3所述的电平转换器，其特征在于，第四电压与第一电压的电压差大于所述电平转换器的特定耐压。
  5. 如权利要求3所述的电平转换器，其特征在于，当所述第一电压大于第一特定值时，所述第三P型晶体管的栅极及所述第四P型晶体管的栅极接收所述第二电压；当所述第一电压小于第二特定值时，所述第三P型晶体管的栅极及所述第四P型晶体管的栅极接收所述第五电压；所述第五电压小于所述第二电压。
  6. 如权利要求3所述的电平转换器，其特征在于，还包括：
    第一电压供应单元，用来提供所述第二电压；
    第二电压供应单元，用来提供所述第五电压；以及
    切换单元，其一端耦接于第二节点，另一端耦接于所述第一电压供应单元，又一端耦接于所述第二电压供应单元；
    其中，当所述第一电压大于第一特定值时，所述切换单元导通所述第二节点与所述第一电压供应单元之间的链接；
    其中，当所述第一电压小于第二特定值时，所述切换单元导通所述第二节点与所述第二电压供应单元之间的链接。
  7. 如权利要求4所述的电平转换器，其特征在于，所述反向器输出第一高电位以及第一低电位，其中所述第一高电位为所述第三电压，所述第一低电位为第四电压。
  8. 如权利要求1所述的电平转换器，其特征在于，所述电平转换器的输出端位于所述第四P型晶体管与所述第二N型晶体管之间。
  9. 如权利要求1所述的电平转换器，其特征在于，还包括：
    输出电路，包括：
    第一P型输出晶体管，耦接于所述第一P型晶体管；
    第二P型输出晶体管，耦接于所述第一P型输出晶体管以及所述第二节点；
    第一N型输出晶体管，耦接于所述第二P型输出晶体管以及所述第三节点；以及
    第二N型输出晶体管，耦接于所述第一N型输出晶体管以及所述第四N型晶体管。
  10. 如权利要求9所述的电平转换器，其特征在于，还包括：
    第一缓冲电路，包括：
    第一缓冲反向器，其输入端耦接于所述第四P型晶体管，其输出端耦接于所述第一P型输出晶体管，其高直流偏压端耦接于所述第一节点，其低直流偏压端耦接于所述第二节点；以及
    第二缓冲反向器，其输入端耦接于所述第四N型晶体管，其输出端耦接于所述第二N型输出晶体管，其高直流偏压端耦接于所述第三节点，其低直流偏压端耦接于所述第四节点。
  11. 如权利要求10所述的电平转换器，其特征在于，所述第一缓冲电路还包括：
    下拉晶体管，耦接于所述第一缓冲反向器的输入端与所述第二节点之间，受控于下拉信号而为断路或导通；以及
    上拉晶体管，耦接于所述第二缓冲反向器的输入端与所述第三节点之间，受控于上拉信号而为断路或导通。
  12. 如权利要求11所述的电平转换器，其特征在于，所述下拉信号相关于所述第一缓冲反向器的第一输出信号，所述上拉信号相关于所述第二缓冲反向器的第二输出信号。
  13. 如权利要求11所述的电平转换器，其特征在于，所述第一缓冲电路还包括：
    多个第一辅助反向器，耦接与所述第一缓冲反向器的输出端与所述第一P型输出晶体管之间；以及
    多个第二辅助反向器，耦接与所述第二缓冲反向器的输出端与所述第二N型输出晶体管之间。
  14. 如权利要求13所述的电平转换器，其特征在于，所述下拉信号相关于所述第一缓冲反向器以及所述多个第一辅助反向器的多个输出信号，所述上拉 信号相关于所述第二缓冲反向器以及所述多个第二辅助反向器的多个输出信号。
  15. 如权利要求11所述的电平转换器，其特征在于，当第一缓冲反向器的输出信号为高电位时，所述下拉晶体管导通；当第二缓冲反向器的输出信号为高电位时，所述上拉晶体管导通。
  16. 如权利要求10所述的电平转换器，其特征在于，还包括：
    第二缓冲电路，耦接于所述第一P型晶体管、所述第三P型晶体管、所述第一N型晶体管以及所述第三N型晶体管；
    其中，所述第二缓冲电路与所述第一缓冲电路具有相同的电路结构。
  17. 如权利要求9所述的电平转换器，其特征在于，所述电平转换器的输出端位于所述第二P型输出晶体管与所述第一N型输出晶体管之间。
  18. 如权利要求1所述的电平转换器，其特征在于，还包括：
    一第一电容，其一端耦接于所述第一P型晶体管与所述第三P型晶体管之间，另一端耦接于所述反向器的输出端；以及
    一第二电容，其一端耦接于所述第二P型晶体管与所述第四P型晶体管之间，另一端耦接于所述反向器的输入端。
  19. 如权利要求1所述的电平转换器，其特征在于，应用于图像传感器的行/列译码器。
PCT/CN2017/097857 2017-08-17 2017-08-17 一种可输出正负电压的电平转换器 WO2019033340A1 (zh)

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EP17911395.6A EP3462617A4 (en) 2017-08-17 2017-08-17 LEVEL TRANSLATOR FOR DELIVERING POSITIVE AND NEGATIVE VOLTAGES
PCT/CN2017/097857 WO2019033340A1 (zh) 2017-08-17 2017-08-17 一种可输出正负电压的电平转换器
US16/197,255 US10924115B2 (en) 2017-08-17 2018-11-20 Level shifter capable of outputting positive and negative voltages

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11277121B1 (en) * 2021-01-28 2022-03-15 Nxp B.V. Level shifter
CN115913214B (zh) * 2023-01-09 2023-06-27 上海芯楷集成电路有限责任公司 正负高压电平转换电路
CN116827333B (zh) * 2023-08-28 2023-11-03 苏州锴威特半导体股份有限公司 一种电平位移电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005175752A (ja) * 2003-12-10 2005-06-30 Nec Yamagata Ltd レベルシフタ回路
CN1764069A (zh) * 2005-09-30 2006-04-26 威盛电子股份有限公司 电压电平转换器
CN102904565A (zh) * 2012-10-09 2013-01-30 长安大学 一种用于dc-dc驱动的超低静态电流的电平移位电路

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834948A (en) * 1995-09-21 1998-11-10 Matsushita Electric Industrial Co.,Ltd. Output circuit
US5969542A (en) * 1997-05-21 1999-10-19 Advanced Micro Devices, Inc. High speed gate oxide protected level shifter
JP3796034B2 (ja) * 1997-12-26 2006-07-12 株式会社ルネサステクノロジ レベル変換回路および半導体集積回路装置
US6166961A (en) * 1999-08-19 2000-12-26 Aplus Flash Technology, Inc. Approach to provide high external voltage for flash memory erase
JP2003298957A (ja) * 2002-03-29 2003-10-17 Sanyo Electric Co Ltd 昇圧回路及びこれを用いた撮像装置
US7215146B2 (en) * 2004-10-29 2007-05-08 Intel Corporation High speed buffered level-up shifters
US7193441B2 (en) * 2004-11-18 2007-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Single gate oxide I/O buffer with improved under-drive feature
JP5181737B2 (ja) * 2008-03-07 2013-04-10 ソニー株式会社 駆動回路、駆動方法、固体撮像装置および電子機器
CN101546999B (zh) * 2008-03-24 2011-05-11 瑞鼎科技股份有限公司 电平转换电路
KR101824027B1 (ko) * 2011-02-01 2018-01-31 삼성전자 주식회사 로우 디코더 및 비휘발성 메모리 장치
US8643425B2 (en) * 2011-09-19 2014-02-04 Freescale Semiconductor, Inc. Level shifter circuit
JP6012196B2 (ja) * 2012-02-17 2016-10-25 キヤノン株式会社 光電変換装置の駆動方法
CN103973103B (zh) * 2013-02-05 2016-12-28 迅宏科技股份有限公司 电压转换电路
KR101531887B1 (ko) * 2013-11-27 2015-06-26 주식회사 동부하이텍 네거티브 레벨 쉬프터
US9674470B2 (en) * 2014-04-11 2017-06-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, method for driving semiconductor device, and method for driving electronic device
US9361995B1 (en) * 2015-01-21 2016-06-07 Silicon Storage Technology, Inc. Flash memory system using complementary voltage supplies
KR20180063084A (ko) * 2015-09-30 2018-06-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 전자 기기
US9859894B1 (en) * 2017-01-26 2018-01-02 Elite Semiconductor Memory Technology Inc. Level shifting circuit and integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005175752A (ja) * 2003-12-10 2005-06-30 Nec Yamagata Ltd レベルシフタ回路
CN1764069A (zh) * 2005-09-30 2006-04-26 威盛电子股份有限公司 电压电平转换器
CN102904565A (zh) * 2012-10-09 2013-01-30 长安大学 一种用于dc-dc驱动的超低静态电流的电平移位电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3462617A4 *

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EP3462617A4 (en) 2019-08-07
CN109417606B (zh) 2021-10-26
EP3462617A1 (en) 2019-04-03
CN109417606A (zh) 2019-03-01
US10924115B2 (en) 2021-02-16

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