WO2019024917A1 - 一种半导体器件及实现自身静电放电保护的高压器件 - Google Patents
一种半导体器件及实现自身静电放电保护的高压器件 Download PDFInfo
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- WO2019024917A1 WO2019024917A1 PCT/CN2018/098511 CN2018098511W WO2019024917A1 WO 2019024917 A1 WO2019024917 A1 WO 2019024917A1 CN 2018098511 W CN2018098511 W CN 2018098511W WO 2019024917 A1 WO2019024917 A1 WO 2019024917A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000005468 ion implantation Methods 0.000 claims abstract description 66
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000001960 triggered effect Effects 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Definitions
- FIG. 1 is a schematic diagram of a conventional high voltage device for realizing self-electrostatic discharge protection
- first well a first well, a second well and a third well formed in the semiconductor substrate, the third well being located between the first well and the second well, the first well and the second well having a conductivity type, the third well has a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types;
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- General Physics & Mathematics (AREA)
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (20)
- 一种实现自身静电放电保护的高压器件,包括:半导体衬底;形成于所述半导体衬底中的第一N-阱、P-阱和第二N-阱;形成于所述第一N-阱中的第一N+离子注入区和第一隔离区;形成于所述P-阱中的第二N+离子注入区和紧贴所述第二N+离子注入区的P+离子注入区;形成于所述第二N-阱中的第三N+离子注入区;及形成于所述半导体衬底中的第二隔离区,所述第二隔离区覆盖部分所述第二N-阱和部分所述P-阱,其中,所述第二N+离子注入区、所述P+离子注入区和所述第三N+离子注入区构成NPN型BJT,通过所述BJT实现所述静电放电保护。
- 根据权利要求1所述的高压器件,其中,所述第二N+离子注入区作为所述BJT的集电极,所述P+离子注入区作为所述BJT的基极,所述第三N+离子注入区作为所述BJT的发射极。
- 根据权利要求1所述的高压器件,其中,所述第一N-阱和所述第二N-阱同时形成且深度相同。
- 根据权利要求1所述的高压器件,其中,通过调整所述第一N-阱和所述第二N-阱之间的间距的大小来实现不同电压的静电放电保护。
- 根据权利要求4所述的高压器件,其中,调整所述间距的大小时保证所述P-阱的下方形成有部分所述第二N-阱。
- 根据权利要求1所述的高压器件,其中,所述P-阱的深度小于所述第一N-阱的深度。
- 根据权利要求1所述的高压器件,其中,所述第一N+离子注入区作为所述高压器件的漏极,所述第二N+离子注入区作为所述高压器件的源极。
- 根据权利要求1所述的高压器件,其中,静电放电引发的电流从所述第一N+离子注入区经由所述第一N-阱和所述第二N-阱流向所述第三N+离子注入区。
- 根据权利要求8所述的高压器件,其中,通过调整所述第一N-阱和所述第二N-阱之间的间距的大小先触发所述BJT,完成对所述高压器件的静 电放电保护。
- 根据权利要求1-9中任一项所述的高压器件,其中,还包括形成在所述半导体衬底上的栅极,所述栅极覆盖部分所述P-阱、部分所述第一N-阱和部分所述第一隔离区。
- 一种半导体器件,包括:半导体衬底;形成于所述半导体衬底中的第一阱,第二阱及第三阱,所述第三阱位于所述第一阱和第二阱之间,所述第一阱和第二阱具有第一导电类型,所述第三阱具有第二导电类型,所述第一导电类型和第二导电类型为相反的导电类型;漏极区,形成于所述第一阱中,具有第一导电类型;源极区,形成于所述第三阱中,具有第一导电类型;第一掺杂区,形成于所述第二阱中,具有第一导电类型;及第二掺杂区,形成于所述第三阱中,具有第二导电类型;所述源极区、第二掺杂区及所述第一掺杂区构成双极结型晶体管。
- 根据权利要求11所述的半导体器件,其中,所述第二掺杂区位于所述源极区和所述第一掺杂区之间。
- 根据权利要求11所述的半导体器件,其中,所述第一导电类型为N型,所述第二导电类型为P型。
- 根据权利要求13所述的半导体器件,其中,所述第一阱是第一N-阱、所述第二阱是第二N-阱,所述第三阱是P-阱,所述漏极区是第一N+离子注入区,所述源极区是第二N+离子注入区,所述第一掺杂区是第三N+离子注入区,所述第二掺杂区是P+离子注入区;所述第二N+离子注入区作为所述BJT的集电极,所述P+离子注入区作为所述BJT的基极,所述第三N+离子注入区作为所述BJT的发射极。
- 根据权利要求11所述的半导体器件,其中,还包括形成于所述漏极区和源极区之间的第一隔离区。
- 根据权利要求11所述的半导体器件,其中,还包括形成于所述第一掺杂区和第二掺杂区之间的第二隔离区。
- 根据权利要求11所述的半导体器件,其中,所述第二阱的一部分位于所述第三阱的下方。
- 根据权利要求15所述的半导体器件,其中,还包括形成在所述半导 体衬底上的栅极,所述栅极覆盖部分所述第三阱、部分所述第一阱和部分所述第一隔离区。
- 根据权利要求11所述的半导体器件,其中,所述第三阱的深度小于所述第一阱的深度。
- 根据权利要求11所述的半导体器件,其中,静电放电引发的电流从所述漏极区经由所述第一阱和所述第二阱流向所述第一掺杂区。
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US16/644,462 US20200266188A1 (en) | 2017-08-03 | 2018-08-03 | Semiconductor device, and high voltage device with self-electrostatic discharge protection |
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CN201710656774.3 | 2017-08-03 | ||
CN201710656774.3A CN109390330B (zh) | 2017-08-03 | 2017-08-03 | 一种实现自身静电放电保护的高压器件 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1402358A (zh) * | 2001-08-22 | 2003-03-12 | 联华电子股份有限公司 | 高基底触发效应的静电放电保护元件结构及其应用电路 |
US20070194380A1 (en) * | 2000-05-15 | 2007-08-23 | Mototsugu Okushima | Method for fabricating an ESD protection apparatus for discharging electric charge in a depth direction |
CN102110686A (zh) * | 2010-12-17 | 2011-06-29 | 无锡华润上华半导体有限公司 | 一种基于scr的集成电路静电保护器件 |
CN103855152A (zh) * | 2012-12-07 | 2014-06-11 | 旺宏电子股份有限公司 | 用于高电压静电放电防护的双向双极型结晶体管 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US6444510B1 (en) * | 2001-12-03 | 2002-09-03 | Nano Silicon Pte. Ltd. | Low triggering N MOS transistor for ESD protection working under fully silicided process without silicide blocks |
TWI455274B (zh) * | 2011-11-09 | 2014-10-01 | Via Tech Inc | 靜電放電保護裝置 |
US9418981B2 (en) * | 2014-11-04 | 2016-08-16 | Macronix International Co., Ltd. | High-voltage electrostatic discharge device incorporating a metal-on-semiconductor and bipolar junction structure |
CN104465653B (zh) * | 2014-12-31 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | 高压静电保护结构 |
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- 2017-08-03 CN CN201710656774.3A patent/CN109390330B/zh active Active
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- 2018-08-03 US US16/644,462 patent/US20200266188A1/en not_active Abandoned
- 2018-08-03 WO PCT/CN2018/098511 patent/WO2019024917A1/zh active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070194380A1 (en) * | 2000-05-15 | 2007-08-23 | Mototsugu Okushima | Method for fabricating an ESD protection apparatus for discharging electric charge in a depth direction |
CN1402358A (zh) * | 2001-08-22 | 2003-03-12 | 联华电子股份有限公司 | 高基底触发效应的静电放电保护元件结构及其应用电路 |
CN102110686A (zh) * | 2010-12-17 | 2011-06-29 | 无锡华润上华半导体有限公司 | 一种基于scr的集成电路静电保护器件 |
CN103855152A (zh) * | 2012-12-07 | 2014-06-11 | 旺宏电子股份有限公司 | 用于高电压静电放电防护的双向双极型结晶体管 |
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CN109390330B (zh) | 2020-10-09 |
US20200266188A1 (en) | 2020-08-20 |
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