WO2019024378A1 - 阵列基板以及显示装置 - Google Patents

阵列基板以及显示装置 Download PDF

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Publication number
WO2019024378A1
WO2019024378A1 PCT/CN2017/115793 CN2017115793W WO2019024378A1 WO 2019024378 A1 WO2019024378 A1 WO 2019024378A1 CN 2017115793 W CN2017115793 W CN 2017115793W WO 2019024378 A1 WO2019024378 A1 WO 2019024378A1
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Prior art keywords
display domain
array substrate
domain region
trace
display
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Ceased
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PCT/CN2017/115793
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English (en)
French (fr)
Inventor
陈猷仁
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US16/634,018 priority Critical patent/US20200241340A1/en
Publication of WO2019024378A1 publication Critical patent/WO2019024378A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present application relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a display device.
  • the liquid crystal display panel is a key component of the liquid crystal display, and the liquid crystal display is currently the most widely used display on the market.
  • liquid crystal display panels are gradually moving toward large size or high resolution.
  • the resolution and resolution of the liquid crystal display panel cannot meet the needs of consumers.
  • the liquid crystal display panel includes a thin film transistor and a pixel electrode, and a drain metal of the thin film transistor is electrically connected through the metal pad and the pixel electrode.
  • the increase in the resolution of the liquid display panel will inevitably result in a reduction in the size of the pixel electrode, and the increase in the trace will significantly reduce the aperture ratio.
  • the pixel electrode becomes smaller, it is limited by the wiring space, and some pads protrude into the display area, which makes the electric field and the topography of the liquid crystal in the open area more complicated. Under the action of external force, the liquid crystal here may appear chaotically arranged. Phenomenon, when the screen is switched, the liquid crystals cannot be arranged in time and orderly. At this time, the image quality of the liquid crystal display panel may be problematic.
  • the embodiment of the present application provides an array substrate and a display device, which can improve the resolution of the high liquid crystal panel and improve the image quality.
  • An embodiment of the present application provides an array substrate, including a substrate, a switch assembly, a metal trace, a pixel electrode, and a plurality of pixel units.
  • the switch assembly is disposed on the substrate; wherein the switch assembly includes a plurality of transistors; the pixel electrode includes a plurality of strip-shaped trunks, and the trunk includes horizontal trunks and vertical trunks that are perpendicular to each other, a drain trace of the transistor is located under a horizontal stem that is closest to a drain of the transistor; each pixel unit includes a plurality of display domain regions, and a plurality of the display domain regions of each pixel unit are related to the horizontal stem or
  • the vertical trunk is symmetrical; the projection of the metal trace on the array substrate coincides with a vertical projection of the horizontal stem or the vertical stem on the array substrate.
  • the pixel unit includes a common electrode trace and a storage capacitor; and the common electrode traces of the pixel unit in the same row are connected to each other; the film layer where the metal trace is located and the common electrode An insulating layer is disposed between the film layers of the line; the common electrode trace and the metal trace are respectively a first electrode and a second electrode of the storage capacitor.
  • the common electrode trace includes a first common electrode trace, and a vertical projection of the first common electrode trace on the array substrate coincides with a vertical projection of the metal trace on the array substrate.
  • the common electrode trace further includes a second common electrode trace, and the second common electrode trace is located at at least one side of the pixel unit.
  • the common electrode trace is disposed in the same layer as the gate of the transistor.
  • the metal traces are disposed in the same layer as the drain of the transistor.
  • the insulating layer is a gate insulating layer of the transistor; a passivation layer is disposed between a film layer where the metal trace is located and a film layer where the pixel electrode is located; and the passivation layer is provided with a passivation layer a hole through which the metal trace is connected to the pixel electrode.
  • a vertical projection of the via hole in the array substrate coincides with a vertical projection of the horizontal stem and/or the vertical stem on the array substrate.
  • each of the pixel units includes a first display domain region, a second display domain region, a third display domain region, and a fourth display domain region; wherein the first display domain region and the second display The third display domain region and the fourth display domain region are disposed in the same direction; the first display domain region and the third display domain region are disposed in the same column; the second display domain region and the The fourth display domain region is arranged in the same column.
  • a gap between the vertical projection of the array substrate and the first display domain region and the second display domain region, the first display domain region, and the third display At least one of a gap between domain regions, a gap between the second display domain region and the fourth display domain region, a gap between the third display domain region and the fourth display domain region overlapping.
  • the metal traces are disposed in a gap between two adjacent display domain regions.
  • the transistor is a metal oxide transistor, a low temperature polysilicon transistor, or an amorphous silicon transistor.
  • the metal trace has a width ranging from 2 micrometers or more to less than or equal to 3 micrometers.
  • An embodiment of the present application provides a display device including a control circuit and a display panel, where The display panel includes the array substrate described above.
  • the pixel electrode size reduction of the drain metal of the transistor in the prior art through the metal pad and the pixel electrode connection can be avoided.
  • the phenomenon that the liquid crystal appears chaotically arranged in the display area does not need to occupy the area of the display area of the pixel unit, thereby increasing the aperture ratio of the pixel. Since the liquid crystal of the gap region of the adjacent two display domain regions in the pixel unit is affected by the electric field of the adjacent two display domain regions, a plurality of the display domain regions of each pixel unit in the embodiment of the present application are related to the horizontal stem or The vertical backbone is symmetrical, eliminating the effect of electric field inhomogeneities on the liquid crystal molecules.
  • 1 is a partial plan view of an exemplary array substrate
  • Figure 2 is an optical inspection diagram of the area indicated by the broken line frame 16 in Figure 1;
  • FIG. 3 is a partial plan view of an array substrate according to an embodiment of the present application.
  • FIG. 4 is an optical inspection diagram of a region indicated by a broken line frame 41 in FIG. 3;
  • FIG. 5 is a partial plan view of still another array substrate according to an embodiment of the present disclosure.
  • Figure 6 is a cross-sectional view taken along line AA' of Figure 5;
  • FIG. 7 is a partial plan view of still another array substrate according to an embodiment of the present application.
  • FIG. 8 is a partial plan view of still another array substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a partial plan view of still another array substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a partial top view of still another array substrate according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 1 is a partial plan view of an exemplary array substrate, see FIG. 1, insulated cross-over data lines 11 And the scan line 12 defines a plurality of pixel units 13.
  • the transistor 14 is connected to the pixel electrode 131 in the pixel unit 13 through the pad 15.
  • the pad 15 extends into the display area of the pixel unit 13, which on the one hand reduces the aperture ratio of the pixel unit 13, and on the other hand, the pad 15 extending into the pixel unit 13 affects the electric field of the surrounding display area.
  • 2 is an optical inspection diagram of a region indicated by a broken line frame 16 in FIG. Referring to FIG.
  • the area where the pad 15 is located is opaque, the aperture ratio of the pixel unit is lowered, and the liquid crystal around the pad 15 is disorderly arranged, resulting in poor display, and the liquid crystal cannot be arranged in time and in sequence when the screen is switched.
  • the phenomenon of afterimage, 52 is the area where the common electrode trace is opaque.
  • FIG. 3 is a partial plan view of an array substrate according to an embodiment of the present disclosure.
  • the array substrate provided by the embodiment of the present application includes: a substrate, the substrate is not shown in the figure; and the switch component and the switch component are disposed on On the substrate, the switch assembly includes a plurality of transistors 20; pixel electrodes 30 and metal traces 40.
  • the pixel electrode 30 includes a plurality of strip-shaped trunks 31.
  • the trunk includes a horizontal trunk 310 and a vertical trunk 311 that are perpendicular to each other.
  • the drain trace 21 of the transistor 20 is located at a horizontal stem 310 that is closest to the transistor 20;
  • the drain 21 is connected to the pixel electrode 30 through the drain trace 21 (the drain trace and the drain are denoted by the same reference numeral 21).
  • the array substrate includes a plurality of pixel units 50 each including a plurality of display domain regions 51; a plurality of display domain regions 51 of the pixel cells 50 are symmetric about the horizontal stem 310 or the vertical stem 311.
  • the vertical projection of the metal traces 40 on the array substrate 10 coincides with the vertical projection of the horizontal stem 310 or the vertical stem 311 on the array substrate.
  • the drain trace 21 of the transistor 20 is disposed under the horizontal stem 310 which is closest to the transistor 20, so that the size of the pixel electrode 30 caused by the connection of the drain metal of the transistor 20 through the metal pad and the pixel electrode 30 can be avoided.
  • the pad protruding into the display area causes a disordered arrangement of the liquid crystal. There is no need to additionally occupy the area of the pixel unit display area, which increases the aperture ratio of the pixel.
  • the gap regions of the adjacent two display domain regions in the pixel unit 50 exhibit a dark state, and the present application
  • the metal trace 40 connecting the drain 21 of the transistor 20 and the pixel electrode 30 is disposed in the gap between two adjacent display domain regions, so that the metal trace arrangement does not need to additionally occupy the area of the display region of the pixel unit 50, thereby improving the opening of the pixel. rate.
  • a plurality of the display domain regions 51 of each pixel unit in the embodiment of the present application are symmetric with respect to the horizontal stem 310 or the vertical stem 311, thereby eliminating the influence of electric field unevenness on liquid crystal molecules.
  • FIG. 4 is an optical inspection diagram of a region indicated by a broken line frame 41 in FIG. 2 is an optical inspection diagram of a region indicated by a broken line frame 16 in FIG. Comparing Figure 2 with Figure 4,
  • the display screen of FIG. 4 shows that the area of the light is larger than the area of the light emitted by the display screen in FIG. 2, and the problem that the pixel element aperture ratio is lowered due to the connection of the drain and the pixel electrode is avoided.
  • the display area of the entire pixel unit does not have picture blur and image sticking phenomenon, because the vertical projection of the metal trace 40 on the array substrate 10 is located in the gap of the adjacent two display domain regions 51 on the array substrate 10.
  • a plurality of the display domain regions 51 of each pixel unit in the embodiment of the present application are symmetric about the horizontal stem 310 or the vertical stem 311, thereby eliminating the influence of electric field unevenness on the liquid crystal molecules, and thus As shown in FIG. 2, the pad 15 causes a change in the surrounding electric field to cause irregularity of the liquid crystal arrangement, and only the area where the common electrode trace 52 is located is opaque.
  • the transistor 20 in the embodiment of the present application may be a metal oxide transistor, a low temperature polysilicon transistor, an amorphous silicon transistor, etc., and the type of the transistor is not limited in the embodiment of the present application.
  • the gate of the transistor 20 is connected to the scan line 12 (the gate of the transistor 20 in FIG. 3 is a part of the scan line 12) for receiving a scan signal, and the source 23 of the transistor 20 is connected to the data line 11 for receiving data. signal.
  • the drain 21 of the transistor is connected to the pixel electrode 30 through a metal trace 40.
  • the width of the metal trace 40 may be set to be greater than or equal to 2 micrometers and less than or equal to 3 micrometers.
  • FIG. 3 divides the pixel unit 50 into four display domain regions 51 in which metal traces 40 are disposed for all gaps in the display domain region 51.
  • the metal trace 40 is disposed in the same layer as the drain 21 of the transistor 20.
  • the material of the metal trace 40 can be selected from the same material as the drain selection of the transistor, that is, the metal trace 40 and the drain 21 of the transistor 20 can be patterned using the same material in the same process, thereby simplifying the fabrication process and reducing production. cost.
  • FIG. 5 is a partial plan view of still another array substrate according to an embodiment of the present application; and FIG. 6 is a cross-sectional view taken along line AA' of FIG. 5.
  • the pixel unit 50 in the array substrate provided by the embodiment of the present application further includes a common electrode trace 52 and a storage capacitor (not shown);
  • the common electrode traces 52 of the pixel unit 50 are connected to each other.
  • the common electrode traces 52 are insulated from the metal traces 40, and an insulating layer 24 is disposed between the common electrode traces 52 and the metal traces 40.
  • the common electrode traces 52 and the metal traces 40 are respectively stored. a first electrode and a second electrode of the capacitor.
  • a passivation layer 25 is disposed between the metal trace 40 and the pixel electrode 30, and the passivation layer 25 is provided with a via hole 26, and the metal trace 40 is connected to the pixel electrode 30 through the via hole 26.
  • the vertical projection of the via hole 26 in the vertical projection of the array substrate is at least perpendicular to the gap between the two adjacent display domain regions 51 on the array substrate The overlap, that is, the vertical projection of the via 26 on the array substrate coincides with the vertical projection of the horizontal stem 310 or the vertical stem 311 on the array substrate.
  • the storage capacitor helps maintain the liquid crystal capacitor potential in the liquid crystal display panel, prolongs the display time of the display panel, and enhances the stability of the display effect of the display panel.
  • the size of the storage capacitor can be changed by adjusting the distance between the common electrode trace 52 and the metal trace 40.
  • the distance between the common electrode trace 52 and the metal trace 40 in the film position of the common electrode trace 52 and the metal trace 40 can be set according to the requirements of the actual product on the size of the storage capacitor.
  • the insulating layer 24 between the film layer where the metal trace 40 is located and the film layer where the common electrode trace 52 is located may be the gate insulating layer of the transistor 20 .
  • the common electrode trace is used as the first electrode of the storage capacitor
  • the pixel electrode is used as the second electrode of the storage capacitor
  • the transistor layer is disposed between the film layer where the pixel electrode is located and the film layer of the common electrode trace.
  • a gate insulating layer and a passivation layer that is, a gate insulating layer and a passivation layer are disposed between the first electrode and the second electrode of the storage capacitor.
  • the array substrate provided by the embodiment of the present application, the first electrode of the storage capacitor and the first The two electrodes may be provided with only the gate insulating layer of the transistor. Therefore, the present application can increase the storage capacitance of the array substrate and enhance the stability of the display effect of the display panel.
  • the common electrode trace 52 includes a first common electrode trace 521, and the vertical projection of the first common electrode trace 521 on the array substrate coincides with the vertical projection of the metal trace 40 on the array substrate.
  • the common electrode trace 52 further includes a second common electrode trace 522 located at at least one side of the pixel unit 50.
  • the common electrode trace 52 is disposed in the same layer as the gate of the transistor 20.
  • the common electrode traces are formed by pattern etching while forming the gate of the transistor 20, which simplifies the fabrication process and reduces the production cost.
  • each pixel unit includes a first display domain region 511, a second display domain region 512, a third display domain region 513, and a fourth display domain region 514 arranged in a 2 ⁇ 2 matrix; wherein, the first display domain The region 511 and the second display domain region 512 are disposed in the same direction, and the third display domain region 513 and the fourth display domain region 514 are disposed in the same direction; the first display domain region 511 and the third display domain region 513 are disposed in the same column; the second display domain region 512 is disposed.
  • the domain regions 514 are arranged in the same column.
  • the embodiment of the present application may set the through hole 26 between the vertical projection of the array substrate and the gap between the first display domain region 511 and the second display domain region 512, between the first display domain region 511 and the third display domain region 513.
  • the gap, the gap between the second display domain region 512 and the fourth display domain region 514, the gap between the third display domain region 513 and the fourth display domain region 514 overlap to increase the relative area of the two electrodes of the storage capacitor .
  • the gap between the first display domain region 511 and the second display domain region 512, the first display domain region 511, and the first At least one of the gap between the three display domain regions 513, the gap between the second display domain region 512 and the fourth display domain region 514, and the gap between the third display domain region 513 and the fourth display domain region 514 is within the vertical projection of the array substrate, the vertical projection of the via 26 in the vertical projection of the array substrate 10 and the gap between the first display domain region 511 and the second display domain region 512, the first display domain region 511 and the third display domain region 513
  • the gap between the gap, the gap between the second display domain region 512 and the fourth display domain region 514, and the gap between the third display domain region 513 and the fourth display domain region 514 may overlap.
  • the vertical projection of the metal trace 40 between the first display domain region 511 and the second display domain region 512 in the vertical projection of the array substrate is within the vertical projection of the array substrate.
  • the via hole overlaps the vertical projection of the array substrate with the gap between the first display domain region 511 and the second display domain region 512.
  • the vertical projection of the metal trace 40 on the array substrate is located between the first display domain region 511 and the second display domain region 512, the first display domain region 511 and the third display domain region.
  • the gap between 513 and the gap between the second display domain region 512 and the fourth display domain region 514 are within the vertical projection of the array substrate.
  • the vertical projection of the via hole (the area indicated by the broken line frame 53 in the figure) overlaps only the gap between the first display domain region 511 and the second display domain region 512 at the vertical projection of the array substrate.
  • the vertical projection of the metal trace 40 on the array substrate is located between the first display domain region 511 and the second display domain region 512, the first display domain region 511 and the third display domain region.
  • the gap between 513 and the gap between the second display domain region 512 and the fourth display domain region 514 are within the vertical projection of the array substrate. It is also possible to provide a gap between the vertical projection of the array substrate and the first display domain region 511 and the third display domain region 513 and the second display domain region 512 and the fourth display in the through hole (the region indicated by the broken line frame 54 in the figure).
  • the gaps between the domain regions 514 overlap.
  • the vertical projection of the metal trace 40 on the array substrate is located between the first display domain region 511 and the second display domain region 512, the first display domain region 511 and the third.
  • the gap between the display domain regions 513 and the gap between the second display domain region 512 and the fourth display domain region 514 are within the vertical projection of the array substrate. It is also possible to provide a gap between the vertical projection of the array substrate and the first display domain region 511 and the second display domain region 512, and the first display domain region 511 in the vertical projection of the via hole (the area indicated by the broken line frame 53 and the broken line frame 54 in the figure).
  • the gap between the third display domain region 513 and the gap between the second display domain region 512 and the fourth display domain region 514 overlap.
  • the size of the storage capacitor can be controlled by adjusting the overlap area of the gap between the metal trace and each display domain and the gap between the via and each display domain.
  • the increase of the storage capacitor contributes to the liquid crystal capacitor potential.
  • the hold of the compensation compensates for the parasitic capacitance.
  • FIG. 11 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • the display panel includes the array substrate 10 in the above embodiment.
  • the display panel provided in the embodiment of the present application includes the array substrate in the above embodiment. Therefore, the display panel provided in the embodiment of the present application also has the beneficial effects described in the foregoing embodiments, and details are not described herein again.
  • the display panel can be, for example, an LCD display panel, an OLED display panel, a QLED display panel, a curved display panel, or other display panel.
  • the display device When the display device is an LCD display device, the display device may be a TN, OCB, VA type, or curved liquid crystal display device, but is not limited thereto.

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Abstract

一种阵列基板以及一种显示装置，包括：一基板；开关组件，开关组件设置于基板上；其中，开关组件包括多个晶体管（20）；金属走线（40）；像素电极（30），像素电极（30）包括多条条状的主干（31），主干（31）包括相互垂直的水平主干（310）与竖直主干（311），晶体管（20）的漏极走线（21）位于离晶体管（20）距离最近的水平主干（310）下；多个像素单元（50），每个像素单元（50）包括多个显示畴区（51），每个像素单元（50）的多个显示畴区（51）关于水平主干（310）或者竖直主干（311）对称；金属走线（40）在阵列基板的投影，与水平主干（310）或者竖直主干（311）在阵列基板的垂直投影重合。

Description

阵列基板以及显示装置 技术领域
本申请涉及液晶显示屏技术领域，尤其涉及一种阵列基板以及一种显示装置。
背景技术
液晶显示面板是液晶显示器的关键部件，液晶显示器目前是市场上运用最为广泛的显示器。
目前液晶显示面板逐渐朝着大尺寸或高解析度的方向发展。特别是液晶显示面板的解析度、分辨率，已经不能满足消费者的需求。
液晶显示面板包括薄膜晶体管和像素电极，薄膜晶体管的漏极金属通过金属焊盘和像素电极电连接。其中液显示面板的解析度的提升必定会造成像素电极尺寸的缩小，同时走线的增加会明显降低开口率。而且像素电极变小之后，受限于布线空间，会有一些焊盘伸入显示区，会使得开口区液晶所处电场和地形更加复杂，在外力作用下，这里的液晶会出现混乱排布的现象，画面切换时液晶不能及时有序排列，此时液晶显示面板的图像质量就会出现问题。
发明内容
本申请实施例提供了一种阵列基板以及一种显示装置，可以改善高液晶面板的解析度，提高图像质量。
本申请实施例提供了一种阵列基板，包括基板、开关组件、金属走线、像素电极以及多个像素单元。所述开关组件设置于所述基板上；其中，所述开关组件包括多个晶体管；所述像素电极包括多条条状的主干，所述主干包括相互垂直的水平主干与竖直主干，所述晶体管的漏极走线位于离所述晶体管的漏极距离最近的水平主干下；每个像素单元包括多个显示畴区，每个像素单元的多个所述显示畴区关于所述水平主干或者所述竖直主干对称；所述金属走线在所述阵列基板的投影，与所述水平主干或者所述竖直主干在所述阵列基板的垂直投影重合。
可选地，所述像素单元包括公共电极走线和存储电容；且位于同一行的所述像素单元的所述公共电极走线相互连接；所述金属走线所在膜层与所述公共电极走线所在膜层之间设置有绝缘层；所述公共电极走线和所述金属走线分别为所述存储电容的第一电极和第二电极。
可选地，所述公共电极走线包括第一公共电极走线，所述第一公共电极走线在所述阵列基板的垂直投影与所述金属走线在所述阵列基板的垂直投影重合。
可选地，所述公共电极走线还包括第二公共电极走线，所述第二公共电极走线位于所述像素单元的至少一个侧边处。
可选地，所述公共电极走线与所述晶体管的栅极同层设置。
可选地，所述金属走线与所述晶体管的漏极同层设置。
可选地，所述绝缘层为所述晶体管的栅极绝缘层；所述金属走线所在膜层与所述像素电极所在膜层之间设置有钝化层；所述钝化层设置有通孔，所述金属走线通过所述通孔与所述像素电极连接。
可选地，所述通孔在所述阵列基板的垂直投影，与所述水平主干和/或所述竖直主干在所述阵列基板的垂直投影重合。
可选地，每个所述像素单元包括第一显示畴区、第二显示畴区、第三显示畴区以及第四显示畴区；其中，所述第一显示畴区和所述第二显示畴区同行设置，所述第三显示畴区和所述第四显示畴区同行设置；所述第一显示畴区和所述第三显示畴区同列设置；所述第二显示畴区和所述第四显示畴区同列设置。
可选地，所述通孔在所述阵列基板的垂直投影与所述第一显示畴区和所述第二显示畴区之间的间隙、所述第一显示畴区和所述第三显示畴区之间的间隙、所述第二显示畴区和所述第四显示畴区之间的间隙、所述第三显示畴区和所述第四显示畴区之间的间隙中的至少一个重叠。
可选地，所述金属走线设置在相邻两显示畴区之间的间隙内。
可选地，所述晶体管为金属氧化物晶体管、低温多晶硅晶体管、或非晶硅晶体管。
可选地，所述金属走线的宽度范围大于等于2微米小于等于3微米。
本申请实施例提供一种显示装置，包括控制电路以及显示面板，其中， 所述显示面板包括上述内容所述的阵列基板。
本申请实施例通过设置晶体管的漏极走线位于离晶体管距离最近的水平主干下，可以避免现有技术中晶体管的漏极金属通过金属焊盘和像素电极连接导致的像素电极尺寸缩小、焊盘伸入显示区引起液晶出现混乱排布的现象，无需额外占用像素单元显示区的面积，提高了像素的开口率。由于像素单元中相邻两显示畴区的间隙区域的液晶受到相邻两个显示畴区的电场作用，本申请实施例中每个像素单元的多个所述显示畴区关于所述水平主干或者所述竖直主干对称，消除了电场不均匀对于液晶分子的影响。
附图说明
通过阅读参照以下附图说明所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将变得更明显。
图1为范例的阵列基板的局部俯视图；
图2为图1中虚线框16所示区域的光学检测图；
图3为本申请实施例提供的一种阵列基板的局部俯视图；
图4为图3中虚线框41所示区域的光学检测图；
图5为本申请实施例提供的又一种阵列基板的局部俯视图；
图6为沿图5中的AA’方向剖面图；
图7为本申请实施例提供的又一种阵列基板的局部俯视图；
图8为本申请实施例提供的又一种阵列基板的局部俯视图；
图9为本申请实施例提供的又一种阵列基板的局部俯视图；
图10为本申请实施例提供的又一种阵列基板的局部俯视图；以及
图11为本申请实施例提供的一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
图1为范例的阵列基板的局部俯视图，参见图1，绝缘交叉的数据线11 和扫描线12限定出多个像素单元13。晶体管14与像素单元13中的像素电极131之间通过焊盘15进行连接。焊盘15伸进像素单元13的显示区中，一方面会减小像素单元13的开口率，另一方面伸进像素单元13的焊盘15会影响周围显示区的电场。图2为图1中虚线框16所示区域的光学检测图。参见图2，可见焊盘15所在区域不透光，降低了像素单元的开口率，并且焊盘15周围液晶出现混乱排布的现象，造成显示不良，画面切换时液晶不能及时有序排列，出现残影现象，52为公共电极走线所在区域不透光。
图3为本申请实施例提供的一种阵列基板的局部俯视图，参考图3，本申请实施例提供的阵列基板包括：一基板，基板在图中并未示出；开关组件，开关组件设置于基板上，开关组件包括多个晶体管20；像素电极30以及金属走线40。其中，像素电极30包括多条条状的主干31，主干包括相互垂直的水平主干310与竖直主干311，晶体管20的漏极走线21位于离晶体管20距离最近的水平主干310下；晶体管20的漏极21通过漏极走线21与像素电极30连接(漏极走线和漏极用同一标号21)。阵列基板包括多个像素单元50，每个像素单元50包括多个显示畴区51；像素单元50的多个显示畴区51关于所述水平主干310或者所述竖直主干311对称。金属走线40在阵列基板10的垂直投影，与水平主干310或者竖直主干311在所述阵列基板的垂直投影重合。
本申请实施例通过设置晶体管20的漏极走线21位于离晶体管20距离最近的水平主干310下，因此可以避免晶体管20的漏极金属通过金属焊盘和像素电极30连接导致的像素电极30尺寸缩小、焊盘伸入显示区引起液晶出现混乱排布的现象。无需额外占用像素单元显示区的面积，提高了像素的开口率。由于像素单元50中相邻两显示畴区51的间隙区域的液晶受到相邻两个显示畴区51的电场作用，因此像素单元50中相邻两显示畴区的间隙区域呈现暗态，本申请将连接晶体管20的漏极21与像素电极30的金属走线40设置在相邻两显示畴区的间隙内，因此金属走线设置无需额外占用像素单元50显示区的面积，提高了像素的开口率。本申请实施例中每个像素单元的多个所述显示畴区51关于所述水平主干310或者所述竖直主干311对称，消除了电场不均匀对于液晶分子的影响。图4为图3中虚线框41所示区域的光学检测图。图2为图1中虚线框16所示区域的光学检测图。对比图2和图4可知， 图4的显示画面显示出光的面积大于图2中显示画面出光的面积，避免了漏极和像素电极的连接导致像素单元开口率降低的问题。此外，参见图4，整个像素单元的显示区并未出现画面模糊以及残影现象，由于设置金属走线40在阵列基板10的垂直投影位于相邻两显示畴区51的间隙在阵列基板10的垂直投影内，本申请实施例中每个像素单元的多个所述显示畴区51关于所述水平主干310或者所述竖直主干311对称，消除了电场不均匀对于液晶分子的影响，因此不会出现如图2中焊盘15引起周围电场变化导致液晶排布不规律的问题，仅存在公共电极走线52所在区域不透光。
需要说明的是，本申请实施例中的晶体管20可以为金属氧化物晶体管、低温多晶硅晶体管以及非晶硅晶体管等，本申请实施例对晶体管的类型不做限定。其中，晶体管20的栅极与扫描线12相连(图3中晶体管20的栅极为扫描线12的一部分)，用于接收扫描信号，晶体管20的源极23和数据线11相连，用于接收数据信号。晶体管的漏极21通过金属走线40与像素电极30相连。可选地，金属走线40的宽度范围可以设置为大于等于2微米小于等于3微米。示例性地，图3将像素单元50划分为4个显示畴区51，在显示畴区51所有间隙均设置了金属走线40。
可选地，金属走线40与晶体管20的漏极21同层设置。金属走线40的材料可以选择与晶体管的漏极选择同样的材料，即金属走线40和晶体管20的漏极21可以在同一工艺中使用同种材料图案化形成，从而简化制作工艺，降低生产成本。
图5为本申请实施例提供的又一种阵列基板的局部俯视图；图6为沿图5中的AA’方向剖面图。
结合图5和图6，在上述实施例的基础上，本申请实施例提供的阵列基板中的像素单元50还包括公共电极走线52和存储电容(图中未示出)；且位于同一行的像素单元50的公共电极走线52相互连接。参见图6，公共电极走线52与金属走线40异层绝缘设置，公共电极走线52与金属走线40之间设置有绝缘层24，公共电极走线52和金属走线40分别为存储电容的第一电极和第二电极。金属走线40与像素电极30之间设置有钝化层25，钝化层25设置有通孔26，金属走线40通过通孔26与像素电极30连接。通孔26在阵列基板的垂直投影至少与两个相邻的显示畴区51的间隙在阵列基板的垂直投影 重叠，即通孔26在阵列基板的垂直投影与水平主干310或者竖直主干311在阵列基板的垂直投影重合。
需要说明的是，存储电容有助于保持液晶显示面板中液晶电容电位的保持，延长显示面板显示的时间，增强显示面板显示效果的稳定性。本申请实施例中可以通过调节公共电极走线52和金属走线40之间的距离改变存储电容的大小。例如可以根据实际产品对存储电容大小的要求，设置公共电极走线52和金属走线40所在膜层位置控制公共电极走线52和金属走线40之间的距离。
可选地，参见图6，金属走线40所在膜层与公共电极走线52所在膜层之间的绝缘层24可以是晶体管20的栅极绝缘层。相比现有技术中使用公共电极走线作为存储电容的第一电极，使用像素电极作为存储电容的第二电极，像素电极所在膜层与公共电极走线所在膜层之间依次设置有晶体管的栅极绝缘层和钝化层，即存储电容的第一电极和第二电极之间设置有栅极绝缘层和钝化层，本申请实施例提供的阵列基板，存储电容的第一电极和第二电极可以仅设置有晶体管的栅极绝缘层，因此本申请可以增大阵列基板的存储电容，增强显示面板显示效果的稳定性。
可选地，参见图5，公共电极走线52包括第一公共电极走线521，第一公共电极走线521在阵列基板的垂直投影与金属走线40在阵列基板的垂直投影重合。
可选地，公共电极走线52还包括第二公共电极走线522，第二公共电极走线522位于像素单元50的至少一个侧边处。
可选地，公共电极走线52与晶体管20的栅极同层设置。在形成晶体管20栅极的同时，通过图案化刻蚀形成公共电极走线，简化了制作工艺，降低了生产成本。
需要说明的是图5示例性的设置每个像素单元包括4个显示畴区，在其他实施方式中，可以根据实际产品的设计需求调整显示畴区的数量。参见图5，每个像素单元包括呈2×2矩阵排列的第一显示畴区511、第二显示畴区512、第三显示畴区513以及第四显示畴区514；其中，第一显示畴区511和第二显示畴区512同行设置，第三显示畴区513和第四显示畴区514同行设置；第一显示畴区511和第三显示畴区513同列设置；第二显示畴区512和第四显 示畴区514同列设置。本申请实施例可以设置通孔26在阵列基板的垂直投影与第一显示畴区511和第二显示畴区512之间的间隙、第一显示畴区511和第三显示畴区513之间的间隙、第二显示畴区512和第四显示畴区514之间的间隙、第三显示畴区513和第四显示畴区514之间的间隙重叠，以增加存储电容的两个电极的相对面积。
需要说明的是，本申请实施例中只要金属走线40在阵列基板的垂直投影还可以位于第一显示畴区511和第二显示畴区512之间的间隙、第一显示畴区511和第三显示畴区513之间的间隙、第二显示畴区512和第四显示畴区514之间的间隙、第三显示畴区513和第四显示畴区514之间的间隙中的至少一个在阵列基板的垂直投影内，通孔26在阵列基板10的垂直投影与第一显示畴区511和第二显示畴区512之间的间隙、第一显示畴区511和第三显示畴区513之间的间隙、第二显示畴区512和第四显示畴区514之间的间隙、第三显示畴区513和第四显示畴区514之间的间隙中的至少一个重叠即可。
参见图7示出的阵列基板，金属走线40在阵列基板的垂直投影位于第一显示畴区511和第二显示畴区512之间的间隙在阵列基板的垂直投影内。通孔(图中虚线框53所示区域)在阵列基板的垂直投影与第一显示畴区511和第二显示畴区512之间的间隙重叠。
参见图8示出的阵列基板，金属走线40在阵列基板的垂直投影位于第一显示畴区511和第二显示畴区512之间的间隙、第一显示畴区511和第三显示畴区513之间的间隙以及第二显示畴区512和第四显示畴区514之间的间隙在阵列基板的垂直投影内。通孔(图中虚线框53所示区域)在阵列基板的垂直投影仅与第一显示畴区511和第二显示畴区512之间的间隙重叠。
参见图9示出的阵列基板，金属走线40在阵列基板的垂直投影位于第一显示畴区511和第二显示畴区512之间的间隙、第一显示畴区511和第三显示畴区513之间的间隙以及第二显示畴区512和第四显示畴区514之间的间隙在阵列基板的垂直投影内。还可以设置通孔(图中虚线框54所示区域)在阵列基板的垂直投影与第一显示畴区511和第三显示畴区513之间的间隙以及第二显示畴区512和第四显示畴区514之间的间隙重叠。
参见图10示出的阵列基板，金属走线40在阵列基板的垂直投影位于第一显示畴区511和第二显示畴区512之间的间隙、第一显示畴区511和第三 显示畴区513之间的间隙以及第二显示畴区512和第四显示畴区514之间的间隙在阵列基板的垂直投影内。还可以设置通孔(图中虚线框53和虚线框54所示区域)在阵列基板的垂直投影与第一显示畴区511和第二显示畴区512之间的间隙、第一显示畴区511和第三显示畴区513之间的间隙以及第二显示畴区512和第四显示畴区514之间的间隙均重叠。通过调整金属走线与各显示畴区之间的间隙交叠面积以及通孔与各显示畴区之间的间隙交叠面积，可以控制存储电容的大小，存储电容增大有助于液晶电容电位的保持，对补偿寄生电容进行补偿。
本申请实施例还提供一种显示装置，包括：控制电路；以及显示面板，其中，显示面板包括上述技术方案中涉及到的阵列基板。图11为本申请实施例提供的一种显示面板的结构示意图。
如图11所示，显示面板包括上述实施例中的阵列基板10。本申请实施例提供的显示面板包括上述实施例中的阵列基板，因此本申请实施例提供的显示面板也具有上述实施例中所描述的有益效果，此处不再赘述。
其中，显示面板可例如为LCD显示面板、OLED显示面板、QLED显示面板、曲面显示面板或其他显示面板。
在该显示装置为LCD显示装置时，该显示装置可以为TN、OCB、VA型、曲面型液晶显示装置，但并不限于此。
注意，上述仅为本申请的较佳实施例及所运用技术原理。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整、相互结合和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申请构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附的权利要求范围决定。

Claims (18)

  1. 一种阵列基板，包括：
    一基板；
    开关组件，所述开关组件设置于所述基板上；
    其中，所述开关组件包括多个晶体管；
    金属走线；
    像素电极，所述像素电极包括多条条状的主干，所述主干包括相互垂直的水平主干与竖直主干，所述晶体管的漏极走线位于离所述晶体管距离最近的水平主干下；以及
    多个像素单元，每个像素单元包括多个显示畴区，每个像素单元的多个所述显示畴区关于所述水平主干或者所述竖直主干对称；
    所述金属走线在所述阵列基板的投影，与所述水平主干或者所述竖直主干在所述阵列基板的垂直投影重合。
  2. 根据权利要求1所述的阵列基板，还包括：
    所述像素单元包括公共电极走线和存储电容；且位于同一行的所述像素单元的所述公共电极走线相互连接；
    所述金属走线所在膜层与所述公共电极走线所在膜层之间设置有绝缘层；所述公共电极走线和所述金属走线分别为所述存储电容的第一电极和第二电极；
    所述公共电极走线包括第一公共电极走线，所述第一公共电极走线在所述阵列基板的垂直投影与所述金属走线在所述阵列基板的垂直投影重合。
  3. 根据权利要求2所述的阵列基板，其中所述公共电极走线还包括第二公共电极走线，所述第二公共电极走线位于所述像素单元的至少一个侧边处。
  4. 根据权利要求2所述的阵列基板，其中所述公共电极走线与所述晶体管的栅极同层设置。
  5. 根据权利要求2所述的阵列基板，其中所述金属走线与所述晶体管的漏极同层设置。
  6. 根据权利要求2所述的阵列基板，其中所述绝缘层为所述晶体管的栅极绝缘层；
    所述金属走线所在膜层与所述像素电极所在膜层之间设置有钝化层；
    所述钝化层设置有通孔，所述金属走线通过所述通孔与所述像素电极连接。
  7. 根据权利要求6所述的阵列基板，其中所述通孔在所述阵列基板的垂直投影，与所述水平主干和/或所述竖直主干在所述阵列基板的垂直投影重合。
  8. 根据权利要求6所述的阵列基板，其中每个所述像素单元包括第一显示畴区、第二显示畴区、第三显示畴区以及第四显示畴区；其中，所述第一显示畴区和所述第二显示畴区同行设置，所述第三显示畴区和所述第四显示畴区同行设置；所述第一显示畴区和所述第三显示畴区同列设置；所述第二显示畴区和所述第四显示畴区同列设置。
  9. 根据权利要求8所述的阵列基板，其中所述通孔在所述阵列基板的垂直投影与所述第一显示畴区和所述第二显示畴区之间的间隙、所述第一显示畴区和所述第三显示畴区之间的间隙、所述第二显示畴区和所述第四显示畴区之间的间隙、所述第三显示畴区和所述第四显示畴区之间的间隙中的至少一个重叠。
  10. 根据权利要求8所述的阵列基板，其中所述金属走线设置在相邻两显示畴区之间的间隙内。
  11. 根据权利要求1所述的阵列基板，其中所述晶体管为金属氧化物晶体管、低温多晶硅晶体管、或非晶硅晶体管。
  12. 根据权利要求1所述的阵列基板，其中所述金属走线的宽度范围大于等于2微米小于等于3微米。
  13. 一种显示装置，包括：
    控制电路；以及
    显示面板，所述显示面板包括如权利要求1所述的阵列基板。
  14. 一种阵列基板，包括：
    一基板；
    开关组件，所述开关组件设置于所述基板上；
    其中，所述开关组件包括多个晶体管；
    金属走线；
    像素电极，所述像素电极包括多条条状的主干，所述主干包括相互垂直的水平主干与竖直主干，所述晶体管的漏极走线位于离所述晶体管距离最近 的水平主干下；以及
    多个像素单元，每个像素单元包括多个显示畴区，每个像素单元的多个所述显示畴区关于所述水平主干或者所述竖直主干对称；
    所述金属走线在所述阵列基板的投影，与所述水平主干或者所述竖直主干在所述阵列基板的垂直投影重合；
    所述像素单元包括公共电极走线和存储电容；且位于同一行的所述像素单元的所述公共电极走线相互连接；
    所述金属走线所在膜层与所述公共电极走线所在膜层之间设置有绝缘层；所述公共电极走线和所述金属走线分别为所述存储电容的第一电极和第二电极；
    所述公共电极走线包括第一公共电极走线，所述第一公共电极走线在所述阵列基板的垂直投影与所述金属走线在所述阵列基板的垂直投影重合；
    所述金属走线的宽度范围大于等于2微米小于等于3微米。
  15. 根据权利要求14所述的阵列基板，其中所述公共电极走线与所述晶体管的栅极同层设置。
  16. 根据权利要求14所述的阵列基板，其中所述金属走线与所述晶体管的漏极同层设置。
  17. 根据权利要求14所述的阵列基板，其中每个所述像素单元包括第一显示畴区、第二显示畴区、第三显示畴区以及第四显示畴区；其中，所述第一显示畴区和所述第二显示畴区同行设置，所述第三显示畴区和所述第四显示畴区同行设置；所述第一显示畴区和所述第三显示畴区同列设置；所述第二显示畴区和所述第四显示畴区同列设置。
  18. 根据权利要求17所述的阵列基板，其中所述金属走线设置在相邻两显示畴区之间的间隙内。
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