WO2019033812A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2019033812A1
WO2019033812A1 PCT/CN2018/087886 CN2018087886W WO2019033812A1 WO 2019033812 A1 WO2019033812 A1 WO 2019033812A1 CN 2018087886 W CN2018087886 W CN 2018087886W WO 2019033812 A1 WO2019033812 A1 WO 2019033812A1
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Prior art keywords
pixel
electrode
pixel unit
lines
sub
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PCT/CN2018/087886
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English (en)
French (fr)
Inventor
龙春平
马永达
徐健
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京东方科技集团股份有限公司
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Priority to US16/326,474 priority Critical patent/US11175549B2/en
Publication of WO2019033812A1 publication Critical patent/WO2019033812A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display substrate, a display panel, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the main structure of the liquid crystal panel of the TFT-LCD includes an array substrate, a color filter substrate, and liquid crystals filled in the box structure formed by the array substrate and the color filter substrate.
  • TFT Thin Film Transistor
  • the black matrix which undoubtedly reduces the aperture ratio of the display device.
  • the pixel electrode is overlaid on the data line to form a modulated electric field, so that liquid crystal molecules corresponding to the position of the data line in the liquid crystal layer can be deflected in a specified direction. Light leakage can be avoided.
  • a disadvantage of the prior art is that, since the data line is disposed between two adjacent columns of pixel units, in order to avoid a short circuit between the pixel electrodes of two adjacent sub-pixels, the pixel electrode can only cover part of the data line, The spacing between the adjacent pixel electrodes is such that the position of the remaining portion of the data line on the color filter substrate that is not covered by the corresponding pixel electrode still needs to be set, so that the aperture ratio of the display device is difficult to be further improved; and the pixel electrode Covering the top of the data line creates a parasitic capacitance, and the resulting crosstalk can cause the display device to display poorly.
  • Embodiments of the present disclosure provide a display substrate including a substrate substrate and a plurality of pixel units arranged in an array on the base substrate, and gate lines disposed in one-to-one correspondence with each row of pixel units and located in any adjacent two a data line between column pixel cells, where:
  • Each pixel unit includes a pixel electrode and a thin film transistor that controls the pixel electrode;
  • Each of the data lines includes a plurality of curved data line portions between two adjacent pixel units of any two rows of pixel units located on both sides of the data line, and each of the data line portions includes the data line a first portion covered by the pixel electrode of the pixel unit on one side and a second portion covered by the pixel electrode of the pixel unit on the other side of the data line portion.
  • the first portion and the second portion of each data line portion are respectively covered by the pixel electrodes of the pixel units on both sides, and for the entire display substrate, most of the data lines except the connection portion are removed. Covered by the pixel electrode to form a modulated electric field, so that the liquid crystal molecules in the corresponding coverage area of the liquid crystal layer can be deflected according to a specified direction, that is, the display device does not need to set a black matrix at a position corresponding to the coverage area, and light leakage can be avoided, thereby improving the opening of the display device.
  • the pixel electrodes of the pixel unit respectively cover the first portion of the data line portion on one side thereof and the second portion of the data line portion on the other side thereof, such that the pixel electrode and the two sides
  • the data line portion respectively generates parasitic capacitance, and since the voltage signals of the adjacent two data lines change in opposite directions, the above parasitic capacitance effects can cancel each other, and the scheme also reduces the occurrence of parasitic capacitance compared with the prior art.
  • Crosstalk improves the display quality of the display device.
  • each of the data line portions further includes a connecting portion connecting the first portion and the second portion.
  • the first portion, the connecting portion and the second portion are respectively a single line, and each of the data line portions includes a first portion, a connecting portion and a second portion that are sequentially connected.
  • the pixel unit is defined by a plurality of gate lines and a plurality of data lines, each of the pixel units includes a thin film transistor, and a gate of the thin film transistor is connected to a corresponding gate line of the pixel unit.
  • the source of the thin film transistor is connected to a data line portion covered by a pixel electrode of the pixel unit, and a drain of the thin film transistor is connected to a pixel electrode of the pixel unit.
  • the source of the thin film transistor may be connected to the first portion of the data line portion that is covered by the pixel electrode on one side of the pixel unit, or may be connected to the data line portion that is covered by the pixel electrode on the other side of the pixel unit.
  • the display substrate further includes a plurality of common electrode lines disposed in the same layer as the gate lines, and each of the common electrode lines is located between two adjacent gate lines, for any two adjacent a pixel unit and a common electrode line between the gate lines, the pixel electrode of the pixel unit covers the common electrode line; for each pixel unit, the common electrode line is a bottom electrode of a storage capacitor of the pixel unit, The pixel electrode is a top electrode of a storage capacitor of the pixel unit.
  • the area of the storage capacitor of the pixel unit is the area of the portion where the pixel electrode overlaps with the common electrode line.
  • the first portion includes a first line segment and a second line segment
  • the second portion is a single line
  • the connecting portion includes a first connecting portion and a second connecting portion
  • each of the data line portions includes an order a first line segment connected, a first connection portion, a second portion, a second connection portion, and a second line segment.
  • each of the gate lines passes through a pixel area of each pixel unit of a row of pixel units corresponding to the gate line, and the pixel area of each pixel unit is divided into a first sub-pixel area and a second a sub-pixel region, the pixel electrode including a first sub-pixel electrode and a second sub-pixel electrode respectively corresponding to the first sub-pixel region and the second sub-pixel region.
  • the first sub-pixel electrode and the second sub-pixel electrode are an integral structure overlying the gate line;
  • Each of the pixel units includes two thin film transistors, and gates of the two thin film transistors are respectively connected to corresponding gate lines of the pixel unit, and sources of the two thin film transistors are respectively connected to the pixel unit. a data line portion covered by the pixel electrode, and drains of the two thin film transistors are respectively connected to the first sub-pixel electrode and the second sub-pixel electrode.
  • the sources of the two thin film transistors are respectively connected to the first line segment or the second line segment of the data line portion which is covered by the pixel electrode on one side of the pixel unit; Located under the second portion of the data line portion, the sources of the two thin film transistors are respectively connected to the second portion of the data line portion which is covered by the pixel electrode on the other side of the pixel unit.
  • the gate line is a bottom electrode of a storage capacitor of the pixel unit
  • the pixel electrode is a top electrode of a storage capacitor of the pixel unit.
  • the area of the storage capacitor of the pixel unit is the area of the overlapping portion of the pixel electrode and the gate line.
  • the first sub-pixel electrode and the second sub-pixel electrode are respectively located on two sides of the gate line and are insulated;
  • Each of the pixel units includes two thin film transistors, and gates of the two thin film transistors are respectively connected to corresponding gate lines of the pixel unit, and sources of the two thin film transistors are respectively connected to the pixel unit. a data line portion covered by the pixel electrode, and drains of the two thin film transistors are respectively connected to the first sub-pixel electrode and the second sub-pixel electrode.
  • the two thin film transistors respectively control the voltages of the first sub-pixel electrode and the second sub-pixel electrode, so that the two sub-pixels can be specifically adjusted according to the areas of the first sub-pixel electrode and the second sub-pixel electrode.
  • the voltage of the electrodes thereby controlling the color brightness of the first sub-pixel region and the second sub-pixel region of the pixel unit, enhances the saturation of the display color, and is advantageous for the design of large-size, high-resolution, and high-refresh frequency display devices.
  • the display substrate further includes a set of common electrode lines disposed in the same layer as the gate lines, the set of common electrode lines includes a plurality of first common electrode lines, and the pixel unit is divided by the plurality of The first common electrode line and the plurality of data lines are cross-defined.
  • the pixel electrodes of the pixel unit respectively cover the sides of the two first common electrode lines close to the pixel unit; a pixel unit, a side of the two first common electrode lines is a bottom electrode of a storage capacitor of the pixel unit, and the pixel electrode is a top electrode of a storage capacitor of the pixel unit.
  • the area of the storage capacitor of the pixel unit is the area of the overlapping portion of the pixel electrode and the two first common electrode lines located on both sides of the pixel unit.
  • the set of common electrode lines further includes a plurality of second common electrode lines, each of the second common electrode lines being located between an adjacent one of the first common electrode lines and one of the gate lines, a pixel unit between adjacent two first common electrode lines, wherein the first sub-pixel electrode and the second sub-pixel electrode of the pixel unit respectively cover the corresponding second common electrode line;
  • the display substrate further includes a metal wiring disposed in the same layer as the drain of the thin film transistor and connected through a drain lead, the metal wiring being located above the second common electrode line; for each pixel unit, the The second common electrode line is a bottom electrode of a storage capacitor of the pixel unit, and the metal wiring is a top electrode of a storage capacitor of the pixel unit.
  • the area of the storage capacitor of the pixel unit is the area of the overlapping portion of the metal wiring and the second common electrode line.
  • the embodiment of the present disclosure further provides a display panel, including the display substrate according to any of the foregoing technical solutions.
  • the pixel aperture ratio of the display panel is greatly increased, and crosstalk due to parasitic capacitance can be effectively suppressed, thereby having better display quality.
  • the embodiment of the present disclosure further provides a display device, including the display panel of the foregoing technical solution.
  • the aperture ratio of the display device is greatly increased, and the display quality is also improved.
  • FIG. 1 is a schematic partial structural view of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic partial structural view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic partial structural view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic partial structural view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 5 is a partial schematic structural view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic partial structural view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 7 is another partial structural schematic view of the display substrate of the embodiment shown in FIG. 6.
  • FIG. 7 is another partial structural schematic view of the display substrate of the embodiment shown in FIG. 6.
  • the embodiment of the present disclosure provides a display substrate, a display panel, and a display device.
  • the present disclosure will be further described in detail in the following examples for the purpose of the present disclosure.
  • a display substrate provided by an embodiment of the present disclosure includes a substrate substrate and a plurality of pixel units arranged in an array on the substrate, and gate lines 10 disposed in one-to-one correspondence with each row of pixel units.
  • a data line 20 located between any two adjacent columns of pixel cells, where:
  • Each pixel unit includes a pixel electrode 30 and a thin film transistor 40 that controls the pixel electrode 30;
  • Each of the data lines 20 includes a plurality of segments of the data line portion 21 between the two adjacent pixel units of the two rows of pixel units located on both sides of the data line 20, and each of the data line portions 21 includes The first portion 22 covered by the pixel electrode 30 of the pixel unit on the side of the data line portion 21 and the second portion 23 covered by the pixel electrode 30 of the pixel unit on the other side of the data line portion 21.
  • the specific material of the base substrate is not limited, and for example, glass, resin, plastic, or the like can be used.
  • the specific material of the gate line 10 and the data line 20 is not limited, and may include, for example, copper Cu, aluminum Al, molybdenum Mo, titanium Ti, chromium Cr, tungsten W, ⁇ Nd or ⁇ Nb, etc.; the gate line 10 and the data line 20 may be The single-layer structure may also be a multi-layer structure. When the gate line 10 and the data line 20 are multi-layered structures, Mo ⁇ Al ⁇ Mo, Ti ⁇ Al ⁇ Ti, Ti ⁇ Cu ⁇ Ti or Mo ⁇ Cu ⁇ Ti may be used. Wait.
  • the line widths of the gate lines 10 and the data lines 20 are not limited in particular.
  • the line width of the gate lines 10 is between 2 and 50 ⁇ m, and the line width of the data lines 20 is between 2 and 20 ⁇ m.
  • the specific material of the pixel electrode 30 is not limited, and for example, indium tin oxide ITO, indium zinc oxide IZO, indium tin zinc oxide ITZO or other transparent metal oxide can be used.
  • the first portion 22 and the second portion 23 of each segment of the data line portion 21 are respectively covered by the pixel electrodes 30 of the pixel units on both sides, and the entire display substrate is removed except for the connection portion 24
  • the partial data lines 20 are all covered by the pixel electrodes 30 to form a modulated electric field, so that liquid crystal molecules corresponding to the coverage areas in the liquid crystal layer can be deflected in a specified direction, that is, the display device does not need to set a black matrix at a position corresponding to the coverage area, and light leakage can be avoided.
  • the aperture ratio of the display device is increased; further, for each pixel unit, the pixel electrode 30 of the pixel unit covers the first portion 22 of the data line portion 21 on one side thereof and the data line portion 21 on the other side thereof, respectively.
  • the pixel electrode 30 and the data line portion 21 on both sides respectively generate parasitic capacitance, and since the voltage signals of the adjacent two data lines 20 change in opposite directions, the above-mentioned parasitic capacitance effects can cancel each other.
  • each of the data line portions 21 further includes a connecting portion 24 connecting the first portion 22 and the second portion 23.
  • the first portion 22, the connecting portion 24, and the second portion 23 are each a single line, and each of the data line portions 21 includes a first portion 22, a connecting portion 24, and a second portion 23 that are sequentially connected.
  • a single line can be understood as a single unbent line segment.
  • each of the data line portions 21 includes three straight segments of the first portion 22, the connecting portion 24, and the second portion 23.
  • the first portion 22 and the second portion 23 may be disposed in parallel, and the bent shape of the data line portion 21 is not limited. In the embodiment shown in FIG.
  • the pixel electrode 30 of the pixel unit covers the first portion 22 of the left data line portion 21 and the second portion 23 of the right data line portion 21 thereof, respectively; In the example, the pixel electrode 30 of the pixel unit covers the second portion 23 of the left data line portion 21 and the first portion 22 of the right data line portion 21 thereof, respectively. Moreover, optionally, the lengths of the first portion 22 and the second portion 23 are equal, which can further reduce the crosstalk caused by the parasitic capacitance and improve the display quality of the display device.
  • the thin film transistor 40 includes a gate electrode 41 formed on the substrate substrate, a gate insulating layer (not shown) formed on the gate electrode 41, and a gate insulating layer.
  • the specific material of the active layer 44 is not limited.
  • amorphous silicon, polycrystalline silicon, or an oxide semiconductor can be used.
  • the specific material of the gate insulating layer is not limited.
  • silicon nitride or silicon oxide can be used.
  • the layer may be a single layer structure or a multilayer structure. When the gate insulating layer has a multilayer structure, silicon oxide/silicon nitride may be used.
  • the pixel unit is defined by a plurality of gate lines 10 and a plurality of data lines 20, each of the pixel units includes a thin film transistor 40, and the gate 41 of the thin film transistor 40 is connected to a corresponding one of the pixel units.
  • the gate line 10, the source 42 of the thin film transistor 40 is connected to the data line portion 21 covered by the pixel electrode 30 of the pixel unit, and the drain electrode 43 of the thin film transistor 40 is connected to the pixel electrode 30 of the pixel unit.
  • the source 42 of the thin film transistor 40 may be connected to the first portion 22 of the data line portion 21 which is covered by the pixel electrode 30 on one side of the pixel unit, or may be covered by the pixel electrode 30 on the other side of the pixel unit.
  • the display substrate further includes a passivation layer or an organic material planarization layer formed on the thin film transistor 40, and the drain electrode 43 of the thin film transistor 40 may be disposed on the passivation layer or the organic material planarization layer.
  • the via is connected to the pixel electrode 30.
  • the specific material of the passivation layer and the planarization layer is not limited.
  • the passivation layer may be silicon nitride
  • the planarization layer may be made of a resin.
  • the display substrate further includes a plurality of common electrode lines 50 disposed in the same layer as the gate lines 10, and each of the common electrode lines 50 is located between adjacent two gate lines 10 for any adjacent a pixel unit and a common electrode line 50 between the two gate lines 10, the pixel electrode 30 of the pixel unit covers the common electrode line 50; for each pixel unit, the common electrode line 50 is the bottom electrode of the storage capacitor of the pixel unit, and the pixel electrode 30 is the top electrode of the storage capacitor of the pixel unit.
  • the area of the storage capacitor of the pixel unit is the area of the portion where the pixel electrode 30 overlaps with the common electrode line 50.
  • the specific material of the common electrode line 50 is not limited, and may include, for example, copper Cu, aluminum Al, molybdenum Mo, titanium Ti, chromium Cr, tungsten W, ⁇ Nd or ⁇ Nb; and the width of the common electrode line 50 is not limited. In the embodiment of the present disclosure, the line width of the common electrode line 50 is between 2 and 30 ⁇ m.
  • the first portion 22 includes a first line segment 221 and a second line segment 222
  • the second portion 23 is a single line
  • the connecting portion 24 includes a first connecting portion 241 and a
  • the two connecting portions 242 each of the data line portions 21 include a first line segment 221, a first connecting portion 241, a second portion 23, a second connecting portion 242, and a second line segment 222 that are sequentially connected.
  • each segment of the data line portion 21 includes a first line segment 221, a first connecting portion 241, a second portion 23, a second connecting portion 242, and a second line segment 222, and a first straight line segment 221 and a second line segment
  • the line segments 222 may be located on the same straight line and disposed in parallel with the second portion 23, and the bent shape of the data line portion 21 is not limited.
  • the pixel electrodes 30 of the pixel unit respectively cover the left side data line thereof.
  • the pixel electrode 30 of the pixel unit covers the second portion 23 of the left data line portion 21 thereof, respectively And the first portion 22 of the right data line portion 21 thereof. Moreover, optionally, the sum of the lengths of the first line segment 221 and the second line segment 222 is equal to the length of the second portion 23, so that the display quality of the display device can be further improved to further reduce the crosstalk caused by the parasitic capacitance.
  • each gate line 10 passes through a pixel area of each pixel unit in a row of pixel units corresponding to the gate line 10, and the pixel area of each pixel unit is divided into first sub-fields.
  • the pixel region and the second sub-pixel region, the pixel electrode 30 includes a first sub-pixel electrode 31 and a second sub-pixel electrode 32 corresponding to the first sub-pixel region and the second sub-pixel region, respectively.
  • the area of the first sub-pixel region and the area of the second sub-pixel region may be equal or may be unequal.
  • the first sub-pixel electrode 31 and the second sub-pixel electrode 32 are an integral structure overlying the gate line 10;
  • Each of the pixel units includes two thin film transistors 40.
  • the gate electrodes 41 of the two thin film transistors 40 are respectively connected to the corresponding gate lines 10 of the pixel units, and the source electrodes 42 of the two thin film transistors 40 are respectively connected to be covered by the pixel electrodes 30 of the pixel unit.
  • the data line portion 21, the drains 43 of the two thin film transistors 40 are connected to the first sub-pixel electrode 31 and the second sub-pixel electrode 32, respectively.
  • the source electrodes 42 of the two thin film transistors 40 are respectively connected to the first line segment 221 of the data line portion 21 which is covered by the pixel electrode 30 on one side of the pixel unit. Or the second line segment 222; when the gate line 10 is located below the second portion 23 of the data line portion 21, the source electrodes 42 of the two thin film transistors 40 are respectively connected to the data lines which are covered by the pixel electrodes 30 on the other side of the pixel unit The second portion 23 of the portion 21.
  • the gate line 10 is the bottom electrode of the storage capacitor of the pixel unit
  • the pixel electrode 30 is the top electrode of the storage capacitor of the pixel unit.
  • the area of the storage capacitor of the pixel unit is the area of the portion where the pixel electrode 30 overlaps the gate line 10.
  • the first sub-pixel electrode 31 and the second sub-pixel electrode 32 are respectively located on two sides of the gate line 10 and are insulated;
  • Each of the pixel units includes two thin film transistors 40.
  • the gate electrodes 41 of the two thin film transistors 40 are respectively connected to the corresponding gate lines 10 of the pixel units, and the source electrodes 42 of the two thin film transistors 40 are respectively connected to be covered by the pixel electrodes 30 of the pixel unit.
  • the data line portion 21, the drains 43 of the two thin film transistors 40 are connected to the first sub-pixel electrode 31 and the second sub-pixel electrode 32, respectively.
  • the two thin film transistors 40 respectively control the voltages of the first sub-pixel electrode 31 and the second sub-pixel electrode 32, and thus can be specifically targeted according to the areas of the first sub-pixel electrode 31 and the second sub-pixel electrode 32. Adjusting the voltages of the two sub-pixel electrodes, thereby controlling the color brightness of the first sub-pixel region and the second sub-pixel region of the pixel unit, enhancing the saturation of the display color, and facilitating the large-size, high-resolution, and high-refresh frequency display devices the design of.
  • the display substrate further includes a set of common electrode lines disposed in the same layer as the gate lines 10.
  • the set of common electrode lines includes a plurality of first common electrode lines 60, and the pixel units are composed of a plurality of first common electrodes.
  • Line 60 and the plurality of data lines 20 are cross-defined.
  • the pixel electrodes 30 of the pixel unit respectively cover the sides of the two first common electrode lines 60 near the pixel unit;
  • the pixel unit, the side of the two first common electrode lines 60 is the bottom electrode of the storage capacitor of the pixel unit, and the pixel electrode 30 is the top electrode of the storage capacitor of the pixel unit.
  • the area of the storage capacitor of the pixel unit is the area of the portion where the pixel electrode 30 overlaps with the two first common electrode lines 60 located on both sides of the pixel unit.
  • a group of common electrode lines further includes a plurality of second common electrode lines 70 , and each of the second common electrode lines 70 is located adjacent to the adjacent one of the first common electrode lines 60 .
  • the first sub-pixel electrode 31 and the second sub-pixel electrode 32 of the pixel unit respectively cover the corresponding second common Electrode line 70;
  • the display substrate further includes a metal wiring 80 disposed in the same layer as the drain electrode 43 of the thin film transistor 40 and connected through the drain wiring 45, the metal wiring 80 being located above the second common electrode line 70; for each pixel unit, the second common electrode Line 70 is the bottom electrode of the storage capacitor of the pixel unit, and metal wiring 80 is the top electrode of the storage capacitor of the pixel unit.
  • the area of the storage capacitor of the pixel unit is the area of the portion where the metal wiring 80 and the second common electrode line 70 overlap.
  • the first sub-pixel electrode 31 and the second sub-pixel electrode 32 of the pixel unit may also cover the sides of the first common electrode line 60 on both sides, which may further increase the area of the storage capacitor of the pixel unit.
  • the display panel may include two metal wires 80 connected to the drains 43 of the two thin film transistors 40 of the pixel unit through the drain leads 45. It can be understood that the two metal wires 80 are respectively located in the pixels.
  • the first sub-pixel region and the second sub-pixel region of the cell are opposite to the second common electrode line 70 in the first sub-pixel region and the second sub-pixel region, respectively.
  • the first sub-pixel electrode 31 and the second sub-pixel electrode 32 can be respectively connected to the metal wiring 80 through via holes provided on the passivation layer or the organic material planarization layer, thereby achieving leakage from the thin film transistor 40.
  • the purpose of pole 43 connection is not limited to pole 43 connection.
  • the first sub-pixel electrode 31 and the second sub-pixel electrode 32 may also be an integrated structure overlying the gate line 10 , thus, for FIG. 5
  • the storage capacitance of the pixel unit is formed by the area of the pixel electrode 30 overlapping the two first common electrode lines 60 on both sides of the pixel unit, and the area of the overlapping portion of the pixel electrode 30 and the gate line 10;
  • the area of the storage capacitor of the pixel unit is constituted by the area of the portion where the metal wiring 80 overlaps with the second common electrode line 70 and the area where the pixel electrode 30 overlaps with the gate line 10.
  • the embodiment of the present disclosure further provides a display panel, including the display substrate of any of the foregoing technical solutions.
  • the display panel further includes a opposite substrate disposed on the display substrate pair, and a position of the corresponding data line connection portion on the opposite substrate is provided with a black matrix to avoid light leakage at the position.
  • the pixel aperture ratio of the display panel is greatly increased, and crosstalk due to parasitic capacitance can be effectively suppressed, thereby having better display quality.
  • the embodiment of the present disclosure further provides a display device including the display panel of the foregoing technical solution.
  • the aperture ratio of the display device is greatly increased, and the display quality is also improved.

Abstract

一种显示基板、显示面板及显示装置，以提高显示装置的开口率，同时提升显示装置的显示品质。显示基板包括位于衬底基板上呈阵列排布的多个像素单元，以及与每行像素单元一一对应设置的栅线（10）和位于任意相邻两列像素单元之间且位于栅线（10）远离衬底基板一侧的数据线（20），每个像素单元包括像素电极（30）以及控制像素电极（30）的薄膜晶体管（40）；每条数据线（20）包括位于该数据线（20）两侧的两列像素单元中任意行向相邻的两个像素单元之间的若干段弯折状的数据线部（21），每段数据线部（21）包括被该数据线部（21）一侧的像素单元的像素电极（30）覆盖的第一部分（22）和被该数据线部（21）另一侧的像素单元的像素电极（30）覆盖的第二部分（23）。

Description

显示基板、显示面板及显示装置
本申请要求在2017年08月18日提交中国专利局、申请号为201710713098.9、公开名称为“一种显示基板、显示面板及显示装置”的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别是涉及一种显示基板、显示面板及显示装置。
背景技术
在平板显示装置中，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)具有体积小、无辐射和制造成本相对较低等特点，在当前的平板显示器市场占据了主导地位。
TFT-LCD的液晶面板的主要结构包括阵列基板、彩膜基板以及填充于阵列基板和彩膜基板所形成的对盒结构内的液晶。阵列基板上形成有多条栅线和多条数据线，多条栅线和多条数据线交叉设置界定出呈阵列排布的多个像素单元，每个像素单元包括像素电极以及控制像素电极的薄膜晶体管(Thin Film Transistor，简称TFT)；彩膜基板上对应每个像素单元的位置分别设置有彩色光阻，同时为了防止出现漏光，彩膜基板上对应栅线和数据线的位置还设置有黑矩阵，这样无疑降低了显示装置的开口率。为了提高开口率，现有技术中在制作阵列基板时，会将像素电极覆盖在数据线的上方以形成调制电场，从而使液晶层中对应数据线位置的液晶分子能够按照指定的方向偏转，进而可以避免漏光现象。
现有技术存在的缺陷在于，由于数据线设置于相邻两列像素单元之间，为了避免行向相邻的两个子像素的像素电极之间发生短路，像素电极只能覆盖部分数据线，以使相邻像素电极之间留有间距，这样，彩膜基板上对应像素电极未能覆盖的剩余部分数据线的位置仍需设置黑矩阵，因此显示装置的 开口率难以进一步提升；并且，像素电极覆盖在数据线的上方会形成寄生电容，由此而产生的串扰会导致显示装置显示不良。
发明内容
本公开实施例的目的是提供一种显示基板、显示面板及显示装置，以提高显示装置的开口率，同时提升显示装置的显示品质。
本公开实施例提供了一种显示基板，包括衬底基板和位于衬底基板上呈阵列排布的多个像素单元，以及与每行像素单元一一对应设置的栅线和位于任意相邻两列像素单元之间的数据线，其中：
每个像素单元包括像素电极以及控制所述像素电极的薄膜晶体管；
每条数据线包括若干段位于该数据线两侧的两列像素单元中任意行向相邻的两个像素单元之间的弯折状的数据线部，每段数据线部包括被该数据线部一侧的像素单元的像素电极覆盖的第一部分和被该数据线部另一侧的像素单元的像素电极覆盖的第二部分。
采用本公开实施例的技术方案，每段数据线部的第一部分和第二部分分别被两侧的像素单元的像素电极所覆盖，对于整个显示基板，除去连接部外的绝大部分数据线均被像素电极覆盖以形成调制电场，使液晶层中对应覆盖区域的液晶分子能够按照指定方向偏转，即显示装置无需在对应覆盖区域的位置设置黑矩阵也可以避免漏光现象，提高了显示装置的开口率；此外，对于每个像素单元，该像素单元的像素电极分别覆盖位于其一侧的数据线部的第一部分以及位于其另一侧的数据线部的第二部分，这样像素电极与两侧的数据线部分别产生寄生电容，而由于相邻两条数据线的电压信号变化方向相反，因此上述寄生电容效应可以相互抵消，相比现有技术，该方案还减弱了由于寄生电容而产生的串扰，提升了显示装置的显示品质。
可选的，每段所述数据线部还包括连接所述第一部分和所述第二部分的连接部。
可选的，所述第一部分、连接部和第二部分分别为单线，每段所述数据 线部包括顺序连接的第一部分、连接部和第二部分。
可选的，所述像素单元由多条栅线和多条数据线交叉界定，每个所述像素单元包括一个薄膜晶体管，所述薄膜晶体管的栅极连接所述像素单元对应的一条栅线，所述薄膜晶体管的源极连接被所述像素单元的像素电极覆盖的数据线部，所述薄膜晶体管的漏极连接所述像素单元的像素电极。这时，薄膜晶体管的源极可以连接位于像素单元的一侧被其像素电极覆盖的数据线部的第一部分，也可以连接位于像素单元的另一侧被其像素电极覆盖的数据线部的第二部分。
可选的，所述显示基板还包括与所述栅线同层设置的多条公共电极线，每条所述公共电极线位于相邻的两条栅线之间，对于位于任意相邻两条栅线之间的像素单元和公共电极线，所述像素单元的像素电极覆盖所述公共电极线；对于每个像素单元，所述公共电极线为所述像素单元的存储电容的底电极，所述像素电极为所述像素单元的存储电容的顶电极。此时，像素单元的存储电容的面积即为像素电极与公共电极线重叠部分的面积。
可选的，所述第一部分包括第一线段和第二线段，所述第二部分为单线，所述连接部包括第一连接部和第二连接部，每段所述数据线部包括顺序连接的第一线段、第一连接部、第二部分、第二连接部和第二线段。
可选的，每条所述栅线穿过与该栅线对应的一行像素单元中的每个像素单元的像素区，且将每个像素单元的像素区划分为第一子像素区和第二子像素区，所述像素电极包括分别对应所述第一子像素区和所述第二子像素区的第一子像素电极和第二子像素电极。
可选的，所述第一子像素电极和第二子像素电极为覆盖于所述栅线之上的一体结构；
每个所述像素单元包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别连接于所述像素单元对应的栅线，所述两个薄膜晶体管的源极分别连接被所述像素单元的像素电极覆盖的数据线部，所述两个薄膜晶体管的漏极分别连接所述第一子像素电极和所述第二子像素电极。
当栅线位于数据线部的第一部分下方时，两个薄膜晶体管的源极分别连接位于像素单元的一侧被其像素电极覆盖的数据线部的第一线段或者第二线段；当栅线位于数据线部的第二部分下方时，两个薄膜晶体管的源极分别连接位于像素单元的另一侧被其像素电极覆盖的数据线部的第二部分。
可选的，对于每个像素单元，所述栅线为所述像素单元的存储电容的底电极，所述像素电极为所述像素单元的存储电容的顶电极。此时，像素单元的存储电容的面积即为像素电极与栅线重叠部分的面积。
可选的，所述第一子像素电极和第二子像素电极分别位于所述栅线的两侧且绝缘设置；
每个所述像素单元包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别连接于所述像素单元对应的栅线，所述两个薄膜晶体管的源极分别连接被所述像素单元的像素电极覆盖的数据线部，所述两个薄膜晶体管的漏极分别连接所述第一子像素电极和所述第二子像素电极。
采用该实施例方案，两个薄膜晶体管分别控制第一子像素电极和第二子像素电极的电压，因此可以根据第一子像素电极和第二子像素电极的面积针对性地调整这两个子像素电极的电压，从而控制像素单元的第一子像素区和第二子像素区的颜色亮度，增强显示色彩的饱和度，有利于大尺寸、高分辨率和高刷新频率显示装置的设计。
可选的，所述显示基板还包括与所述栅线同层设置的一组公共电极线，所述一组公共电极线包括多条第一公共电极线，所述像素单元由所述多条第一公共电极线和多条数据线交叉界定。
可选的，对于位于任意相邻两条第一公共电极线之间的像素单元，所述像素单元的像素电极分别覆盖所述两条第一公共电极线靠近该像素单元的侧部；对于每个像素单元，所述两条第一公共电极线的侧部为所述像素单元的存储电容的底电极，所述像素电极为所述像素单元的存储电容的顶电极。此时，像素单元的存储电容的面积即为像素电极与位于该像素单元两侧的两条第一公共电极线重叠部分的面积。
可选的，所述一组公共电极线还包括多条第二公共电极线，每条所述第二公共电极线位于相邻的一条第一公共电极线和一条栅线之间，对于位于任意相邻两条第一公共电极线之间的像素单元，所述像素单元的第一子像素电极和第二子像素电极分别覆盖对应的第二公共电极线；
所述显示基板还包括与所述薄膜晶体管的漏极同层设置且通过漏极引线连接的金属布线，所述金属布线位于所述第二公共电极线的上方；对于每个像素单元，所述第二公共电极线为所述像素单元的存储电容的底电极，所述金属布线为所述像素单元的存储电容的顶电极。
此时，像素单元的存储电容的面积即为金属布线与第二公共电极线重叠部分的面积。
本公开实施例还提供了一种显示面板，包括前述任一技术方案所述的显示基板。该显示面板的像素开口率大大增加，同时可以有效抑制由于寄生电容而产生的串扰，因此，具有较佳的显示品质。
本公开实施例还提供了一种显示装置，包括前述技术方案所述的显示面板。该显示装置的开口率大大增加，显示品质也得以提升。
附图说明
图1为本公开一实施例显示基板的局部结构示意图；
图2为本公开另一实施例显示基板的局部结构示意图；
图3为本公开另一实施例显示基板的局部结构示意图；
图4为本公开另一实施例显示基板的局部结构示意图；
图5为本公开另一实施例显示基板的局部结构示意图；
图6为本公开另一实施例显示基板的局部结构示意图；
图7为图6所示实施例显示基板的另一局部结构示意图。
附图标记：
10-栅线 20-数据线 30-像素电极 40-薄膜晶体管
21-数据线部 22-第一部分 23-第二部分 24-连接部
41-栅极 42-源极 43-漏极 44-有源层 50-公共电极线
221-第一线段 222-第二线段 241-第一连接部 242-第二连接部
31-第一子像素电极 32-第二子像素电极 60-第一公共电极线
70-第二公共电极线 80-金属布线 45-漏极引线
具体实施方式
为提高显示装置的开口率，同时提升显示装置的显示品质，本公开实施例提供了一种显示基板、显示面板及显示装置。为使本公开的目的、技术方案和优点更加清楚，以下举实施例对本公开作进一步详细说明。
如图1所示，本公开实施例提供的显示基板，包括衬底基板和位于衬底基板上呈阵列排布的多个像素单元，以及与每行像素单元一一对应设置的栅线10和位于任意相邻两列像素单元之间的数据线20，其中：
每个像素单元包括像素电极30以及控制像素电极30的薄膜晶体管40；
每条数据线20包括若干段位于该数据线20两侧的两列像素单元中任意行向相邻的两个像素单元之间的弯折状的数据线部21，每段数据线部21包括被该数据线部21一侧的像素单元的像素电极30覆盖的第一部分22和被该数据线部21另一侧的像素单元的像素电极30覆盖的第二部分23。
其中，衬底基板的具体材质不限，例如可以采用玻璃、树脂或塑料等。栅线10、数据线20的具体材质不限，例如可以包括铜Cu、铝Al、钼Mo、钛Ti、铬Cr、钨W、钕Nd或铌Nb等；栅线10和数据线20可以是单层结构，也可以是多层结构，当栅线10和数据线20为多层结构时，可以采用Mo\Al\Mo、Ti\Al\Ti、Ti\Cu\Ti或者Mo\Cu\Ti等。栅线10和数据线20的线宽具体不限，在本公开实施例中，栅线10的线宽在2～50μm间，数据线20的线宽在2～20μm之间。像素电极30的具体材质不限，例如可以采用铟锡氧化物ITO、铟锌氧化物IZO、铟锡锌氧化物ITZO或其它透明金属氧化物等。
采用本公开实施例技术方案，每段数据线部21的第一部分22和第二部分23分别被两侧的像素单元的像素电极30所覆盖，对于整个显示基板，除 去连接部24外的绝大部分数据线20均被像素电极30覆盖以形成调制电场，使液晶层中对应覆盖区域的液晶分子能够按照指定方向偏转，即显示装置无需在对应覆盖区域的位置设置黑矩阵也可以避免漏光现象，提高了显示装置的开口率；此外，对于每个像素单元，该像素单元的像素电极30分别覆盖位于其一侧的数据线部21的第一部分22以及位于其另一侧的数据线部21的第二部分23，这样像素电极30与两侧的数据线部21分别产生寄生电容，而由于相邻两条数据线20的电压信号变化方向相反，因此上述寄生电容效应可以相互抵消，相比现有技术，该方案还减弱了由于寄生电容而产生的串扰，提升了显示装置的显示品质。
其中，第一部分22和第二部分23的具体连接方式不限，在本公开实施例中，每段数据线部21还包括连接第一部分22和第二部分23的连接部24。
在本公开的一个具体实施例中，第一部分22、连接部24和第二部分23分别为单线，每段数据线部21包括顺序连接的第一部分22、连接部24和第二部分23，在本公开实施例中，单线可以理解为单独的一条无弯折线段。此时，每段数据线部21包括第一部分22、连接部24和第二部分23三个直线段，第一部分22和第二部分23可以平行设置，数据线部21的弯折形状不限，在图1所示的实施例中，像素单元的像素电极30分别覆盖其左侧数据线部21的第一部分22以及其右侧数据线部21的第二部分23；在图2所示的实施例中，像素单元的像素电极30分别覆盖其左侧数据线部21的第二部分23以及其右侧数据线部21的第一部分22。并且，可选的，第一部分22与第二部分23的长度相等，这样可以进一步减弱由于寄生电容而产生的串扰，提升显示装置的显示品质。
对于本领域技术人员可知，薄膜晶体管40包括形成于衬底基板之上的栅极41、形成于栅极41之上的栅极绝缘层(图中未示出)、形成于栅极绝缘层之上的有源层44和分别与有源层44连接的源极42和漏极43。其中，有源层44的具体材质不限，例如可以采用非晶硅、多晶硅或氧化物半导体等；栅极绝缘层的具体材质不限，例如可以采用氮化硅或氧化硅等，栅极绝缘层可以 是单层结构，也可以是多层结构，当栅极绝缘层为多层结构时，可以采用氧化硅\氮化硅。
在本公开的可选实施例中，像素单元由多条栅线10和多条数据线20交叉界定，每个像素单元包括一个薄膜晶体管40，薄膜晶体管40的栅极41连接像素单元对应的一条栅线10，薄膜晶体管40的源极42连接被像素单元的像素电极30覆盖的数据线部21，薄膜晶体管40的漏极43连接像素单元的像素电极30。这时，薄膜晶体管40的源极42可以连接位于像素单元的一侧被其像素电极30覆盖的数据线部21的第一部分22，也可以连接位于像素单元的另一侧被其像素电极30覆盖的数据线部21的第二部分23。需要说明的是，显示基板还包括形成于薄膜晶体管40之上的钝化层或者有机材料平坦化层，薄膜晶体管40的漏极43可通过设置于上述钝化层或者有机材料平坦化层上的过孔与像素电极30连接。其中，钝化层和平坦化层的具体材质不限，例如钝化层可以采用氮化硅，平坦化层可以采用树脂。
请继续参考图1所示，显示基板还包括与栅线10同层设置的多条公共电极线50，每条公共电极线50位于相邻的两条栅线10之间，对于位于任意相邻两条栅线10之间的像素单元和公共电极线50，像素单元的像素电极30覆盖公共电极线50；对于每个像素单元，公共电极线50为像素单元的存储电容的底电极，像素电极30为像素单元的存储电容的顶电极。此时，像素单元的存储电容的面积即为像素电极30与公共电极线50重叠部分的面积。其中，公共电极线50的具体材质不限，例如可以包括铜Cu、铝Al、钼Mo、钛Ti、铬Cr、钨W、钕Nd或铌Nb等；公共电极线50的线宽也不限，在本公开实施例中，公共电极线50的线宽在2～30μm之间。
如图3所示，在本公开的另一具体实施例中，第一部分22包括第一线段221和第二线段222，第二部分23为单线，连接部24包括第一连接部241和第二连接部242，每段数据线部21包括顺序连接的第一线段221、第一连接部241、第二部分23、第二连接部242和第二线段222。此时，每段数据线部21包括第一线段221、第一连接部241、第二部分23、第二连接部242和第 二线段222五个直线段，第一线段221和第二线段222可以位于同一直线上并与第二部分23平行设置，数据线部21的弯折形状不限，在图3所示的实施例中，像素单元的像素电极30分别覆盖其左侧数据线部21的第一部分22以及其右侧数据线部21的第二部分23；在图4所示的实施例中，像素单元的像素电极30分别覆盖其左侧数据线部21的第二部分23以及其右侧数据线部21的第一部分22。并且，可选的，第一线段221和第二线段222长度之和与第二部分23的长度相等，这样可以进一步为了进一步减弱由于寄生电容而产生的串扰，提升显示装置的显示品质。
如图3和图4所示，每条栅线10穿过与该栅线10对应的一行像素单元中的每个像素单元的像素区，且将每个像素单元的像素区划分为第一子像素区和第二子像素区，像素电极30包括分别对应第一子像素区和第二子像素区的第一子像素电极31和第二子像素电极32。第一子像素区的面积与第二子像素区的面积可以相等，也可以不等。
在本公开的一个可选实施例中，第一子像素电极31和第二子像素电极32为覆盖于栅线10之上的一体结构；
每个像素单元包括两个薄膜晶体管40，两个薄膜晶体管40的栅极41分别连接于像素单元对应的栅线10，两个薄膜晶体管40的源极42分别连接被像素单元的像素电极30覆盖的数据线部21，两个薄膜晶体管40的漏极43分别连接第一子像素电极31和第二子像素电极32。
当栅线10位于数据线部21的第一部分22下方时，两个薄膜晶体管40的源极42分别连接位于像素单元的一侧被其像素电极30覆盖的数据线部21的第一线段221或者第二线段222；当栅线10位于数据线部21的第二部分23下方时，两个薄膜晶体管40的源极42分别连接位于像素单元的另一侧被其像素电极30覆盖的数据线部21的第二部分23。
可选的，对于每个像素单元，栅线10为像素单元的存储电容的底电极，像素电极30为像素单元的存储电容的顶电极。此时，像素单元的存储电容的面积即为像素电极30与栅线10重叠部分的面积。
如图5所示，在本公开的另一可选实施例中，第一子像素电极31和第二子像素电极32分别位于栅线10的两侧且绝缘设置；
每个像素单元包括两个薄膜晶体管40，两个薄膜晶体管40的栅极41分别连接于像素单元对应的栅线10，两个薄膜晶体管40的源极42分别连接被像素单元的像素电极30覆盖的数据线部21，两个薄膜晶体管40的漏极43分别连接第一子像素电极31和第二子像素电极32。
采用该实施例方案，两个薄膜晶体管40分别控制第一子像素电极31和第二子像素电极32的电压，因此可以根据第一子像素电极31和第二子像素电极32的面积针对性地调整这两个子像素电极的电压，从而控制像素单元的第一子像素区和第二子像素区的颜色亮度，增强显示色彩的饱和度，有利于大尺寸、高分辨率和高刷新频率显示装置的设计。
如图5所示实施例，显示基板还包括与栅线10同层设置的一组公共电极线，一组公共电极线包括多条第一公共电极线60，像素单元由多条第一公共电极线60和多条数据线20交叉界定。
可选的，对于位于任意相邻两条第一公共电极线60之间的像素单元，像素单元的像素电极30分别覆盖两条第一公共电极线60靠近该像素单元的侧部；对于每个像素单元，两条第一公共电极线60的侧部为像素单元的存储电容的底电极，像素电极30为像素单元的存储电容的顶电极。此时，像素单元的存储电容的面积即为像素电极30与位于该像素单元两侧的两条第一公共电极线60重叠部分的面积。
如图6和图7所示实施例，可选的，一组公共电极线还包括多条第二公共电极线70，每条第二公共电极线70位于相邻的一条第一公共电极线60和一条栅线10之间，对于位于任意相邻两条第一公共电极线60之间的像素单元，像素单元的第一子像素电极31和第二子像素电极32分别覆盖对应的第二公共电极线70；
显示基板还包括与薄膜晶体管40的漏极43同层设置且通过漏极引线45连接的金属布线80，金属布线80位于第二公共电极线70的上方；对于每个 像素单元，第二公共电极线70为像素单元的存储电容的底电极，金属布线80为像素单元的存储电容的顶电极。
此时，像素单元的存储电容的面积即为金属布线80与第二公共电极线70重叠部分的面积。当然，像素单元的第一子像素电极31和第二子像素电极32也可以分别覆盖两侧的第一公共电极线60的侧部，这样可以进一步增加像素单元的存储电容的面积。在本实施例方案中，显示面板可以包括与像素单元的两个薄膜晶体管40的漏极43分别通过漏极引线45连接的两条金属布线80，可以理解的，两条金属布线80分别位于像素单元的第一子像素区和第二子像素区，并分别与第一子像素区和第二子像素区内的第二公共电极线70位置相对。采用该方案，第一子像素电极31和第二子像素电极32可分别通过设置于钝化层或者有机材料平坦化层上的过孔与金属布线80连接，以此实现与薄膜晶体管40的漏极43连接的目的。
需要说明的是，在图5至图7所示实施例中，第一子像素电极31和第二子像素电极32也可以为覆盖于栅线10之上的一体结构，这样，对于图5所示实施例，像素单元的存储电容由像素电极30与位于该像素单元两侧的两条第一公共电极线60重叠部分的面积，以及像素电极30与栅线10重叠部分的面积共同构成；对于图6和图7所示实施例，像素单元的存储电容的面积由金属布线80与第二公共电极线70重叠部分的面积，以及像素电极30与栅线10重叠部分的面积共同构成。
本公开实施例还提供了一种显示面板，包括前述任一技术方案的显示基板。可以理解的，显示面板还包括与显示基板对盒设置的对侧基板，该对侧基板上对应数据线连接部的位置设置有黑矩阵，以避免该位置产生漏光。该显示面板的像素开口率大大增加，同时可以有效抑制由于寄生电容而产生的串扰，因此，具有较佳的显示品质。
本公开实施例还提供了一种显示装置，包括前述技术方案的显示面板。该显示装置的开口率大大增加，显示品质也得以提升。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本 公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种显示基板，包括衬底基板和位于衬底基板上呈阵列排布的多个像素单元，以及与每行像素单元一一对应设置的栅线和位于任意相邻两列像素单元之间的数据线，其中：
    每个像素单元包括像素电极以及控制所述像素电极的薄膜晶体管；
    每条数据线包括若干段位于该数据线两侧的两列像素单元中任意行向相邻的两个像素单元之间的弯折状的数据线部，每段数据线部包括被该数据线部一侧的像素单元的像素电极覆盖的第一部分和被该数据线部另一侧的像素单元的像素电极覆盖的第二部分。
  2. 如权利要求1所述的显示基板，其中，每段所述数据线部还包括连接所述第一部分和所述第二部分的连接部。
  3. 如权利要求2所述的显示基板，其中，所述第一部分和所述第二部分分别为单线，每段所述数据线部包括顺序连接的第一部分、连接部和第二部分。
  4. 如权利要求3所述的显示基板，其中，所述像素单元由多条栅线和多条数据线交叉界定，每个所述像素单元包括一个薄膜晶体管，所述薄膜晶体管的栅极连接所述像素单元对应的一条栅线，所述薄膜晶体管的源极连接被所述像素单元的像素电极覆盖的数据线部，所述薄膜晶体管的漏极连接所述像素单元的像素电极。
  5. 如权利要求4所述的显示基板，其中，所述显示基板还包括与所述栅线同层设置的多条公共电极线，每条所述公共电极线位于相邻的两条栅线之间，对于位于任意相邻两条栅线之间的像素单元和公共电极线，所述像素单元的像素电极覆盖所述公共电极线；对于每个像素单元，所述公共电极线为所述像素单元的存储电容的底电极，所述像素电极为所述像素单元的存储电容的顶电极。
  6. 如权利要求2所述的显示基板，其中，所述第一部分包括第一线段和 第二线段，所述第二部分为单线，所述连接部包括第一连接部和第二连接部，每段所述数据线部包括顺序连接的第一线段、第一连接部、第二部分、第二连接部和第二线段。
  7. 如权利要求6所述的显示基板，其中，每条所述栅线穿过与该栅线对应的一行像素单元中的每个像素单元的像素区，且将每个像素单元的像素区划分为第一子像素区和第二子像素区，所述像素电极包括分别对应所述第一子像素区和所述第二子像素区的第一子像素电极和第二子像素电极。
  8. 如权利要求7所述的显示基板，其中，所述第一子像素电极和第二子像素电极为覆盖于所述栅线之上的一体结构；
    每个所述像素单元包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别连接于所述像素单元对应的栅线，所述两个薄膜晶体管的源极分别连接被所述像素单元的像素电极覆盖的数据线部，所述两个薄膜晶体管的漏极分别连接所述第一子像素电极和所述第二子像素电极。
  9. 如权利要求8所述的显示基板，其中，对于每个像素单元，所述栅线为所述像素单元的存储电容的底电极，所述像素电极为所述像素单元的存储电容的顶电极。
  10. 如权利要求7所述的显示基板，其中，所述第一子像素电极和第二子像素电极分别位于所述栅线的两侧且绝缘设置；
    每个所述像素单元包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别连接于所述像素单元对应的栅线，所述两个薄膜晶体管的源极分别连接被所述像素单元的像素电极覆盖的数据线部，所述两个薄膜晶体管的漏极分别连接所述第一子像素电极和所述第二子像素电极。
  11. 如权利要求10所述的显示基板，其中，所述显示基板还包括与所述栅线同层设置的一组公共电极线，所述一组公共电极线包括多条第一公共电极线，所述像素单元由所述多条第一公共电极线和多条数据线交叉界定。
  12. 如权利要求11所述的显示基板，其中，对于位于任意相邻两条第一公共电极线之间的像素单元，所述像素单元的像素电极分别覆盖所述两条第 一公共电极线靠近该像素单元的侧部；对于每个像素单元，所述两条第一公共电极线的侧部为所述像素单元的存储电容的底电极，所述像素电极为所述像素单元的存储电容的顶电极。
  13. 如权利要求11所述的显示基板，其中，所述一组公共电极线还包括多条第二公共电极线，每条所述第二公共电极线位于相邻的一条第一公共电极线和一条栅线之间，对于位于任意相邻两条第一公共电极线之间的像素单元，所述像素单元的第一子像素电极和第二子像素电极分别覆盖对应的第二公共电极线；
    所述显示基板还包括与所述薄膜晶体管的漏极同层设置且通过漏极引线连接的金属布线，所述金属布线位于所述第二公共电极线的上方；对于每个像素单元，所述第二公共电极线为所述像素单元的存储电容的底电极，所述金属布线为所述像素单元的存储电容的顶电极。
  14. 一种显示面板，包括如权利要求1～13任一项所述的显示基板。
  15. 一种显示装置，包括如权利要求14所述的显示面板。
PCT/CN2018/087886 2017-08-18 2018-05-22 显示基板、显示面板及显示装置 WO2019033812A1 (zh)

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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107272292B (zh) 2017-08-18 2020-02-18 京东方科技集团股份有限公司 一种显示基板、显示面板及显示装置
CN108732805B (zh) * 2018-05-28 2021-09-14 京东方科技集团股份有限公司 一种显示基板、显示面板及显示装置
CN108628049B (zh) 2018-05-31 2021-01-26 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN110376813A (zh) * 2019-07-09 2019-10-25 深圳市华星光电半导体显示技术有限公司 一种像素结构及显示面板
CN110596987B (zh) * 2019-09-30 2023-09-08 京东方科技集团股份有限公司 显示基板和显示装置
CN111308801A (zh) * 2020-03-09 2020-06-19 Tcl华星光电技术有限公司 液晶显示面板
WO2021196089A1 (zh) * 2020-04-01 2021-10-07 京东方科技集团股份有限公司 阵列基板和显示装置
KR20210127842A (ko) * 2020-04-14 2021-10-25 삼성디스플레이 주식회사 액정 표시 장치
CN113805392A (zh) * 2020-06-12 2021-12-17 京东方科技集团股份有限公司 显示基板、显示面板及显示基板的制作方法
CN114038408B (zh) * 2021-11-23 2023-02-24 武汉华星光电半导体显示技术有限公司 显示面板及其驱动方法、显示装置
CN114879423B (zh) * 2022-06-07 2023-08-29 厦门天马微电子有限公司 一种显示面板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020003588A1 (en) * 2000-03-30 2002-01-10 Yoshihiro Okada Active matrix type liquid crystal display apparatus
CN1932591A (zh) * 2006-10-16 2007-03-21 友达光电股份有限公司 液晶显示器及其薄膜晶体管基板
CN101868756A (zh) * 2008-02-21 2010-10-20 夏普株式会社 有源矩阵基板和液晶显示装置
CN107272292A (zh) * 2017-08-18 2017-10-20 京东方科技集团股份有限公司 一种显示基板、显示面板及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070051037A (ko) * 2005-11-14 2007-05-17 삼성전자주식회사 액정 표시 장치
CN101644863B (zh) * 2008-08-06 2011-08-31 北京京东方光电科技有限公司 Tft-lcd像素结构及其制造方法
JP5448875B2 (ja) * 2010-01-22 2014-03-19 株式会社ジャパンディスプレイ 液晶表示装置
KR102095027B1 (ko) * 2013-07-12 2020-04-16 삼성디스플레이 주식회사 액정 표시 장치
KR20160061536A (ko) * 2014-11-21 2016-06-01 삼성디스플레이 주식회사 액정 표시 장치
US10303026B2 (en) * 2017-02-17 2019-05-28 Shenzhen China Star Optoelectronics Technology Co., Ltd Liquid crystal displays and the pixel circuit structure thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020003588A1 (en) * 2000-03-30 2002-01-10 Yoshihiro Okada Active matrix type liquid crystal display apparatus
CN1932591A (zh) * 2006-10-16 2007-03-21 友达光电股份有限公司 液晶显示器及其薄膜晶体管基板
CN101868756A (zh) * 2008-02-21 2010-10-20 夏普株式会社 有源矩阵基板和液晶显示装置
CN107272292A (zh) * 2017-08-18 2017-10-20 京东方科技集团股份有限公司 一种显示基板、显示面板及显示装置

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