WO2019021517A1 - 電力変換装置及び電力変換装置の制御方法 - Google Patents

電力変換装置及び電力変換装置の制御方法 Download PDF

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Publication number
WO2019021517A1
WO2019021517A1 PCT/JP2018/007145 JP2018007145W WO2019021517A1 WO 2019021517 A1 WO2019021517 A1 WO 2019021517A1 JP 2018007145 W JP2018007145 W JP 2018007145W WO 2019021517 A1 WO2019021517 A1 WO 2019021517A1
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Prior art keywords
switching element
turned
state
connection point
control process
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PCT/JP2018/007145
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English (en)
French (fr)
Japanese (ja)
Inventor
小林　健二
祐介 大内
溝上　恭生
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オムロン株式会社
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Publication of WO2019021517A1 publication Critical patent/WO2019021517A1/ja

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to a power converter and a control method of the power converter, and more particularly, to a power converter including a full bridge circuit and a short circuit capable of shorting the output of the full bridge circuit, and such a power converter Control method of
  • a power conditioner for a solar cell includes a circuit having a full bridge circuit and a circuit for shorting the output of the full bridge circuit as shown in FIG. It is known that each switching element in the type circuit is turned ON / OFF as shown in FIG. 2 every switching cycle (T SW ) (see, for example, Patent Document 1).
  • An object of the present invention is to provide a technology capable of controlling a HERIC type circuit more efficiently.
  • a power converter includes a first output terminal and a second output terminal to which a load is connected, and a first switching element which is a high side switching element and a second side which is a low side switching element.
  • a first connection point which is a connection point of the element and the second switching element is connected to the first output terminal, and a second connection which is a connection point of the third switching element and the fourth switching element of the second leg.
  • a full bridge inverter circuit whose point is connected to the second output terminal, and a short circuit between the first connection point and the second connection point
  • a fifth switching element capable of turning on / off a current flowing from the second connection point side to the first connection point side, and from the first connection point side to the second connection point side.
  • a short circuit including a sixth switching element capable of turning on / off a flowing current, and a control unit performing on / off control of each switching element in the full bridge inverter circuit and the short circuit, the fifth switching While the element is on and the sixth switching element is off, the second switching element and the third switching element are on, and the fifth switching element is off. And the first switching element and the fourth switching element are turned on while the sixth switching element is on, and the first switching element is turned on.
  • the fifth switching element is turned on and the second and third switching elements are turned off, And a control unit that repeats a control process of turning on the sixth switching element before the fifth switching element is turned off.
  • the fifth switching element is turned on and the sixth switching element is turned off after the first predetermined time after the first and fourth switching elements are turned off.
  • the second and third switching elements are turned on after a second predetermined time from the second to the third switching elements are turned on after a third predetermined time after the second and third switching elements are turned off, and the fifth switching element is turned on It may be processing to turn on the first and fourth switching elements after a fourth predetermined time after turning off.
  • the first to fourth predetermined times may be the same time, or may be times determined in accordance with the turn-on / off times of the switching elements to be switched.
  • control unit of the power conversion device performs dead time compensation processing for compensating for distortion of an output waveform due to providing the first to fourth predetermined times between control timings of switching elements together with the control processing. May be performed.
  • a first output terminal and a second output terminal to which a load is connected a first switching element as a high side switching element, and a second switching element as a low side switching element
  • a second leg including a third switching element that is a high side switching element and a fourth switching element that is a low side switching element, and the first switching element of the first leg and the first leg
  • a first connection point, which is a connection point of a second switching element, is connected to the first output terminal, and a second connection point, which is a connection point of the third switching element and the fourth switching element of the second leg is the A full bridge inverter circuit connected to a second output terminal, and a short circuit capable of shorting between the first connection point and the second connection point
  • a fifth switching element capable of turning on / off a current flowing from the second connection point side to the first connection point side, and a current flowing from the first connection point side to the second connection point side
  • a short circuit including a sixth
  • the second switching element is in a period in which the fifth switching element is turned on and the sixth switching element is turned off by a computer.
  • the third switching element is on, the fifth switching element is off, and the first switching element and the fourth switching element are in a period during which the sixth switching element is on.
  • control method of the power conversion device of the present invention during control of the HERIC type circuit, current flows in a different path from the conventional one (see FIG. 2), so the HERIC type circuit is more efficient than the conventional one. Can operate.
  • the “computer” in the control method of the power conversion device of the present invention may be a computer (control unit or the like) in the power conversion device or a computer outside the power conversion device.
  • FIG. 1 is an explanatory view of a HERIC type circuit.
  • FIG. 2 is a timing chart for explaining the contents of conventional control processing of the HERIC type circuit.
  • FIG. 3 is an explanatory view of a configuration and a usage pattern of the power conversion device according to the embodiment of the present invention.
  • FIG. 4 is an explanatory diagram of a configuration of an inverter circuit included in the power conversion device according to the embodiment.
  • FIG. 5 is a timing chart for explaining the contents of control processing performed by the control unit included in the power conversion device according to the embodiment.
  • FIG. 6A is an explanatory view of the ON / OFF state of each switching element in each state formed by the old control process (conventional control process) and the output voltage of the inverter circuit in each state.
  • FIG. 1 is an explanatory view of a HERIC type circuit.
  • FIG. 2 is a timing chart for explaining the contents of conventional control processing of the HERIC type circuit.
  • FIG. 3 is an explanatory view
  • FIG. 6B is an explanatory diagram of ON / OFF states of the switching elements in each state formed by the new control process (control process performed by the control unit) and an output voltage of the inverter circuit in each state.
  • FIG. 7-1 is an explanatory diagram of current paths during old control processing and new control processing when the inverter instantaneous output current is 0 or more.
  • FIG. 7-2 is an explanatory diagram of a current path during old control processing and new control processing in the case where the inverter instantaneous output current is 0 or more, following FIG. 7-1.
  • FIG. 8-1 is a diagram for explaining the loss that occurs in each state when the inverter instantaneous output current is 0 or more due to the execution of the old control process.
  • FIG. 7-1 is an explanatory diagram of current paths during old control processing and new control processing when the inverter instantaneous output current is 0 or more.
  • FIG. 8-2 is a diagram for describing the loss that occurs in each state when the instantaneous inverter output current is 0 or more due to the execution of the old control processing, which is subsequent to FIG. 8-1.
  • FIG. 9-1 is a diagram for explaining the loss that occurs in each state when the inverter instantaneous output current is 0 or more due to the execution of the new control process.
  • FIG. 9-2 is a diagram for explaining the loss that occurs in each state when the instantaneous inverter output current is 0 or more due to the execution of the new control process, following FIG. 9-1.
  • FIG. 10A is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is 0 or more, due to the old control processing.
  • FIG. 10A is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is 0 or more, due to the old control processing.
  • FIG. 10B is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is 0 or more, by the new control process.
  • FIG. 11A is an explanatory diagram of current paths during old control processing and new control processing when the inverter instantaneous output current is less than zero.
  • FIG. 11-2 is an explanatory diagram of a current path during old control processing and new control processing in the case where the inverter instantaneous output current is less than 0, following FIG. 11-1.
  • FIG. 12A is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is less than 0 due to the old control processing.
  • FIG. 11A is an explanatory diagram of current paths during old control processing and new control processing when the inverter instantaneous output current is less than zero.
  • FIG. 12B is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is less than 0 by the new control process.
  • FIG. 13A is an explanatory diagram of a current path during old control processing and new control processing when the sign of the inverter instantaneous output current changes.
  • FIG. 13-2 is an explanatory diagram of a current path during old control processing and new control processing in the case where the sign of the inverter instantaneous output current changes, following FIG. 13-1.
  • FIG. 14A is an explanatory diagram of the inverter instantaneous output current generated by the old control process when the output current is small.
  • FIG. 14B is an explanatory diagram of the inverter instantaneous output current generated by the new control process when the output current is small.
  • FIG. 15A is an explanatory diagram of the number of occurrences of various losses when the sign of the inverter instantaneous output current changes due to the old control processing.
  • FIG. 15B is an explanatory diagram of the number of occurrences of various losses when the sign of the inverter instantaneous output current changes due to the new control process.
  • FIG. 16A is a diagram for explaining the amount of dead time compensation that is required when the old control processing is performed under the condition that the inverter instantaneous output current is 0 or more.
  • FIG. 16B is a diagram for describing the amount of dead time compensation that is required when the new control process is performed under the situation where the inverter instantaneous output current is 0 or more.
  • FIG. 17A is a diagram for explaining the amount of dead time compensation that is required when the old control processing is performed in a situation where the inverter instantaneous output current is less than zero.
  • FIG. 17B is a diagram for explaining the amount of dead time compensation required when performing new control processing under a situation where the inverter instantaneous output current is less than zero.
  • FIG. 18A is a diagram for describing the amount of dead time compensation that is required when the old control processing is performed under the situation where the sign of the inverter instantaneous output current changes.
  • FIG. 18B is a diagram for explaining the amount of dead time compensation that is required when new control processing is performed in a situation where the sign of the inverter instantaneous output current changes.
  • FIG. 19 is an explanatory diagram of a dead time compensation process performed by the control unit.
  • FIG. 3 shows the configuration and usage of the power conversion device 10 according to an embodiment of the present invention.
  • the power conversion device 10 is a power conditioner that can be connected to a grid and used in connection with a solar cell (solar cell array) 35. As illustrated, the power conversion device 10 includes a booster circuit 11, an inverter circuit (INV circuit) 12, a pair of output terminals 21 and 22, and a control unit 30.
  • a booster circuit 11 an inverter circuit (INV circuit) 12
  • a pair of output terminals 21 and 22 and a control unit 30.
  • the pair of output terminals 21 and 22 included in the power conversion device 10 are output terminals to which an AC consumer device in the home is connected as the load 40 and to which the output of the inverter circuit 12 is supplied at the time of a self sustaining operation.
  • a capacitor 17 is disposed between the output terminals 21 and 22.
  • the power conversion device 10 since the power conversion device 10 can be interconnected with the system, the power conversion device 10 also includes a pair of output terminals (not shown) to which the output of the inverter circuit 12 is supplied during the interconnection operation.
  • the boosting circuit 11 is a boosting chopper circuit in which a switching element and a passive element (reactor, diode or the like) are combined in order to boost the output voltage of the solar cell 35.
  • a capacitor 15 is disposed between the input terminals of the booster circuit 11 (between the input terminals of the power conversion device 10).
  • the inverter circuit 12 is a HERIC type circuit (details will be described later) for converting a DC voltage output from the booster circuit 11 into an AC voltage. As illustrated, a capacitor 16 is disposed between the input terminals of the inverter circuit 12 (between the output terminals of the booster circuit 11). Further, each output terminal of the inverter circuit 12 is connected to the output terminal 21 or the output terminal 22 via the reactor 18.
  • the inverter circuit 12 is a full bridge circuit composed of a first leg 25 and a second leg 26 connected in parallel between a pair of input terminals 23 p and 23 n of the inverter circuit 12. Prepare.
  • the first leg 25 is composed of switching elements UH and UL connected in series, and a free wheeling diode disposed between the emitters and collectors of the switching elements (IGBTs).
  • the second leg 26 is configured of the switching elements WH and WL connected in series, and a free wheeling diode disposed between the emitter and the collector of each switching element.
  • the connection point 25c of the switching element UH and UL of the first leg 25 is connected to the output terminal 21 through the reactor 18, and the connection point 26c of the switching elements WH and WL of the second leg 26 is It is connected to the output terminal 22 via the reactor 18.
  • the input terminal 23p is an input terminal on the high potential side. Therefore, the switching elements UH and WH are high side switching elements, and the switching elements UL and WL are low side switching elements.
  • the inverter circuit 12 includes a short circuit 27.
  • the short circuit 27 includes a switching element WS having an emitter connected to the connection point 25c, a switching element US having a collector connected to the collector of the switching element WS, and an emitter connected to the connection point 26c. And a free wheeling diode disposed between the emitter and the collector of each switching element. That is, the short circuit 27 can turn on / off the current flowing from the connection point 25c side to the connection point 26c side (the current flowing from the output terminal 21 side to the output terminal 22 side) by turning on / off the switching element WS.
  • the on / off of the switching element US makes it possible to turn on / off the current flowing from the connection point 26c to the connection point 25c.
  • the control unit 30 is a unit that integrally controls each unit (the booster circuit 11 and the inverter circuit 12) in the power conversion device 10.
  • the control unit 30 is composed of a processor (CPU, microcontroller, etc.) and its peripheral circuits, and in the control unit 30, sensors (current sensor, voltage sensor; not shown) provided at various places of the power conversion device 10. The output of is input.
  • the control unit 30 is configured (programming) so as to repeat control processing of turning on / off each switching element in the inverter circuit 12 in the pattern shown in FIG. 5 every switching cycle (T SW ) during the self-sustaining operation. It is done.
  • control unit 30 turns on / off each switching element in inverter circuit 12 so as to satisfy the following conditions.
  • Condition 1 While the switching element US is on and the switching element WS is off, the switching element UL and the switching element WH are on.
  • Condition 2 The switching element UH and the switching element WL are turned on while the switching element US is off and the switching element WS is on.
  • Condition 3 The switching element US is turned on after the switching elements UH and WL are turned off and before the switching element WS is turned off.
  • Condition 4 The switching element WS is turned on after the switching elements UL and WH are turned off and before the switching element US is turned off.
  • Condition 5 The time from turning on the switching elements UH and WL to turning on the switching element US, the time from turning on the switching element WS to turning on the switching elements UL and WH, turning off the switching elements UL and WH The time from when the switching element WS is turned on to the time from when the switching element US is turned off to when the switching elements UH and WL are turned on all have a preset dead time (in the present embodiment, 2 ⁇ s).
  • the contents of this control process are obtained as a result of earnest research conducted to improve the efficiency of the inverter circuit 12 which is a HERIC type circuit.
  • the effect obtained by the control process will be specifically described by comparing with the conventional control process (FIG. 2).
  • the HERIC type circuit shown in FIG. 1 is also referred to as the inverter circuit 12, and the input voltage of the inverter circuit 12 (the output voltage of the booster circuit 11 and the voltage between the terminals of the capacitor 16) is referred to as DDV. write.
  • the conventional control process (FIG. 2) and the control process (FIG. 5) performed by the control unit 30 will be referred to as an old control process and a new control process, respectively.
  • FIG. 6A shows ON / OFF states of the switching elements in the states 1 to 8 formed by the old control process (FIG. 2), together with the output voltage of the inverter circuit 12 in each state.
  • FIG. 6B shows ON / OFF states of the switching elements in the states 1 to 8 formed by the new control process (FIG. 5), together with the output voltage of the inverter circuit 12 in each state.
  • each switching element in the full bridge circuit of the inverter circuit 12 is on / off controlled in the same manner as the old control process.
  • the control contents for the switching elements US and WS are completely different from the old control process. Therefore, when the new control process is performed, the current path in the inverter circuit 12 changes with time in a pattern different from that in the old control process.
  • the difference in time change pattern of the current path in the inverter circuit 12 due to the new control processing and the old control processing is less than 0 when the inverter instantaneous output current during one control processing (during one switching cycle) is 0 or more. And the case where the sign of the inverter instantaneous output current changes during one control process will be described separately.
  • FIGS. 7-1 and 7-2 the current path in the inverter circuit 12 temporally changes as shown in FIGS. 7-1 and 7-2 by the new control process and the old control process.
  • the current paths in the inverter circuit 12 in the states 1, 3 to 7 are the same even when the old control process is performed or the new control process is performed. It will be the same. However, when new control processing is performed, in the state 2 (see the explanatory diagrams (A2) and (B2)) and the state 8 (see the explanatory diagrams (A8) and (B8)), the inside of the inverter circuit 12 is Current flows in a different path from when processing is performed.
  • the current paths in the inverter circuit 12 in the states 1, 3 to 7 are the same even when the old control process is performed or the new control process is performed. It will be the same. However, when new control processing is performed, in the state 2 (see the explanatory diagrams (A2) and (B2)) and the state 8 (see the explanatory diagrams (A8) and (B8)), the inside of the inverter circuit 12 is Current flows in a different path from when processing is performed.
  • the inverter circuit 12 can be controlled more efficiently than the old control process.
  • state 3 since the flow through the diode D US and the switching element WS current, the conduction loss Esat conduction losses of the diode D US Ef and the switching element WS occurs. Further, at the time of transition from state 3 to state 4, the switching element WS in the state in which current is flowing is turned off, so that the turn-off loss Eoff of the switching element WS occurs. Therefore, in state 3, the turn-off loss Eoff, the conduction loss Esat, and the conduction loss Ef occur once each.
  • state 7 current flows through the diode D US and the switching element WS. Also, as described above, at the transition from state 6 to state 7, turn-on loss Eon of switching element WS occurs. Then, at the transition from the state 7 to the state 8, since the switching element US in which no current flows is only turned off, no particular loss occurs. Therefore, in the state 7, as shown in FIG. 9-2, the turn-on loss Eon, the conduction loss Esat and the conduction loss Ef are generated once each.
  • each loss is generated as illustrated in FIG. 10A and the new control process is performed. Will cause each loss as shown in FIG. 10B.
  • inverter instantaneous output current 00 when inverter instantaneous output current 00, the total of conduction losses of the switching element and the free wheeling diode does not change if new control processing is performed, but switching losses (turn-on loss, turn-off loss and Recovery losses can be reduced seven times in total. Therefore, if new control processing is performed when the inverter instantaneous output current 00, the inverter circuit 12 can be operated more efficiently (with less loss) than the old control processing.
  • FIGS. 11-1 and 11-2 the current path in the inverter circuit 12 changes with time as shown in FIGS. 11-1 and 11-2 by the new control process and the old control process.
  • the turn-on loss Eon, turn-off loss Eoff and conduction loss Esat of the switching element and the number of occurrences of conduction loss Ef of the diode and recovery loss Err are shown in FIG. It becomes what was shown to 12B.
  • the recovery loss Err is treated as a loss in the state X.
  • the current path in the inverter circuit 12 changes with time as shown in FIGS. 13-1 and 13-2 by the new control process and the old control process.
  • the state of the inverter circuit 12 in which the old control process is being performed is the state 1, and the inverter instantaneous output current is negative. It is explanatory drawing of the current pathway in.
  • the state of the inverter circuit 12 in which the old control process is performed is the state 1, and the inverter instantaneous output current is positive. It is explanatory drawing of the current pathway in.
  • the state of the inverter circuit 12 in which the old control process is being performed is the state 5, and the inverter instantaneous output current is positive. It is explanatory drawing of the current pathway in.
  • the state of the inverter circuit 12 in which the old control process is being performed is the state 5 and the inverter instantaneous output current is negative. It is explanatory drawing of the current pathway in.
  • the state of the inverter circuit 12 in which the new control process is being performed is the state 1, and the inverter instantaneous output current is negative. It is explanatory drawing of the current pathway in.
  • the state of the inverter circuit 12 in which the new control process is performed is the state 1, and the inverter instantaneous output current is positive. It is explanatory drawing of the current pathway in.
  • the state of the inverter circuit 12 in which the new control process is performed is the state 5, and the inverter instantaneous output current is positive. It is explanatory drawing of the current pathway in.
  • the state of the inverter circuit 12 in which the new control process is performed is the state 5, and the inverter instantaneous output current is negative. It is explanatory drawing of the current pathway in.
  • the inverter instantaneous output current changes as shown in FIG. 14A. Therefore, the current path in the inverter circuit 12 (HERIC type circuit) changes during the period when the state of the inverter circuit 12 (HERIC type circuit) is the state 1 and during the period when the state 5 (FIG. 13-1 and FIG. Explanatory drawing (A1a) of 13-2, (A1b), (A5a) (refer (A5b)). Even when the sign of the inverter instantaneous output current changes during the new control process, the inverter instantaneous output current changes as shown in FIG. 14B.
  • the current path in the inverter circuit 12 changes during the period when the state of the inverter circuit 12 is the state 1 and during the period when the state 5 is (see FIGS. 13-1 and 13-2).
  • Explanatory drawing (B1a), (B1b), (B5a) (refer to (B5b)).
  • the recovery loss Err is treated as a loss in the state X.
  • the new control process As described above, even when the inverter instantaneous output current is 0 or more, the inverter circuit 12 is more efficient than the old control process even when the inverter instantaneous output current is less than 0. Operation (with less loss). Therefore, according to the new control process, it is always possible to operate the inverter circuit 12 more efficiently (with less loss) than the old control process.
  • the new control process reduces the leading edge side and the trailing edge side of each pulse supplied to the gate of each switching element by 1 ⁇ s in order to provide the 2 ⁇ s dead time described above (see “Condition 5”) It is processing.
  • the new control process when the inverter instantaneous output current is 0 or more, the current path changes with time as shown in the explanatory diagrams (B1) to (B8) in FIGS. 7-1 and 7-2. Therefore, in the new control process, when the inverter instantaneous output current is 0 or more, as shown in FIG. 16B, the dead time for “DDV ⁇ 4 ⁇ s” in total to compensate for the change in the output due to the dead time. It will be good to do compensation.
  • the current path changes with time as in the explanatory diagrams (A1) to (A8) in FIG. 11-1 and FIG. Then, as shown in the explanatory diagrams (B1) to (B8) in FIG. 11-1 and FIG. 11-2, the current path changes with time. Therefore, when the inverter instantaneous output current is less than 0, in the old control processing, as shown in FIG. 17A, in order to compensate for the change of the output due to the dead time, a total of “-DDV ⁇ 8 ⁇ s” dead It will be necessary to perform time compensation. On the other hand, in the new control process, when the inverter instantaneous output current is less than 0, as shown in FIG. 17B, in order to compensate for the change in the output due to the dead time, a total of “-DDV ⁇ 4 ⁇ s” dead It will be good to do time compensation.
  • the new control process is a process in which the amount of dead time compensation required to compensate for the change in output due to the dead time is smaller than that of the old control process. And since energy for performing dead time compensation is supplied from the DDV, according to the new control processing, the inverter circuit is obtained even if the DDV is low because the consumed DDV for the dead time compensation is small. 12 can function without problems. Therefore, the power conversion device 10 (power conditioner) is configured to set the minimum output voltage of the solar battery 35 which is determined to be operable lower.
  • the control unit 30 performs dead time compensation processing together with the above-described control processing.
  • the inverter instantaneous output current during one control process is 0 or more (that is, when a relatively large positive current is to be output) It is sufficient to compensate for the dead time by 4 ⁇ s, and when the inverter instantaneous output current during one control process is less than 0 (that is, when a relatively large negative current is to be output), A dead time compensation process for .times.4 .mu.s "may be performed.
  • the control unit 30 performs dead time compensation for “DDV ⁇ 4 ⁇ s”, and the output current If it is a predetermined threshold value ( ⁇ 0), dead time compensation for “ ⁇ DDV ⁇ 4 ⁇ s” is performed, and if the output current is near “0”, dead time compensation in an amount proportional to the output current Is configured to do.
  • the control unit 30 of the power conversion device 10 repeats the control process of turning on / off each switching element in the inverter circuit 12 so as to satisfy the conditions 1 to 6 described above. Therefore, according to the power conversion device 10 according to the present embodiment, the inverter circuit 12 (HERIC type circuit) can be operated more efficiently than in the related art.
  • the power conversion device 10 can perform various modifications.
  • the time from turning on switching elements UH and WL to turning on switching element US the time from turning on switching element WS to turning on switching elements UL and WH, turning off switching elements UL and WH
  • the time from when the switching element WS is turned on to the time when the switching element US is turned off until the switching elements UH and WL are turned on may be transformed into a device that is not the same.
  • the control unit 30 may be modified to perform dead time compensation processing in which the amount of dead time compensation increases stepwise as the output current increases, when the output current is near “0”. Also, it is natural that the function of performing dead time compensation may be removed from the power conversion device 10, or the power conversion device 10 may be transformed into a device that is not a power conditioner. is there.

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PCT/JP2018/007145 2017-07-27 2018-02-27 電力変換装置及び電力変換装置の制御方法 WO2019021517A1 (ja)

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US11404974B2 (en) 2019-01-22 2022-08-02 Sumitomo Electric Industries, Ltd. Power converter for performing conversion from DC to AC or vice versa, and method for controlling the power converter
CN115296556B (zh) * 2022-07-15 2024-07-05 华为数字能源技术有限公司 逆变器及其控制方法

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