WO2019021517A1 - Power conversion device and power conversion device control method - Google Patents

Power conversion device and power conversion device control method Download PDF

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Publication number
WO2019021517A1
WO2019021517A1 PCT/JP2018/007145 JP2018007145W WO2019021517A1 WO 2019021517 A1 WO2019021517 A1 WO 2019021517A1 JP 2018007145 W JP2018007145 W JP 2018007145W WO 2019021517 A1 WO2019021517 A1 WO 2019021517A1
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Prior art keywords
switching
turned
state
control
connection point
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PCT/JP2018/007145
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French (fr)
Japanese (ja)
Inventor
小林 健二
祐介 大内
溝上 恭生
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オムロン株式会社
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Priority to JP2017145321A priority Critical patent/JP6394760B1/en
Priority to JP2017-145321 priority
Application filed by オムロン株式会社 filed Critical オムロン株式会社
Publication of WO2019021517A1 publication Critical patent/WO2019021517A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Abstract

Provided is a technique with which a highly efficient and reliable inverter concept (HERIC) circuit can be controlled more efficiently. A control unit 30 controls each SW element of a HERIC circuit 12 so that: a SW element UL and a SW element WH turn on during a period in which a SW element US is on and a SW element WS is off; a SW element UH and a SW element WL turn on during a period in which the SW element US is off and the SW element WS is on; the SW element US turns on after the SW elements UH, WL have turned off and before the SW element WS turns off; and the SW element WS turns on after the SW elements UL, WH have turned off and before the SW element US turns off.

Description

POWER CONVERTER AND CONTROL METHOD OF POWER CONVERTER

The present invention relates to a power converter and a control method of the power converter, and more particularly, to a power converter including a full bridge circuit and a short circuit capable of shorting the output of the full bridge circuit, and such a power converter Control method of

A power conditioner for a solar cell includes a circuit having a full bridge circuit and a circuit for shorting the output of the full bridge circuit as shown in FIG. It is known that each switching element in the type circuit is turned ON / OFF as shown in FIG. 2 every switching cycle (T SW ) (see, for example, Patent Document 1).

JP, 2015-77061, A

An object of the present invention is to provide a technology capable of controlling a HERIC type circuit more efficiently.

In order to achieve the above object, a power converter according to the present invention includes a first output terminal and a second output terminal to which a load is connected, and a first switching element which is a high side switching element and a second side which is a low side switching element. A first leg including a switching element, a third leg including a third switching element which is a high side switching element, and a fourth switching element which is a low side switching element, the first switching of the first leg A first connection point which is a connection point of the element and the second switching element is connected to the first output terminal, and a second connection which is a connection point of the third switching element and the fourth switching element of the second leg. A full bridge inverter circuit whose point is connected to the second output terminal, and a short circuit between the first connection point and the second connection point A fifth switching element capable of turning on / off a current flowing from the second connection point side to the first connection point side, and from the first connection point side to the second connection point side. A short circuit including a sixth switching element capable of turning on / off a flowing current, and a control unit performing on / off control of each switching element in the full bridge inverter circuit and the short circuit, the fifth switching While the element is on and the sixth switching element is off, the second switching element and the third switching element are on, and the fifth switching element is off. And the first switching element and the fourth switching element are turned on while the sixth switching element is on, and the first switching element is turned on. After the fourth switching element is turned off and before the sixth switching element is turned off, the fifth switching element is turned on and the second and third switching elements are turned off, And a control unit that repeats a control process of turning on the sixth switching element before the fifth switching element is turned off.

The contents of the above-mentioned control processing of the control unit of the power conversion device are obtained as a result of intensive research conducted to improve the efficiency of the HERIC type circuit (full bridge circuit and short circuit). According to the above control process, during processing (control), current flows through a path different from that of the conventional one (see FIG. 2) (details will be described later). be able to.

In the control process executed by the control unit of the power conversion device according to the present invention, the fifth switching element is turned on and the sixth switching element is turned off after the first predetermined time after the first and fourth switching elements are turned off. The second and third switching elements are turned on after a second predetermined time from the second to the third switching elements are turned on after a third predetermined time after the second and third switching elements are turned off, and the fifth switching element is turned on It may be processing to turn on the first and fourth switching elements after a fourth predetermined time after turning off. The first to fourth predetermined times may be the same time, or may be times determined in accordance with the turn-on / off times of the switching elements to be switched.

Further, the control unit of the power conversion device according to the present invention performs dead time compensation processing for compensating for distortion of an output waveform due to providing the first to fourth predetermined times between control timings of switching elements together with the control processing. May be performed.

Further, according to a control method of a power conversion device of the present invention, a first output terminal and a second output terminal to which a load is connected, a first switching element as a high side switching element, and a second switching element as a low side switching element And a second leg including a third switching element that is a high side switching element and a fourth switching element that is a low side switching element, and the first switching element of the first leg and the first leg A first connection point, which is a connection point of a second switching element, is connected to the first output terminal, and a second connection point, which is a connection point of the third switching element and the fourth switching element of the second leg, is the A full bridge inverter circuit connected to a second output terminal, and a short circuit capable of shorting between the first connection point and the second connection point A fifth switching element capable of turning on / off a current flowing from the second connection point side to the first connection point side, and a current flowing from the first connection point side to the second connection point side And a short circuit including a sixth switching element that can be turned on / off. And in the control method of the power converter according to the present invention, the second switching element is in a period in which the fifth switching element is turned on and the sixth switching element is turned off by a computer. And the third switching element is on, the fifth switching element is off, and the first switching element and the fourth switching element are in a period during which the sixth switching element is on. Are turned on, and the fifth switching element is turned on before the sixth switching element is turned off after the first and fourth switching elements are turned off, and the second and third switching elements are turned on. Control to turn on the sixth switching element after the second switching element is turned off and before the fifth switching element is turned off. The process is repeated.

According to the control method of the power conversion device of the present invention, during control of the HERIC type circuit, current flows in a different path from the conventional one (see FIG. 2), so the HERIC type circuit is more efficient than the conventional one. Can operate. The “computer” in the control method of the power conversion device of the present invention may be a computer (control unit or the like) in the power conversion device or a computer outside the power conversion device.

According to the present invention, it is possible to provide a technology capable of controlling a HERIC type circuit more efficiently.

FIG. 1 is an explanatory view of a HERIC type circuit. FIG. 2 is a timing chart for explaining the contents of conventional control processing of the HERIC type circuit. FIG. 3 is an explanatory view of a configuration and a usage pattern of the power conversion device according to the embodiment of the present invention. FIG. 4 is an explanatory diagram of a configuration of an inverter circuit included in the power conversion device according to the embodiment. FIG. 5 is a timing chart for explaining the contents of control processing performed by the control unit included in the power conversion device according to the embodiment. FIG. 6A is an explanatory view of the ON / OFF state of each switching element in each state formed by the old control process (conventional control process) and the output voltage of the inverter circuit in each state. FIG. 6B is an explanatory diagram of ON / OFF states of the switching elements in each state formed by the new control process (control process performed by the control unit) and an output voltage of the inverter circuit in each state. FIG. 7-1 is an explanatory diagram of current paths during old control processing and new control processing when the inverter instantaneous output current is 0 or more. FIG. 7-2 is an explanatory diagram of a current path during old control processing and new control processing in the case where the inverter instantaneous output current is 0 or more, following FIG. 7-1. FIG. 8-1 is a diagram for explaining the loss that occurs in each state when the inverter instantaneous output current is 0 or more due to the execution of the old control process. FIG. 8-2 is a diagram for describing the loss that occurs in each state when the instantaneous inverter output current is 0 or more due to the execution of the old control processing, which is subsequent to FIG. 8-1. FIG. 9-1 is a diagram for explaining the loss that occurs in each state when the inverter instantaneous output current is 0 or more due to the execution of the new control process. FIG. 9-2 is a diagram for explaining the loss that occurs in each state when the instantaneous inverter output current is 0 or more due to the execution of the new control process, following FIG. 9-1. FIG. 10A is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is 0 or more, due to the old control processing. FIG. 10B is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is 0 or more, by the new control process. FIG. 11A is an explanatory diagram of current paths during old control processing and new control processing when the inverter instantaneous output current is less than zero. FIG. 11-2 is an explanatory diagram of a current path during old control processing and new control processing in the case where the inverter instantaneous output current is less than 0, following FIG. 11-1. FIG. 12A is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is less than 0 due to the old control processing. FIG. 12B is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is less than 0 by the new control process. FIG. 13A is an explanatory diagram of a current path during old control processing and new control processing when the sign of the inverter instantaneous output current changes. FIG. 13-2 is an explanatory diagram of a current path during old control processing and new control processing in the case where the sign of the inverter instantaneous output current changes, following FIG. 13-1. FIG. 14A is an explanatory diagram of the inverter instantaneous output current generated by the old control process when the output current is small. FIG. 14B is an explanatory diagram of the inverter instantaneous output current generated by the new control process when the output current is small. FIG. 15A is an explanatory diagram of the number of occurrences of various losses when the sign of the inverter instantaneous output current changes due to the old control processing. FIG. 15B is an explanatory diagram of the number of occurrences of various losses when the sign of the inverter instantaneous output current changes due to the new control process. FIG. 16A is a diagram for explaining the amount of dead time compensation that is required when the old control processing is performed under the condition that the inverter instantaneous output current is 0 or more. FIG. 16B is a diagram for describing the amount of dead time compensation that is required when the new control process is performed under the situation where the inverter instantaneous output current is 0 or more. FIG. 17A is a diagram for explaining the amount of dead time compensation that is required when the old control processing is performed in a situation where the inverter instantaneous output current is less than zero. FIG. 17B is a diagram for explaining the amount of dead time compensation required when performing new control processing under a situation where the inverter instantaneous output current is less than zero. FIG. 18A is a diagram for describing the amount of dead time compensation that is required when the old control processing is performed under the situation where the sign of the inverter instantaneous output current changes. FIG. 18B is a diagram for explaining the amount of dead time compensation that is required when new control processing is performed in a situation where the sign of the inverter instantaneous output current changes. FIG. 19 is an explanatory diagram of a dead time compensation process performed by the control unit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The configuration of the embodiment described below is an exemplification, and the present invention is not limited to the configuration of the embodiment.

FIG. 3 shows the configuration and usage of the power conversion device 10 according to an embodiment of the present invention.

The power conversion device 10 according to the present embodiment is a power conditioner that can be connected to a grid and used in connection with a solar cell (solar cell array) 35. As illustrated, the power conversion device 10 includes a booster circuit 11, an inverter circuit (INV circuit) 12, a pair of output terminals 21 and 22, and a control unit 30.

The pair of output terminals 21 and 22 included in the power conversion device 10 are output terminals to which an AC consumer device in the home is connected as the load 40 and to which the output of the inverter circuit 12 is supplied at the time of a self sustaining operation. A capacitor 17 is disposed between the output terminals 21 and 22. In addition, since the power conversion device 10 can be interconnected with the system, the power conversion device 10 also includes a pair of output terminals (not shown) to which the output of the inverter circuit 12 is supplied during the interconnection operation.

The boosting circuit 11 is a boosting chopper circuit in which a switching element and a passive element (reactor, diode or the like) are combined in order to boost the output voltage of the solar cell 35. A capacitor 15 is disposed between the input terminals of the booster circuit 11 (between the input terminals of the power conversion device 10).

The inverter circuit 12 is a HERIC type circuit (details will be described later) for converting a DC voltage output from the booster circuit 11 into an AC voltage. As illustrated, a capacitor 16 is disposed between the input terminals of the inverter circuit 12 (between the output terminals of the booster circuit 11). Further, each output terminal of the inverter circuit 12 is connected to the output terminal 21 or the output terminal 22 via the reactor 18.

Hereinafter, the configuration of the inverter circuit 12 will be more specifically described with reference to FIG.

As shown in FIG. 4, the inverter circuit 12 is a full bridge circuit composed of a first leg 25 and a second leg 26 connected in parallel between a pair of input terminals 23 p and 23 n of the inverter circuit 12. Prepare.

The first leg 25 is composed of switching elements UH and UL connected in series, and a free wheeling diode disposed between the emitters and collectors of the switching elements (IGBTs). The second leg 26 is configured of the switching elements WH and WL connected in series, and a free wheeling diode disposed between the emitter and the collector of each switching element. The connection point 25c of the switching element UH and UL of the first leg 25 is connected to the output terminal 21 through the reactor 18, and the connection point 26c of the switching elements WH and WL of the second leg 26 is It is connected to the output terminal 22 via the reactor 18. The input terminal 23p is an input terminal on the high potential side. Therefore, the switching elements UH and WH are high side switching elements, and the switching elements UL and WL are low side switching elements.

Furthermore, the inverter circuit 12 includes a short circuit 27. As shown, the short circuit 27 includes a switching element WS having an emitter connected to the connection point 25c, a switching element US having a collector connected to the collector of the switching element WS, and an emitter connected to the connection point 26c. And a free wheeling diode disposed between the emitter and the collector of each switching element. That is, the short circuit 27 can turn on / off the current flowing from the connection point 25c side to the connection point 26c side (the current flowing from the output terminal 21 side to the output terminal 22 side) by turning on / off the switching element WS. At the same time, the on / off of the switching element US makes it possible to turn on / off the current flowing from the connection point 26c to the connection point 25c.

Returning to FIG. 3, the description of the configuration of the power conversion device 10 will be continued.

The control unit 30 is a unit that integrally controls each unit (the booster circuit 11 and the inverter circuit 12) in the power conversion device 10. The control unit 30 is composed of a processor (CPU, microcontroller, etc.) and its peripheral circuits, and in the control unit 30, sensors (current sensor, voltage sensor; not shown) provided at various places of the power conversion device 10. The output of is input.

Hereinafter, the control function of the inverter circuit 12 in the self-sustaining operation of the control unit 30 of the power conversion device 10 according to the present embodiment will be described.

The control unit 30 is configured (programming) so as to repeat control processing of turning on / off each switching element in the inverter circuit 12 in the pattern shown in FIG. 5 every switching cycle (T SW ) during the self-sustaining operation. It is done.

That is, at the time of control processing, control unit 30 turns on / off each switching element in inverter circuit 12 so as to satisfy the following conditions.

Condition 1: While the switching element US is on and the switching element WS is off, the switching element UL and the switching element WH are on. Condition 2: The switching element UH and the switching element WL are turned on while the switching element US is off and the switching element WS is on. Condition 3: The switching element US is turned on after the switching elements UH and WL are turned off and before the switching element WS is turned off. Condition 4: The switching element WS is turned on after the switching elements UL and WH are turned off and before the switching element US is turned off. Condition 5: The time from turning on the switching elements UH and WL to turning on the switching element US, the time from turning on the switching element WS to turning on the switching elements UL and WH, turning off the switching elements UL and WH The time from when the switching element WS is turned on to the time from when the switching element US is turned off to when the switching elements UH and WL are turned on all have a preset dead time (in the present embodiment, 2 μs).

The contents of this control process are obtained as a result of earnest research conducted to improve the efficiency of the inverter circuit 12 which is a HERIC type circuit. Hereinafter, the effect obtained by the control process will be specifically described by comparing with the conventional control process (FIG. 2). In the following, the HERIC type circuit shown in FIG. 1 is also referred to as the inverter circuit 12, and the input voltage of the inverter circuit 12 (the output voltage of the booster circuit 11 and the voltage between the terminals of the capacitor 16) is referred to as DDV. write. Further, the conventional control process (FIG. 2) and the control process (FIG. 5) performed by the control unit 30 will be referred to as an old control process and a new control process, respectively.

FIG. 6A shows ON / OFF states of the switching elements in the states 1 to 8 formed by the old control process (FIG. 2), together with the output voltage of the inverter circuit 12 in each state. Further, FIG. 6B shows ON / OFF states of the switching elements in the states 1 to 8 formed by the new control process (FIG. 5), together with the output voltage of the inverter circuit 12 in each state.

As apparent from these figures, in the new control process, each switching element in the full bridge circuit of the inverter circuit 12 is on / off controlled in the same manner as the old control process. However, in the new control process, the control contents for the switching elements US and WS are completely different from the old control process. Therefore, when the new control process is performed, the current path in the inverter circuit 12 changes with time in a pattern different from that in the old control process.

Hereinafter, the difference in time change pattern of the current path in the inverter circuit 12 due to the new control processing and the old control processing is less than 0 when the inverter instantaneous output current during one control processing (during one switching cycle) is 0 or more. And the case where the sign of the inverter instantaneous output current changes during one control process will be described separately.

In the case where the inverter instantaneous output current ≧ 0 In this case, the current path in the inverter circuit 12 temporally changes as shown in FIGS. 7-1 and 7-2 by the new control process and the old control process. The diagrams labeled (An) (n = 1 to 8) in FIGS. 7-1 and 7-2 correspond to the state n in the inverter circuit 12 where the old control process is being performed. It is explanatory drawing of a current pathway. The diagrams labeled (Bn) (n = 1 to 8) in FIGS. 7-1 and 7-2 are current paths in the state n in the inverter circuit 12 in which the new control process is performed. FIG. In each explanatory view, a switching element whose name (“UH”, “WH”, etc.) is enclosed by a rectangular frame is a switching element which is turned on.

As is clear from FIGS. 7-1 and 7-2, the current paths in the inverter circuit 12 in the states 1, 3 to 7 are the same even when the old control process is performed or the new control process is performed. It will be the same. However, when new control processing is performed, in the state 2 (see the explanatory diagrams (A2) and (B2)) and the state 8 (see the explanatory diagrams (A8) and (B8)), the inside of the inverter circuit 12 is Current flows in a different path from when processing is performed.

As is clear from FIGS. 7-1 and 7-2, the current paths in the inverter circuit 12 in the states 1, 3 to 7 are the same even when the old control process is performed or the new control process is performed. It will be the same. However, when new control processing is performed, in the state 2 (see the explanatory diagrams (A2) and (B2)) and the state 8 (see the explanatory diagrams (A8) and (B8)), the inside of the inverter circuit 12 is Current flows in a different path from when processing is performed.

Therefore, according to the new control process, the inverter circuit 12 can be controlled more efficiently than the old control process.

Specifically, in the inverter circuit 12, a turn-on loss Eon, a turn-off loss Eoff and a conduction loss Esat of each switching element, and a conduction loss Ef and a recovery loss Err of each diode may occur. If the turn-on loss Eon generated at the transition to the state X (X = 1 to 8), the turn-off loss Eoff generated at the transition from the state X to the next state, and the recovery loss Err are treated as losses in the state X, old control processing Then, each loss will occur as shown in FIGS. 8-1 and 8-2.

That is, as shown in FIG. 8-1, when the old control process is performed, current flows through switching element UH and switching element WL in state 1, and therefore, conduction loss Esat of switching element UH and the switching element A conduction loss Esat of WL occurs. Further, at the time of transition from state 1 to state 2, the switching elements UH and WL in which current flows are turned off, and the output potential of the inverter circuit 12 is inverted. Therefore, when the transition from state 1 to state 2, and the recovery loss Err of turn-off loss Eoff and the diode D WS of the turn-off loss Eoff and switching element WL of the switching elements UH occurs. In the above description and the following description, the diode D α (α = WS, UH, etc.) is a free wheeling diode connected in parallel to the switching element α.

Further, at the time of transition from the state 8 (see Figure 8-2) to state 1, the switching elements UH and WL is turned on, the current flowing through diode D UL and D WH is to flow through the switching elements UH and WH As a result, the output potential of the inverter circuit 12 is inverted. Therefore, at the time of transition from state 8 to state 1, turn-on loss Eon of switching elements UH and WL occurs and recovery loss Err of diodes D UL , D WH and D US occur. However, as already described, the diode D UL, recovery loss Err of D WH and D US are treated as a loss in the state 8. Therefore, in state 1, as shown in FIG. 8-1, turn-on loss Eon, turn-off loss Eoff, conduction loss Esat, and recovery loss Err occur twice, twice, once, respectively. become.

Further, as is shown in Figure 8-1, in state 2, since the flow through the diode D UL and the diode D WH current, the conduction loss Ef conduction losses Ef and the diode D WH diode D UL occurs . Then, at the time of transition from state 2 to state 3, the switching elements US and WS are turned on, and the current flowing through the diodes DUL and DWH flows through the diode DUS and the switching element WS. Therefore, although conduction loss Ef of the diode D UL and D WH and the turn-on loss Eon of the switching element WS occurs, the turn-on loss Eon of the switching element WS is treated as a loss of state 3. Therefore, in the state 2, the conduction loss Ef and the recovery loss Err occur twice each.

As shown in FIG. 8-1, in the state 3, current flows through the diode D US and the switching element WS. In addition, at the time of transition from state 3 to state 4, the switching element WS through which current flows is turned off. Then, as described above, since the turn-on loss Eon of the switching element WS occurs at the transition from the state 2 to the state 3, in the state 3, the turn-on loss Eon, the turn-off loss Eoff, the conduction loss Esat, the conduction loss Ef , Each occurs once.

As shown in FIG. 8-1, in state 4, current flows through the diode D UL and the diode D WH . Therefore, in state 4, conduction loss Ef occurs twice. Although the switching elements UL and WH are turned on at the transition from the state 4 to the state 5, even if the switching elements UL and WH are turned on, no current flows in each switching element. Therefore, in the state 4, the turn-on loss Eon does not occur, but only the conduction loss Ef occurs twice.

As shown in FIG. 8-2, in state 5 also, current flows through the diode D UL and the diode D WH . Since no current flows in switching elements UL and WH in state 5, turn-off loss Eoff does not occur even if switching elements UL and WH are turned off at the time of transition to state 6. Therefore, in state 5, only conduction loss Ef occurs twice.

As shown in FIG. 8-2, in state 6, current also flows through the diode D UL and the diode D WH . Therefore, conduction loss Ef of diode D UL and conduction loss Ef of diode D WH occur. Further, at the time of transition from state 6 to state 7, the switching element WS is turned on, and the current flowing through the diodes DUL and DWH flows through the diode DUS and the switching element WS. Therefore, when the transition from state 6 to state 7, and turn-on loss Eon of recovery loss of the diode D UL and D WH Err and the switching element WS occurs. However, since the turn-on loss Eon of the switching element WS is treated as a loss of the state 7, the conduction loss Ef and the recovery loss Err occur twice each in the state 6.

As it is shown in Figure 8-2, in the state 7, since the flow through the diode D US and the switching element WS current, the conduction loss Esat conduction losses Ef and the switching element WS diode D US occurs. Also, as described above, at the transition from state 6 to state 7, turn-on loss Eon of switching element WS occurs. Furthermore, at the time of transition from state 7 to state 8, the switching element WS through which current flows is turned off, so that the turn-off loss Eoff of the switching element WS occurs. Therefore, in the state 7, the turn-on loss Eon, the turn-off loss Eoff, the conduction loss Esat and the conduction loss Ef occur once respectively.

As shown in FIG. 8-2, in the transition from the state 7 to the state 8, the switching element WS in which the current is flowing is turned off, and after the transition to the state 8, the diode D UL and the diode D WH are A current flows. Then, as described above, at the time of transition from state 8 to state 1, recovery losses Err of diodes D UL , D WH and D US occur, so that conduction loss Ef occurs twice in state 8 and recovery Loss Err occurs 3 times.

On the other hand, when new control processing is performed, each loss occurs as shown in FIGS. 9-1 and 9-2.

That is, as shown in FIG. 9-1, even when the new control process is performed, the state changes from state 8 to state 1 as in the case where the old control process is performed (see FIG. 8-1). At the time of transition, the switching element UH and the switching element WL are turned on. Further, even when the new control process is performed, current flows through the switching element UH and the switching element WL after the transition of the state 1 as in the case where the old control process is performed. Therefore, even in state 1 when the new control processing is performed, the turn-on loss Eon of the switching elements UH and WL and the conduction loss Esat of the switching elements UH and WL occur.

In addition, even in the new control process, at the time of transition from state 1 to state 2, the switching elements UH and WL in which current flows are turned off. Therefore, the turn-off loss Eoff of the switching elements UH and WL occurs even in the state 1 when the new control process is performed. However, when a new control process is performed, the output potential of the inverter circuit 12 is not inverted when transitioning from the state 1 to the state 2 as shown in FIG. 9-1. Therefore, in state 1 when new control processing is performed, the recovery loss Err does not occur (see FIG. 8-1), and the turn-on loss Eon, the turn-off loss Eoff, and the conduction loss Esat occur twice each. It will be done.

When a new control process is being performed, current flows through the diode D US and the switching element WS in the state 2 as shown in FIG. 9-1. Therefore, in state 2, and the conduction loss Ef conduction losses Esat and diode D US switching element WS generated. Further, at the time of transition from state 2 to state 3, the switching element US is turned on. However, even if the switching element US is turned on, no current flows in the switching element US, so the turn-on loss Eon of the switching element US does not occur. Therefore, in the state 2, the conduction loss Esat and the conduction loss Ef respectively occur once.

Also in state 3, since the flow through the diode D US and the switching element WS current, the conduction loss Esat conduction losses of the diode D US Ef and the switching element WS occurs. Further, at the time of transition from state 3 to state 4, the switching element WS in the state in which current is flowing is turned off, so that the turn-off loss Eoff of the switching element WS occurs. Therefore, in state 3, the turn-off loss Eoff, the conduction loss Esat, and the conduction loss Ef occur once each.

As shown in FIG. 9-1, in the state 4, current flows through the diode D UL and the diode D WH . In addition, at the time of transition from state 4 to state 5, the switching elements UL and WH are turned on, but no current flows in each switching element even if each switching element is turned on. Therefore, in the state 4, the conduction loss Ef occurs twice without the occurrence of the turn-on loss Eon.

Also in the state 5, as in the state 4, current flows through the diode D UL and the diode D WH . At the time of transition from state 5 to state 6, switching elements UL and WH are turned off. However, as shown in FIG. 9-1, since no current flows through switching elements UL and WH in state 5, turn-off loss Eoff does not occur. Therefore, in state 5, only conduction loss Ef occurs twice.

As it is shown in Figure 9-2, in the state 6, to flow a diode D UL and the diode D WH current, the conduction loss Ef conduction losses Ef and the diode D WH diode D UL occurs. Further, at the time of transition from state 6 to state 7, the switching element WS is turned on, and the current flowing through the diodes DUL and DWH flows through the diode DUS and the switching element WS. Therefore, when the transition from state 6 to state 7, and turn-on loss Eon of recovery loss of the diode D UL and D WH Err and the switching element WS occurs. However, since the turn-on loss Eon of the switching element WS is treated as a loss of the state 7, the conduction loss Ef and the recovery loss Err occur twice each in the state 6.

In state 7, current flows through the diode D US and the switching element WS. Also, as described above, at the transition from state 6 to state 7, turn-on loss Eon of switching element WS occurs. Then, at the transition from the state 7 to the state 8, since the switching element US in which no current flows is only turned off, no particular loss occurs. Therefore, in the state 7, as shown in FIG. 9-2, the turn-on loss Eon, the conduction loss Esat and the conduction loss Ef are generated once each.

Also in the state 8, since current flows through the diode D US and the switching element WS, a conduction loss Esat of the switching element WS and a conduction loss Ef of the diode D US occur. Then, when transitioning from state 8 to state 1, the output potential of inverter circuit 12 is inverted and recovery loss Err of diode D US occurs, so that in state 8 conduction loss Esat, conduction loss Ef and recovery loss Err Each will occur once.

As described above, when the number of occurrences of each loss described for each control process and each state is summarized, when the old control process is performed, each loss is generated as illustrated in FIG. 10A and the new control process is performed. Will cause each loss as shown in FIG. 10B.

As apparent from these figures, when inverter instantaneous output current 00, the total of conduction losses of the switching element and the free wheeling diode does not change if new control processing is performed, but switching losses (turn-on loss, turn-off loss and Recovery losses can be reduced seven times in total. Therefore, if new control processing is performed when the inverter instantaneous output current 00, the inverter circuit 12 can be operated more efficiently (with less loss) than the old control processing.

Case where Inverter Instantaneous Output Current <0 In this case, the current path in the inverter circuit 12 changes with time as shown in FIGS. 11-1 and 11-2 by the new control process and the old control process. The diagrams labeled (An) (n = 1 to 8) in FIGS. 11-1 and 11-2 are the states in the inverter circuit 12 where the old control process is being performed. It is explanatory drawing of a current pathway. The diagrams labeled (Bn) (n = 1 to 8) in FIGS. 11-1 and 11-2 are current paths in the state n in the inverter circuit 12 in which the new control process is performed. FIG. In each explanatory view, a switching element whose name (“UH”, “WH”, etc.) is enclosed by a rectangular frame is a switching element which is turned on.

As is apparent from FIGS. 11-1 and 11-2, in any of the control processes, the current paths in the inverter circuit 12 in the states 1 to 3, 5, 7 and 8 are the same. However, when new control processing is performed, the state of the inverter circuit 12 is in the state 4 (see the explanatory diagrams (A4) and (B4)) and in the state 6 (see the explanatory diagrams (A6) and (B6)) Then, current flows in the inverter circuit 12 through a path different from that in the old control process.

Therefore, when the old control process and the new control process are performed, the turn-on loss Eon, turn-off loss Eoff and conduction loss Esat of the switching element and the number of occurrences of conduction loss Ef of the diode and recovery loss Err are shown in FIG. It becomes what was shown to 12B. The number of times of occurrence of each loss shown in these figures is also the turn-on loss Eon generated at the transition to the state X (X = 1 to 8), the turn-off loss Eoff generated at the transition from the state X to the next state The recovery loss Err is treated as a loss in the state X.

As apparent from FIGS. 12A and 12B, when the inverter instantaneous output current is less than 0, the total of the conduction loss of the switching element and the free wheeling diode does not change if new control processing is performed, but the switching loss (turn on loss, turn off Losses and recovery losses) can be reduced a total of seven times. Therefore, if the new control process is performed when the inverter instantaneous output current is less than 0, the inverter circuit 12 can be operated more efficiently (with less loss) than the old control process.

When the sign of the inverter instantaneous output current changes: The current path in the inverter circuit 12 changes with time as shown in FIGS. 13-1 and 13-2 by the new control process and the old control process.

The diagrams labeled (An) (n = 2 to 4, 6 to 8) in FIGS. 13A and 13B are the states in the inverter circuit 12 in which the old control process is being performed. It is explanatory drawing of the current pathway in n. In the diagram labeled (A1a) in FIG. 13A, the state of the inverter circuit 12 in which the old control process is being performed is the state 1, and the inverter instantaneous output current is negative. It is explanatory drawing of the current pathway in. In the diagram labeled (A1b) in FIG. 13A, the state of the inverter circuit 12 in which the old control process is performed is the state 1, and the inverter instantaneous output current is positive. It is explanatory drawing of the current pathway in. In the diagram labeled (A5a) in FIG. 13-2, the state of the inverter circuit 12 in which the old control process is being performed is the state 5, and the inverter instantaneous output current is positive. It is explanatory drawing of the current pathway in. In the diagram labeled (A5b) in FIG. 13B, the state of the inverter circuit 12 in which the old control process is being performed is the state 5 and the inverter instantaneous output current is negative. It is explanatory drawing of the current pathway in.

The diagrams labeled (Bn) (n = 2 to 4, 6 to 8) in FIGS. 13-1 and 13-2 are the states in the inverter circuit 12 in which the new control process is being performed. It is explanatory drawing of the current pathway in n. In the diagram labeled (B1a) in FIG. 13A, the state of the inverter circuit 12 in which the new control process is being performed is the state 1, and the inverter instantaneous output current is negative. It is explanatory drawing of the current pathway in. In the diagram labeled (B1b) in FIG. 13A, the state of the inverter circuit 12 in which the new control process is performed is the state 1, and the inverter instantaneous output current is positive. It is explanatory drawing of the current pathway in. In the diagram labeled (B5a) in FIG. 13B, the state of the inverter circuit 12 in which the new control process is performed is the state 5, and the inverter instantaneous output current is positive. It is explanatory drawing of the current pathway in. In the diagram labeled (B5b) in FIG. 13B, the state of the inverter circuit 12 in which the new control process is performed is the state 5, and the inverter instantaneous output current is negative. It is explanatory drawing of the current pathway in.

That is, when the sign of the inverter instantaneous output current changes during the old control process, the inverter instantaneous output current changes as shown in FIG. 14A. Therefore, the current path in the inverter circuit 12 (HERIC type circuit) changes during the period when the state of the inverter circuit 12 (HERIC type circuit) is the state 1 and during the period when the state 5 (FIG. 13-1 and FIG. Explanatory drawing (A1a) of 13-2, (A1b), (A5a) (refer (A5b)). Even when the sign of the inverter instantaneous output current changes during the new control process, the inverter instantaneous output current changes as shown in FIG. 14B. Therefore, also during the new control process, the current path in the inverter circuit 12 changes during the period when the state of the inverter circuit 12 is the state 1 and during the period when the state 5 is (see FIGS. 13-1 and 13-2). Explanatory drawing (B1a), (B1b), (B5a) (refer to (B5b)).

From FIG. 13-1 and FIG. 13-2, occurrence of turn-on loss Eon, turn-off loss Eoff, conduction loss Esat of the switching element, conduction loss Ef of the diode and recovery loss Err when the old control process and the new control process are performed. When the number of times is counted, the number of occurrences of each loss when the old control process is performed is as shown in FIG. 15A. Further, the number of occurrences of each loss when the new control process is performed is as shown in FIG. 15B. The number of times of occurrence of each loss shown in these figures is also the turn-on loss Eon generated at the transition to the state X (X = 1 to 8), the turn-off loss Eoff generated at the transition from the state X to the next state The recovery loss Err is treated as a loss in the state X.

As apparent from FIGS. 15A and 15B, when the sign of the inverter instantaneous output current changes, the total of the conduction loss of the switching element and the free wheeling diode does not change if new control processing is performed, but the switching loss (turn on loss, turn off Losses and recovery losses) can be reduced a total of eight times.

Then, according to the new control process, as described above, even when the inverter instantaneous output current is 0 or more, the inverter circuit 12 is more efficient than the old control process even when the inverter instantaneous output current is less than 0. Operation (with less loss). Therefore, according to the new control process, it is always possible to operate the inverter circuit 12 more efficiently (with less loss) than the old control process.

Moreover, according to the new control processing, it is also possible to reduce the dead time compensation amount.

Specifically, the new control process reduces the leading edge side and the trailing edge side of each pulse supplied to the gate of each switching element by 1 μs in order to provide the 2 μs dead time described above (see “Condition 5”) It is processing.

Assuming that the old control process is also a process of reducing the leading edge side and the trailing edge side of each pulse supplied to the gate of each switching element by 1 μs, when the inverter instantaneous output current is 0 or more, FIG. And in the old control process in which the current path changes with time as in the explanatory diagrams (A1) to (A8) in FIG. 7-2, DDV should be originally output at the time of transition from state 1 to state 2 Nevertheless, there will be a 1 μs time for DDV to be output. In addition, at the time of transition from state 2 to state 3, there is also 1 μs of time during which -D DV is output, although 0 V should be originally output. Similarly, regarding the other transitions, in the old control process, when the inverter instantaneous output current is 0 or more, as shown in FIG. 16A, in order to compensate for the change in the output due to the dead time, It will be necessary to perform dead time compensation for “DDV × 8 μs” in total.

On the other hand, in the new control process, when the inverter instantaneous output current is 0 or more, the current path changes with time as shown in the explanatory diagrams (B1) to (B8) in FIGS. 7-1 and 7-2. Therefore, in the new control process, when the inverter instantaneous output current is 0 or more, as shown in FIG. 16B, the dead time for “DDV × 4 μs” in total to compensate for the change in the output due to the dead time. It will be good to do compensation.

Also, when the inverter instantaneous output current is less than 0, in the old control process, the current path changes with time as in the explanatory diagrams (A1) to (A8) in FIG. 11-1 and FIG. Then, as shown in the explanatory diagrams (B1) to (B8) in FIG. 11-1 and FIG. 11-2, the current path changes with time. Therefore, when the inverter instantaneous output current is less than 0, in the old control processing, as shown in FIG. 17A, in order to compensate for the change of the output due to the dead time, a total of “-DDV × 8 μs” dead It will be necessary to perform time compensation. On the other hand, in the new control process, when the inverter instantaneous output current is less than 0, as shown in FIG. 17B, in order to compensate for the change in the output due to the dead time, a total of “-DDV × 4 μs” dead It will be good to do time compensation.

Also, when the sign of the inverter instantaneous output current changes, in the old control process, the current path changes with time as in the explanatory diagrams (A1a) to (A8) in FIGS. 13-1 and 13-2. The current paths change with time as illustrated in (B1a) to (B8) in FIGS. 13-1 and 13-2. Therefore, when the sign of the inverter instantaneous output current changes, in the old control processing, as shown in FIG. 18A, it is not necessary to compensate for the change in the output due to the dead time. Further, even in the new control process, as shown in FIG. 18B, it is not necessary to compensate for the change in the output due to the dead time.

As apparent from the above description, the new control process is a process in which the amount of dead time compensation required to compensate for the change in output due to the dead time is smaller than that of the old control process. And since energy for performing dead time compensation is supplied from the DDV, according to the new control processing, the inverter circuit is obtained even if the DDV is low because the consumed DDV for the dead time compensation is small. 12 can function without problems. Therefore, the power conversion device 10 (power conditioner) is configured to set the minimum output voltage of the solar battery 35 which is determined to be operable lower.

Finally, dead time compensation processing performed by the control unit 30 will be described.
The control unit 30 performs dead time compensation processing together with the above-described control processing. As described above, in the control process performed by the control unit 30, when the inverter instantaneous output current during one control process is 0 or more (that is, when a relatively large positive current is to be output) It is sufficient to compensate for the dead time by 4 μs, and when the inverter instantaneous output current during one control process is less than 0 (that is, when a relatively large negative current is to be output), A dead time compensation process for .times.4 .mu.s "may be performed.

Therefore, as schematically shown in FIG. 19, when the output current is a predetermined threshold (> 0), the control unit 30 performs dead time compensation for “DDV × 4 μs”, and the output current If it is a predetermined threshold value (<0), dead time compensation for “−DDV × 4 μs” is performed, and if the output current is near “0”, dead time compensation in an amount proportional to the output current Is configured to do.

As described above, the control unit 30 of the power conversion device 10 according to the present embodiment repeats the control process of turning on / off each switching element in the inverter circuit 12 so as to satisfy the conditions 1 to 6 described above. Therefore, according to the power conversion device 10 according to the present embodiment, the inverter circuit 12 (HERIC type circuit) can be operated more efficiently than in the related art.

<< Modified form >>
The power conversion device 10 according to the above-described embodiment can perform various modifications. For example, the time from turning on switching elements UH and WL to turning on switching element US, the time from turning on switching element WS to turning on switching elements UL and WH, turning off switching elements UL and WH The time from when the switching element WS is turned on to the time when the switching element US is turned off until the switching elements UH and WL are turned on may be transformed into a device that is not the same.

The control unit 30 may be modified to perform dead time compensation processing in which the amount of dead time compensation increases stepwise as the output current increases, when the output current is near “0”. Also, it is natural that the function of performing dead time compensation may be removed from the power conversion device 10, or the power conversion device 10 may be transformed into a device that is not a power conditioner. is there.

DESCRIPTION OF SYMBOLS 10 Power conversion apparatus 11 Boost circuit 12 Inverter circuit 15, 16, 17 Capacitor 18 Reactor 21, 22 Output terminal 23p, 23n Input terminal 25c, 26c Connection point 25 1st leg 26 2nd leg 27 Short circuit 30 Control part 35 Solar battery 40 load

Claims (4)

  1. A first output terminal and a second output terminal to which a load is connected;
    A first leg including a first switching element as a high side switching element and a second switching element as a low side switching element; a third switching element as a high side switching element; and a fourth switching element as a low side switching element And a second connection point, which is a connection point between the first switching element and the second switching element, of the first leg is connected to the first output terminal, and the second leg includes the second leg. A full bridge inverter circuit in which a second connection point, which is a connection point of a third switching element and the fourth switching element, is connected to the second output terminal;
    A fifth switching element that is a short circuit capable of shorting between the first connection point and the second connection point, and capable of turning on / off a current flowing from the second connection point side to the first connection point side A short circuit including a sixth switching element capable of turning on / off a current flowing from the first connection point side to the second connection point side;
    A control unit that performs on / off control of each switching element in the full bridge inverter circuit and the short circuit, wherein the fifth switching element is on, and the sixth switching element is off. During the period, the second switching element and the third switching element are turned on, the fifth switching element is turned off, and the sixth switching element is on. After the first switching element and the fourth switching element are turned on, and the first and fourth switching elements are turned off, and before the sixth switching element is turned off, the fifth switching element is selected. After the second and third switching elements are turned off and before the fifth switching element is turned off A control unit for repeating the control process for turning on the sixth switching element,
    A power converter comprising:
  2. The control process turns on the fifth switching element after a first predetermined time after turning off the first and fourth switching elements, and after the second predetermined time after turning off the sixth switching element. The third switching element is turned on, and the sixth switching element is turned on after a third predetermined time after the second and third switching elements are turned off. The first switching element is turned on after a fourth predetermined time after the fifth switching element is turned off. The power conversion device according to claim 1, wherein the processing is to turn on the fourth switching element.
  3. The control unit performs, together with the control process, a dead time compensation process that compensates for distortion of an output waveform caused by providing the first to fourth predetermined times between control timings of switching elements.
    The power converter according to claim 2, characterized in that.
  4. A first output terminal and a second output terminal to which a load is connected;
    A first leg including a first switching element as a high side switching element and a second switching element as a low side switching element; a third switching element as a high side switching element; and a fourth switching element as a low side switching element And a second connection point, which is a connection point between the first switching element and the second switching element, of the first leg is connected to the first output terminal, and the second leg includes the second leg. A full bridge inverter circuit in which a second connection point, which is a connection point of a third switching element and the fourth switching element, is connected to the second output terminal;
    A fifth switching element that is a short circuit capable of shorting between the first connection point and the second connection point, and capable of turning on / off a current flowing from the second connection point side to the first connection point side A short circuit including a sixth switching element capable of turning on / off a current flowing from the first connection point side to the second connection point side;
    A control method of a power converter comprising:
    The computer is
    While the fifth switching element is on and the sixth switching element is off, the second switching element and the third switching element are turned on, and the fifth switching element is turned on. The first switching element and the fourth switching element are turned on and the first and fourth switching elements are turned off during a period in which the sixth switching element is turned off and the sixth switching element is turned on. Then, before the sixth switching element is turned off, the fifth switching element is turned on, and after the second and third switching elements are turned off, the fifth switching element is turned off. The control process of turning on the sixth switching element is repeated before
    And controlling the power converter.
PCT/JP2018/007145 2017-07-27 2018-02-27 Power conversion device and power conversion device control method WO2019021517A1 (en)

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Citations (2)

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TWI296460B (en) * 2006-01-18 2008-05-01 Univ Yuan Ze High-performance power conditioner for clean energy with low input voltage
JP5048149B2 (en) * 2010-10-19 2012-10-17 Thk株式会社 Measuring apparatus and measuring method
JP6201613B2 (en) * 2013-10-11 2017-09-27 オムロン株式会社 Inverter device, power conditioner, power generation system, and inverter device control method
JP6303819B2 (en) * 2014-05-29 2018-04-04 住友電気工業株式会社 Power converter and three-phase AC power supply
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WO2011105588A1 (en) * 2010-02-26 2011-09-01 三洋電機株式会社 Power conversion apparatus, grid connection apparatus, and grid connection system
JP2016171631A (en) * 2015-03-11 2016-09-23 パナソニックIpマネジメント株式会社 Power conversion circuit and power conversion device using the same

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