WO2019019610A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2019019610A1
WO2019019610A1 PCT/CN2018/075833 CN2018075833W WO2019019610A1 WO 2019019610 A1 WO2019019610 A1 WO 2019019610A1 CN 2018075833 W CN2018075833 W CN 2018075833W WO 2019019610 A1 WO2019019610 A1 WO 2019019610A1
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Prior art keywords
insulating layer
electrodes
groove
shaped sub
strip
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PCT/CN2018/075833
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English (en)
French (fr)
Inventor
范昊翔
李哲
栗鹏
李晓吉
顾可可
刘文亮
秦鹏
卢俊宏
朱维
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US16/082,247 priority Critical patent/US20210208458A1/en
Publication of WO2019019610A1 publication Critical patent/WO2019019610A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the ground is used in the field of high performance display.
  • the conventional liquid crystal display device includes various display modes, such as TN (Twist Nematic), ADS (Advanced-Super Dimensional Switching, IPS (In Plane Switch) type, etc.
  • TN Transmission Nematic
  • ADS Advanced-Super Dimensional Switching
  • IPS In Plane Switch
  • the ADS type display mode is widely used in the field of television display due to its wide viewing angle.
  • An embodiment of the present disclosure provides an array substrate including a slit electrode and a planar electrode disposed in each sub-pixel on a substrate, and the planar electrode is located adjacent to the lining of the slit electrode
  • the slit electrode includes a plurality of strip-shaped sub-electrodes, and in each of the sub-pixels, an insulating layer is disposed between the slit electrode and the planar electrode, and the insulating layer faces away from
  • the surface of the base substrate is provided with a groove between at least one of the plurality of strip-shaped sub-electrodes.
  • a surface of the insulating layer facing away from the base substrate is disposed between each adjacent two strip-shaped sub-electrodes of the plurality of strip-shaped sub-electrodes.
  • the surface of the insulating layer facing away from the base substrate is integrally recessed in a region defined between each adjacent one of the plurality of strip-shaped sub-electrodes to form the recess.
  • the array substrate further includes a dielectric layer between the base substrate and the planar electrode, the dielectric layer including a pad portion corresponding to the position of the groove.
  • the insulating layer includes a gate insulating layer and a protective layer disposed in sequence, and the gate insulating layer is located on a side of the protective layer adjacent to the substrate; in each of the sub-pixels
  • the gate insulating layer has a planar structure
  • the protective layer has a hollow portion, and the hollow portion and a portion of the gate insulating layer corresponding to the hollow portion constitute the groove.
  • the insulating layer includes a gate insulating layer and a protective layer disposed in sequence, and the gate insulating layer is located on a side of the protective layer adjacent to the substrate; in each of the sub-pixels
  • the gate insulating layer is a planar structure, and the recess is located in the protective layer.
  • the protective layer includes a first protective layer and a second protective layer sequentially disposed on the gate insulating layer, the second protective layer has a hollow portion, the hollow portion, and the first A portion of a protective layer corresponding to the hollow portion constitutes the groove.
  • the groove has a groove depth of 0.4 ⁇ m to 0.7 ⁇ m.
  • the groove has a groove depth of 0.4 ⁇ m to 0.7 ⁇ m, and a distance from the groove bottom of the groove to a surface of the gate insulating layer facing away from the substrate substrate is 0.15 ⁇ m to 0.25. Mm.
  • Another aspect of an embodiment of the present disclosure further provides a display device including the above array substrate.
  • a further aspect of the embodiments of the present disclosure further provides a method for fabricating an array substrate, the method comprising: forming a planar electrode at least on each sub-pixel to be formed on a substrate; forming a planar electrode on the planar electrode An insulating layer, and forming a groove at a position between the surface of the insulating layer corresponding to at least one of the plurality of adjacent strip-shaped sub-electrodes in the slit electrode to be formed by a patterning process; The slit electrode is formed on the insulating layer of the groove.
  • the insulating layer is formed on the planar electrode, and a concave surface is formed on a surface of the insulating layer corresponding to at least one set of adjacent strip-shaped sub-electrodes among the slit electrodes to be formed by a patterning process.
  • the groove specifically includes: forming a gate insulating layer on the planar electrode; forming a protective layer on the gate insulating layer, and corresponding to the slit electrode to be formed on a surface of the protective layer by a patterning process a position between at least one of the plurality of adjacent strip-shaped sub-electrodes forms a groove; or a protective layer is formed on the gate insulating layer, and the protective layer is formed by a patterning process a surface corresponding to a position between at least one of the plurality of adjacent strip-shaped sub-electrodes in the slit electrode to be formed to form a hollow portion, the hollow portion, and the gate insulation A portion of the layer corresponding to the hollow portion constitutes a groove.
  • the insulating layer is formed on the planar electrode, and at least a surface of the plurality of adjacent strip sub-electrodes in the slit electrode to be formed is corresponding to a surface of the insulating layer by a patterning process.
  • Forming a groove between a group of adjacent strip-shaped sub-electrodes specifically includes: forming a gate insulating layer on the planar electrode; forming a first protective layer on the gate insulating layer; at the first protection Forming a second protective layer on the layer, and correspondingly at least one set of adjacent strip-shaped sub-electrodes of the plurality of adjacent strip-shaped sub-electrodes in the slit electrode to be formed on the surface of the second protective layer by a patterning process
  • the position between the hollow portions is formed, and the hollow portion and a portion of the first protective layer corresponding to the hollow portion constitute a groove.
  • the insulating layer is formed on the planar electrode, and at least a surface of the plurality of adjacent strip sub-electrodes in the slit electrode to be formed is corresponding to a surface of the insulating layer by a patterning process.
  • Forming a groove between a group of adjacent strip-shaped sub-electrodes specifically includes: forming an insulating layer on the planar electrode, and corresponding to the slit electrode to be formed on a surface of the insulating layer by a patterning process A position between each of the adjacent two strip-shaped sub-electrodes in the plurality of adjacent strip-shaped sub-electrodes forms a groove.
  • FIG. 1 is a schematic structural view of an exemplary ADS type liquid crystal display panel
  • FIG. 2 is a schematic plan view showing a planar structure of an ADS type array substrate according to an embodiment of the present disclosure
  • Figure 3a is a schematic cross-sectional view of the position of Figure 2 along the O-O' position
  • 3b is a schematic cross-sectional structural view of another ADS type array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional structural diagram of still another ADS type array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional structural diagram of still another ADS type array substrate according to the disclosed embodiment.
  • FIG. 6 is a schematic structural diagram of an ADS type display device according to an embodiment of the present disclosure.
  • FIG. 7 is a graph showing transmittance and voltage of an ADS type display device in an embodiment of the present disclosure and the embodiment shown in FIG. 1;
  • FIG. 8 is a graph showing transmittance and light wavelength of an ADS type display device in an embodiment of the present disclosure and the embodiment shown in FIG. 1;
  • FIG. 9 is a flowchart of a method for fabricating an ADS type array substrate according to an embodiment of the present disclosure.
  • FIG. 1 shows an example of a liquid crystal display panel of an ADS mode.
  • the liquid crystal display panel of the ADS mode includes an array substrate 01, a color filter substrate 03, and a liquid crystal layer 02 between the array substrate 01 and the color filter substrate 03.
  • the array substrate 01 includes a planar electrode 10 for driving the liquid crystal layer 02 and a slit electrode 20, and the slit electrode 20 is adjacent to the liquid crystal layer 02 with respect to the planar electrode 10.
  • the area between the planar electrode and the slit electrode is relatively large, and the storage capacitor has a significant increase in capacitance required for the normal display, which may adversely affect the display screen. .
  • a method of increasing the distance between the planar electrode and the slit electrode may be employed to reduce the storage capacitance between the two.
  • the utilization of the electric field is lowered, and the operating voltage Vop of the display device is increased. That is, by adjusting the distance between the planar electrode and the slit electrode, the storage capacitance decreases while the operating voltage Vop increases; or, while the operating voltage Vop decreases, the storage capacitance increases.
  • FIG. 2 shows an example of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate 01 includes a slit electrode 20 and a planar electrode 10 disposed in each sub-pixel P on a base substrate 100 (not shown in FIG. 2, which can be referred to FIG. 3a), and is shown in FIG. 3a ( 2 is a schematic view showing a cross-sectional structure along the O-O' position.
  • the planar electrode 10 is located on a side of the slit electrode 20 adjacent to the base substrate 100, and the slit electrode 20 includes a plurality of strip-shaped sub-electrodes 201, that is, the array substrate 01.
  • an insulating layer 30 is disposed between the slit electrode 20 and the planar electrode 10, and the surface of the insulating layer 30 facing away from the substrate 100 is adjacent to at least one of the plurality of strip-shaped sub-electrodes 201.
  • a groove 301 is disposed between the strip-shaped sub-electrodes.
  • the above-mentioned planar electrode 10 means that the electrode has a full-surface structure, and there is no gap or hollow portion in the electrode. Further, the planar electrode may be flat or non-flat, and may be determined depending on the form of the bearing surface on which the planar electrode is placed.
  • the groove means a structure having a bottom surface, that is, an insulating layer is provided between the slit electrode 20 and the planar electrode 10 at the bottom surface position of the corresponding groove 301.
  • the slit electrode 20 may be a ladder-shaped slit electrode as shown in FIG. 2 , or may be a dressing slit electrode, and may of course be a slit electrode of other shapes, which is not limited in the present disclosure.
  • the groove 301 is disposed at a position between the adjacent strip-shaped sub-electrodes 201 of the plurality of strip-shaped sub-electrodes 201 in the insulating layer 30 between the slit electrode 20 and the planar electrode 10, that is, the insulation
  • the thickness of the layer 30 between adjacent ones of the plurality of strip-shaped sub-electrodes 201 is reduced. In this way, compared to the scheme in which the thickness of the entire insulating layer 30 is uniform in the exemplary embodiment shown in FIG. 1, in the embodiment provided in FIG. 3a of the present disclosure, the slit electrode 20 and the planar electrode 10 can be secured.
  • the opposing area is constant, that is, on the basis of not increasing the storage capacitance, by reducing the thickness of the insulating layer 30 between the corresponding adjacent strip-shaped sub-electrodes 201, the insulating layer 30 is opposed to the slit electrode 20 and the planar electrode 10
  • the weakening effect of the electric field formed therebetween improves the utilization of the electric field between the planar electrode 10 and the slit electrode 20, thereby lowering the operating voltage Vop, that is, for the display device including the array substrate, the work can be reduced Consumption.
  • the array substrate 01 further includes a dielectric layer between the base substrate 100 and the planar electrode 10, the dielectric layer including the corresponding The height portion 200 at the position of the groove 301.
  • the planar electrode 10 can be raised at the position of the recess 301 by the padding portion.
  • the planar electrode 10 has a non-flat structure, and the distance of the planar electrode 10 with respect to the slit electrode 20 is reduced at the position corresponding to the groove 301, so that the utilization of the electric field is improved, and the operating voltage Vop is lowered.
  • the pad portion 200 may be processed by a single fabrication process with the gate lines in the array substrate, that is, the pad portion 200 is disposed in the same layer as the gate lines, and the materials are the same.
  • padding portion 200 that is, the planar electrode 10 as a flat structure.
  • the surface of the insulating layer 30 facing away from the substrate 100 is adjacent to each other.
  • a groove 301 is disposed between the two strip-shaped sub-electrodes 201. That is, in each of the sub-pixels P, a groove 301 is disposed between any two adjacent strip-shaped sub-electrodes 201 of the plurality of strip-shaped sub-electrodes 201, thereby further reducing the insulating layer 30 to the slit electrode 20 as a whole.
  • the weakening effect of the electric field formed between the planar electrode 10 and the planar electrode 10 improves the utilization of the electric field between the planar electrode 10 and the slit electrode 20, thereby effectively reducing the operating voltage Vop.
  • the insulating layer 30 faces away from the surface of the substrate 100.
  • a region defined between each adjacent two strip-shaped sub-electrodes in each of the strip-shaped sub-electrodes 201 is integrally recessed to form a recess 301. That is, the opening of the groove 301 is two strip-shaped sub-electrodes among the plurality of strip-shaped sub-electrodes 201 adjacent to the groove at two edges in the width direction of each of the plurality of strip-shaped sub-electrodes 201 The two adjacent sides of the 201 overlap in this direction.
  • the insulating layer 30 has a strip-like convex structure under the corresponding strip-shaped sub-electrodes 201 of the plurality of strip-shaped sub-electrodes 201, and the surface of the convex structure is the same period and concentric with the strip-shaped sub-electrodes, both of which are The orthographic projections on the base substrate coincide. In this way, the weakening effect of the electric field formed between the slit electrode 20 and the planar electrode 10 by the insulating layer 30 can be minimized, and the utilization ratio of the electric field between the planar electrode 10 and the slit electrode 20 can be further improved. .
  • the portion of the insulating layer 30 under the corresponding strip-shaped sub-electrode 201 of the plurality of strip-shaped sub-electrodes 201 has a trapezoidal structure.
  • the portion of the portion that is in contact with the corresponding one of the plurality of strip-shaped sub-electrodes 201 has a smaller width dimension, and the width of the portion that is away from the corresponding one of the plurality of strip-shaped sub-electrodes 201 is gradually increased. That is, the side of the portion is inclined. Generally, the angle of the side of the portion is about 60°.
  • the processing of the recess 301 is mostly formed by a patterning process (including exposure, development, etching, stripping, etc.), and in the etching process, due to the process, the direction toward the bottom of the groove is The concentration of the etching solution is lowered, and the etching time is relatively short, so that the groove formed by the etching process is inverted trapezoidal.
  • the insulating layer 30 includes a gate insulating layer 31 and a protective layer 32 which are sequentially disposed, and the gate insulating layer 31 is located on a side of the protective layer 32 close to the substrate substrate 100.
  • the insulating layer 30 between the slit electrode 20 and the planar electrode 10 is generally shared with the insulating layer in the thin film transistor (that is, by the same fabrication process).
  • a gate insulating layer (GI) 31 and a protective layer (PVX) 32 may be employed as the insulating layer 30.
  • the arrangement of the grooves 301 can be as follows:
  • the gate insulating layer 31 is a planar structure, and the protective layer 32 has a hollow portion thereon.
  • the hollow portion and a portion of the gate insulating layer 31 corresponding to the hollow portion constitute a groove 301. That is, the portion of the gate insulating layer 31 corresponding to the hollow portion constitutes the bottom of the recess 301, and the side wall of the hollow portion on the protective layer 32 constitutes the sidewall of the recess 301.
  • the gate insulating layer 31 is a planar structure, and the recess 301 is located in the protective layer 32. That is, the side walls of the entire groove 301 and the groove bottom are located in the protective layer 32.
  • the protective layer 32 includes a first protective layer 321 and a second protective layer 322 which are sequentially disposed on the gate insulating layer 31.
  • the second protective layer 322 has a hollow portion, and the hollow portion and a portion of the first protective layer 321 corresponding to the hollow portion constitute a recess 301. That is, the portion of the first protective layer 321 corresponding to the hollow portion constitutes the bottom of the recess 301, and the sidewall of the hollow portion of the second protective layer 322 constitutes the sidewall of the recess 301.
  • the grooves may optionally have a groove depth of 0.4 ⁇ m to 0.7 ⁇ m.
  • the thickness of the insulating layer 30 between the corresponding adjacent strip-shaped sub-electrodes 201 of the plurality of strip-shaped sub-electrodes 201 is still large, that is, the pair of insulating layers 30 cannot be significantly reduced.
  • the groove may have a groove depth between 0.4 [mu]m and 0.7 [mu]m.
  • the storage capacitance between the slit electrode 20 and the planar electrode 10 is larger than the actually required storage capacitance, for example, normal.
  • the storage capacitance shown is 300 pF to 500 pF, and the storage capacitance between the slit electrode 20 and the planar electrode 10 in the ADS type array substrate may reach 600 pF or more, so in order to appropriately reduce the storage capacitance, in some embodiments of the present disclosure
  • the groove 301 may have a groove depth of 0.4 ⁇ m to 0.7 ⁇ m.
  • the distance from the groove bottom of the recess 301 to the surface of the gate insulating layer 31 facing away from the base substrate 100 may be 0.15 ⁇ m. 0.25 ⁇ m (wherein the thickness of the first protective layer 321 is 0.15 ⁇ m to 0.25 ⁇ m for the array substrate shown in FIG. 5), so as to appropriately increase the distance between the slit electrode 20 and the planar electrode 10, thereby reducing
  • the storage capacitance between the slit electrode 20 and the planar electrode 10 is such as to achieve the capacitance required for normal display.
  • the embodiment of the present disclosure further provides a display device, including any of the foregoing array substrates, having the same structure and advantageous effects as the array substrate provided by the foregoing embodiments. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the array substrate, details are not described herein again.
  • the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone or a tablet computer.
  • the display device includes an array substrate 01, a color filter substrate 03, and a liquid crystal layer 02 between the array substrate 01 and the color filter substrate 03.
  • the display device is located on both sides of the liquid crystal layer 02.
  • the alignment layer PI and the like which will not be repeated here.
  • the array substrate in FIG. 6 of the present disclosure and the array substrate in FIG. 1 are further described by comparing the relevant parameters of the storage capacitor, the operating voltage, and the like by actual measurement when applied to the display device.
  • the thickness of the gate insulating layer (GI) 31 is 0.4 ⁇ m
  • the thickness of the first protective layer (PVX1) 321 is 0.2 ⁇ m
  • the thickness of the second protective layer (PVX2) 322 is 0.6 ⁇ m (i.e., the groove depth of the groove is 0.6 ⁇ m)
  • the average thickness of the liquid crystal layer 02 is 3.55 ⁇ m.
  • the corresponding gate insulating layer (GI) has a thickness of 0.4 ⁇ m
  • the protective layer (PVX) has a thickness of 0.6 ⁇ m
  • the liquid crystal layer 02 has a thickness of 3.55 ⁇ m.
  • the storage capacity in the embodiment shown in FIG. 6 is 87.3%, which is equivalent to a decrease of 12.7%, based on the measured storage capacity and transmittance measured in the embodiment shown in FIG.
  • the voltage corresponding to the maximum transmittance in the embodiment shown in FIG. 6 is about 7.2 V
  • the voltage corresponding to the overshoot is about 8.4V. That is, the operating voltage (7.2 V) of the embodiment shown in Fig. 6 is significantly smaller than the operating voltage (8.4 V) in the embodiment shown in Fig. 1.
  • the design in the embodiment shown in FIG. 6 will reduce the transmittance of the display device relative to the embodiment shown in FIG. 1, but it is not obvious and will not have an actual impact on the display. .
  • the scheme of the present disclosure is substantially consistent with the color temperature in the embodiment shown in FIG. That is, in FIG. 8, the scheme of the present disclosure substantially coincides with the curve of the light wavelength and the transmittance compared with the technical scheme of the embodiment shown in FIG. 1.
  • the solution provided by the embodiment of the present disclosure can reduce the operating voltage without changing the color temperature, and can also reduce the storage capacitance.
  • the embodiment of the present disclosure further provides a method for fabricating an array substrate. As shown in FIG. 9 , the manufacturing method includes (may be combined with the schematic diagram of the array substrate in FIG. 2 and FIG. 3 a ):
  • Step S101 forming a planar electrode 10 at least in a region where each sub-pixel P on the base substrate 100 is to be formed.
  • Step S102 forming an insulating layer 30 on the planar electrode 10, and correspondingly at least one set of adjacent strip-shaped sub-electrodes 201 of the plurality of strip-shaped sub-electrodes 201 in the slit electrode 20 to be formed on the surface of the insulating layer 30 by a patterning process.
  • a groove 301 is formed at a position between them.
  • the slit electrode 20 to be formed refers to the slit electrode 20 formed in a subsequent process.
  • Step S103 the slit electrode 20 is formed on the insulating layer 30 having the groove 301 on the surface.
  • the array substrate fabricated by the solution of the present disclosure corresponds to the position between adjacent strip-shaped sub-electrodes 201 of the plurality of strip-shaped sub-electrodes 201 in the insulating layer 30 between the slit electrode 20 and the planar electrode 10.
  • the groove 301 is provided, that is, the thickness of the insulating layer 30 between the adjacent strip-shaped sub-electrodes 201 corresponding to the plurality of strip-shaped sub-electrodes 201 is reduced. In this way, compared with the solution in which the thickness of the entire insulating layer 30 is uniform in the embodiment shown in FIG. 1, in the embodiment of the present disclosure, the area of the slit electrode 20 and the planar electrode 10 can be ensured to be unchanged. .
  • the insulating layer 30 is reduced to the slit electrodes 20 and the planar shape.
  • the weakening effect of the electric field formed between the electrodes 10 improves the utilization of the electric field between the planar electrode 10 and the slit electrode 20, thereby lowering the operating voltage, that is, for the display device including the array substrate, it is possible to reduce Power consumption.
  • the insulating layer 30 is formed on the planar electrode 10, and adjacent to at least one of the plurality of strip-shaped sub-electrodes 201 in the slit electrode 20 to be formed on the surface of the insulating layer 30 by a patterning process.
  • the specific case where the position between the strip-shaped sub-electrodes 201 forms the groove 301 is further explained.
  • the step S102 may include (refer to FIG. 4):
  • a gate insulating layer 31 is formed on the planar electrode 10.
  • the protective layer 32 is formed on the gate insulating layer 31, and at least one of the plurality of strip-shaped sub-electrodes 201 in the slit electrode 20 to be formed is corresponding to the surface of the protective layer 32 by a patterning process.
  • the position between the electrodes 201 forms a groove 301.
  • this step S102 can include (refer to Figure 3a):
  • a gate insulating layer 31 is formed on the planar electrode 10.
  • the protective layer 32 is formed on the gate insulating layer 31, and at least one of the plurality of strip-shaped sub-electrodes 201 in the slit electrode 20 to be formed is corresponding to the surface of the protective layer 32 by a patterning process.
  • the position between the electrodes 201 forms a hollow portion, and the hollow portion, and a portion of the gate insulating layer 31 corresponding to the hollow portion constitutes a groove 301.
  • the step S102 may include (refer to FIG. 5):
  • a gate insulating layer 31 is formed on the planar electrode 10.
  • a first protective layer 321 is formed on the gate insulating layer 31.
  • a second protective layer 322 is formed on the first protective layer 321 and corresponds to at least one of the plurality of strip-shaped sub-electrodes 201 in the slit electrode 20 to be formed on the surface of the second protective layer 322 by a patterning process.
  • the position between the adjacent strip-shaped sub-electrodes 201 forms a hollow portion, and the hollow portion, and a portion of the first protective layer 321 corresponding to the hollow portion constitutes a groove 301.
  • the above step S102 may include (refer to FIG. 3a):
  • An insulating layer 30 is formed on the planar electrode 10, and is disposed between the adjacent two strip-shaped sub-electrodes 201 of the plurality of strip-shaped sub-electrodes 201 in the slit electrode 20 to be formed on the surface of the insulating layer 30 by a patterning process.
  • the grooves are formed in positions.
  • the patterning process may include a photolithography process, or may include a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, and development.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present disclosure.

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Abstract

一种阵列基板（01）及其制作方法、显示装置。阵列基板（01）包括设置于衬底基板（100）上位于每个亚像素（P）中的狭缝电极（20）和面状电极（10），且面状电极（10）位于狭缝电极（20）靠近衬底基板（100）的一侧，狭缝电极（20）包括多个条状子电极（201），在每个亚像素（P）中，狭缝电极（20）和面状电极（10）之间设置有绝缘层（30），绝缘层（30）背离衬底基板（100）的表面在多个条状子电极（201）中的至少一组相邻条状子电极（201）之间设置有凹槽（301）。

Description

阵列基板及其制作方法、显示装置
本申请要求于2017年7月28日提交中国专利局、申请号为201710637585.1、发明名称为“一种阵列基板及其制作方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)作为一种平板显示装置，因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
现有的液晶显示装置包括多种显示模式，例如TN(Twist Nematic，扭曲向列)型、ADS(Advanced-Super Dimensional Switching，高级超维场开关、IPS(In Plane Switch，横向电场效应)型等。ADS型显示模式由于其宽视角，广泛应用于电视显示领域。
发明内容
本公开实施例一方面提供一种阵列基板，包括设置于衬底基板上位于每个亚像素中的狭缝电极和面状电极，且所述面状电极位于所述狭缝电极靠近所述衬底基板的一侧，所述狭缝电极包括多个条状子电极，在所述每个亚像素中，所述狭缝电极和所述面状电极之间设置有绝缘层，所述绝缘层背离所述衬底基板的表面在所述多个条状子电极中的至少一组相邻条状子电极之间设置有凹槽。
可选地，所述绝缘层背离所述衬底基板的表面在所述多个条状子电极中的每相邻两个条状子电极之间均设置有凹槽。
可选地，所述绝缘层背离所述衬底基板的表面在所述多个条状子电极中的每相邻两个条状子电极之间限定的区域内整体凹陷以形 成所述凹槽。
可选地，所述阵列基板还包括位于所述衬底基板与所述面状电极之间的介质层，所述介质层包括对应所述凹槽位置的垫高部。
可选地，所述绝缘层包括依次设置的栅极绝缘层和保护层，且所述栅极绝缘层位于所述保护层靠近所述衬底基板的一侧；在所述每个亚像素中，所述栅极绝缘层为面状结构，所述保护层上具有镂空部，所述镂空部、以及所述栅极绝缘层中对应于所述镂空部的部分构成所述凹槽。
可选地，所述绝缘层包括依次设置的栅极绝缘层和保护层，且所述栅极绝缘层位于所述保护层靠近所述衬底基板的一侧；在所述每个亚像素中，所述栅极绝缘层为面状结构，所述凹槽位于所述保护层中。
可选地，所述保护层包括依次设置于所述栅极绝缘层上的第一保护层和第二保护层，所述第二保护层上具有镂空部，所述镂空部、以及所述第一保护层中对应于所述镂空部的部分构成所述凹槽。
可选地，所述凹槽的槽深为0.4μm～0.7μm。
可选地，所述凹槽的槽深为0.4μm～0.7μm，且所述凹槽的槽底到所述栅极绝缘层背离所述衬底基板一侧的表面的距离为0.15μm～0.25μm。
本公开实施例另一方面还提供一种显示装置，包括上述的阵列基板。
本公开实施例再一方面还提供一种阵列基板的制作方法，所述制作方法包括：至少在衬底基板上的每个亚像素待形成区域形成面状电极；在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应待形成的狭缝电极中多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成凹槽；在表面具有凹槽的绝缘层上形成所述狭缝电极。
可选地，所述在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应待形成的狭缝电极中至少一组相邻条状子 电极之间的位置形成凹槽具体包括：在所述面状电极上形成栅极绝缘层；在所述栅极绝缘层上形成保护层，并通过构图工艺在所述保护层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成凹槽；或者，在所述栅极绝缘层上形成保护层，并通过构图工艺在所述保护层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成镂空部，所述镂空部、以及所述栅极绝缘层中对应于所述镂空部的部分构成凹槽。
可选地，所述在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成凹槽具体包括：在所述面状电极上形成栅极绝缘层；在所述栅极绝缘层上形成第一保护层；在所述第一保护层上形成第二保护层，并通过构图工艺在所述第二保护层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成镂空部，所述镂空部、以及所述第一保护层中对应于所述镂空部的部分构成凹槽。
可选地，所述在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成凹槽具体包括：所述在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的每相邻两个条状子电极之间的位置均形成凹槽。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种示例性ADS型液晶显示面板的结构示意图；
图2为本公开实施例中提供的一种ADS型阵列基板的平面结构示意图；
图3a为图2沿O-O’位置的剖面结构示意图；
图3b为本公开实施例提供的另一种ADS型阵列基板的剖面结构示意图；
图4为本公开实施例提供的又一种ADS型阵列基板的剖面结构示意图；
图5为公开实施例提供的再一种ADS型阵列基板的剖面结构示意图；
图6为本公开实施例提供的一种ADS型显示装置的结构示意图；
图7为本公开实施例以及图1所示实施例中的ADS型显示装置透过率与电压的曲线图；
图8为本公开实施例以及图1所示实施例中的ADS型显示装置透过率与光线波长的曲线图；
图9为本公开实施例提供的一种ADS型阵列基板的制作方法的流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1示出了ADS模式的液晶显示面板的示例。该ADS模式的液晶显示面板包括阵列基板01、彩膜基板03以及位于阵列基板01和彩膜基板03之间的液晶层02。阵列基板01中包括用于驱动液晶层02的面状电极10和狭缝电极20，且狭缝电极20相对于面状电极10靠近液晶层02。该ADS模式的显示面板中，面状电极和狭缝电极之 间正对的面积较大，两者之间存储电容相对于正常显示的所需电容明显增加，可能会对显示画面会造成不良影响。
可以采用增加面状电极和狭缝电极之间距离的方法(即增加两者之间的绝缘层的厚度)，来降低两者之间的存储电容。但是采用该方法降低存储电容的同时，会导致电场的利用率降低，进而使得显示装置的工作电压Vop增加。即通过调整面状电极和狭缝电极之间距离，会出现存储电容降低的同时，工作电压Vop增加；或者，工作电压Vop降低的同时，存储电容增加。
图2示出了本公开实施例提供的一种阵列基板的示例。该阵列基板01包括设置于衬底基板100(图2中未示出，可参考图3a)上位于每个亚像素P中的狭缝电极20和面状电极10，且如图3a所示(图2沿O-O’位置的剖面结构的示意图)，面状电极10位于狭缝电极20靠近衬底基板100的一侧，狭缝电极20包括多个条状子电极201，即该阵列基板01为ADS型。在每个亚像素P中，狭缝电极20和面状电极10之间设置有绝缘层30，该绝缘层30背离衬底基板100的表面在多个条状子电极201中的至少一组相邻条状子电极之间设置有凹槽301。
此处需要说明的是，第一，对于上述面状电极10而言，是指该电极为整面结构，该电极中不存在缝隙或者镂空部分。另外，该面状电极的可以是平坦的，也可以是非平坦的，依据承载该面状电极的承载面的形态决定。
第二，对于上述凹槽301，应当理解到凹槽是指具有底面的结构，即狭缝电极20与面状电极10之间在对应凹槽301的底面位置处具有绝缘层。
第三，狭缝电极20可以是如图2所示的梯状狭缝电极，也可以是梳妆狭缝电极，当然也可以是其他形状的狭缝电极，本公开对此不做限定。
综上所述，由于在狭缝电极20和面状电极10之间的绝缘层30中对应多个条状子电极201中的相邻条状子电极201之间的位置设置 有凹槽301，即绝缘层30在对应多个条状子电极201中的相邻条状子电极201之间的厚度减小。这样一来，相比于图1所示的示例性实施例中整个绝缘层30的厚度一致的方案而言，本公开图3a提供的实施例中，能够保证狭缝电极20和面状电极10正对的面积不变，即不增加存储电容的基础上，通过减小绝缘层30在对应相邻条状子电极201之间的厚度，降低了绝缘层30对狭缝电极20和面状电极10之间形成的电场的削弱作用，从而提高了面状电极10和狭缝电极20之间电场的利用率，进而降低了工作电压Vop，即对于包含该阵列基板的显示装置而言，能够降低功耗。
当然，为了更进一步的提高电场的利用率，降低工作电压Vop，如图3b所示，该阵列基板01还包括位于衬底基板100与面状电极10之间的介质层，该介质层包括对应凹槽301位置的垫高部200。这样一来，通过垫高部可以在凹槽301位置将面状电极10垫高。此时面状电极10为非平坦结构，在对应凹槽301的位置处，面状电极10相对于狭缝电极20的距离减小，进而使得电场的利用率提高，工作电压Vop降低。当然考虑到制作工艺，该垫高部200可以与阵列基板中的栅线通过一次制作工艺加工而成，即该垫高部200与栅线同层设置，且材料相同。
为了便于说明，以下实施例均是以未设置上述垫高部200，即面状电极10为平坦结构为例，对本公开做进一步的解释说明。
可选地，为了进一步的降低绝缘层30对狭缝电极20和面状电极10之间形成的电场的削弱作用，如图3a所示，绝缘层30背离衬底基板100的表面在每相邻两个条状子电极201之间均设置有凹槽301。即在每个亚像素P中，多个条状子电极201中的任意相邻的两个条状子电极201之间均设置凹槽301，从而在整体上进一步的降低绝缘层30对狭缝电极20和面状电极10之间形成的电场的削弱作用，即全面的提高了面状电极10和狭缝电极20之间电场的利用率，进而有效的降低工作电压Vop。
进一步可选地，为了最大程度的降低绝缘层30对狭缝电极20 和面状电极10之间形成的电场的削弱作用，如图3a所示，绝缘层30背离衬底基板100的表面在多个条状子电极201中的每相邻两个条状子电极之间限定的区域内整体凹陷以形成凹槽301。即凹槽301的开口在沿多个条状子电极201中的每个条状子电极201的宽度方向上的两个边缘与该凹槽相邻的多个条状子电极201中的两个条状子电极201在该方向上相邻的两个边分别重合。也就是说绝缘层30在多个条状子电极201中的对应的条状子电极201下方呈条状的凸起结构，且该凸起结构的表面与条状子电极同周期、同中心，两者在衬底基板上的正投影重合。这样一来，能够最大程度的降低绝缘层30对狭缝电极20和面状电极10之间形成的电场的削弱作用，更进一步的提高面状电极10和狭缝电极20之间电场的利用率。
需要说明的是，从图3a中可以看出，绝缘层30在多个条状子电极201中的对应的条状子电极201下方的部分的截面呈梯形结构。该部分中与多个条状子电极201中的对应的条状子电极201接触的部分的宽度尺寸较小，而向远离多个条状子电极201中的对应的条状子电极201一侧的宽度逐渐增加，即该部分的侧面呈倾斜状。一般的，该部分的侧面的倾斜角度在60°左右。本领域的技术人员应当理解到，凹槽301的加工多采用构图工艺形成(包括曝光、显影、刻蚀、剥离等)，在进行刻蚀过程中由于工艺的原因，越往凹槽底方向，刻蚀液的浓度降低，且刻蚀时间相对较短，从而使得采用刻蚀工艺形成凹槽呈倒梯形。基于此，对于上述在每相邻两个条状子电极201之间限定的区域内整体凹陷以形成凹槽301而言，只要保证凹槽301的开口与多个条状子电极201中的对应位置的相邻的条状子电极201的两个边缘分别重合即可。
以下对上述绝缘层30上的凹槽301的设置情况做进一步的说明。
参考图2和图3a，绝缘层30包括依次设置的栅极绝缘层31和保护层32，且栅极绝缘层31位于保护层32靠近衬底基板100的一侧。对此，本领域的技术人员应当理解到，在阵列基板制作的过程中除了 狭缝电极20与面状电极10以外，还有其他的很多结构，例如薄膜晶体管。因此在实际制作中，为了简化工艺，位于狭缝电极20与面状电极10之间的绝缘层30一般与制作薄膜晶体管中的绝缘层共用(即通过同一次制作工艺制成)。例如，可以采用栅极绝缘层(GI)31和保护层(PVX)32作为绝缘层30。
基于上述的绝缘层30设置情况下，凹槽301的设置可以如下：
例如，参考图2和图3a，在每个亚像素P中，栅极绝缘层31为面状结构，保护层32上具有镂空部。该镂空部、以及栅极绝缘层31中对应于镂空部的部分构成凹槽301。即栅极绝缘层31中对应于镂空部的部分构成凹槽301的底部，保护层32上的镂空部的侧壁构成凹槽301的侧壁。
又例如，参考图2和图4，在每个亚像素P中，栅极绝缘层31为面状结构，凹槽301位于保护层32中。即整个凹槽301的侧壁以及槽底均位于保护层32中。
当然，对于凹槽301位于保护层32中的情况下，还可以如图5所示，保护层32包括依次设置于栅极绝缘层31上的第一保护层321和第二保护层322。第二保护层322上具有镂空部，该镂空部、以及第一保护层321中对应于镂空部的部分构成凹槽301。即第一保护层321中对应于镂空部的部分构成凹槽301的底部，第二保护层322上的镂空部的侧壁构成凹槽301的侧壁。
基于上述凹槽301的设置结构，可选地，凹槽的槽深为0.4μm～0.7μm。
示例性的，若凹槽的槽深小于0.4μm，绝缘层30在多个条状子电极201中的对应相邻条状子电极201之间的厚度仍然较大，即不能明显的降低绝缘层30对狭缝电极20和面状电极10之间形成的电场的削弱作用。若凹槽的槽深大于0.7μm，必然要求狭缝电极20与面状电极10的绝缘层30的厚度足够大，考虑到阵列基板实际制作中各膜层的制作厚度以及轻薄化的设置理念，因此，在本公开的一些实施例中，凹槽的槽深可在0.4μm～0.7μm之间。
当然，考虑到ADS型阵列基板中由于狭缝电极20与面状电极10的正对面积较大，使得狭缝电极20与面状电极10之间的存储电容大于实际需要的存储电容，例如正常显示的存储电容为300pF～500pF，而ADS型阵列基板中狭缝电极20与面状电极10之间的存储电容会达到600pF以上，因此为了适当的降低存储电容，在本公开的一些实施例中，凹槽301的槽深可为0.4μm～0.7μm。且凹槽301位于保护层32的情况下，如图4和图5所示，可以设置凹槽301的槽底到栅极绝缘层31背离衬底基板100一侧的表面的距离为0.15μm～0.25μm(其中对于图5所示的阵列基板而言，相当于第一保护层321的厚度为0.15μm～0.25μm)，以适当的增加狭缝电极20与面状电极10的距离，从而降低狭缝电极20与面状电极10之间的存储电容以达到正常显示所需要的电容量。
本公开实施例还提供一种显示装置，包括前述的任一种阵列基板，具有与前述实施例提供的阵列基板相同的结构和有益效果。由于前述实施例已经对阵列基板的结构和有益效果进行了详细的描述，此处不再赘述。
需要说明的是，该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
具体的，如图6所示，该显示装置包括阵列基板01、彩膜基板03以及位于阵列基板01和彩膜基板03之间的液晶层02，当然，该显示装置位于液晶层02的两侧还包括取向层PI等等，此处不再一一赘述。
以下对本公开图6中的阵列基板和图1中的阵列基板在应用于显示装置时通过实际的测定对存储电容、工作电压等相关参数做进一步的比较说明。
以图5中示出的阵列基板01为例(可参考图6的显示装置)，栅极绝缘层(GI)31的厚度为0.4μm，第一保护层(PVX1)321的厚度为0.2μm，第二保护层(PVX2)322的厚度为0.6μm(即凹槽的槽深为0.6μm)，液晶层02的平均厚度3.55μm。
可参考图1，相应的栅极绝缘层(GI)的厚度为0.4μm，保护层(PVX)的厚度为0.6μm，液晶层02的厚度3.55μm。
基于上述的设置参数，通过实际的测定，如下表所示：
Figure PCTCN2018075833-appb-000001
可以看出，以图1所示实施例中测得的存储电容量和透过率为100％为基准，图6所示实施例中的存储电容量为87.3％，相当于降低了12.7％。具体的，结合上表与图7中电压与透过率的关系可以看出，图6所示实施例中最大透过率对应的电压在7.2V左右，而图1所示实施例中最大透过率对应的电压在8.4V左右。即图6所示实施例的工作电压(7.2V)明显小于图1所示实施例中的工作电压(8.4V)。当然上表也可以看出图6所示实施例中的设计方案会使得显示装置的透过率相对于图1所示实施例有所降低，但并不明显，不会对显示造成实际的影响。
另外，如图8所示，本公开的方案与图1所示实施例中的色温基本保持一致。即图8中，本公开的方案与图1所示实施例的技术方案相比，两者对光波长与透过率的曲线基本重合。
综上所述，相比于图1所示实施例而言，采用本公开实施例提供的方案能够在不改变色温的基础上，降低工作电压，并且还可以降低存储电容。
本公开实施例还提供一种阵列基板的制作方法，如图9所示，该制作方法包括(可结合图2和图3a中的阵列基板示意图)：
步骤S101、至少在衬底基板100上的每个亚像素P待形成区域形成面状电极10。
步骤S102、在面状电极10上形成绝缘层30，并通过构图工艺 在绝缘层30的表面对应待形成的狭缝电极20中多个条状子电极201中的至少一组相邻条状子电极201之间的位置形成凹槽301。
其中，上述待形成的狭缝电极20是指，在后续工艺中制作形成的狭缝电极20。
步骤S103、在表面具有凹槽301的绝缘层30上形成狭缝电极20。
基于此，采用本公开的方案制作的阵列基板，由于在狭缝电极20和面状电极10之间的绝缘层30中对应多个条状子电极201中的相邻条状子电极201之间的位置设置凹槽301，即绝缘层30在对应多个条状子电极201中的相邻条状子电极201之间的厚度减小。这样一来，相比于图1所示实施例中整个绝缘层30的厚度一致的方案而言，本公开的实施例中，能够保证狭缝电极20和面状电极10正对的面积不变。即不增加存储电容的基础上，通过减小绝缘层30在对应多个条状子电极201中的相邻条状子电极201之间的厚度，从而降低了绝缘层30对狭缝电极20和面状电极10之间形成的电场的削弱作用，从而提高了面状电极10和狭缝电极20之间电场的利用率，进而降低了工作电压，即对于包含该阵列基板的显示装置而言，能够降低功耗。
以下对上述步骤S102中，在面状电极10上形成绝缘层30，并通过构图工艺在绝缘层30的表面对应待形成的狭缝电极20中多个条状子电极201中的至少一组相邻条状子电极201之间的位置形成凹槽301的具体情况做进一步的说明。
具体的，该步骤S102可以包括(参考图4)：
第一步、在面状电极10上形成栅极绝缘层31。
第二步、在栅极绝缘层31上形成保护层32，并通过构图工艺在保护层32的表面对应待形成的狭缝电极20中多个条状子电极201中的至少一组相邻条状子电极201之间的位置形成凹槽301。
当然，该步骤S102可以包括(参考图3a)：
第一步、在面状电极10上形成栅极绝缘层31。
第二步、在栅极绝缘层31上形成保护层32，并通过构图工艺 在保护层32的表面对应待形成的狭缝电极20中多个条状子电极201中的至少一组相邻条状子电极201之间的位置形成镂空部，镂空部、以及栅极绝缘层31中对应于镂空部的部分构成凹槽301。
或者，该步骤S102可以包括(参考图5)：
第一步、在面状电极10上形成栅极绝缘层31。
第二步、在栅极绝缘层31上形成第一保护层321。
第三步、在第一保护层321上形成第二保护层322，并通过构图工艺在第二保护层322的表面对应待形成的狭缝电极20中多个条状子电极201中的至少一组相邻条状子电极201之间的位置形成镂空部，镂空部、以及第一保护层321中对应于镂空部的部分构成凹槽301。
另外，为了最大程度的降低绝缘层30对狭缝电极20和面状电极10之间形成的电场的削弱作用，在本公开的一些实施例中，上述步骤S102可以包括(可参考图3a)：
在面状电极10上形成绝缘层30，并通过构图工艺在绝缘层30的表面对应待形成的狭缝电极20中多个条状子电极201中的每相邻两个条状子电极201之间的位置均形成凹槽301。
需要说明的是，在本公开中，构图工艺，可指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本公开中所形成的结构选择相应的构图工艺。
另外，对于该实施例中阵列基板的制作方法相关的其他信息，也可以参考前述阵列基板实施例中的具体描述，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种阵列基板，包括设置于衬底基板上位于每个亚像素中的狭缝电极和面状电极，且所述面状电极位于所述狭缝电极靠近所述衬底基板的一侧，所述狭缝电极包括多个条状子电极，其中，在所述每个亚像素中，所述狭缝电极和所述面状电极之间设置有绝缘层，所述绝缘层背离所述衬底基板的表面在所述多个条状子电极中的至少一组相邻条状子电极之间设置有凹槽。
  2. 根据权利要求1所述的阵列基板，其中，所述绝缘层背离所述衬底基板的表面在所述多个条状子电极中的每相邻两个条状子电极之间均设置有凹槽。
  3. 根据权利要求2所述的阵列基板，其中，所述绝缘层背离所述衬底基板的表面在所述多个条状子电极中的每相邻两个条状子电极之间限定的区域内整体凹陷以形成所述凹槽。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括位于所述衬底基板与所述面状电极之间的介质层，所述介质层包括对应所述凹槽位置的垫高部。
  5. 根据权利要求1所述的阵列基板，其中，所述绝缘层包括依次设置的栅极绝缘层和保护层，且所述栅极绝缘层位于所述保护层靠近所述衬底基板的一侧；
    在所述每个亚像素中，所述栅极绝缘层为面状结构，所述保护层上具有镂空部，所述镂空部、以及所述栅极绝缘层中对应于所述镂空部的部分构成所述凹槽。
  6. 根据权利要求1所述的阵列基板，其中，所述绝缘层包括依次设置的栅极绝缘层和保护层，且所述栅极绝缘层位于所述保护层靠近所述衬底基板的一侧；
    在所述每个亚像素中，所述栅极绝缘层为面状结构，所述凹槽位于所述保护层中。
  7. 根据权利要求6所述的阵列基板，其中，所述保护层包括依次设置于所述栅极绝缘层上的第一保护层和第二保护层，所述第二保护层上具有镂空部，所述镂空部、以及所述第一保护层中对应于所述镂空部的部分构成所述凹槽。
  8. 根据权利要求1-7任一项所述的阵列基板，其中，所述凹槽的槽深为0.4μm～0.7μm。
  9. 根据权利要求6或7任一项所述的阵列基板，其中，所述凹槽的槽深为0.4μm～0.7μm，且所述凹槽的槽底到所述栅极绝缘层背离所述衬底基板一侧的表面的距离为0.15μm～0.25μm。
  10. 一种显示装置，包括权利要求1-9任一项所述的阵列基板。
  11. 一种阵列基板的制作方法，所述制作方法包括：
    至少在衬底基板上的每个亚像素待形成区域形成面状电极；
    在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应待形成的狭缝电极中多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成凹槽；
    在表面具有凹槽的绝缘层上形成所述狭缝电极。
  12. 根据权利要求11所述的制作方法，其中，所述在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成凹槽具体包括：
    在所述面状电极上形成栅极绝缘层；
    在所述栅极绝缘层上形成保护层，并通过构图工艺在所述保护层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成凹槽；
    或者，在所述栅极绝缘层上形成保护层，并通过构图工艺在所述保护层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成镂空部，所述镂空部、以及所述栅 极绝缘层中对应于所述镂空部的部分构成凹槽。
  13. 根据权利要求11所述的制作方法，其中，所述在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成凹槽具体包括：
    在所述面状电极上形成栅极绝缘层；
    在所述栅极绝缘层上形成第一保护层；
    在所述第一保护层上形成第二保护层，并通过构图工艺在所述第二保护层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成镂空部，所述镂空部、以及所述第一保护层中对应于所述镂空部的部分构成凹槽。
  14. 根据权利要求11所述的制作方法，其中，所述在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的至少一组相邻条状子电极之间的位置形成凹槽具体包括：
    所述在所述面状电极上形成绝缘层，并通过构图工艺在所述绝缘层的表面对应所述待形成的狭缝电极中所述多个相邻条状子电极中的每相邻两个条状子电极之间的位置均形成凹槽。
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