WO2019019437A1 - 一种阵列基板和一种显示设备 - Google Patents

一种阵列基板和一种显示设备 Download PDF

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Publication number
WO2019019437A1
WO2019019437A1 PCT/CN2017/107146 CN2017107146W WO2019019437A1 WO 2019019437 A1 WO2019019437 A1 WO 2019019437A1 CN 2017107146 W CN2017107146 W CN 2017107146W WO 2019019437 A1 WO2019019437 A1 WO 2019019437A1
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Prior art keywords
line
pixel circuit
lines
gate
array substrate
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Ceased
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PCT/CN2017/107146
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English (en)
French (fr)
Inventor
韩约白
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/740,980 priority Critical patent/US20190386039A1/en
Publication of WO2019019437A1 publication Critical patent/WO2019019437A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • the inventors of the present application have unexpectedly discovered a technical problem that has not been found in the prior art, that is, due to the complicated process of the low-temperature polysilicon device, the low-temperature polysilicon display panel is more likely to cause electrostatic discharge in the process (Electro-Static) Discharge, ESD static, so there will be a large amount of charge accumulation, which will cause the edge of the panel edge and the polysilicon layer to be damaged, which will cause short circuit between the gate and the polysilicon layer, and input the gate signal to the polysilicon layer, causing electrical failure.
  • ESD static Electro-Static Discharge
  • FIG. 1 is a schematic view showing the configuration of an array substrate 100 in the prior art.
  • the array substrate 100 includes a base layer 10 (shown portion), and a polysilicon layer 11 above the base layer 10, that is, an inverted U-shaped layer in the figure.
  • the line symbol 15 and the above-mentioned "above” are merely illustrative of the relative positional relationship, and are not necessarily in close contact with each other.
  • the unnumbered portion in Fig. 1 is the same as the reference numeral in the upper left corner of Fig. 1 and its meaning.
  • the configuration of the array substrate 100 shown in the figure may cause damage to the edge of the panel and the polysilicon layer, that is, the gate line and the polysilicon layer shown in FIG. 1 are projected at the overlap 16 in the vertical direction.
  • the position is broken, which causes a short circuit between the gate and the polysilicon layer, and the gate signal is input to the polysilicon layer, causing electrical failure.
  • orientation based on the array substrate or display panel (or device) referred to in this specification is only used to indicate the relative orientation relationship; for the purposes of this specification, the specific orientation It is defined on the basis of the positional relationship of the display panel relative to the placement of the observer in the usual case of use, for example, close to the viewer is referred to as "upper” and away from the viewer is referred to as "lower”.
  • the invention provides an array substrate and a display device, which are intended to solve the problem that the existing display panel is electrically defective due to electrostatic discharge during the process.
  • a first embodiment of the present invention provides an array substrate, comprising: a base layer; a pixel circuit disposed on the base layer in a matrix arrangement; and a signal line disposed on the base layer in a row or column direction, coupled to the a pixel circuit; wherein at least two of the signal lines in the same direction are respectively disposed on a relatively outermost side of the pixel circuit of the matrix arrangement; the signal line includes a first data line and a second data line disposed in a column direction; The number of the second data lines is one, located at the rightmost side of the array substrate, and the corresponding pixel circuit coupled to the second data line is located on the left side of the second data line; The signal lines that are disposed in the other columns are all the first data lines, and all of the first data lines are located on the left side of the corresponding pixel circuit coupled thereto; the signal lines a first gate line and a second gate line disposed in a row direction; the number of the second gate lines is one, located at a lowermost side of the array substrate,
  • a second aspect of the present invention provides an array substrate, comprising: a base layer; a pixel circuit disposed on the base layer in a matrix arrangement; and signal lines disposed on the base layer in a row or column direction, and coupled to the substrate a pixel circuit; wherein at least two of the signal lines in the same direction are respectively disposed at opposite outermost sides of the pixel circuits arranged in the matrix.
  • a third aspect of the embodiments of the present invention provides a display device, including: a base layer; a pixel circuit disposed on the base layer in a matrix arrangement; and a signal line disposed on the base layer in a row or column direction, and coupled to the substrate a pixel circuit; wherein at least two of the signal lines in the same direction are respectively disposed at opposite outermost sides of the pixel circuits arranged in the matrix.
  • the technical solution provided by the present invention has the beneficial effects that the pixel circuit of the entire panel is designed as an array structure in the prior art, and the gate line and the polysilicon layer are easily damaged due to electrostatic discharge.
  • at least two signals in the same direction are respectively disposed at the outermost side of the pixel circuit arranged with respect to the matrix, so that the electrostatic discharge charge at least two ends of the display panel can pass through the device.
  • the signal line is exported, which effectively reduces the probability of electrical failure and improves product yield.
  • FIG. 1 is a schematic structural view of an array substrate provided in the background art of the present invention.
  • FIG. 2 is a schematic structural diagram of an array substrate according to a first embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another array substrate according to a first embodiment of the present invention.
  • FIG. 4 is a partial cross-sectional view showing another array substrate according to a first embodiment of the present invention along a direction in which a longitudinal signal line extends;
  • FIG. 5 is a schematic structural diagram of another array substrate according to a first embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another array substrate according to a first embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a display device according to a first embodiment of the present invention.
  • the first embodiment of the present invention provides an array substrate, comprising: a base layer; a pixel circuit disposed on the base layer in a matrix arrangement; and a signal line disposed on the base layer in a row or column direction, coupled to the pixel a circuit; wherein at least two of the signal lines in the same direction are respectively disposed on opposite outermost sides of the pixel circuit of the matrix arrangement.
  • FIG. 2 is a schematic structural view of an array substrate 200 according to a first embodiment of the present invention.
  • the array substrate 200 includes a base layer, a pixel circuit 21, and a signal line 22.
  • the pixel circuits 21 are arranged on the base layer in a matrix arrangement, and the signal lines 22 are disposed on the base layer in a row or column direction, and coupled to the pixel circuit. 21, wherein at least two of the same signal lines 22 are respectively disposed on the outermost side of the pixel circuit 21 of the matrix arrangement.
  • Fig. 2 is merely an exemplary description, and a broken line symbol 24 indicating repeated extension in this direction is used in Fig. 2.
  • the base layer is located at the bottom layer of the light shielding layer 20 indicated by the projection in the vertical direction in FIG. 2 and the black square block partially overlapping the projection of the signal line 22 in the vertical direction.
  • FIG. 2 is a plan view showing the invention of the present application, which is convenient for expression and because it must comply with the requirements of the drawings (using black lines), so the base layer is not shown, according to the orientation relationship defined in the present application, the base layer Generally located below all line construction layers.
  • the base layer may be located below the pixel circuit 21 and the signal line 22 shown in FIG. 2.
  • the pixel circuit 21 may include a polysilicon layer, that is, a portion having an inverted U-shaped distribution in FIG. 2 with a black square block, and the pixel circuit 21 shown in FIG. 2 may be a polysilicon layer.
  • the signal line 22 may include a gate line and a data line
  • the laterally arranged signal line 22 shown in FIG. 2 may be a gate line
  • the vertically arranged signal line 22 may be a data line.
  • the meaning that the signal line 22 is disposed on the base layer in the row or column direction may include the signal line 22 being in close contact with the base layer, or the signal line 22 may be located above the base layer, but not in close contact.
  • the signal line 22 is coupled to the pixel circuit 21, and the longitudinally arranged signal line 22 is coupled to the polysilicon layer of the pixel circuit 21.
  • the vertical signal line 22, the horizontal signal line 22, the light shielding layer 20 of the pixel circuit 21, and the vertical layer of the base layer are overlapped, and the foregoing layers are the base layer, the light shielding layer 20, and the pixel circuit layer 21 from bottom to top.
  • the horizontal signal line 22 and the vertical signal line 22 are overlapped, and the foregoing layers are the base layer, the light shielding layer 20, and the pixel circuit layer 21 from bottom to top.
  • At least two of the same signal lines 22 in which at least two of the same-directional signal lines 22 are respectively disposed on the outermost side of the matrix-arranged pixel circuits 21 may be the leftmost vertical arrangement illustrated in FIG. 2 .
  • At least two signal lines 22 in the same direction are respectively disposed on the outermost side of the pixel circuit 21 of the matrix arrangement, so that the accumulated charge or the incoming charge can be made from the leftmost longitudinally arranged signal line as exemplified in FIG. 2 . 22 and the rightmost longitudinally arranged signal line 22 are quickly derived, effectively avoiding the accumulated electric charge so that the position of the lateral signal line 22 and the pixel circuit layer 21 in the vertical direction of the projection overlap 25 is damaged, which can effectively reduce the electrical defect. Probability increases product yield.
  • FIG. 3 is a schematic diagram showing the configuration of another array substrate 300 according to the first embodiment of the present invention.
  • the array substrate 300 illustrated in FIG. 3 may further include a via 23 for connecting the pixel circuit 21 and the signal line 22, FIG.
  • the via 23 shown in the drawing can communicate with the vertical signal line 22 and the pixel circuit 21.
  • the reference numerals not shown in FIG. 3 and their meanings can be the same as those described with respect to FIG. 2 and will not be described again.
  • FIG. 4 is a partial cross-sectional view of the array substrate 300 according to the first embodiment of the present invention along a direction in which a longitudinal signal line extends, a pixel circuit 21, a longitudinal signal line layer 22, and a pixel circuit 21 and a vertical signal line layer.
  • the polysilicon layer included in the pixel circuit 21 can be coupled to the signal line 22 through the via 23, and the polysilicon layer included in the pixel circuit 21 is coupled to the vertical signal line 22 through the via 23 in FIG.
  • the polysilicon layer can be coupled to the data line through the via 23 .
  • the accumulated charge can be transferred from the polysilicon layer through the via 23 to the data line, and then derived from the data line, which can effectively avoid the accumulated charge so that the lateral signal line 22 (which can be the gate line) and the polysilicon layer are projected in the vertical direction.
  • the position of the overlap 25 is broken, thereby avoiding a short circuit between the gate line and the polysilicon layer, and inputting a gate signal to the polysilicon layer, causing electrical failure.
  • the polysilicon layer can be a low temperature polysilicon layer.
  • FIG. 5 is a schematic structural diagram of another array substrate 400 according to an embodiment of the present invention.
  • the signal line 22 includes a first data line 221 and a second data line 222 arranged in a column direction, and the second data line 222.
  • the number is one, located at the rightmost side of the array substrate 200, and the corresponding pixel circuit 21 coupled to the second data line 222 is located on the left side of the second data line 222, except for the second data line 222, the other columns are arranged.
  • the signal lines are all the first data lines 221, and all of the first data lines 221 are located on the left side of the corresponding pixel circuit 21 coupled thereto, and the labels not shown in FIG. 5 and their meanings may be related to FIG. 2 or FIG. The description is the same and will not be described again.
  • the number of the second data lines 222 may not be one.
  • any plurality of second data lines 222 may be inserted between the second data line 222 and the first data line 221 of the rightmost side in FIG. 5 . .
  • FIG. 6 a circuit configuration diagram of another array substrate 500 is shown in FIG. 6.
  • the signal line 22 includes a first data line 221 and a second data line 222 arranged in a column direction.
  • the number of the first data lines 221 is one.
  • the corresponding pixel circuit 21 coupled to the first data line 221 is located on the right side of the first data line 221, and the remaining signal lines 22 are arranged in the column except the first data line 221.
  • All of the second data lines 222, and all of the second data lines 222 are located on the right side of the corresponding pixel circuit 21 coupled thereto, the labels not depicted in FIG. 6 and their meanings may be related to the description of FIG. 2 or FIG. The same, no longer repeat them.
  • the number of the first data lines 221 may not be one.
  • any plurality of first data lines 221 may be inserted between the first data line 221 and the second data line 222 on the leftmost side in FIG. 6 . .
  • the array substrate 300 illustrated in FIG. 5 and the array substrate 400 illustrated in FIG. 6 can well solve the technical problem that the right side of the display panel discovered by the inventor has electrical defects, and improve the yield of the display panel. .
  • the signal line 22 includes a first gate line and a second gate line disposed in a row direction, and the number of the second gate lines is one, located at a lowermost side of the array substrate 200, coupled to the second gate line
  • the corresponding pixel circuit 21 is located on the upper side of the second gate line, except for the second gate line, the remaining signal lines 22 are all the first gate lines, and all the first gate lines are Located on the upper side of the corresponding pixel circuit 21 coupled thereto.
  • the number of the second gate lines may not be one, and the number of the second data lines or the first data lines may not be similar to the foregoing, and details are not described herein again.
  • the signal line 22 includes a first gate line and a second gate line disposed in a row direction.
  • the number of the first gate lines is one, and is located at an uppermost side of the array substrate 200 and coupled to the first gate line.
  • the corresponding pixel circuit 21 is located on the lower side of the second gate line. Except for the first gate line, the remaining line-up signal lines 22 are all second gate lines, and all the second gate lines are located. The lower side of the corresponding pixel circuit 21 coupled thereto.
  • the number of the first gate lines may not be one, and the number of the second data lines or the first data lines or the second gate lines may not be similar to the foregoing, and details are not described herein again.
  • the description of the case where the signal line 22 includes the first gate line and the second gate line disposed in the row direction and the foregoing signal line 22 include the first data line 221 and the second data line 222 disposed in the column direction.
  • the signal line 22 includes the first data line 221 and the second data line 222 disposed in the column direction.
  • the signal line 22 includes the first gate disposed in the row direction.
  • the case of the polar line and the second gate line will not be described again.
  • the related descriptions in FIGS. 2, 3, and 4 can be applied to the case where the aforementioned signal line 22 includes the first data line 221 and the second data line 222 which are arranged in the column direction, and the signal line 22 includes the line.
  • the foregoing signal line 22 includes a case where the first data line 221 and the second data line 222 are arranged in a column direction, and the signal line 22 includes a row direction.
  • the array substrate may further include a via for connecting the pixel circuit and the signal line
  • the pixel circuit may include a polysilicon layer
  • the signal line includes a data line
  • the via may be used to connect the pixel
  • the polysilicon layer and the data line of the circuit can transfer the accumulated charge from the polysilicon layer to the data line through the via hole, and then be derived from the data line
  • the polysilicon layer can be a low temperature polysilicon layer.
  • the pixel circuit 21 includes a polysilicon layer 211, and the polysilicon layer 221 is coupled to the signal line 22 through the via 23 .
  • the entire panel pixel circuit is designed as an array structure, which is likely to cause a short circuit caused by a flaw in the gate line and the polysilicon layer, resulting in electrical failure.
  • at least two signals in the same direction are used.
  • the lines are respectively disposed at the outermost sides of the pixel circuits arranged with respect to the matrix, so that the electrostatic discharge charges of at least two ends of the display panel can be derived through the signal lines, thereby effectively reducing the probability of electrical failure and improving the product yield.
  • the accumulated charge can be quickly exported through the signal line, which can greatly reduce the edge defects of the product and improve the display quality.
  • a display device includes: a base layer; a pixel circuit disposed on the base layer in a matrix arrangement; and a signal line disposed on the base layer in a row or column direction, coupled to the a pixel circuit; wherein at least two of the signal lines in the same direction are respectively disposed on opposite outermost sides of the pixel circuit arranged in the matrix.
  • FIG. 7 is a schematic structural diagram of a display device 300 according to a second embodiment of the present invention.
  • FIG. 7 only shows a portion related to the second embodiment of the present invention, and the display device 700
  • the pixel circuit 32 is disposed on the base layer 31 in a matrix arrangement; the signal line 33 is disposed on the base layer 31 in a row or column direction, and coupled to the pixel circuit 32; wherein at least two signals in the same direction are connected 33 are respectively disposed on the outermost side of the pixel circuit 32 in which the matrix is arranged.
  • Fig. 7 is merely an exemplary description, and a broken line symbol 34 indicating repeated extension in the direction is used in Fig. 7.
  • the signal line includes a first data line and a second data line that are arranged in a column direction.
  • the number of the second data lines is one, located at a rightmost side of the array substrate, and the corresponding pixel circuit coupled to the second data line is located.
  • the remaining listed signal lines are all first data lines, and all of the first data lines are located on the left side of the corresponding pixel circuit coupled thereto.
  • the signal line includes a first data line and a second data line that are arranged in a column direction.
  • the first data line has a number of one, located at a leftmost side of the array substrate, and the corresponding pixel circuit coupled to the first data line is located.
  • the remaining listed signal lines are all second data lines, and all of the second data lines are located on the right side of the corresponding pixel circuit coupled thereto.
  • the signal line includes a first gate line and a second gate line disposed in a row direction, and the number of the second gate lines is one, located at a lowermost side of the array substrate, coupled to the second gate line.
  • the corresponding pixel circuit is located on the upper side of the second gate line, except for the second gate line, the remaining signal lines are all disposed on the first gate line, and all the first gate lines are coupled thereto Corresponding to the upper side of the pixel circuit.
  • the signal line includes a first gate line and a second gate line disposed in a row direction.
  • the number of the first gate lines is one, and is located at an uppermost side of the array substrate, and the corresponding pixel circuit coupled to the first gate line is located at the second The lower side of the gate line, except for the first gate line, the remaining signal lines are all the second gate lines, and all the second gate lines are located under the corresponding pixel circuits coupled thereto side.
  • the pixel circuit includes a polysilicon layer, and the polysilicon layer is coupled to the signal line through the via.
  • the polysilicon layer is low temperature polysilicon.
  • the display device embodiment is based on the same concept as the array substrate embodiment, and the technical effects thereof are the same as those in the embodiment of the present invention.
  • the display device embodiment is based on the same concept as the array substrate embodiment, and the technical effects thereof are the same as those in the embodiment of the present invention.
  • the display device embodiment is based on the same concept as the array substrate embodiment, and the technical effects thereof are the same as those in the embodiment of the present invention.
  • the display device embodiment is based on the same concept as the array substrate embodiment, and the technical effects thereof are the same as those in the embodiment of the present invention.
  • the description in the embodiment of the array substrate and details are not described herein.

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Abstract

一种阵列基板（200）和一种显示设备，阵列基板（200）包括基层、像素电路（21）和信号线（22），像素电路（21）以矩阵排列方式设置于基层上，信号线（22）以行或列方向设置于基层上，耦接像素电路（21），至少两条同向的信号线（22）分别设置于矩阵排列的像素电路（21）相对最外侧。通过将至少两条同向的信号线（22）分别设置在相对于矩阵排列的像素电路（21）的最外侧，如此可使得显示面板至少两端的静电释放电荷可通过该信号线（22）导出，有效降低了电气不良的概率，提高了产品良率。

Description

一种阵列基板和一种显示设备
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板和一种显示设备。
【背景技术】
本申请发明人意外发现现有技术中未曾被发现的技术问题，即由于低温多晶硅器件制程较复杂，使得低温多晶硅显示面板在制程中更容易引起静电释放（Electro-Static discharge，ESD静电），如此会有大量的电荷聚集从而造成面板边缘栅极和多晶硅层炸伤，进而造成栅极和多晶硅层发生短路，将栅极信号输入到多晶硅层，引起电气不良。
图1中示出了现有技术中阵列基板100的构造示意图，阵列基板100包括基层10（示出部分），位于基层10之上的多晶硅层11，即图中呈倒U形的层，位于多晶硅层11之上的栅极线层12，位于栅极线层12之上的数据线层13，用于连接多晶硅层11和数据线层13的过孔14，表示在该方向重复延伸的折断线符号15，前述“位于……之上的”只是说明相对位置关系，并不一定紧贴，图1中未标号部分与图1中左上角标号的部分对标号及其含义相同。
本申请发明人发现图中所示的阵列基板100的构造会造成面板边缘栅极和多晶硅层发生炸伤，即图1中所示的栅极线与多晶硅层在垂直方向上投影重叠处16的位置发生炸伤，进而造成栅极和多晶硅层发生短路，将栅极信号输入到多晶硅层，引起电气不良。
在本说明书中所称的基于阵列基板或显示面板（或设备）的方位（例如显示面板的最右侧、上、下等）仅用以表示相对的方位关系；对于本说明书而言，具体方位是在显示面板在使用的通常情况下相对于观察者的放置的位置关系确定后，在此基础上定义的，例如接近观看者称为“上”，而远离观看者称为“下”。
【发明内容】
本发明提供了一种阵列基板和一种显示设备，旨在解决现有的显示面板在制程中因静电释放导致电气不良的问题。
发明实施例的第一方面提供一种阵列基板，包括：基层；像素电路，以矩阵排列方式设置于所述基层上；信号线，以行或列方向设置于所述基层上，耦接所述像素电路；其中，至少两条同向的所述信号线分别设置于所述矩阵排列的所述像素电路相对最外侧；所述信号线包括列向设置的第一数据线和第二数据线；所述第二数据线数量为一，位于所述阵列基板的最右侧，与所述第二数据线耦接的对应所述像素电路位于所述第二数据线的左侧；除所述第二数据线之外，其余列向设置的信号线均为所述第一数据线，且所有的所述第一数据线均位于与其耦接的对应所述像素电路的左侧；所述信号线包括行向设置的第一栅极线和第二栅极线；所述第二栅极线数量为一，位于所述阵列基板的最下侧，与所述第二栅极线耦接的对应所述像素电路位于所述第二栅极线的上侧；除所述第二栅极线之外，其余列向设置的信号线均为所述第一栅极线，且所有的所述第一栅极线均位于与其耦接的对应所述像素电路的上侧。
本发明实施例的第二方面提供一种阵列基板，包括：基层；像素电路，以矩阵排列方式设置于所述基层上；信号线，以行或列方向设置于所述基层上，耦接所述像素电路；其中，至少两条同向的所述信号线分别设置于在所述矩阵排列的所述像素电路相对最外侧。
本发明实施例的第三方面提供一种显示设备，包括：基层；像素电路，以矩阵排列方式设置于所述基层上；信号线，以行或列方向设置于所述基层上，耦接所述像素电路；其中，至少两条同向的所述信号线分别设置于在所述矩阵排列的所述像素电路相对最外侧。
本发明提供的技术方案与现有技术相比存在的有益效果是：区别于现有技术中整张面板像素电路均为阵列结构的设计，因静电释放易造成栅极线路与多晶硅层发生炸伤引起短路，导致电气不良的情况，本发明实施例将至少两条同向的信号线分别设置在相对于矩阵排列的像素电路的最外侧，如此可使得显示面板至少两端的静电释放电荷可通过该信号线导出，有效降低了电气不良的概率，提高了产品良率。
【附图说明】
图1是本发明背景技术中提供的阵列基板的构造示意图；
图2是本发明第一实施例提供的一种阵列基板的构造示意图；
图3是本发明第一实施例提供的另一种阵列基板的构造示意图；
图4是本发明第一实施例提供的另一种阵列基板的沿纵向信号线延伸方向的局部剖面图；
图5是本发明第一实施例提供的另一种阵列基板的构造示意图；
图6是本发明第一实施例提供的另一种阵列基板的构造示意图；
图7是本发明第一实施例提供的一种显示设备的示意图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。
以下描述中，为了说明而不是为了限定，给出了诸多技术特征的说明示意图，以便透彻理解本发明实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本发明。在其它情况中，省略对众所周知的结构的详细说明，以免不必要的细节妨碍本发明的描述。
本发明第一实施例提供一种阵列基板，包括：基层；像素电路，以矩阵排列方式设置于所述基层上；信号线，以行或列方向设置于所述基层上，耦接所述像素电路；其中，至少两条同向的所述信号线分别设置于所述矩阵排列的所述像素电路相对最外侧。以下通过文字与示例性附图进行详细说明。
参阅图2，图2示出了本发明第一实施例提供的一种阵列基板200的构造示意图，为了便于说明，图2仅示出了与本发明第一实施例相关的部分。如图2所示，阵列基板200包括：基层、像素电路21和信号线22，像素电路21以矩阵排列方式设置于基层上，信号线22以行或列方向设置于基层上，耦接像素电路21，其中，至少两条同向的信号线22分别设置于矩阵排列的像素电路21相对最外侧。图2只是示例性描述，图2中使用了表示在该方向重复延伸的折断线符号24。
可选的是，基层位于图2中在垂直方向上的投影与信号线22在垂直方向上的投影有部分重叠的黑色方形块表示的遮光层20的底层。
需要说明的是，图2选用平面视图来表现本申请的发明点，便于表达和由于须符合附图的规定（采用黑色线条），因此基层未示出，根据本申请中定义的方位关系，基层一般位于所有线路构造层之下。
可选的是，基层可位于图2中所示的像素电路21和信号线22之下。
可选的是，像素电路21可包括多晶硅层，即图2中呈倒U形分布的一端带黑色方形块的部分，图2中示出的像素电路21可为多晶硅层。
可选的是，信号线22可包括栅极线和数据线，图2中示出的横向排布的信号线22可为栅极线，纵向排布的信号线22可为数据线。
可选的是，信号线22以行或列方向设置于基层上的含义可包括信号线22与基层紧贴，也可包括信号线22位于基层之上，但并不紧贴。
可选的是，信号线22耦接像素电路21可为纵向排布的信号线22耦接像素电路21的多晶硅层。
需要说明的是，如上虽为简单描述，但本领域技术人员可结合现有技术对其进行清楚的理解和界定。
可选的是，在纵向信号线22、横向信号线22、像素电路21遮光层20和基层垂直方向投影重叠的部分，前述各层从下到上依次为基层、遮光层20、像素电路层21、横向信号线22、纵向信号线22。
可选的是，“至少两条同向的信号线22分别设置于矩阵排列的像素电路21相对最外侧”中至少两条同向的信号线22可为图2中示例的最左边纵向排布的信号线22和最右边纵向排布的信号线22。
需要说明的是，为了便于说明问题，图2中未标号部分与图2中左上角标号的部分对标号及其含义相同。
需要说明的是，至少两条同向的信号线22分别设置于矩阵排列的像素电路21相对最外侧，可使得聚集电荷或外界进入的电荷从图2中示例的最左边纵向排布的信号线22和最右边纵向排布的信号线22快速导出，有效避免了聚集电荷使得横向信号线22与像素电路层21在垂直方向上投影重叠处25的位置发生炸伤，可有效降低了电气不良的概率，提高了产品良率。
图3示出了本发明第一实施例提供的另一种阵列基板300的构造示意图，图3示例的阵列基板300还可包括用于连通像素电路21和信号线22的过孔23，图3中示出的过孔23可连通纵向信号线22与像素电路21，图3中未描述的标号及其含义可与关于图2的描述相同，不再赘述。
图4示出了本发明第一实施例提供的一种阵列基板300的沿纵向信号线延伸方向的局部剖面图，像素电路21，纵向信号线层22，介于像素电路21与纵向信号线层22之间的间隔层30，以及连接像素电路21和纵向信号线22的过孔23。
可选的是，包括于像素电路21的多晶硅层可通过过孔23与信号线22耦接，图3中示出的为包括于像素电路21的多晶硅层通过过孔23与纵向信号线22耦接，即可为多晶硅层通过过孔23与数据线耦接。
如此，可将聚集电荷从多晶硅层通过过孔23传递到数据线，而后由数据线导出，可有效避免了聚集电荷使得横向信号线22（可为栅极线）与多晶硅层在垂直方向上投影重叠处25的位置发生炸伤，进而避免了栅极线和多晶硅层发生短路，将栅极信号输入到多晶硅层，引起电气不良。
可选的是，多晶硅层可为低温多晶硅层。
可选的是，图5中示出了本发明实施例另一种阵列基板400的构造示意图，信号线22包括列向设置的第一数据线221和第二数据线222，第二数据线222数量为一，位于阵列基板200的最右侧，与第二数据线222耦接的对应像素电路21位于第二数据线222的左侧，除第二数据线222之外，其余列向设置的信号线均为第一数据线221，且所有的第一数据线221均位于与其耦接的对应像素电路21的左侧，图5中未描述的标号及其含义可与关于图2或图3的描述相同，不再赘述。
可选的是，第二数据线222数量也可以不为一个，例如可在图5中最右侧的第二数据线222和第一数据线221之间可插入任意多个第二数据线222。
可选的是，图6中示出了另一种阵列基板500的电路构造示意图，信号线22包括列向设置的第一数据线221和第二数据线222，第一数据线221数量为一，位于阵列基板20的最左侧，与第一数据线221耦接的对应像素电路21位于第一数据线221的右侧，除第一数据线221之外，其余列向设置的信号线22均为第二数据线222，且所有的第二数据线222均位于与其耦接的对应像素电路21的右侧，图6中未描述的标号及其含义可与关于图2或图3的描述相同，不再赘述。
可选的是，第一数据线221数量也可以不为一个，例如可在图6中最左侧的第一数据线221和第二数据线222之间可插入任意多个第一数据线221。
需要说明的是，上述图5中示例的阵列基板300和图6中示例的阵列基板400可良好地解决发明人发现的显示面板的最右侧出现电气不良的技术问题，提高显示面板的良率。
可选的是，信号线22包括行向设置的第一栅极线和第二栅极线，第二栅极线数量为一，位于阵列基板200的最下侧，与第二栅极线耦接的对应像素电路21位于第二栅极线的上侧，除第二栅极线之外，其余行向设置的信号线22均为第一栅极线，且所有的第一栅极线均位于与其耦接的对应像素电路21的上侧。
可选的是，第二栅极线的数量也可以不为一个，说明与前述关于第二数据线或第一数据线的数量也可以不为一个类似，不再赘述。
可选的是，信号线22包括行向设置的第一栅极线和第二栅极线，第一栅极线数量为一，位于阵列基板200的最上侧，与第一栅极线耦接的对应像素电路21位于第二栅极线的下侧，除第一栅极线之外，其余行向设置的信号线22均为第二栅极线，且所有的第二栅极线均位于与其耦接的对应像素电路21的下侧。
可选的是，第一栅极线的数量也可以不为一个，说明与前述关于第二数据线或第一数据线或第二栅极线的数量也可以不为一个类似，不再赘述。
可选的是，信号线22包括行向设置的第一栅极线和第二栅极线的情况的描述与前述信号线22包括列向设置的第一数据线221和第二数据线222的情况类似，本领域技术人员在前述关于信号线22包括列向设置的第一数据线221和第二数据线222的情况的相关描述下，可明确实现信号线22包括行向设置的第一栅极线和第二栅极线的情况，不再赘述。
可选的是，关于图2、图3和图4中的相关描述均可应用于前述信号线22包括列向设置的第一数据线221和第二数据线222的情况以及信号线22包括行向设置的第一栅极线和第二栅极线的情况，例如，前述信号线22包括列向设置的第一数据线221和第二数据线222的情况以及信号线22包括行向设置的第一栅极线和第二栅极线的情况中阵列基板还可包括用于连通像素电路和信号线的过孔，像素电路可包括多晶硅层，信号线包括数据线，过孔可用于连接像素电路的多晶硅层和数据线，可将聚集电荷从多晶硅层通过过孔传递到数据线，而后由数据线导出，再如多晶硅层可为低温多晶硅层。
可选的是，像素电路21包括多晶硅层211，多晶硅层221通过过孔23与信号线22耦接。
相比于现有技术中整张面板像素电路均为阵列结构的设计易造成栅极线路与多晶硅层发生炸伤引起短路，导致电气不良的情况，本发明实施例将至少两条同向的信号线分别设置在相对于矩阵排列的像素电路的最外侧，如此可使得显示面板至少两端的静电释放电荷可通过该信号线导出，有效降低了电气不良的概率，提高了产品良率。另一方面，可快速将聚集电荷通过信号线导出，可大幅度减小产品的边缘亮点不良，提高显示品质。
本发明第二实施例提供的一种显示设备，包括：基层；像素电路，以矩阵排列方式设置于所述基层上；信号线，以行或列方向设置于所述基层上，耦接所述像素电路；其中，至少两条同向的所述信号线分别设置于在所述矩阵排列的所述像素电路相对最外侧。
参阅图7，图7示出了本发明第二实施例提供的一种显示设备300的构造示意图，为了便于说明，图7仅示出了与本发明第二实施例相关的部分，显示设备700包括：基层31；像素电路32，以矩阵排列方式设置于基层31上；信号线33，以行或列方向设置于基层31上，耦接像素电路32；其中，至少两条同向的信号线33分别设置于矩阵排列的像素电路32相对最外侧。图7只是示例性描述，图7中使用了表示在该方向重复延伸的折断线符号34。
可选的是，信号线包括列向设置的第一数据线和第二数据线，第二数据线数量为一，位于阵列基板的最右侧，与第二数据线耦接的对应像素电路位于第二数据线的左侧，除第二数据线之外，其余列向设置的信号线均为第一数据线，且所有的第一数据线均位于与其耦接的对应像素电路的左侧。
可选的是，信号线包括列向设置的第一数据线和第二数据线，第一数据线数量为一，位于阵列基板的最左侧，与第一数据线耦接的对应像素电路位于第二数据线的右侧，除第一数据线之外，其余列向设置的信号线均为第二数据线，且所有的第二数据线均位于与其耦接的对应像素电路的右侧。
可选的是，信号线包括行向设置的第一栅极线和第二栅极线，第二栅极线数量为一，位于阵列基板的最下侧，与第二栅极线耦接的对应像素电路位于第二栅极线的上侧，除第二栅极线之外，其余行向设置的信号线均为第一栅极线，且所有的第一栅极线均位于与其耦接的对应像素电路的上侧。
信号线包括行向设置的第一栅极线和第二栅极线，第一栅极线数量为一，位于阵列基板的最上侧，与第一栅极线耦接的对应像素电路位于第二栅极线的下侧，除第一栅极线之外，其余行向设置的信号线均为第二栅极线，且所有的第二栅极线均位于与其耦接的对应像素电路的下侧。
可选的是，像素电路包括多晶硅层，多晶硅层通过过孔与信号线耦接。
可选的是，可选的是，多晶硅层为低温多晶硅。
前述阵列基板实施例中对相应名词、句子含义的解释均可用于本实施例，在此不再赘述。
需要说明的是，显示设备实施例由于与阵列基板实施例基于同一构思，其带来的技术效果与本发明实施例相同，具体内容可参见阵列基板实施例中的叙述，不再赘述。
需要说明的是，本发明所有实施例中涉及“第一”、“第二”等词，例如第一数据线、第二数据线等在此仅为表述和指代的方便，并不意味着在本发明的具体实现方式中一定会有与之对应的第一数据线和第二数据线。
以上所述仅为结合具体的实施例对本发明原理及实施方式所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明，只是用于帮助理解本发明的方法及其核心思想；同时，对于本发明所属技术领域的普通技术人员而言，在不脱离本发明构思的前提下，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，都应当视为属于本发明的专利保护范围。

Claims (17)

  1. 一种阵列基板，包括：
    基层；
    像素电路，以矩阵排列方式设置于所述基层上；
    信号线，以行或列方向设置于所述基层上，耦接所述像素电路；
    其中，至少两条同向的所述信号线分别设置于所述矩阵排列的所述像素电路相对最外侧；
    所述信号线包括列向设置的第一数据线和第二数据线；所述第二数据线数量为一，位于所述阵列基板的最右侧，与所述第二数据线耦接的对应所述像素电路位于所述第二数据线的左侧；除所述第二数据线之外，其余列向设置的信号线均为所述第一数据线，且所有的所述第一数据线均位于与其耦接的对应所述像素电路的左侧；
    所述信号线包括行向设置的第一栅极线和第二栅极线；所述第二栅极线数量为一，位于所述阵列基板的最下侧，与所述第二栅极线耦接的对应所述像素电路位于所述第二栅极线的上侧；除所述第二栅极线之外，其余列向设置的信号线均为所述第一栅极线，且所有的所述第一栅极线均位于与其耦接的对应所述像素电路的上侧。
  2. 根据权利要求1所述的阵列基板，其中，
    所述阵列基板进一步包括遮光层，设置于所述基层上，所述像素电路及所述信号线之下，且所述遮光层与所述像素电路和所述像素电极的耦接处对应设置。
  3. 根据权利要求1所述的阵列基板，其中，
    所述像素电路包括多晶硅层，所述多晶硅层通过过孔与所述信号线耦接。
  4. 一种阵列基板，包括：
    基层；
    像素电路，以矩阵排列方式设置于所述基层上；
    信号线，以行或列方向设置于所述基层上，耦接所述像素电路；
    其中，至少两条同向的所述信号线分别设置于所述矩阵排列的所述像素电路相对最外侧。
  5. 根据权利要求4所述的阵列基板，其中，
    所述信号线包括列向设置的第一数据线和第二数据线；
    所述第二数据线数量为一，位于所述阵列基板的最右侧，与所述第二数据线耦接的对应所述像素电路位于所述第二数据线的左侧；
    除所述第二数据线之外，其余列向设置的信号线均为所述第一数据线，且所有的所述第一数据线均位于与其耦接的对应所述像素电路的左侧。
  6. 根据权利要求4所述的阵列基板，其中，
    所述信号线包括列向设置的第一数据线和第二数据线；
    所述第一数据线数量为一，位于所述阵列基板的最左侧，与所述第一数据线耦接的对应所述像素电路位于所述第一数据线的右侧；
    除所述第一数据线之外，其余列向设置的信号线均为所述第二数据线，且所有的所述第二数据线均位于与其耦接的对应所述像素电路的右侧。
  7. 根据权利要求4所述的阵列基板，其中，
    所述信号线包括行向设置的第一栅极线和第二栅极线；
    所述第二栅极线数量为一，位于所述阵列基板的最下侧，与所述第二栅极线耦接的对应所述像素电路位于所述第二栅极线的上侧；
    除所述第二栅极线之外，其余列向设置的信号线均为所述第一栅极线，且所有的所述第一栅极线均位于与其耦接的对应所述像素电路的上侧。
  8. 根据权利要求4所述的阵列基板，其中，
    所述信号线包括行向设置的第一栅极线和第二栅极线；
    所述第一栅极线数量为一，位于所述阵列基板的最上侧，与所述第一栅极线耦接的对应所述像素电路位于所述第二栅极线的下侧；
    除所述第一栅极线之外，其余列向设置的信号线均为所述第二栅极线，且所有的所述第二栅极线均位于与其耦接的对应所述像素电路的下侧。
  9. 根据权利要求4所述的阵列基板，其中，
    所述像素电路包括多晶硅层，所述多晶硅层通过过孔与所述信号线耦接。
  10. 根据权利要求4所述的阵列基板，其中，
    所述阵列基板进一步包括遮光层，设置于所述基层上，所述像素电路及所述信号线之下，且所述遮光层与所述像素电路和所述像素电极的耦接处对应设置。
  11. 一种显示设备，包括：
    基层；
    像素电路，以矩阵排列方式设置于所述基层上；
    信号线，以行或列方向设置于所述基层上，耦接所述像素电路；
    其中，至少两条同向的所述信号线分别设置于在所述矩阵排列的所述像素电路相对最外侧。
  12. 根据权利要求11所述的显示设备，其中，
    所述信号线包括列向设置的第一数据线和第二数据线；
    所述第二数据线数量为一，位于所述阵列基板的最右侧，与所述第二数据线耦接的对应所述像素电路位于所述第二数据线的左侧；
    除所述第二数据线之外，其余列向设置的信号线均为所述第一数据线，且所有的所述第一数据线均位于与其耦接的对应所述像素电路的左侧。
  13. 根据权利要求11所述的显示设备，其中，
    所述信号线包括列向设置的第一数据线和第二数据线；
    所述第一数据线数量为一，位于所述阵列基板的最左侧，与所述第一数据线耦接的对应所述像素电路位于所述第二数据线的右侧；
    除所述第一数据线之外，其余列向设置的信号线均为所述第二数据线，且所有的所述第二数据线均位于与其耦接的对应所述像素电路的右侧。
  14. 根据权利要求11所述的显示设备，其中，
    所述信号线包括行向设置的第一栅极线和第二栅极线；
    所述第二栅极线数量为一，位于所述阵列基板的最下侧，与所述第二栅极线耦接的对应所述像素电路位于所述第二栅极线的上侧；
    除所述第二栅极线之外，其余列向设置的信号线均为所述第一栅极线，且所有的所述第一栅极线均位于与其耦接的对应所述像素电路的上侧。
  15. 根据权利要求11所述的显示设备，其中，
    所述信号线包括行向设置的第一栅极线和第二栅极线；
    所述第一栅极线数量为一，位于所述阵列基板的最上侧，与所述第一栅极线耦接的对应所述像素电路位于所述第二栅极线的下侧；
    除所述第一栅极线之外，其余列向设置的信号线均为所述第二栅极线，且所有的所述第二栅极线均位于与其耦接的对应所述像素电路的下侧。
  16. 根据权利要求11所述的显示设备，其中，
    所述像素电路包括多晶硅层，所述多晶硅层通过过孔与所述信号线耦接。
  17. 根据权利要求11所述的显示设备，其中，
    所述显示设备进一步包括遮光层，设置于所述基层上，所述像素电路及所述信号线之下，且所述遮光层与所述像素电路和所述像素电极的耦接处对应设置。
PCT/CN2017/107146 2017-07-25 2017-10-20 一种阵列基板和一种显示设备 Ceased WO2019019437A1 (zh)

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