WO2019017447A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2019017447A1
WO2019017447A1 PCT/JP2018/027161 JP2018027161W WO2019017447A1 WO 2019017447 A1 WO2019017447 A1 WO 2019017447A1 JP 2018027161 W JP2018027161 W JP 2018027161W WO 2019017447 A1 WO2019017447 A1 WO 2019017447A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
layer
gate
region
liner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/027161
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
勇志 萩野
健太 合田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Publication of WO2019017447A1 publication Critical patent/WO2019017447A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes

Definitions

  • a P-type outer peripheral resurf layer 28 is formed below the shield liner 27. Furthermore, in the outer peripheral region 2, a P-type layer 29 connected to the outer peripheral resurf layer 28 is formed in a region different from the lower side of the shield liner 27.
  • a guard ring 30 surrounding the cell region 1 is configured by connecting the outer circumferential resurf layer 28 and the P-type layer 29.
  • the P-type layer 29 corresponds to the third impurity region.

Landscapes

  • Electrodes Of Semiconductors (AREA)
PCT/JP2018/027161 2017-07-21 2018-07-19 半導体装置およびその製造方法 Ceased WO2019017447A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017141943A JP6866792B2 (ja) 2017-07-21 2017-07-21 半導体装置およびその製造方法
JP2017-141943 2017-07-21

Publications (1)

Publication Number Publication Date
WO2019017447A1 true WO2019017447A1 (ja) 2019-01-24

Family

ID=65015516

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/027161 Ceased WO2019017447A1 (ja) 2017-07-21 2018-07-19 半導体装置およびその製造方法

Country Status (2)

Country Link
JP (1) JP6866792B2 (enExample)
WO (1) WO2019017447A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114078710A (zh) * 2020-08-13 2022-02-22 意法半导体有限公司 具有自对准多晶对多晶隔离的分裂栅沟槽功率mosfet
WO2022045135A1 (ja) * 2020-08-26 2022-03-03 株式会社デンソー 半導体装置
WO2022045136A1 (ja) * 2020-08-26 2022-03-03 株式会社デンソー 半導体装置およびその製造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7319754B2 (ja) * 2020-08-19 2023-08-02 株式会社東芝 半導体装置
JPWO2022201893A1 (enExample) * 2021-03-26 2022-09-29
KR102564714B1 (ko) * 2021-12-16 2023-08-09 파워큐브세미 (주) P 베이스에 전기적으로 연결된 쉴드를 갖는 트렌치 게이트 모스펫 및 그 제조 방법
CN118077058B (zh) * 2022-09-23 2025-11-21 华为数字能源技术有限公司 半导体器件、制备方法、功率转换电路及车辆
CN118140314B (zh) * 2022-09-23 2025-11-21 华为数字能源技术有限公司 半导体器件、制备方法、功率转换电路及车辆

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04162572A (ja) * 1990-10-25 1992-06-08 Toshiba Corp 半導体装置
WO1999012214A1 (fr) * 1997-08-29 1999-03-11 Mitsubishi Denki Kabushiki Kaisha Dispositif a semi-conducteur a grille isolee et procede de fabrication
JP2012059841A (ja) * 2010-09-07 2012-03-22 Toshiba Corp 半導体装置
JP2013143522A (ja) * 2012-01-12 2013-07-22 Toyota Motor Corp スイッチング素子
US20140197483A1 (en) * 2008-11-14 2014-07-17 Semiconductor Components Industries, Llc Trench shielding structure for semiconductor device and method
JP2017017078A (ja) * 2015-06-29 2017-01-19 株式会社東芝 半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8174067B2 (en) * 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04162572A (ja) * 1990-10-25 1992-06-08 Toshiba Corp 半導体装置
WO1999012214A1 (fr) * 1997-08-29 1999-03-11 Mitsubishi Denki Kabushiki Kaisha Dispositif a semi-conducteur a grille isolee et procede de fabrication
US20140197483A1 (en) * 2008-11-14 2014-07-17 Semiconductor Components Industries, Llc Trench shielding structure for semiconductor device and method
JP2012059841A (ja) * 2010-09-07 2012-03-22 Toshiba Corp 半導体装置
JP2013143522A (ja) * 2012-01-12 2013-07-22 Toyota Motor Corp スイッチング素子
JP2017017078A (ja) * 2015-06-29 2017-01-19 株式会社東芝 半導体装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114078710A (zh) * 2020-08-13 2022-02-22 意法半导体有限公司 具有自对准多晶对多晶隔离的分裂栅沟槽功率mosfet
WO2022045135A1 (ja) * 2020-08-26 2022-03-03 株式会社デンソー 半導体装置
WO2022045136A1 (ja) * 2020-08-26 2022-03-03 株式会社デンソー 半導体装置およびその製造方法
JP2022038240A (ja) * 2020-08-26 2022-03-10 株式会社デンソー 半導体装置
JP2022038239A (ja) * 2020-08-26 2022-03-10 株式会社デンソー 半導体装置
JP7392613B2 (ja) 2020-08-26 2023-12-06 株式会社デンソー 半導体装置
JP7392612B2 (ja) 2020-08-26 2023-12-06 株式会社デンソー 半導体装置

Also Published As

Publication number Publication date
JP2019021871A (ja) 2019-02-07
JP6866792B2 (ja) 2021-04-28

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