WO2019017447A1

WO2019017447A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2019017447A1
Application number: PCT/JP2018/027161
Authority: WO
Inventors: 勇志萩野; 健太合田
Original assignee: 株式会社デンソー
Priority date: 2017-07-21
Filing date: 2018-07-19
Publication date: 2019-01-24
Also published as: JP6866792B2; JP2019021871A

Abstract

The present invention is provided with: a semiconductor substrate (10) including a drift layer (12), a channel layer (13), a first impurity region (15), and a second impurity region (11); a trench gate structure having a gate electrode (18) disposed in a trench (16) via a gate insulation film (17); and a gate liner (19) electrically connected to a gate electrode (18). The gate liner (19) is formed into a state of extending in a direction intersecting the longitudinal direction of the trench (16) and of intersecting the trench (16), when viewed from a normal direction with respect to the plane direction of the semiconductor substrate (10). The channel layer (13) is formed in a region different from a region positioned below the gate liner (19). A RESURF layer (14) connected to the channel layer (19) is formed, on the drift layer (12), in a region positioned below the gate liner (19).

Description

Semiconductor device and method of manufacturing the same

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on Japanese Patent Application No. 201-141,943 filed on July 21, 2017, the contents of which are incorporated herein by reference.

The present disclosure relates to a semiconductor device having a trench gate structure and a method of manufacturing the same.

Conventionally, a semiconductor device in which a MOSFET having a trench gate structure (that is, a Metal Oxide Semiconductor Field Effect Transistor) element is formed has been proposed (see, for example, Patent Document 1). Specifically, this semiconductor device is configured using a semiconductor substrate in which a P-type channel layer is formed on an N ⁻ -type drift layer, and an N ⁺ -type source layer is formed on the surface layer portion of the channel layer. ing. In the semiconductor substrate, a plurality of trenches are formed from one side so as to penetrate the source layer and the channel layer. Each trench is filled with a gate insulating film formed on the wall surface and a gate electrode formed on the gate insulating film. In addition, on one surface of the semiconductor substrate, a gate liner electrically connected to the gate electrode is formed at a portion different from the portion where the trench is formed. In other words, the gate liner is formed on one surface of the semiconductor substrate so as not to cross the trench.

Furthermore, on one surface of the semiconductor substrate, a first electrode electrically connected to the source layer and the channel layer is disposed. Further, on the other surface opposite to the one surface of the semiconductor substrate, a second electrode electrically connected to the drain layer is disposed.

Such a semiconductor device is manufactured as follows. That is, first, a trench is formed in a semiconductor substrate, and a gate insulating film is formed on the wall surface of the trench by thermal oxidation or the like. Next, polysilicon (hereinafter referred to as Poly-Si) is deposited by CVD (that is, Chemical Vapor Deposition) or the like so as to fill the trench, and a gate electrode is formed. Subsequently, Poly-Si formed on the semiconductor substrate is patterned to form a gate liner. Then, a channel layer and a source layer are formed by ion implantation of a P-type impurity or an N-type impurity and heat treatment. Thereafter, the semiconductor device is manufactured by appropriately forming the first electrode, the second electrode, and the like.

JP, 2017-45827, A

By the way, in recent years, it has been desired to miniaturize a semiconductor device. For this reason, the present inventors examined making the semiconductor device smaller by forming the gate liner so as to cross the trench. However, if a semiconductor device in which the gate liner intersects with the trench is manufactured by the above manufacturing method, the gate liner functions as a mask to form a channel layer or the like after forming the gate liner and ion implantation of impurities. The channel layer is not formed in the area under the liner. That is, the drift layer directly reaches one surface of the semiconductor substrate below the gate liner. Therefore, when the semiconductor device is manufactured by the above manufacturing method, the high electric field is likely to be concentrated in the region under the gate liner, and the leak current is easily generated.

An object of the present disclosure is to provide a semiconductor device which can make it difficult to generate a leak current while miniaturizing the semiconductor device, and a method of manufacturing the same.

According to one aspect of the present disclosure, a semiconductor device having a trench gate structure includes a drift layer of a first conductivity type, a channel layer of a second conductivity type formed on the drift layer, and a surface layer portion of the channel layer. A first conductivity type or a second conductivity type formed on the opposite side of the channel layer from the formed first impurity region of the first conductivity type and the drift layer and having a higher impurity concentration than the drift layer A semiconductor substrate having an impurity region, the first impurity region and the channel layer are penetrated to reach the drift layer, and a predetermined gate voltage is applied through a gate insulating film in a trench whose longitudinal direction is a predetermined direction. A trench gate structure in which a gate electrode is disposed, and a gate liner formed on a semiconductor substrate and electrically connected to the gate electrode, the gate liner facing in the surface direction of the semiconductor substrate When viewed from the normal direction, the channel layer extends in a direction intersecting with the longitudinal direction of the trench and intersects the trench, and the channel layer is formed in a region different from the region located below the gate liner. The resurf layer of the first conductivity type connected to the channel layer is formed on the drift layer and in the region located below the gate liner.

According to this, the gate liner is formed to intersect with the trench when viewed from the normal direction to the surface direction of the semiconductor substrate. Therefore, the semiconductor device can be miniaturized as compared with the case where the gate liner is formed so as not to cross the trench.

Also, a resurf layer is formed below the gate liner. Therefore, compared with the case where the resurf layer is not formed, the high electric field extending from the drain layer side can be suppressed from reaching the region under the gate liner, and the generation of the leak current can be suppressed.

Further, according to another aspect of the present disclosure, in a method of manufacturing a semiconductor device having a trench gate structure, preparing a semiconductor substrate having a drift layer of a first conductivity type, and using the semiconductor substrate in a predetermined direction as a longitudinal direction. Forming a trench gate structure by forming a trench to be formed, forming a gate electrode to which a predetermined gate voltage is applied through the gate insulating film in the trench, and forming a gate electrode and electricity on the semiconductor substrate And forming a channel layer of the second conductivity type on the drift layer by forming a gate liner to be connected to each other and forming a gate liner, and then ion-implanting impurities and performing heat treatment. Forming a first impurity region of the first conductivity type in the surface layer portion of the semiconductor device, and forming the gate liner in the direction of the surface of the semiconductor substrate. When viewed from the normal direction, the gate liner is formed to extend in a direction intersecting with the longitudinal direction of the trench and to cross the trench, and the region under the gate liner is formed before forming the trench. The formation of the resurf layer of the second conductivity type is performed, and the formation of the channel layer is such that the channel layer connected to the resurf layer is formed.

According to this, the resurf layer is formed before forming the gate liner. Therefore, a semiconductor device in which the resurf layer is formed under the gate liner can be manufactured.

The reference numerals in parentheses attached to each component, etc., shows an example of a relationship of the specific component such as described in the following embodiments and their components, and the like.

FIG. 2 is a plan layout view of the semiconductor device. FIG. 2 is a cross-sectional view taken along the line II-II in FIG. FIG. 3 is a cross-sectional view taken along the line III-III in FIG. FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 2; FIG. 5B is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5A; FIG. 5C is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5B; FIG. 5C is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5C; FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 3; It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. 6A. FIG. 6C is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 6B; FIG. 6C is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 6C; FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 4; FIG. 7B is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 7A; FIG. 7C is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 7B; FIG. 7C is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 7C; It is sectional drawing of the semiconductor device in 2nd Embodiment. FIG. 19 is a cross-sectional view of a semiconductor device different from FIG. 8 in the second embodiment. It is a plane layout figure of the semiconductor device in a 2nd embodiment. FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 8; FIG. 11B is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 11A. FIG. 11C is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 11B; FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 9; It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. 12A. FIG. 12C is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 12B; It is a plane layout figure of the semiconductor device in a 3rd embodiment. It is a plane layout figure of the semiconductor device in a 4th embodiment.

Hereinafter, embodiments of the present disclosure will be described based on the drawings. In the following embodiments, parts that are the same as or equivalent to each other will be described with the same reference numerals.

First Embodiment
The first embodiment will be described. First, the configuration of the semiconductor device of the present embodiment will be described. As shown in FIG. 1, the semiconductor device of this embodiment has a cell region 1 and an outer peripheral region 2 surrounding the cell region. The cell area 1 has a main area 1a and a connection area 1b. FIG. 1 is a plan layout view showing the positional relationship between the gate electrode 18, the gate liner 19, and the resurf layer 14 which will be described later, and is not a cross sectional view, but the gate electrode 18 and the gate liner are easy to understand. 19 is hatched. In addition, the cell region 1 of the present embodiment is a portion in which a gate electrode 18 described later is disposed and mainly exerts a function as an element for flowing a current. The connection region 1 b is a region in which a gate liner 19 described later in the cell region 1 is disposed, and the main region 1 a is a region different from the connection region 1 b in the cell region 1.

The semiconductor device is formed on the surfaces of the N ⁺ -type drain layer 11 and the drain layer 11 as shown in FIGS. 2 to 4 and has an N ⁻ -type drift whose impurity concentration is lower than that of the drain layer 11. A semiconductor substrate 10 having a layer 12 is provided. The drain layer 11 is formed of an N ⁺ -type silicon substrate or the like in which the impurity concentration is high. Further, in the present embodiment, the drain layer 11 corresponds to the second impurity region.

On the drift layer 12 (ie, on the side of the surface 10a of the semiconductor substrate 10), as shown in FIGS. 2 and 4, the P-type channel layer 13 having a relatively low impurity concentration is set in the main region 1a. It is formed. Further, as shown in FIGS. 3 and 4, on the drift layer 12, a P-type resurf layer 14 in which the impurity concentration is substantially equal to that of the channel layer 13 is formed in the connection region 1b. In the present embodiment, the resurf layer 14 is formed to substantially the same depth as the channel layer 13. In addition, the resurf layer 14 is formed along the extending direction of the gate liner 19 described later, and is formed in the entire region below the gate liner 19. That is, the resurf layer 14 is formed such that the gate liner 19 described later is located in the resurf layer 14 when viewed from the normal direction to the one surface 10 a of the semiconductor substrate 10 (that is, the normal direction to the surface direction). ing.

As shown in FIGS. 2 and 4, an N ⁺ -type source layer 15 having an impurity concentration higher than that of the drift layer 12 is formed on the channel layer 13. That is, in the main region 1 a, the channel layer 13 and the source layer 15 are formed in order from the drift layer 12 side on the drift layer 12. In the present embodiment, the source layer 15 corresponds to the first impurity region.

Further, as shown in FIG. 2 and FIG. 3, a plurality of trenches 16 reaching the drift layer 12 from the one surface 10 a side are formed in the semiconductor substrate 10. In the present embodiment, the plurality of trenches 16 are formed at equal intervals in stripes along the predetermined direction of the surface direction of the surface 10a of the semiconductor substrate 10, and are formed in the main region 1a and the connection region 1b.

Specifically, the trench 16 is formed to penetrate the source layer 15 and the channel layer 13 to reach the drift layer 12 in the main region 1a, and to penetrate the drift layer 12 in the connection region 1b. It is formed to reach.

Each trench 16 is filled with a gate insulating film 17 formed so as to cover the wall surface of each trench 16 and a gate electrode 18 formed on the gate insulating film 17. Thus, a trench gate structure is configured. In the present embodiment, the gate insulating film 17 is formed of an oxide film or the like, and the gate electrode 18 is formed of Poly-Si or the like.

In the connection region 1b, as shown in FIGS. 1, 3 and 4, a gate liner 19 made of Poly-Si or the like is formed on the surface 10a of the semiconductor substrate 10. Specifically, gate liner 19 extends in a direction intersecting with the extending direction (i.e., the longitudinal direction) of trench 16 (i.e., gate electrode 18) when viewed from the normal direction to one surface 10 a of semiconductor substrate 10. It is provided and formed to intersect each trench 16. The gate liner 19 is electrically connected to each gate electrode 18 on the opening of each trench 16.

Further, in the present embodiment, the gate liner 19 is formed so as to be located in the resurf layer 14 when viewed in the normal direction to the one surface 10 a of the semiconductor substrate 10. In other words, the resurf layer 14 is formed in the entire area under the gate liner 19.

Furthermore, as shown in FIGS. 2 to 4, an interlayer insulating film 20 made of an oxide film or the like is formed on the surface 10 a of the semiconductor substrate 10 so as to cover the gate electrode 18 and the gate liner 19. There is. In the interlayer insulating film 20, a first contact hole 21 for exposing the source layer 15 and the channel layer 13 is formed in the main region 1a. Further, in the interlayer insulating film 20, a second contact hole 22 for exposing the gate liner 19 is formed in the connection region 1b.

Specifically, a plurality of first contact holes 21 are formed, and are formed so as to penetrate the source layer 15 and reach the channel layer 13 between the adjacent trenches 16 respectively. Thus, the source layer 15 is exposed from the side surface of the first contact hole 21, and the channel layer 13 is exposed from the side surface and the bottom surface of the first contact hole 21.

Further, a plurality of second contact holes 22 are formed, and are formed to expose the gate liner 19. The second contact hole 22 may be configured to expose at least a part of the gate liner 19. That is, a plurality of second contact holes 22 may be formed, or only one may be formed, for example.

A source electrode layer 23 electrically connected to the source layer 15 and the channel layer 13 through the first contact hole 21 is formed on the interlayer insulating film 20. Further, on the interlayer insulating film 20, a gate electrode layer 24 connected to the gate liner 19 through the second contact hole 22 and electrically connected to the gate electrode 18 via the gate liner 19 is formed.

In the present embodiment, the source electrode layer 23 is disposed on the interlayer insulating film 20 so as to be electrically connected to the first embedded electrode portion 23 a and the first embedded electrode portion 23 a embedded in the first contact hole 21. And a first upper electrode portion 23b. Similarly, the gate electrode layer 24 is disposed on the interlayer insulating film 20 and electrically connected to the second embedded electrode portion 24 a, and the second embedded electrode portion 24 a embedded in the second contact hole 22. It is set as the structure which has the 2nd upper layer electrode part 24b. In the present embodiment, the first and second embedded

electrode portions

23a and 24a are made of W (i.e., tungsten). That is, the first and second embedded

electrode portions

23a and 24a are so-called W plugs. The first and second upper

layer electrode portions

23b and 24b are made of Al (that is, aluminum) or the like.

A drain electrode 25 electrically connected to the drain layer 11 is formed on the opposite side of the drain layer 11 from the drift layer 12. That is, the drain electrode 25 electrically connected to the drain layer 11 is formed on the other surface 10 b of the semiconductor substrate 10.

Although not shown, a guard ring for improving the withstand voltage, an outer peripheral electrode electrically connected to the guard ring, and the like are appropriately formed in the outer peripheral region 2.

The above is the configuration of the semiconductor device in this embodiment. In the present embodiment, the N ⁺ type, the N type, and the N ⁻ type correspond to the first conductivity type, and the P type and the P ⁺ type correspond to the second conductivity type. Further, as described above, the semiconductor substrate 10 of the present embodiment is configured to include the drain layer 11, the drift layer 12, the channel layer 13, and the source layer 15.

In such a semiconductor device, a P-type resurf layer 14 is formed below the gate liner 19 in the cell region 1. Therefore, as compared with the case where the resurf layer 14 is not formed below the gate liner 19, concentration of the high electric field below the gate liner 19 can be suppressed. Therefore, it is possible to suppress the occurrence of the leak current in the portion below the gate liner 19.

Next, manufacturing steps of the semiconductor device will be described with reference to FIGS. 5A to 5D, 6A to 6D, and 7A to 7D. 5A to 5D are cross-sectional views corresponding to FIG. 2, FIGS. 6A to 6D are cross-sectional views corresponding to FIG. 3, and FIGS. 7A to 7D are cross-sectional views corresponding to FIG. It is. 5A, 6A, and 7A show the state of the same process, and FIGS. 5B, 6B, and 7B show the state of the same process. 5C, 6C and 7C show the state of the same process, and FIGS. 5D, 6D and 7D show the state of the same process.

First, as shown in FIGS. 5A, 6A, and 7A, the semiconductor substrate 10 in which the drift layer 12 is stacked on the drain layer 11 is prepared. Here, an example of preparing the semiconductor substrate 10 in which the drift layer 12 is stacked on the drain layer 11 will be described, but after performing the following steps, the other steps of the semiconductor substrate 10 are performed by ion implantation and heat treatment. The drain layer 11 may be formed on the surface 10 b side.

Next, a mask (not shown) is disposed on one surface 10 a of the semiconductor substrate 10, and a P-type impurity is appropriately ion-implanted and thermally diffused in a region under the gate liner 19 to form the resurf layer 14. . After that, the mask is removed.

Then, as shown in FIG. 5B, FIG. 6B, and FIG. 7B, a mask (not shown) is disposed, and dry etching or the like is performed to form the trench 16. Thereafter, thermal oxidation or the like is performed to form the gate insulating film 17 on the wall surface of the trench 16. In this step, an insulating film is also formed on one surface 10 a of the semiconductor substrate 10.

Subsequently, as shown in FIGS. 5C, 6C, and 7C, a Poly-Si film is formed by a CVD method or the like so that each trench 16 is buried. Thus, each trench 16 has a trench gate structure in which the gate electrode 18 is disposed via the gate insulating film 17. Then, a mask (not shown) is disposed and dry etching or the like is performed, and poly-Si formed on one surface 10 a of the semiconductor substrate 10 is appropriately patterned to form a gate liner 19. At this time, as described above, the gate liner 19 is formed so as to intersect the respective trenches 16 and to locate the resurf layer 14 below when viewed from the normal direction to the one surface 10 a of the semiconductor substrate 10. Be done. After that, the mask is removed.

In the step of forming the resurf layer 14 and the step of forming the gate liner 19, the resurf layer 14 is positioned so that the gate liner 19 is positioned in the resurf layer 14 when viewed from the normal direction to the one surface 10 a of the semiconductor substrate 10. And the gate liner 19 is formed.

Next, as shown in FIGS. 5D, 6D, and 7D, the channel layer 13 and the source layer 15 are formed by ion implantation and thermal diffusion of a P-type impurity and an N-type impurity. At this time, no impurity is implanted below the gate liner 19 by using the gate liner 19 as a mask. However, in the present embodiment, the resurf layer 14 is already formed below the gate liner 19. Therefore, in this step, the channel layer 13 is formed so as to connect the channel layer 13 and the resurf layer 14. As a result, in the cell region 1, the channel layer 13 or the resurf layer 14 is formed on the drift layer 12.

Thereafter, although not shown in the drawings, interlayer insulating film 20 is formed by CVD or the like so as to cover gate electrode 18 and gate liner 19. Then, a photoresist or the like is disposed on the interlayer insulating film 20, and the first contact hole 21 and the second contact hole 22 are formed in the interlayer insulating film 20 using the photoresist as a mask.

Subsequently, the source electrode layer 23 electrically connected to the channel layer 13 and the source layer 15 is formed, and the gate electrode layer 24 connected to the gate liner 19 is formed. When forming the source electrode layer 23 and the gate electrode layer 24, first, for example, W is embedded in the first contact hole 21 and the second contact hole 22 by the CVD method or the like, and the first and second embedded electrode portions are formed.

Form

23a, 24a. Next, the W film stacked on the interlayer insulating film 20 is removed. Thereafter, a metal film such as Al is formed on the interlayer insulating film 20 by the CVD method or the like. Then, by patterning the formed metal film, a first upper layer electrode portion 23b electrically connected to the first embedded electrode portion 23a is formed, and also electrically connected to the second embedded electrode portion 24a. To form a second upper electrode portion 24b. As described above, the semiconductor device of the present embodiment is manufactured.

As described above, in the present embodiment, the gate liner 19 is formed to intersect the trench 16 when viewed in the normal direction to the surface 10 a of the semiconductor substrate 10. Therefore, the semiconductor device can be miniaturized as compared with the case where the gate liner 19 is formed so as not to cross the trench 16.

Further, a resurf layer 14 is formed below the gate liner 19. Therefore, compared to the case where the resurf layer 14 is not formed, the high electric field extending from the drain layer 11 side can be suppressed from reaching the region under the gate liner 19, and the generation of the leak current can be suppressed.

Furthermore, the gate liner 19 is formed to be located in the resurf layer 14 when viewed in the normal direction to the one surface 10 a of the semiconductor substrate 10. That is, in the cell region 1, the channel layer 13 or the resurf layer 14 is formed on the drift layer 12. Therefore, it is possible to further suppress the occurrence of the leak current.

The resurf layer 14 is formed before the gate liner 19 is formed. Therefore, a semiconductor device in which the resurf layer 14 is disposed below the gate liner 19 can be easily manufactured.

The channel layer 13 and the source layer 15 are formed after forming the trench gate structure. Therefore, for example, conditions such as ion implantation and heat treatment at the time of forming the channel layer 13 and the source layer 15 can be changed based on a slight change in the quality of the trench 16, and a semiconductor device with high reliability can be manufactured.

Second Embodiment
The second embodiment will be described. The present embodiment is the same as the first embodiment except that the trench gate structure is modified, and the other parts are the same as the first embodiment, and thus the description thereof is omitted here.

In the present embodiment, as shown in FIGS. 8 and 9, the trench gate structure is a so-called split gate structure. Specifically, in each trench 16, the shield electrode 26 is disposed on the bottom side, and the gate electrode 18 is disposed on the opening side. That is, in each trench 16, the shield electrode 26 and the gate electrode 18 are stacked and disposed. The gate electrode 18 disposed on the upper side of the trench 16 constitutes an upper gate structure, and the shield electrode 26 disposed on the bottom side of the trench 16 constitutes a lower gate structure.

A gate insulating film 17 is disposed between the shield electrode 26 and the gate electrode 18. The gate electrode 18 is formed from the one surface 10 a side of the semiconductor substrate 10 to a position deeper than the bottom of the channel layer 13. That is, although the gate electrode 18 is disposed on the opening side of the trench 16, it is disposed such that a channel connecting the source layer 15 and the drift layer 12 is formed in the channel layer 13 when the gate voltage is applied. ing. Each gate electrode 18 is electrically connected to the gate liner 19 as in the first embodiment.

Each trench 16 is extended from the cell area 1 to the outer peripheral area 2 as shown in FIG. In the present embodiment, the trench 16 is formed such that one end in the extending direction is located in the outer peripheral region 2. Then, each shield electrode 26 is drawn to the opening of trench 16 at a portion positioned in outer periphery region 2 of trench 16 as shown in FIGS. 9 and 10, and the shield formed in outer periphery region 2 It is electrically connected to the liner 27.

In the present embodiment, the shield liner 27 is electrically connected to the source electrode layer 23 through an Al wiring or the like in a cross section different from that in FIG. 9 and has the same potential as the source electrode layer 23. That is, the shield electrode 26 is maintained at the potential of the source electrode layer 23. The shield liner 27 is extended in a direction perpendicular to the extending direction of the trench 16 on one end side in the extending direction of the trench 16 and has a shape having an end.

In the outer peripheral area 2, as shown in FIGS. 9 and 10, a P-type outer peripheral resurf layer 28 is formed below the shield liner 27. Furthermore, in the outer peripheral region 2, a P-type layer 29 connected to the outer peripheral resurf layer 28 is formed in a region different from the lower side of the shield liner 27. In the present embodiment, a guard ring 30 surrounding the cell region 1 is configured by connecting the outer circumferential resurf layer 28 and the P-type layer 29. In the present embodiment, the P-type layer 29 corresponds to the third impurity region.

The above is the configuration of the semiconductor device in this embodiment. Next, manufacturing steps of the semiconductor device will be described with reference to FIGS. 11A to 11C and FIGS. 12A to 12C. 11A to 11C are cross-sectional views corresponding to FIG. 8, and FIGS. 12A to 12C are cross-sectional views corresponding to FIG. 11A and 12A show the state of the same step, FIGS. 12B and 12B show the state of the same step, and FIGS. 11C and 12C show the state of the same step.

First, as shown in FIGS. 11A and 12A, a mask (not shown) is disposed on one surface 10a of the semiconductor substrate 10, and a P-type impurity is appropriately ion implanted at a position including the lower region where the shield liner 27 is formed. The outer peripheral resurf layer 28 is formed by heat diffusion. After that, the mask is removed. Although not shown in the drawings, this step is performed simultaneously with the step of forming the resurf layer 14.

Next, as shown in FIGS. 11B and 12B, after the trench 16 is formed, thermal oxidation, a CVD method, and the like are appropriately performed to form the above-mentioned split gate structure. At this time, the trench 16 is extended to the outer peripheral region 2. When forming the shield electrode 26, the shield electrode 26 is drawn to the opening of the trench 16 at a portion located in the outer peripheral region 2 of the trench 16. Then, Poly-Si formed on one surface 10 a of the semiconductor substrate 10 is appropriately patterned to form a shield liner 27 electrically connected to the shield electrode 26.

Subsequently, as shown in FIGS. 11C and 12C, the channel layer 13 and the source layer 15 are formed by ion implantation and thermal diffusion of a P-type impurity and an N-type impurity. In this process, below the shield liner 27, the shield liner 27 serves as a mask and no impurities are implanted. Therefore, the guard ring 30 is formed in the outer peripheral region 2 by forming the P-type layer 29 so as to be connected to the outer peripheral resurf layer 28 already formed in a cross section different from that in FIG. 12C.

After that, although not shown in the drawings, the semiconductor device is manufactured by forming the source electrode layer 23, the gate electrode layer 24, and the like as in the first embodiment.

Thus, the semiconductor device may have a split gate structure. Further, by arranging the shield electrode 26 on the bottom side of the trench 16, the occurrence of electric field concentration at the bottom of the trench 16 can be suppressed, and the breakdown voltage can be improved.

Third Embodiment
A third embodiment will be described. The present embodiment is the same as the second embodiment except that the configuration of the shield liner 27 is changed, and the other parts are the same as the second embodiment, and thus the description thereof is omitted here.

In the present embodiment, as shown in FIG. 13, shield liners 27 are formed in the outer peripheral region 2 on both end sides in the extending direction of the trench 16. Further, although not particularly illustrated, both ends of the trench 16 in the extending direction are extended to the outer peripheral region 2. The shield electrode 26 is drawn to the opening at both end sides in the extending direction of the trench 16 and is electrically connected to the shield liners 27 formed in the outer peripheral region 2.

Further, in the outer peripheral area 2, a P-type outer peripheral resurf layer 28 is formed below each shield liner 27. Then, in a region different from the lower side of the shield liner 27, a P-type layer 29 is formed which is connected to each outer circumferential resurf layer 28 and which constitutes the guard ring 30 together with each outer circumferential resurf layer 28.

As described above, in the present embodiment, each shield electrode 26 is drawn from both end sides in the extending direction of the trench 16 and is electrically connected to each shield electrode 26. Therefore, the potential in the shield electrode 26 can be made substantially even.

Such a semiconductor device is manufactured as follows, although not shown. That is, in the process of FIG. 11A and FIG. 12A, the outer circumferential resurf layer 28 is formed at a position including the lower region where each shield liner 27 is to be formed. Then, in the process of FIG. 11B and FIG. 12B, the trench 16 is formed so that both ends in the extending direction are located in the outer peripheral area 2, and the shield electrode 26 and the shield liner 27 are used at both ends located in the outer peripheral area 2. Are electrically connected.

Fourth Embodiment
A fourth embodiment will be described. The present embodiment is the same as the third embodiment except that the configuration of the shield liner 27 is changed, and the other parts are the same as the third embodiment, and thus the description thereof is omitted here.

In the present embodiment, as shown in FIG. 14, the shield liner 27 is formed so as to surround the cell region 1. That is, the shield liner 27 is formed in a frame shape and has a shape having no end. Then, an outer circumferential resurf layer 28 is formed below the shield liner 27 so as to surround the cell region 1. That is, in the present embodiment, the guard ring 30 is configured only by the outer circumferential resurf layer 28, and the P-type layer 29 is not formed.

As described above, in the present embodiment, the shield liner 27 is formed so as to surround the cell region 1. Therefore, in the entire region on the cell region 1 side in the outer peripheral region 2, it is possible to reduce the electric field strength.

Such a semiconductor device is manufactured as follows, although not shown. 11A and 12A, outer periphery RESURF layer 28 is formed to surround cell region 1, and shield liner 27 is formed to surround cell region 1 in the steps of FIG. 11B and 12B. Manufactured.

(Other embodiments)
Although the present disclosure has been described in accordance with the embodiment, it is understood that the present disclosure is not limited to the embodiment or the structure. The present disclosure also includes various modifications and variations within the equivalent range. In addition, various combinations and forms, and further, other combinations and forms including only one element, or more or less than these elements are also within the scope and the scope of the present disclosure.

For example, in each of the above embodiments, the case where the first conductivity type is N type and the second conductivity type is P type has been described, but a semiconductor device in which the first conductivity type is P type and the second conductivity type is N type It may be That is, the conductivity type of each part described in each of the above embodiments may be reversed.

In the above embodiments, the resurf layer 14 may have a higher impurity concentration than the channel layer 13. In each of the above embodiments, the resurf layer 14 may be deeper than the channel layer 13. According to these, the concentration of the high electric field can be further suppressed below the gate liner 19, and the generation of the leakage current can be further suppressed.

Furthermore, in the above embodiments, the resurf layer 14 may have a lower impurity concentration than the channel layer 13. In each of the above embodiments, the resurf layer 14 may be formed shallower than the channel layer 13. Even in such a semiconductor device, the formation of the resurf layer 14 can suppress the concentration of the high electric field below the gate liner 19.

And in the above-mentioned each embodiment, the resurf layer 14 may be formed in a part of region under the gate liner 19. Such a semiconductor device can also suppress concentration of a high electric field below the gate liner 19 as compared to the case where the resurf layer 14 is not formed.

Furthermore, in each of the above embodiments, the gate electrode 18 and the gate liner 19 may be formed of different materials. For example, the gate liner 19 may be made of aluminum or the like. Similarly, in the second to fourth embodiments, the shield electrode 26 and the shield liner 27 may be formed of different materials. For example, the shield liner 27 may be made of aluminum or the like.

In each of the above-described embodiments, instead of the drain layer 11, a P-type collector layer may be provided. That is, an IGBT (ie, Insulated Gate Bipolar Transistor) element may be formed on the semiconductor substrate 10. In such a configuration, the collector layer corresponds to the second impurity region. Further, the semiconductor device may have a super junction structure in which an N-type column region and a P-type column region are disposed on the drain layer 11.

Furthermore, in each of the above embodiments, the drain layer 11 may be formed on the surface layer portion of the drift layer 12, and a lateral semiconductor device may be used in which current flows in the surface direction of the semiconductor substrate 10.

Furthermore, in each of the above embodiments, a barrier metal made of Ti (i.e., titanium) or TiN (i.e., titanium nitride) is formed on the wall surfaces of the first contact hole 21 and the second contact hole 22. It is also good. Such a barrier metal is formed, for example, by sputtering before forming the first and second embedded

electrode portions

23a and 24a.

In each of the above embodiments, in the source electrode layer 23, the first embedded electrode portion 23a and the first upper layer electrode portion 23b may be made of the same material, and are made of, for example, aluminum. It is also good. Similarly, in the gate electrode layer 24, the second embedded electrode portion 24a and the second upper layer electrode portion 24b may be formed of the same material, and may be formed of, for example, aluminum.

Furthermore, in each of the above embodiments, the source layer 15 may be selectively formed in the surface layer portion of the channel layer 13. That is, one surface 10 a of the semiconductor substrate 10 may be configured to have the channel layer 13 and the source layer 15. In this case, the first contact hole 21 may not be formed deeper than the one surface 10 a of the semiconductor substrate 10 as long as the channel layer 13 and the source layer 15 are exposed. That is, the first contact hole 21 may be formed to expose the channel layer 13 and the source layer 15 from the one surface 10 a of the semiconductor substrate 10.

Claims

A semiconductor device having a trench gate structure, comprising:
A first conductivity type drift layer (12),
A second conductivity type channel layer (13) formed on the drift layer;
A first impurity region (15) of the first conductivity type formed in the surface layer portion of the channel layer;
A semiconductor substrate having a first impurity type or a second impurity type impurity region (11) of the first conductivity type or the second conductivity type formed opposite to the channel layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer (10),
A gate which penetrates the first impurity region and the channel layer to reach the drift layer and to which a predetermined gate voltage is applied through a gate insulating film (17) in a trench (16) whose longitudinal direction is a predetermined direction. Said trench gate structure in which an electrode (18) is arranged;
And a gate liner (19) formed on the semiconductor substrate and electrically connected to the gate electrode.
The gate liner is formed to extend in a direction intersecting the longitudinal direction of the trench and to intersect the trench when viewed in a direction normal to the surface direction of the semiconductor substrate.
The channel layer is formed in a region different from the region located below the gate liner,
A semiconductor device, wherein a resurf layer (14) of a second conductivity type connected to the channel layer is formed on the drift layer and in a region located below the gate liner.
The semiconductor device according to claim 1, wherein the gate liner is located in the resurf layer when viewed in a direction normal to a surface direction of the semiconductor substrate.
The semiconductor device according to claim 1, wherein the resurf layer has an impurity concentration higher than that of the channel layer.
The semiconductor device according to any one of claims 1 to 3, wherein the resurf layer is formed deeper than the channel layer.
In the trench, a shield electrode (26) maintained at a predetermined potential is disposed on the bottom side of the trench via the gate insulating film, and the gate electrode is disposed on the opening side of the trench. ,
Assuming that a region where the gate electrode is disposed is a cell region (1) and a region surrounding the cell region is an outer peripheral region (2):
The longitudinal end of the trench extends to the outer peripheral region,
The shield electrode is drawn to the opening of the trench at a portion located in the outer peripheral region of the trench,
A shield liner (27) electrically connected to the shield electrode at the opening of the trench is formed on the semiconductor substrate,
An outer circumferential resurf layer (28) of a second conductivity type is formed on the drift layer and in a region located below the shield liner,
The semiconductor device according to any one of claims 1 to 4, wherein a guard ring (30) including the outer circumferential resurf layer is formed in the outer circumferential region.
A method of manufacturing a semiconductor device having a trench gate structure, comprising:
Preparing a semiconductor substrate (10) having a drift layer (12) of a first conductivity type;
Forming a trench (16) having a predetermined direction as a longitudinal direction in the semiconductor substrate;
Forming the trench gate structure by forming a gate electrode (18) to which a predetermined gate voltage is applied through the gate insulating film (17) in the trench;
Forming a gate liner (19) electrically connected to the gate electrode on the semiconductor substrate;
After forming the gate liner, impurities are ion-implanted and heat treated to form a channel layer (13) of the second conductivity type on the drift layer, and to form a first conductive layer on the surface layer of the channel layer. Forming a first impurity region (15) of the
In forming the gate liner, when viewed in a direction normal to the surface direction of the semiconductor substrate, the gate liner is extended in a direction intersecting the longitudinal direction of the trench and intersects the trench. Form
Prior to forming the trench, forming a resurf layer (14) of a second conductivity type in the area below the gate liner;
A method of manufacturing a semiconductor device, comprising forming the channel layer connected to the resurf layer by forming the channel layer.
In preparing the semiconductor substrate, the semiconductor substrate having the cell region (1) in which the gate electrode is disposed and the outer peripheral region (2) surrounding the cell region is prepared.
In forming the trench, the trench extending from the cell region to the outer peripheral region is formed;
In forming the trench gate structure, forming a shield electrode (26) maintained at a predetermined potential on the bottom side of the trench, forming the gate electrode on the opening side of the trench, and Do,
In forming the shield electrode, the shield electrode drawn to the opening of the trench is formed at a portion located in the outer peripheral region of the trench,
Forming a shield liner (27) electrically connected to the shield electrode in the outer peripheral region;
Prior to forming the trench, a peripheral resurf layer (28) of a second conductivity type comprising at least a portion of a guard ring (30) surrounding the cell region, including a region beneath the shield liner. The method of manufacturing a semiconductor device according to claim 6, wherein forming is performed.
Forming the shield liner forms the shield liner having an end,
In the formation of the channel layer and the first impurity region, the ion implantation and the heat treatment are performed to connect with the outer circumferential resurf layer and form the guard ring together with the outer circumferential resurf layer. The method of manufacturing a semiconductor device according to claim 7, wherein the third impurity region (29) is formed.