JPH04162572A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04162572A JPH04162572A JP2285781A JP28578190A JPH04162572A JP H04162572 A JPH04162572 A JP H04162572A JP 2285781 A JP2285781 A JP 2285781A JP 28578190 A JP28578190 A JP 28578190A JP H04162572 A JPH04162572 A JP H04162572A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- trench
- source region
- conductivity type
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000005669 field effect Effects 0.000 claims abstract description 6
- 230000000149 penetrating effect Effects 0.000 claims abstract 2
- 239000010410 layer Substances 0.000 claims description 61
- 239000012535 impurity Substances 0.000 claims description 10
- 239000002344 surface layer Substances 0.000 claims description 4
- 108091006146 Channels Proteins 0.000 abstract description 20
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 5
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- NLZUEZXRPGMBCV-UHFFFAOYSA-N Butylhydroxytoluene Chemical compound CC1=CC(C(C)(C)C)=C(O)C(C(C)(C)C)=C1 NLZUEZXRPGMBCV-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、電力用絶縁ゲート型電界効果トランジスタ（
以下、パワーＭＯ５ＦＥＴと記す）単体を有する個別半
導体装置あるいはパワーＭＯＳ ＦＥＴを組み込んだ
ＭＯ５集積回路などの半導体装置に係り、特に断面Ｕ字
状の溝（トレンチ）構造を有する縦型のパワーＭＯ５Ｆ
ＥＴの構造に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a power insulated gate field effect transistor (
Regarding semiconductor devices such as individual semiconductor devices having a single unit (hereinafter referred to as power MO5FET) or MO5 integrated circuits incorporating power MOS FETs, in particular, vertical power MO5Fs having a trench structure with a U-shaped cross section.
Regarding the structure of ET.
（従来の技術）
パワーＭＯ５ＦＥＴは、微細加工技術の進歩により低オ
ン抵抗化の動きが急速に進んで（する。特に、低耐圧の
６０Ｖ〜１００ＶクラスのパワーＭＯＳ ＦＥＴは、
低オン抵抗化の傾向か顕著であり、現在では、フォトレ
ジスト上の制約からセルサイズの縮小に限界かみえてい
る平面構造の拡散自己整合（Ｄ Ｓ Ａ ； Ｄｉｒｆ
ｕｓｉｏｎ ５ｅｌｆ＾ｌｊｇｒ＋ｍｅｎｔ ）タイプ
を更に一歩進め、Ｉ Ｅ Ｄ ｂｌ（Ｉｎｔｅｒｎａｔ
ｉｏｎａｌ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅｓ Ｍｅ
ｅｔｉｎｇ）８６ ’−６３８などの文献に開示されて
いるよう１こ、セルサイズをより小型化できるトレンチ
構造を有スル縦型パワーＭＯＳ ＦＥＴの開発か進め
られている。(Prior art) Power MOSFETs are rapidly becoming lower on-resistance due to advances in microfabrication technology.In particular, power MOSFETs in the 60V to 100V class with low breakdown voltage are
There is a noticeable trend towards lower on-resistance, and currently there appears to be a limit to the reduction of cell size due to photoresist constraints.
Taking the I E D bl (Internat) type one step further,
ional Electron Devices Me
86'-638, a vertical power MOS FET with a trench structure that can further reduce the cell size is being developed.
第６図は、従来の縦型パワーＭＯ５ＦＥＴ（例えばＮチ
ャネルトランジスタ）における一部のセル領域を斜め方
向から見た断面構造を示しており、単位セルの平面パタ
ーンを第７図に示している。FIG. 6 shows a cross-sectional structure of a part of a cell region of a conventional vertical power MO5FET (for example, an N-channel transistor) viewed from an oblique direction, and FIG. 7 shows a planar pattern of a unit cell.
このパワーＭＯ５ＦＥＴにおいて、Ｎ５は単一セルの長
さてあり、Ｎ５ＸＮｓのセルサイズを有する単位セルの
パワーＭＯ５ＦＥＴが縦横に規則正しく多数配設されて
おり、各セルは、第１導電型（本例ではＮ＋型）のシリ
コンからなる半導体基板１０の主面に設けられている。In this power MO5FET, N5 is the length of a single cell, and a large number of unit cell power MO5FETs having a cell size of N5 The semiconductor substrate 10 is provided on the main surface of a semiconductor substrate 10 made of silicon.
ここで、１１は上記Ｎ１型の半導体基板１０の主面に設
けられた低不純物濃度を有するＮ型の第１の半導体層（
エピタキシャル層、ドレイン領域）、１２はこのエピタ
キシャル層１１の上面に拡散によって設けられた第２導
電型（本例ではＰ型）の第２の半導体層（チャネル形成
層）、１３・・・はこのチャネル形成層１２の表層部に
格子状に設けられたＮ＋型の第３の半導体層（ソース領
域）、１４はこのソース領域１３の中央部表面から前記
チャネル形成層１２の一部を貫いて前記エピタキシャル
層１１に達するように設けられた格子状のパターンを有
する幅１μｍ、深さ４μｍのトレンチ、１５はこのトレ
ンチ１４の内壁面に形成されたゲート酸化膜、Ｇはこの
ゲート絶縁膜１５上で上記トレンチ１４を埋めるように
設けられたゲート電極、１７はこのゲート電極Ｇ上を覆
うと共に前記トレンチ１４の端部から僅かに張り出して
前記ソース領域１３の一部を覆うように設けられた絶縁
膜、Ｓはこの絶縁膜１７上および前記ソース領域１３の
露出表面上および前記チャネル形成層１２の露出表面上
に設けられたソース電極、Ｄは前記半導体基板１０の裏
面に設けられたドレイン電極である。この場合、ソース
電極Ｓおよびドレイン電極りは各セルに対して一体的に
設けられ、各セルのゲート電極Ｇは共通に接続されてい
るので、各セルは並列に接続されている。Here, 11 is an N-type first semiconductor layer (with a low impurity concentration) provided on the main surface of the N1-type semiconductor substrate 10.
(epitaxial layer, drain region), 12 is a second semiconductor layer (channel forming layer) of the second conductivity type (in this example, P type) provided by diffusion on the upper surface of this epitaxial layer 11; A third N+ type semiconductor layer (source region) 14 provided in a lattice pattern on the surface layer of the channel forming layer 12 extends from the central surface of the source region 13 through a part of the channel forming layer 12 to form the third semiconductor layer 14. A trench with a width of 1 μm and a depth of 4 μm is provided to reach the epitaxial layer 11 and has a lattice pattern, 15 is a gate oxide film formed on the inner wall surface of this trench 14, and G is a trench formed on the gate insulating film 15. A gate electrode 17 is provided to fill the trench 14, and an insulating film 17 is provided to cover the gate electrode G and slightly protrude from the end of the trench 14 to cover a part of the source region 13. , S is a source electrode provided on the insulating film 17, the exposed surface of the source region 13, and the exposed surface of the channel forming layer 12, and D is a drain electrode provided on the back surface of the semiconductor substrate 10. . In this case, the source electrode S and the drain electrode are integrally provided for each cell, and the gate electrodes G of each cell are connected in common, so that each cell is connected in parallel.
このような縦型パワーＭＯＳ ＦＥＴは、幅１μｍの
トレンチ１４内にゲート電極Ｇを埋込む構造を有するの
で、セルサイズを１０μｍＸ１０μｍ以下とすることが
でき、オン抵抗を極めて小さく （１，８ｍΩ・ｃｍ
−２程度）することができるようになってきた。Such a vertical power MOS FET has a structure in which the gate electrode G is buried in the trench 14 with a width of 1 μm, so the cell size can be reduced to 10 μm x 10 μm or less, and the on-resistance is extremely small (1.8 mΩ・cm
-2).
ここで、上記パワーＭＯＳ ＦＥＴの動作原理を述べ
ておく。即ち、ソース電極Ｓを接地し、ドレイン電極り
およびゲート電極Ｇに正の電圧を印加する。このような
順バイアスの時、ゲート電圧を上げていくと、チャネル
形成層１２のうちのゲート電極Ｇに対向するトレンチ側
面領域（チャネル部）がＮ型に反転して反転層となり、
ソース領域Ｓから反転層直下のエピタキシャル層１１領
域に電子が流れる。Here, the operating principle of the power MOS FET will be described. That is, the source electrode S is grounded, and a positive voltage is applied to the drain electrode and the gate electrode G. When the gate voltage is increased under such forward bias, the trench side surface region (channel portion) facing the gate electrode G in the channel forming layer 12 is inverted to N type and becomes an inversion layer.
Electrons flow from the source region S to the epitaxial layer 11 region directly below the inversion layer.
ところで、上記したような縦型パワー
ＭＯ５ＦＥＴの構造のままで実際に形成した場合、次に
述べるような特性上の不具合が発生することが分った。By the way, it has been found that when the structure of the vertical power MO5FET as described above is actually formed, the following characteristic defects occur.
即ち、トレンチ１４の側面の凸状のコーナー部Ａ”とそ
の他の部分Ｂ”とでゲート酸化膜１５の厚さおよび膜質
が異なるという現象が生じ、その結果、閾値電圧ＶＴＲ
％出力特性（Ｉ ｎｓ−ｌ Ｙ＋ｓｌ ）が上記Ａ″部
とＢ″部とで異なることになり、特性面で様々なアンバ
ランスを引き起こすことになり、好ましくない。また、
トレンチ１４の側面のコーナー部が凹状の場合でも上記
と同様の結果となり、しかも、トレンチ１４の側面の凹
凸部に形成されるゲート酸化膜は膜質が悪く、この部分
をＭＯＳ ＦＥＴのゲート酸化膜として使用する場合
には信頼性上の不具合（例えば高温逆バイアス寿命試験
における閾値電圧ＶＴＨの劣化、リーク電流の増大など
）か発生する。That is, a phenomenon occurs in which the thickness and film quality of the gate oxide film 15 differ between the convex corner portion A'' on the side surface of the trench 14 and the other portion B'', and as a result, the threshold voltage VTR
% output characteristics (I ns-l Y+sl ) will be different between the above-mentioned A'' section and B'' section, which will cause various unbalances in terms of characteristics, which is not preferable. Also,
Even if the corner portions of the side surfaces of the trench 14 are concave, the same results as above will be obtained.Moreover, the gate oxide film formed on the uneven portions of the side surfaces of the trench 14 is of poor quality, and this portion is used as the gate oxide film of the MOS FET. When used, reliability problems (eg, deterioration of threshold voltage VTH in high temperature reverse bias life test, increase in leakage current, etc.) may occur.
そこで、トレンチ１４の側面でのゲート酸化膜の不具合
を防止するために、トレンチ１４の側面のコーナー部の
形状を滑らかに丸めるように工夫することか考えられる
か、この方法は、改善効果が低く、微細化を進める上で
も大きな制約となってくる。Therefore, in order to prevent defects in the gate oxide film on the side surfaces of the trench 14, is it possible to consider making the shape of the corners of the side surfaces of the trench 14 smoothly rounded?This method has a low improvement effect. , which becomes a major constraint in advancing miniaturization.
（発明が解決しようとする課題）
上記したように超低オン抵抗化を図った従来の縦型パワ
ーＭＯ３ＦＥＴは、トレンチの側面のコーナー部とその
他の部分とでゲート酸化膜の厚さおよび膜質か異なり、
特性面で様々なアンバランスを引き起こしたり、信頼性
上の不具合が発生するという問題がある。(Problems to be Solved by the Invention) As described above, in the conventional vertical power MO3FET that has achieved ultra-low on-resistance, the thickness and film quality of the gate oxide film differs between the corners of the trench side and other parts. Unlike,
There are problems in that it causes various imbalances in characteristics and reliability problems.
本発明は、上記問題点を解決すべくなされたもので、そ
の目的は、超低オン抵抗を有すると共に信頼性が高く、
特性面で安定な良質な縦型パワーＭＯ３ＦＥＴを有する
半導体装置を提供することにある。The present invention was made to solve the above problems, and its purpose is to have ultra-low on-resistance, high reliability,
An object of the present invention is to provide a semiconductor device having a high-quality vertical power MO3FET with stable characteristics.
［発明の構成コ
（課題を解決するための手段）
本発明は、第１導電型の半導体基板と、この半導体基板
の主面に設けられた低不純物濃度を有するドレイン領域
用の第１導電型の第１の半導体層と、この第１の半導体
層の上面に設けられたチャネル領域形成用の第２導電型
の第２の半導体層と、この第２の半導体層の表層部の一
部に設けられたソース領域用の第１導電型の第３の半導
体層と、この第３の半導体層の表面から前記第２の半導
体層の一部を貫いて前記第１の半導体層に達するように
設けられたトレンチの内壁面に形成されたゲート絶縁膜
と、このゲート絶縁膜上で前記溝を埋めるように設けら
れたゲート電極と、このゲート電極上を覆うように設け
られた絶縁膜と、この絶縁膜上および前記第３の半導体
層の露出表面上ならびに前記第２の半導体層の露出表面
上に設けられたソース電極と、前記半導体基板の裏面に
設けられたドレイン電極を備えた縦型の電力用絶縁ゲー
ト型電界効果トランジスタを有する半導体装置において
、前記溝の側面のコーナー部は絶縁ゲート型電界効果ト
ランジスタとしての機能か抑制されていることを特徴と
する。[Structure of the Invention (Means for Solving the Problem) The present invention provides a semiconductor substrate of a first conductivity type, and a first conductivity type semiconductor substrate for a drain region having a low impurity concentration provided on the main surface of the semiconductor substrate. a second semiconductor layer of a second conductivity type for forming a channel region provided on the upper surface of the first semiconductor layer, and a part of the surface layer of the second semiconductor layer. a third semiconductor layer of a first conductivity type for a source region provided, and a third semiconductor layer extending from a surface of the third semiconductor layer through a part of the second semiconductor layer to reach the first semiconductor layer. a gate insulating film formed on the inner wall surface of the provided trench, a gate electrode provided on the gate insulating film to fill the trench, and an insulating film provided to cover the gate electrode; A vertical type comprising a source electrode provided on the insulating film, the exposed surface of the third semiconductor layer, and the exposed surface of the second semiconductor layer, and a drain electrode provided on the back surface of the semiconductor substrate. In the semiconductor device having an insulated gate field effect transistor for power use, the corner portion of the side surface of the trench is characterized in that the function as an insulated gate field effect transistor is suppressed.
（作 用）
従来は不具合か生していたトレンチの側面のコーナー部
でのＭＯＳ ＦＥＴとしての機能か抑制されており、
トレンチの側面のコーナー部以外にのみ均一なチャネル
を形成することか可能になるので、超低オン抵抗を有す
ると共に信頼性が高く、特性面で安定な良質な縦型パワ
ーＭＯＳ ＦＥＴが得られる。(Function) The function as a MOS FET at the corner of the side of the trench, which used to be a problem, is suppressed.
Since it is possible to form a uniform channel only at the corners of the trench sides, a high-quality vertical power MOS FET with ultra-low on-resistance, high reliability, and stable characteristics can be obtained.
（実施例）
以下、図面を参照して本発明の実施例を詳細に説明する
。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は、個別半導体装置あるいはＭＯ５集積回路に形
成される第１実施例に係る縦型パワーＭＯＳ ＦＥＴ
の単位セルの平面パターンを示しており、この縦型パワ
ーＭＯ５ＦＥＴは、第６図および第７図を参照して前述
した従来の縦型パワーＭＯ５ＦＥＴの断面構造および平
面パターンとほぼ同様であるが、前記溝の側面のコーナ
ー部はＭＯＳ ＦＥＴとしての機能が抑制されている
点が異なり、その他は同じであるので第６図中と同じ符
号を付している。FIG. 1 shows a vertical power MOS FET according to a first embodiment formed in an individual semiconductor device or an MO5 integrated circuit.
This vertical power MO5FET has almost the same cross-sectional structure and planar pattern as the conventional vertical power MO5FET described above with reference to FIGS. 6 and 7. The difference is that the corner portions of the side surfaces of the grooves are inhibited from functioning as MOS FETs, and the rest are the same, so the same reference numerals as in FIG. 6 are given.
上記したように溝の側面のコーナー部におけるＭＯＳ
ＦＥＴとしての機能を抑制する構造の一具体例として
は、トレンチ１４によってチャネル形成層１２が分割さ
れたセルパターンのコーナー部には前記ソース領域１３
を形成しなければよく、この場合の第１図の縦型パワー
ＭＯ５ＦＥＴの形成方法の一例について第２図（ａ）乃
至（ｅ）を参照しながら簡単に説明する。As mentioned above, MOS at the corner of the side surface of the groove
As a specific example of a structure that suppresses the function as an FET, the source region 13 is located at the corner of the cell pattern where the channel forming layer 12 is divided by the trench 14.
An example of a method for forming the vertical power MO5FET shown in FIG. 1 in this case will be briefly described with reference to FIGS. 2(a) to 2(e).
まず、第２図（ａ）に示すように、不純物濃度がｌ Ｑ
”ｃ ｍ−３で厚さ１５０μｍのＮ＋型のシリコンか
らなる半導体基板１０の主面に、不純物濃度が５Ｘ１０
”ｃｍ−’で厚さが約１０μｍのＮ型のエピタキシャル
層１１をエピタキシャル成長により形成する。さらに、
このエピタキシャル層１１上に、不純物濃度がｌ Ｑ
１７ｃ ｍ−’程度で厚さが約２μｍのＰ型のチャネル
形成層１２を拡散によって形成する。引き続き、ＰＥＰ
（光蝕刻プロセス）工程およびイオン注入法を用いて
、チャネル形成層１２の表層部に不純物濃度が１０２０
ｃｍ−３程度で厚さ０．５μｍのＮ゛型の・ノース領域
１３を格子状に設ける。この場合、特にチャネル形成層
１２の露出部Ｃ゛とトレンチ形成予定領域の交差部Ａ″
にはソース領域１３を形成しないことが重要である。First, as shown in FIG. 2(a), the impurity concentration is lQ
The main surface of a semiconductor substrate 10 made of N+ type silicon with a thickness of 150 μm and an impurity concentration of 5×10
An N-type epitaxial layer 11 having a thickness of approximately 10 μm in cm is formed by epitaxial growth.
On this epitaxial layer 11, the impurity concentration is lQ
A P-type channel forming layer 12 having a thickness of about 17 cm-' and a thickness of about 2 μm is formed by diffusion. Continuing, PEP
(Photoetching process) process and ion implantation method are used to increase the impurity concentration to 1020 in the surface layer of the channel forming layer 12.
N-type north regions 13 having a width of about cm-3 and a thickness of 0.5 μm are provided in a grid pattern. In this case, in particular, the intersection A'' of the exposed portion C'' of the channel forming layer 12 and the region where the trench is to be formed.
It is important that the source region 13 is not formed.
次に、第２図（ｂ）に示すように、ドライエ・ソチング
、例えばＲＩＥ （反応性イオンエツチング）法により
、ウニノー２０のソース領域１３の中央部表面から前記
チャネル形成層１２の一部を貫いて前記エピタキシャル
層１１に達するように、幅１μｍ、深さ４μｍのトレン
チ１４を形成する。この場合、トレンチ１４をソース領
域１３の中央に沿って設けるので、トレンチ１４は格子
状のノくターンを有することになる。ここで、図中、２
１は例えば熱酸化膜、窒化膜、ＣＶＤ （気相成長）酸
化膜が順次形成された積層膜である。Next, as shown in FIG. 2(b), a part of the channel forming layer 12 is etched from the central surface of the source region 13 of the UniNo 20 by dry etching, such as RIE (reactive ion etching). A trench 14 having a width of 1 μm and a depth of 4 μm is formed so as to reach the epitaxial layer 11. In this case, since the trench 14 is provided along the center of the source region 13, the trench 14 has a grid-like notch. Here, in the figure, 2
1 is a laminated film in which, for example, a thermal oxide film, a nitride film, and a CVD (vapor phase growth) oxide film are sequentially formed.
次に、第２図（Ｃ）に示すように、ウェハ２０上の主要
全域に厚さ５００人のＳｉＯ２膜１５膜形５する。これ
によりトレンチ１４の内壁面を覆うようにゲート酸化膜
１５が形成される。引き続き、リンかドープされたポリ
シリコン膜１６をトレンチ１４が十分に埋まるまで堆積
する。このポリシリコン膜１６は後でゲート電極Ｇとし
て用いられるので、低抵抗であることが望ましく、上記
ポリシリコン膜１６を堆積した後で高濃度の不純物をド
ープしてもよい。Next, as shown in FIG. 2C, a 500-thick SiO2 film 15 is formed over the main area of the wafer 20. As a result, gate oxide film 15 is formed to cover the inner wall surface of trench 14. Subsequently, a polysilicon film 16 doped with phosphorous is deposited until the trench 14 is sufficiently filled. Since this polysilicon film 16 will be used later as a gate electrode G, it is desirable that it has a low resistance, and it may be doped with a high concentration of impurity after depositing the polysilicon film 16.
次に、第２図（ｄ）に示すように、トレンチ１４内にゲ
ート電極Ｇとなるポリシリコン膜を残すようにポリシリ
コン膜１６をエッチバックする。Next, as shown in FIG. 2(d), the polysilicon film 16 is etched back so as to leave the polysilicon film that will become the gate electrode G in the trench 14.
次に、第２図（ｅ）に示すように、全面に厚さ６０００
人のＰＳＧ （リンシリケートガラス）膜からなる絶縁
膜１７をＣＶＤ法により堆積し、ＰＥＰ工程により上記
絶縁膜１７の一部（チャネル形成層１２上の全部および
ソース領域１３上の一部）にコンタクト孔を開口する。Next, as shown in FIG. 2(e), the entire surface is coated with a thickness of 6000
An insulating film 17 made of a PSG (phosphosilicate glass) film is deposited by the CVD method, and a part of the insulating film 17 (all on the channel forming layer 12 and a part on the source region 13) is contacted by a PEP process. Open the hole.
これにより、ゲート電極Ｇ上およびトレンチ１４の端部
から僅かに張り出してソース領域１３上の一部を覆うよ
うに絶縁膜１７が設けられる。この後、全面に厚さ４μ
ｍのアルミニウム（１） ）あるいはアルミニウム・シ
リコン合金（ＡＩｌ−５ｉ）からなるソース電極Ｓを蒸
着する。さらに、前記半導体基板１０の裏面にもドレイ
ン電極りを形成し、第１図に示したような縦型パワーＭ
ＯＳ ＦＥＴを得る。Thereby, the insulating film 17 is provided so as to slightly protrude from the gate electrode G and the end of the trench 14 and cover a part of the source region 13. After this, apply a layer of 4μ thick to the entire surface.
A source electrode S made of aluminum (1) or an aluminum-silicon alloy (AIl-5i) is deposited. Furthermore, a drain electrode layer is also formed on the back surface of the semiconductor substrate 10, and a vertical power M as shown in FIG.
Obtain OS FET.
上記実施例の縦型パワーＭＯＳ ＦＥＴによれば、基
本的には前述した従来の縦型パワーＭＯ５ＦＥＴと同様
の動作が得られるが、従来の縦型パワーＭＯＳ ＦＥ
Ｔの技術の延長上でソースＰＥＰ工程のマスク変更・に
よって単にソース領域１３の拡散形状を変更するだけで
（新規な技術を必要としないで）、従来は不具合が生じ
ていたトレンチ１４の側面のコーナー部でのＭＯＳ
ＦＥＴとしての機能を抑制し、トレンチ１４の側面のコ
ーナー部以外にのみ均一なチャネル部を形成することが
可能になるので、超低オン抵抗を有すると共に信頼性が
高く、特性面で安定な良質な縦型パワーＭＯ５ＦＥＴが
得られる。According to the vertical power MOS FET of the above embodiment, basically the same operation as the conventional vertical power MO5FET described above can be obtained;
By simply changing the diffusion shape of the source region 13 by changing the mask in the source PEP process (no new technology is required), the side surface of the trench 14, which has conventionally caused problems, can be improved. MOS at the corner
Since it is possible to suppress the function as an FET and form a uniform channel section only in the corners other than the sidewalls of the trench 14, it has ultra-low on-resistance, high reliability, and high quality with stable characteristics. A vertical power MO5FET can be obtained.
第３図乃至第５図は、それぞれ本発明に係る縦型パワー
ＭＯ５ＦＥＴの他の実施例を示している。3 to 5 each show other embodiments of the vertical power MO5FET according to the present invention.
即ち、第３図に示す縦型パワーＭＯ３ＦＥＴは、第１図
に示した縦型パワーＭＯＳ ＦＥＴと比べて、前記ト
レンチ１４によって前記チャネル形成層１２が分割され
たセルパターンの各コーナー部にＰ＋型の第４の半導体
層３０が拡散によって形成されている点が異なり、その
他は同しであるので第１図中と同じ符号を付している。That is, the vertical power MO3FET shown in FIG. 3 differs from the vertical power MOSFET shown in FIG. The difference is that the fourth semiconductor layer 30 in FIG. 1 is formed by diffusion, and the other features are the same, so the same reference numerals as in FIG. 1 are given.
この縦型パワーＭＯ３ＦＥＴによっても、トレンチ１４
の側面のコーナー部はＭＯＳ ＦＥＴとしての動作が
阻止されるので、第１図の縦型パワーＭＯ３ＦＥＴと同
様の効果が得られる。なお、セルパターンの各コーナー
部には、ソース領域１３が形成されていてもいなくそも
よい。Even with this vertical power MO3FET, the trench 14
Since the corner portions of the side faces are prevented from operating as a MOS FET, the same effect as the vertical power MO3FET shown in FIG. 1 can be obtained. Note that it is not a problem even if the source region 13 is formed at each corner of the cell pattern.
また、第４図に示す縦型パワーＭＯ５ＦＥＴは、第１図
に示した縦型パワーＭＯＳ ＦＥＴと比べて、前記ト
レンチ１４によ、って前記チャネル形成層１２が分割さ
れたセルパターンは略長方形であり、このセルパターン
のコーナー部以外の長辺側にのみ前記ソース領域１３が
形成されている（短辺側にはソース領域１３が形成され
ていない）点が異なり、その他は同しであるので第１図
中と同じ符号を付している。Furthermore, in the vertical power MOSFET shown in FIG. 4, compared to the vertical power MOSFET shown in FIG. 1, the cell pattern in which the channel forming layer 12 is divided by the trench 14 is approximately rectangular. They are the same except that the source region 13 is formed only on the long side of the cell pattern other than the corner portion (the source region 13 is not formed on the short side). Therefore, the same reference numerals as in FIG. 1 are given.
この縦型パワーＭＯ３ＦＥＴによれば、第１図の縦型パ
ワーＭＯ５ＦＥＴと同様の効果か得られるほか、均一な
チャネル幅を効率よく確保することができる。According to this vertical power MO3FET, not only the same effect as the vertical power MO5FET shown in FIG. 1 can be obtained, but also a uniform channel width can be efficiently ensured.
また、第５図に示す縦型パワーＭＯ５ＦＥＴは、第１図
に示した縦型パワーＭＯ５ＦＥＴと比べて、前記トレン
チ１４か構造的に各々分離独立しており、互いに独立に
各トレンチ１４内にそれぞれ形成されたゲート電極Ｇ相
互を電気的に接続する例えば不純物がドープされたポリ
シリコンからなるゲート配線５１が設けられ、このゲー
ト配線５１の直下には寄生素子動作を防ぐために前記ソ
ース領域１３が形成されていない点が異なり、その他は
同じであるので第１図中と同じ符号を付している。Further, in the vertical power MO5FET shown in FIG. 5, compared to the vertical power MO5FET shown in FIG. A gate wiring 51 made of polysilicon doped with impurities, for example, is provided to electrically connect the formed gate electrodes G to each other, and the source region 13 is formed directly under this gate wiring 51 in order to prevent parasitic element operation. The difference is that this is not the case, and the rest is the same, so the same reference numerals as in FIG. 1 are given.
この縦型パワーＭＯ３ＦＥＴにおいても、トレンチ１４
の側面のゲート酸化膜１５の膜厚および膜質の不均一が
あっても、トレンチ１４の側面のコーナー部はＭＯＳ
ＦＥＴとしての機能が抑制されているので、第１図の
縦型パワーＭＯ３ＦＥＴと同様の効果が得られる。Also in this vertical power MO3FET, the trench 14
Even if there is non-uniformity in the thickness and quality of the gate oxide film 15 on the side surfaces of the trench 14, the corner portions on the side surfaces of the trench 14 are
Since the function as an FET is suppressed, the same effect as the vertical power MO3FET shown in FIG. 1 can be obtained.
［発明の効果コ
上述したように本発明によれば、超低オン抵抗を有する
と共に信頼性が高く、特性面で安定な良質な縦型パワー
ＭＯＳ ＦＥＴを有する半導体装置を実現することが
できる。[Effects of the Invention] As described above, according to the present invention, it is possible to realize a semiconductor device having a high-quality vertical power MOS FET that has ultra-low on-resistance, high reliability, and stable characteristics.
第１図は本発明の一実施例に係る縦型パワーＭＯ３ＦＥ
Ｔの単位セルを示す平面図、断面図、第２図（ａ）乃至
（ｅ）は第１図の縦型パワーＭＯ３ＦＥＴの形成方法の
一例を模式的に示す斜視図および断面図、第３図は本発
明の他の実施例に係る縦型パワーＭＯ５ＦＥＴを示す斜
視図、第４図および第５図はそれぞれ本発明のさらに他
の実施例に係る縦型パワーＭＯＳ ＦＥＴを示す平面
図、第６図は縦型パワーＭＯ８ＦＥＴにおける一部のセ
ル領域を取り出して一部断面で示す斜視図、第７図は従
来の縦型パワーＭＯ５ＦＥＴの単位セルを示す平面図で
ある。
１０・・・Ｎ＋型の半導体基板、１１・・・Ｎ型の第１
の半導体層（エピタキシャル層、ドレイン領域）、１２
・・Ｐ型の第２の半導体層（チャネル形成層）、１３・
・・Ｎ゛型の第３の半導体層（ソース領域）、１４・・
・トレンチ、１５・・・ゲート酸化膜、１６・・・ポリ
シリコン膜、１７・・・絶縁膜、Ｇ・・・ゲート電極、
Ｓ・・・ソース電極、Ｄ・・・ドレイン電極、２０・・
・ウェハ、３０・・・Ｐ゛型の第４の半導体層、５１・
・・ゲート配線。
出願人代理人 弁理士 鈴江武彦
）り
第１図
（ａ）
第２図
（ｄ）
（ｅ）
第２図
第３図
第４図
第５図
第６図FIG. 1 shows a vertical power MO3FE according to an embodiment of the present invention.
2 (a) to (e) are a perspective view and a sectional view schematically showing an example of a method for forming the vertical power MO3FET of FIG. 1, and FIG. 6 is a perspective view showing a vertical power MO5FET according to another embodiment of the present invention, FIGS. 4 and 5 are plan views showing a vertical power MOSFET according to still another embodiment of the present invention, respectively The figure is a perspective view showing a partial cross section of a part of the cell area of a vertical power MO8FET, and FIG. 7 is a plan view showing a unit cell of a conventional vertical power MO5FET. 10...N+ type semiconductor substrate, 11...N type first
semiconductor layer (epitaxial layer, drain region), 12
... P-type second semiconductor layer (channel forming layer), 13.
...N-type third semiconductor layer (source region), 14...
・Trench, 15... Gate oxide film, 16... Polysilicon film, 17... Insulating film, G... Gate electrode,
S...source electrode, D...drain electrode, 20...
・Wafer, 30...P'' type fourth semiconductor layer, 51.
・Gate wiring. Applicant's representative (patent attorney Takehiko Suzue) Figure 1 (a) Figure 2 (d) (e) Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
るドレイン領域用の第１導電型の第１の半導体層と、 この第１の半導体層の上面に設けられたチャネル領域形
成用の第２導電型の第２の半導体層と、この第２の半導
体層の表層部の一部に設けられたソース領域用の第１導
電型の第３の半導体層と、この第３の半導体層の表面か
ら前記第２の半導体層の一部を貫いて前記第１の半導体
層に達するように設けられた溝の内壁面に形成されたゲ
ート絶縁膜と、 このゲート絶縁膜上で前記溝を埋めるように設けられた
ゲート電極と、 このゲート電極上を覆うように設けられた絶縁膜と、 この絶縁膜上および前記第３の半導体層の露出表面上な
らびに前記第２の半導体層の露出表面上に設けられたソ
ース電極と、 前記半導体基板の裏面に設けられたドレイン電極とを備
えた縦型の電力用絶縁ゲート型電界効果トランジスタを
有する半導体装置において、前記溝の側面のコーナー部
は絶縁ゲート型電界効果トランジスタとしての機能が抑
制されていることを特徴とする半導体装置。（２）前記
溝によって前記第２の半導体層が分割されたセルパター
ンを有し、このセルパターンのコーナー部には前記ソー
ス領域用の第１導電型の第３の半導体層が形成されてい
ないことを特徴とする請求項１記載の半導体装置。 （３）前記セルパターンのコーナー部には高不純物濃度
を有する第２導電型の第４の半導体層が形成されている
ことを特徴とする請求項１または２記載の半導体装置。 （４）前記溝によって前記第２の半導体層が分割された
セルパターンを有し、このセルパターンは略長方形であ
り、このセルパターンのコーナー部以外の長辺側にのみ
前記ソース領域用の第１導電型の第３の半導体層が形成
されていることを特徴とする請求項１記載の半導体装置
。 （５）前記溝が構造的に各々分離独立しており、互いに
独立に各溝内にそれぞれ形成されたゲート電極相互を電
気的に接続する配線が設けられ、この配線の直下には前
記ソース領域用の第１導電型の第３の半導体層が形成さ
れていないことを特徴とする請求項１記載の半導体装置
。[Claims] (1) A semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type for a drain region having a low impurity concentration provided on the main surface of the semiconductor substrate; A second semiconductor layer of a second conductivity type for forming a channel region provided on the upper surface of the first semiconductor layer, and a first semiconductor layer for forming a source region provided in a part of the surface layer of the second semiconductor layer. A third semiconductor layer of a conductivity type, and an inner wall surface of a groove provided to reach the first semiconductor layer by penetrating a part of the second semiconductor layer from the surface of the third semiconductor layer. a gate insulating film provided on this gate insulating film to fill the groove; an insulating film provided to cover the gate electrode; A vertical power insulated gate field effect comprising a source electrode provided on the exposed surface of the semiconductor layer and the exposed surface of the second semiconductor layer, and a drain electrode provided on the back surface of the semiconductor substrate. 1. A semiconductor device having a transistor, wherein a corner portion of a side surface of the trench is suppressed from functioning as an insulated gate field effect transistor. (2) A cell pattern is formed in which the second semiconductor layer is divided by the groove, and a third semiconductor layer of the first conductivity type for the source region is not formed in a corner portion of the cell pattern. The semiconductor device according to claim 1, characterized in that: (3) The semiconductor device according to claim 1 or 2, wherein a fourth semiconductor layer of the second conductivity type having a high impurity concentration is formed in a corner portion of the cell pattern. (4) It has a cell pattern in which the second semiconductor layer is divided by the groove, and this cell pattern is approximately rectangular, and the cell pattern for the source region is provided only on the long sides other than the corner portions of the cell pattern. 2. The semiconductor device according to claim 1, further comprising a third semiconductor layer of one conductivity type. (5) The trenches are structurally separated and independent, and wiring is provided to electrically connect the gate electrodes formed in each trench independently, and the source region is directly under the wiring. 2. The semiconductor device according to claim 1, wherein the third semiconductor layer of the first conductivity type is not formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2285781A JP2894820B2 (en) | 1990-10-25 | 1990-10-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2285781A JP2894820B2 (en) | 1990-10-25 | 1990-10-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04162572A true JPH04162572A (en) | 1992-06-08 |
| JP2894820B2 JP2894820B2 (en) | 1999-05-24 |
Family
ID=17695987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2285781A Expired - Lifetime JP2894820B2 (en) | 1990-10-25 | 1990-10-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2894820B2 (en) |
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|---|---|---|---|---|
| JPH09500241A (en) * | 1994-06-03 | 1997-01-07 | シリコニックス インコーポレーテッド | Trench type DMOS transistor having channel blocking means at corner of cell trench |
| US5864159A (en) * | 1994-12-13 | 1999-01-26 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device structure to prevent a reduction in breakdown voltage |
| WO2000057478A3 (en) * | 1999-03-18 | 2001-08-16 | Koninkl Philips Electronics Nv | An electronic device comprising a trench gate field effect device |
| US6525375B1 (en) | 1999-10-19 | 2003-02-25 | Denso Corporation | Semiconductor device having trench filled up with gate electrode |
| US6670673B2 (en) | 2001-04-18 | 2003-12-30 | Denso Corporation | Semiconductor device and method for manufacturing semiconductor device |
| US6838735B1 (en) * | 2000-02-24 | 2005-01-04 | International Rectifier Corporation | Trench FET with non overlapping poly and remote contact therefor |
| JP2007513523A (en) * | 2003-12-02 | 2007-05-24 | ビシェイ−シリコニクス | Closed cell trench MOS field effect transistor |
| JP2011119425A (en) * | 2009-12-03 | 2011-06-16 | Renesas Electronics Corp | Semiconductor device |
| US9425271B2 (en) | 2011-03-09 | 2016-08-23 | Toyota Jidosha Kabushiki Kaisha | Insulated-gate bipolar transistor |
| JP5983864B2 (en) * | 2013-04-02 | 2016-09-06 | トヨタ自動車株式会社 | IGBT using trench gate electrode |
| JP2017017222A (en) * | 2015-07-02 | 2017-01-19 | 株式会社豊田中央研究所 | Semiconductor device |
| WO2019017447A1 (en) * | 2017-07-21 | 2019-01-24 | 株式会社デンソー | Semiconductor device and manufacturing method therefor |
| JP2019176013A (en) * | 2018-03-28 | 2019-10-10 | トヨタ自動車株式会社 | Method for manufacturing switching element |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3344381B2 (en) | 1999-08-23 | 2002-11-11 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
-
1990
- 1990-10-25 JP JP2285781A patent/JP2894820B2/en not_active Expired - Lifetime
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| WO2000057478A3 (en) * | 1999-03-18 | 2001-08-16 | Koninkl Philips Electronics Nv | An electronic device comprising a trench gate field effect device |
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| JP2011119425A (en) * | 2009-12-03 | 2011-06-16 | Renesas Electronics Corp | Semiconductor device |
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| JP5983864B2 (en) * | 2013-04-02 | 2016-09-06 | トヨタ自動車株式会社 | IGBT using trench gate electrode |
| JP2017017222A (en) * | 2015-07-02 | 2017-01-19 | 株式会社豊田中央研究所 | Semiconductor device |
| WO2019017447A1 (en) * | 2017-07-21 | 2019-01-24 | 株式会社デンソー | Semiconductor device and manufacturing method therefor |
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