WO2019015751A1 - Convertisseur analogique-numérique en pipeline comportant au moins trois canaux d'échantillonnage - Google Patents

Convertisseur analogique-numérique en pipeline comportant au moins trois canaux d'échantillonnage Download PDF

Info

Publication number
WO2019015751A1
WO2019015751A1 PCT/EP2017/068251 EP2017068251W WO2019015751A1 WO 2019015751 A1 WO2019015751 A1 WO 2019015751A1 EP 2017068251 W EP2017068251 W EP 2017068251W WO 2019015751 A1 WO2019015751 A1 WO 2019015751A1
Authority
WO
WIPO (PCT)
Prior art keywords
sample
cycle
circuit
channels
analog
Prior art date
Application number
PCT/EP2017/068251
Other languages
English (en)
Inventor
Hashem ZARE HOSEINI
Tamim FAIQ
Zhifeng LUO
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to PCT/EP2017/068251 priority Critical patent/WO2019015751A1/fr
Priority to CN201780093363.6A priority patent/CN111295843B/zh
Publication of WO2019015751A1 publication Critical patent/WO2019015751A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
    • H03M1/146—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters

Definitions

  • An analog to digital converter converts an input analog signal into a digital signal by sampling the input analog signal at uniform time intervals (i.e. the sampling period) and assigning a digital value comprising one or more bits to each sample.
  • An ADC may be implemented using several different architectures such as, but not limited to, flash (which may also be referred to as a direct-conversion or parallel), successive approximation, ramp- compare, Wilkinson, integrating, delta-encoded (which also may be referred to as a counter- ramp), sigma-delta, time-interleaved, and pipelined.
  • a pipelined ADC divides the conversion of each sample into a plurality of lower resolution cascaded stages wherein each stage generates one or more bits of the digital value assigned to the sample.
  • an ADC configured to generate a 12-bit value for each sample (which may be referred to as a 12-bit ADC) may be divided into four 3-bit stages.
  • Each stage (other than the last stage) receives an analog signal (the input analog signal or the residue from the previous stage), samples and holds the received signal, and quantizes the sample to a predetermined number of bits (e.g. 3 bits).
  • the quantized value is then converted to an analog signal and subtracted from the sample to generate a residue signal.
  • the residue signal is amplified and then passed to the next stage.
  • the last stage simply samples and quantizes the received residue signal.
  • Each stage can concurrently operate on a different sample of the input analog signal.
  • the first stage operates on the most recent sample, while the following stages operate on the residue from previous samples.
  • the concurrent operation of the stages makes pipelined ADCs suitable for applications that require high speed analog to digital conversion, such as multi GS/s applications.
  • Other suitable ADCs for high speed applications are time-interleaved ADCs, but time-interleaved ADCs suffer from time-interleaved spurs.
  • pipelined ADCs provide superior performance compared to time-interleaved ADCs in terms of spurs, conventional pipelined ADCs configured for high speed conversion suffer from high power consumption.
  • the embodiments described below are provided by way of example only and are not limiting of implementations which solve any or all of the disadvantages of known pipelined analog to digital converters.
  • a pipelined analog to digital converter comprising: a plurality of stages configured to generate one or more bits of an output digital signal from an input analog signal, at least one stage of the plurality of stages comprising: an input sample circuit comprising three or more channels, wherein one of the three or more channels is configured to sample the input analog signal in a cycle; a quantization circuit configured, in the cycle, to receive a sample from a different one of the three or more channels and quantize the received sample into one or more bits of the output digital signal; and an amplification circuit configured, in the cycle, to receive a sample from a further different one of the three or more channels and the one or more quantized bits
  • each of the input sample circuit, the quantization circuit and the amplification circuit allows each of the input sample circuit, the quantization circuit and the amplification circuit to concurrently operate on a different sample. This reduces the time constraints on these circuits allowing lower power components to be used for one or more of the input sample circuit, the quantization circuit, and the amplification circuit thus reducing the power consumption of the pipelined analog to digital converter for a given sampling rate.
  • such a pipelined analog to digital converter consumes less power than a conventional pipelined analog to digital converter for a given sampling frequency; and/or has an increased sampling rate compared to a conventional pipelined analog to digital converter for a given power consumption.
  • the quantization circuit is configured to quantize the received sample within a maximum time period, the maximum time being a sample period of the pipelined analog to digital converter. Providing the quantization circuit with a whole cycle to quantize the received sample allows lower power components (e.g. a lower power flash ADC) to be used to implement the quantization circuit thus reducing the power consumption of the pipelined analog to digital converter.
  • lower power components e.g. a lower power flash ADC
  • the amplification circuit is configured to generate the amplified residue signal for the received sample within a maximum time period, the maximum time period being a sample period of the pipelined analog to digital converter.
  • the amplification circuit with a whole cycle to generate the amplified residue signal allows lower power components (e.g. a lower power amplifier) to be used to implement the amplification circuit thus reducing the power consumption of the pipelined analog to digital converter.
  • each of the three or more channels is configured to sample the input analog signal within a maximum time period, the maximum time period being a sample period of the pipelined analog to digital converter.
  • each channel with a whole cycle to generate/obtain a sample from the input analog signal eases the requirements on the circuit driving the pipelined analog to digital converter. Specifically, it allows the circuit driving the pipelined analog to digital converter to be implemented using lower power components thus reducing the power consumption of a system comprising the pipelined analog to digital converter.
  • At least one channel of the three or more channels of the input sample circuit comprises a first sample and hold circuit and a second sample and hold circuit
  • the first sample and hold circuit is configured to sample the input analog signal in a first cycle and output the sample to the quantization circuit in a second cycle following the first cycle
  • the second sample and hold circuit is configured to sample the input analog signal in the first cycle and output the sample to the amplification circuit in a third cycle that follows the second cycle. This allows the sample to be provided to the two subsequent circuits (e.g. the quantization circuit and the amplification circuit) in different cycles.
  • the first sample and hold circuit comprises a first switch network, a capacitor network, and a second switch network, the first switch network is enabled in the first cycle so that the input analog signal is sampled onto the capacitor network in the first cycle, and the second switch network is enabled in the second cycle so as to provide the sample to the quantization circuit in the second cycle.
  • the second sample and hold circuit comprises a first switch network, a capacitor network, and a second switch network, the first switch network is enabled in the first cycle so that the input analog signal is sampled onto the capacitor network in the first cycle, and the second switch network is enabled in the third cycle so as to provide the sample to the amplification circuit in the third cycle.
  • the quantization circuit comprises a single sub-analog to digital converter that is shared by the three or more channels.
  • the single sub-analog to digital converter is a flash analog to digital converter. Flash ADCs provide a fast way to convert an analog signal to a digital signal.
  • the amplification circuit is configured to: convert the one or more bits to a second analog signal; subtract the second analog signal from the received sample to produce a residue signal; and amplify the residue signal to produce the amplified residue signal.
  • the amplification circuit comprises an amplifier configured to amplify the residue signal to produce the amplified residue signal, and the amplification circuit is further configured to, prior to amplifying the residue signal to produce the amplified residue signal, reset the amplifier.
  • An amplifier that operates continuously (e.g. without a reset) may cause memory effects. Thus, resetting the amplifier each cycle at least reduces (and, in some cases, eliminates) these memory effects.
  • the amplification circuit comprises a multiplying digital to analog converter circuit.
  • the quantization circuit quantizes the sample from a third channel of the three or more channels, and the amplification circuit generates an amplified residue signal based on the sample from a second channel of the three or more channels; in a second reference cycle immediately following the first reference cycle the second channel samples the input analog signal, the quantization circuit quantizes the sample from the first channel, and the amplification circuit generates an amplified residue signal based on the sample from the third channel; and in a third reference cycle immediately following the second reference cycle the third channel samples the input analog signal, the quantization circuit quantizes the sample from the second channel, and the amplification circuit generates an amplified residue signal based on the sample from the first channel.
  • each of the three or more channels is configured to sample the input analog signal at a rate of one third of a sampling rate of the pipelined analog to digital converter.
  • the plurality of stages comprises a second stage that follows the at least one stage, the second stage comprising one of: (i) a flash analog to digital converter; (ii) a successive approximation analog to digital converter; and (iii) a second input sample circuit comprising three or more channels, in the cycle one of the three or more channels of the second input sample circuit is configured to sample the amplified residue signal; a second quantization circuit configured, in the cycle, to receive a sample from a different one of the three or more channels of the second input sample circuit and quantize the received sample into one or more bits of the output digital signal; and a second amplification circuit configured, in the cycle, to receive a sample from a further different one of the three or more channels of the second input sample circuit and the one or more quantized bits corresponding to that sample and generate a second amplified residue signal based on the received sample and the one or more quantized bits.
  • the three or more channels comprises only three channels.
  • a method of generating one or more bits of an output digital signal representing an input analog signal comprising, in a cycle: sampling, by one channel of three or more channels, the input analog signal, the one channel of the three or more channels selected in a round-robin manner; quantizing, by a quantization circuit, a sample from a different channel of the three or more channels into one or more bits of the output digital signal; and generating, by an amplification circuit, an amplified residue signal from a sample from a further different channel of the three or more channels and the one or more bits corresponding to that sample.
  • FIG. 1 is a block diagram of a conventional pipelined ADC
  • FIG. 2 is a block diagram of an example pipelined ADC with three sample channels
  • FIG. 3 is a timing diagram illustrating an example operation of the pipelined ADC of FIG. 2;
  • FIG. 4 is a block diagram of an example implementation of the input sample circuit of FIG. 3;
  • FIG. 5 is a block diagram of an example implementation of the sample and hold circuits of FIG. 4;
  • FIG. 6 is a timing diagram illustrating example control signals for the switch networks of FIG. 5;
  • FIG. 7 is a circuit diagram of an example implementation of the sample and hold circuits of FIG. 5;
  • FIG. 8 is a flow diagram of an example method of generating a predetermined number of bits of a digital value from an analog signal.
  • an ADC is configured to convert an input analog signal into a digital signal by sampling the input analog signal at uniform time intervals (the sampling period) and assigning a digital value comprising one or more bits to each sample.
  • the term 'cycle' used herein is used to refer to the sample cycle (i.e. the sample period or sampling interval) of the ADC which is defined by the sampling frequency (or sampling rate) of the ADC.
  • the sampling frequency (or sampling rate) is the average number of samples obtained in one second.
  • Described herein are pipelined ADCs with reduced power consumption compared to conventional pipelined ADCs for the same sampling rate.
  • the reduced power consumption is achieved by having at least one stage of the pipelined ADC implement at least three sample channels.
  • the at least one stage comprises an input sample circuit, a quantization circuit and an amplification circuit.
  • the input sample circuit comprises three or more channels and each cycle one of the three or more channels samples the received analog signal.
  • the quantization circuit receives the samples from the input sample circuit one cycle after they were generated, such that the quantization circuit receives a sample from one of the three or more channels each cycle, and quantizes each received sample into one or more bits of the digital word for that sample.
  • the amplification circuit receives the samples from the input sample circuit two cycles after they were generated and the bits corresponding to that sample (or an analog signal representing the value of those bits) one cycle after they were generated, such that the amplification circuit receives a sample from one of the three or more channels and the corresponding bits from the quantization circuit (or an analog signal representing the value of those bits) each cycle, and generates an amplified residue signal based thereon.
  • each sub-circuit (the input sample circuit, quantization circuit, amplification circuit) to have a whole cycle to perform its function - i.e. the input sample circuit has a whole cycle to sample the analog signal, the quantization circuit has a whole cycle to quantize the received sample, and the amplification circuit has a whole cycle to generate the amplified residue signal.
  • FIG. 1 illustrates an example of a conventional pipelined ADC 100.
  • the conventional pipelined ADC 100 converts an input analog signal to a digital signal.
  • the conventional pipelined ADC 100 samples the input analog signal at a predetermined sampling rate and generates an X-bit digital value for each sample where X is the resolution of the conventional pipelined ADC 100.
  • the conventional pipelined ADC 100 comprises a plurality of cascaded stages 102, 104 and a time alignment module 106.
  • Each stage 102, 104 generates one or more bits of the digital value for a sample. For example, in FIG. 1 the first stage generates N1 bits, the second stage generates N2 bits, the third stage generates N3 bits and so on.
  • the first stage generates the most significant bits of the digital value and the final stage 104 generates the least significant bits of the digital value.
  • Each stage 102 other than the final stage 104, comprises a first sample and hold circuit 108, a second sample and hold circuit 1 10, a sub-analog to digital converter (sub- ADC) 1 12, a digital to analog converter (DAC) 1 14, a subtraction circuit 1 16 and an amplifier 1 18.
  • the sample and hold circuits 108, 1 10 are configured to sample the voltage of a received analog signal in a first phase (e.g. first portion) of a cycle and hold its value.
  • a second phase e.g. second portion
  • the sub-ADC 1 12 quantizes the sample from the first sample and hold circuit 108 into one or more bits (e.g. N1 , N2, N3, N4 bits) and outputs the one or more bits.
  • the DAC 1 14 converts the one or more bits output by the sub-ADC into an analog signal
  • the subtraction circuit 1 16 subtracts the analog signal from the DAC 1 14 from the sample from the second sample and hold circuit 1 10 to generate a residue signal
  • the amplifier 1 18 applies a gain (G) to the residue signal to generate an amplified residue signal.
  • the amplified residue signal is then provided to the next stage 102, 104.
  • the residue then continues through the subsequent stages (e.g. stages 2, 3 and 4) until it reaches the last or final stage 104.
  • the final stage 104 simply samples the amplified residue signal received from the previous stage (e.g. stage 4 in the example of FIG. 1 ) and quantizes the sample into a predetermined number of bits.
  • the final stage 104 is typically implemented using a flash ADC.
  • the time alignment module 106 time aligns the bits corresponding to a particular sample (e.g. via shift registers) to generate a final digital value for that sample.
  • the time alignment module 106 may also be configured to perform digital error correction on the final digital value before the final value is output.
  • stage Once a stage has processed a first sample it can process another sample in a subsequent cycle. This allows the stages to operate continuously and concurrently on different samples making pipelined ADCs suitable for high throughput or high-speed applications.
  • Each non-final stage 102 can be described as performing three main functions or operations: sampling, quantization (or digitization), and amplification (i.e. generating the amplified residue signal). Since each non-final stage 102 can only process one sample at a time the sampling, quantization, and amplification functions are all performed in the same cycle. This means that each of these three functions is completed/performed in less than a full cycle (e.g. the sampling may take 1/3 of a cycle, the quantization may take 1/3 of a cycle and the amplification may take 1/3 of a cycle). Where such conventional pipelined ADCs are used in high speed applications (e.g.
  • high speed sub- ADCs are required to provide enough time for the amplified residue signal to be generated in the same cycle as the quantization.
  • Such high speed sub-ADCs typically consume more power than lower speed sub-ADCs which increases the total power consumption of the pipelined ADC.
  • Even with a high speed sub-ADC a high-speed amplifier is typically required to implement a high speed pipelined ADC.
  • a high-speed amplifier typically consumes more power than lower speed amplifier which increases the total power consumption of the pipelined ADC.
  • One proposed solution to this problem is to reduce the time it takes to sample the received analog signal. By reducing the time it takes to sample the received analog signal, a greater portion of the fixed cycle (which is set by the fixed sampling clock) is provided to complete the quantization and amplification functions which allows a lower power sub-ADC and/or amplifier to be used. However, this increases the power consumption of the system or component that drives the ADC (i.e. the ADC driver) and thus increases the power consumption of the larger system in which the pipelined ADC forms part of.
  • a stage with a ping-pong configuration can process or operate on two samples at the same time.
  • a stage can generate/obtain a second sample without losing the first sample (e.g. it may have two sampling circuits that work in an interleaved or alternating manner). This gives the stage two cycles to process each sample. In other words, this gives the stage two cycles to perform the three key functions - sampling, quantization and amplification - for each sample.
  • the sampling is performed during a first cycle and the amplification is performed in a second cycle and the quantization is performed during the first cycle or the second cycle.
  • the received analog signal is sampled into a first sampling circuit
  • quantization and amplification is performed on the sample from the first sampling circuit while the received analog signal is sampled into a second sampling circuit. While a ping-pong configuration may provide some benefits since more time is provided to perform the three functions it still has many drawbacks.
  • the quantization is performed in the same cycle as the sampling then to significantly reduce the power of the sub-ADC (such that a lower power sub-ADC may be used) a significant portion or fraction of the first cycle has to be dedicated to the quantization, leaving only a small fraction of a cycle for the sampling. This may increase the power consumption of the ADC driver which increases the power consumption of the larger system in which the pipelined ADC forms part of.
  • both functions have to be performed in one cycle which generally requires a high-speed (and high-power consuming) quantization circuit or a high speed (and high-power consuming) amplification circuit. Accordingly, the speed of pipelined ADCs with one or more ping-pong stages is limited to achieve reasonable power consumption.
  • pipelined ADCs with at least three sample channels.
  • the pipelined ADCs described herein comprise an input sample circuit that comprises at least three sample channels which sample (and hold) the received analog signal in a round-robin, or alternating, manner.
  • the samples from the three or more channels are then provided to a quantization circuit; and subsequently to an amplification circuit in the order in which they are generated (sampled).
  • the quantization circuit quantizes the received samples and the amplification circuit generates an amplified residue signal therefrom.
  • each sub-circuit (the input sample circuit, the quantization circuit, and the amplification circuit) can operate on a different sample each cycle allowing each sub-circuit (the input sample circuit, the quantization circuit, and the amplification circuit) to have a whole cycle to perform its function.
  • the input sample circuit comprises three sample channels, however, in other examples the input sample circuit may comprise more than three sample channels.
  • the pipelined analog to digital converter may implement an N-cycle repeating pattern where N is the number of channels.
  • FIG. 2 illustrates an example pipelined ADC 200 with reduced power consumption compared to the conventional pipelined ADC 100 of FIG. 1 for the same sample period (or sampling frequency).
  • the pipelined ADC 200 of Fig. 2 converts an input analog signal to a digital signal by sampling the input analog signal at a predetermined sampling rate and generating an X-bit digital value for each sample where X is the resolution of the pipelined ADC 200.
  • the pipelined ADC 200 of FIG. 2 like the conventional pipelined ADC 100 of FIG. 1 , comprises a plurality of cascaded stages 202, 203, 204 - one or more non-final stages 202, 203 and one final stage 204 - and a time alignment module 206.
  • Each stage 202, 203, 204 is configured to generate one or more bits of the digital value for each sample. For example, in FIG. 2 the first stage generates N1 bits, the second stage generates N2 bits, the third stage generates N3 bits and so on.
  • Each stage 202, 203, 204 may generate the same number of bits (e.g.
  • five stages 202, 203, 204 are shown in FIG. 2 it will be evident to a person of skill in the art that in other examples the pipelined ADC 200 may have only two pipeline stages (e.g. a non-final stage and a final stage) or any number of stages greater than two.
  • the time alignment module 206 like the time alignment module of FIG. 1 , time aligns the bits corresponding to a particular sample (e.g. via shift registers) to generate a final digital value for that sample.
  • the time alignment module 206 may also be configured to perform digital error correction on the final digital value before the final value is output.
  • a non-final stage 202, 203 is a stage that generates a residue signal for a subsequent stage. At least one of the non-final stages 202, 203 is a modified non-final stage 202 that comprises an input sample circuit 208, a quantization circuit 210 and an amplification circuit 212.
  • the input sample circuit 208 comprises three channels 214, 216, 218 wherein the channels operate in a round-robin, or alternating, manner such that each cycle one of the channels 214, 216, 218 samples the received analog signal.
  • the first channel 214 may sample the received analog signal
  • the second channel 216 may sample the received analog signal
  • the third channel 218 may sample the received analog signal
  • the first channel 214 may sample the received analog signal and so on. In this manner each channel 214, 216 and 218 samples the received analog signal at a rate of one third of the sampling rate of the pipelined ADC 200.
  • each channel may comprise a plurality of sample and hold circuits.
  • the input sample circuit 208 and the channels 214, 216 and 218 thereof may be implemented in any suitable manner.
  • the quantization circuit 210 is configured to receive a sample from one of the three channels 214, 216, 218 of the input sample circuit 208 in each cycle and quantize the received sample into one or more bits.
  • quantization is the process of converting a real number with an approximation from a finite set of discrete values which are represented by a predetermined number of bits.
  • the number of bits used to represent the values determines the number of discrete values. For example, if eight bits are used to represent the values, then there will be 256 different discrete values.
  • the quantization circuit 210 may comprise a sub analog to digital converter (sub-ADC) 220 that quantizes the received sample into a digital value comprising one or more bits (e.g. N bits).
  • the sub-ADC is a flash ADC.
  • a flash ADC which also may be referred to as a direct conversion ADC or a parallel ADC
  • the quantization circuit 210 is configured to receive the samples from the channels 214, 216, 218 of the input sample circuit 208 in the cycle after the sample was generated by the respective channel of the input sample circuit 208.
  • the quantization circuit 210 may receive the sample from the first channel 214 and quantize that sample while a second channel 216 of the input sample circuit 208 samples the received analog signal, then in a third cycle the quantization circuit 210 may receive the sample from the second channel and quantize that sample while a third channel 218 of the input sample circuit 208 samples the received analog signal.
  • the amplification circuit 212 is configured to receive, each cycle, a sample from one of the three channels 214, 216, 218 of the input sample circuit 208 and the one or more quantized bits corresponding to that sample from the quantization circuit 210 (or an analog signal representing the value of those bits) and generate an amplified residue signal therefrom. Specifically, the amplification circuit 212 is configured to convert the one or more quantized bits into a second analog signal representing the value of those bits (if an analog signal representing the value of those bits was not initially received), subtract that second analog signal from the received sample to produce a residue signal, and amplify the residue signal to produce an amplified residue signal. The amplified residue signal is then provided to the next stage 203, 204.
  • the amplification circuit 212 may be implemented as a multiplying digital to analog converter (MDAC) circuit which is configured to generate an amplified residue signal for the sample received from one of the channels 214, 216, 218.
  • MDAC multiplying digital to analog converter
  • An example MDAC circuit is shown in FIG. 2 and comprises a digital to analog converter (DAC) 222, a subtraction circuit 224, and an amplifier 226.
  • the digital to analog converter 222 receives, each cycle, one or more bits from the quantization circuit 210 that represents bits of the sample of a particular channel and converts the one or more bits into a second analog signal.
  • the subtraction circuit 224 receives the second analog signal from the digital to analog converter 222 and a sample from one of the channels 214, 216, 218 and subtracts the second analog signal from the sample to generate a residue signal.
  • the amplifier 226 applies a gain to the residue signal generated by the subtraction circuit 224 to generate an amplified residue signal.
  • the amplification circuit 212 may be implemented in any suitable manner.
  • FIG. 2 shows a separate DAC 222 component, in other examples the DAC 222 functionality may be implemented by, or incorporated into, another component.
  • the amplification circuit 212 may be configured to reset the amplifier 226 each cycle, prior to performing the amplification. Specifically, if the amplifier 226 is configured to operate continuously (e.g. on in both phases of the cycle) this may cause memory effects because the amplifier 226 is not reset. In a conventional pipelined ADC, since less time is allocated to perform the amplification function, if a reset is performed then either the speed of the circuit is reduced or a higher speed amplifier is used (which consumes significantly more power than a lower speed amplifier) to compensate. Since a whole cycle is provided to the amplification circuit 212 to generate the amplified residue signal a reset can be inserted without having to reduce the speed of the amplification circuit 212 or significantly increase the power consumption of the amplification circuit 212.
  • the amplification circuit 212 is configured to receive the samples from the channels 214, 216, 218 of the input sample circuit 208 two cycles after the sample was generated by the respective channel of the input sample circuit 208 and to receive the one or more bits corresponding to that sample (or an analog signal representing the value of the one or more bits) in the cycle after the one or more bits were generated.
  • the first channel 214 of the input sample circuit 208 may sample the received analog signal; then in a second cycle the quantization circuit 210 may receive the sample from the first channel 214 and quantize that sample while a second channel 216 of the input sample circuit 208 samples the received analog signal; then in a third cycle the amplification circuit 212 receives the sample from the first channel 214 and the one or more bits from the quantization circuit 210 corresponding to the sample from the first channel 214 while the quantization circuit 210 receives the sample from the second channel 216 and quantizes that sample, and a third channel 218 of the input sample circuit 208 samples the received analog signal.
  • Using at least three sample channels in the input sample circuit 208 allows each of the input sample circuit 208, the quantization circuit 210, and the amplification circuit 212 to concurrently generate, or perform an operation on, a sample of a different channel of the three or more channels 214, 216, 218 in the same cycle.
  • a first channel 214 of the three channels may sample the input analog signal
  • the quantization circuit 210 may quantize the sample from the third channel 218 of the three channels and the amplification circuit 212 may generate an amplified residue signal based on the sample from a second channel 216 of the three channels.
  • each channel continuously rotates being associated with the three circuits 208, 210, 212 - i.e. each channel rotates being associated with the input sample circuit 208, the quantization circuit 210, and the amplification circuit 212.
  • each of these circuits (the input sample circuit 208, the quantization circuit 210, and the amplification circuit 212) to be allocated a maximum period to perform its function(s) equal to a full cycle.
  • each of these circuits has a full cycle to perform its function.
  • the input sample circuit 208 has a full cycle to sample the received analog signal
  • the quantization circuit 210 has a full cycle to quantize a received sample
  • the amplification circuit 212 has a whole cycle to generate the amplified residue signal for the received sample.
  • each of these circuits 208, 210, 212 with a whole cycle to perform its function(s) allows a relaxation of the time constraints on each of these circuits (i.e. each of these circuits has more time to perform its function) compared to the conventional pipelined ADC.
  • This relaxation of the time constraint allows lower power components to be used to implement these circuits thus decreasing the overall power consumption of the pipelined ADC.
  • the quantization stage is implemented by a sub-ADC it allows a lower-power sub-ADC to be used and at the same time it allows a low-power amplifier to be used in the amplification circuit.
  • the time constraints are relaxed on the input sample circuit this reduces the requirements on the component providing the input to the at least one stage (e.g. the previous stage or the driver of the pipelined ADC 200).
  • a pipelined ADC with a single modified non-final stage may improve the power consumption of the pipelined ADC compared to the conventional pipelined ADC, the more non-final stages that are implemented as modified non-final stages the more significant the reduction in the power consumption of the pipelined ADC.
  • the modified non-final stage 202 may be the first stage as shown in FIG. 2 or may be a middle stage (i.e. a stage that receives a residue signal from an earlier stage and provides a residue signal to a later stage).
  • One or more of the other stage(s) 203, 204 of the ADC may be the same as or different than the modified non-final stage.
  • the modified non-final stage may be followed by another modified non-final stage.
  • the modified non-final stage may be followed by a second modified non-final stage that comprises a second input sample circuit comprising three or more channels wherein in a cycle one of the three or more channels of the second input sample circuit is configured to sample the amplified residue signal generated by the previous modified non- final stage; a second quantization circuit configured, in the cycle to receive a sample from one of the three or more channels of the second input sample circuit and quantize the received sample into one or more bits; and a second amplification circuit configured, in the cycle, to receive a sample from one of the three or more channels of the second input sample circuit and the one or more quantized bits corresponding to that sample (or an analog signal representing the value of those bits) and generate a second amplified residue signal based on the received sample and the one or more quantized bits (or the analog signal representing the value of those bits).
  • a second modified non-final stage that comprises a second input sample circuit comprising three or more channels wherein in a cycle one of the three or more channels of the second input sample circuit is configured to sample
  • the at least one modified non-final stage may be followed by a stage 203, 204 that is implemented using any known ADC stage configuration.
  • the modified non-final stage 202 may be followed by a stage that is implemented as a flash analog to digital converter (which may be the final stage), a successive approximation analog to digital converter etc.
  • the input sample circuit 208 comprises three channels 214, 216, 218 wherein each channel comprises a first sample and hold circuit 402, 404, 406 and a second sample and hold circuit 408, 410, 412.
  • the first channel 214 comprises a first sample and hold and circuit 402 and a second sample and hold circuit 408, the second channel 216 comprises a first sample and hold circuit 404 and a second sample and hold circuit 410, and the third channel 218 comprises a first sample and hold circuit 406 and a second sample and hold circuit 412.
  • the first sample and hold circuit 402, 404, 406 of each channel is configured to sample the received analog signal every Nth cycle (where N is the number of channels) and hold the sample at least until the next cycle. In the cycle after the sample was taken (or generated) the sample is provided by the first sample and hold circuit 402, 404, 406 to the quantization circuit 210 for quantization.
  • the first sample and hold circuits 402, 404, 406 are configured to work in an alternating manner so that only one of the first sample and hold circuits 402, 404, 406 samples the received analog signal in any cycle.
  • the first sample and hold circuit 402 of the first channel 214 may sample the received analog signal; in a second cycle the first sample and hold circuit 402 of the first channel 214 may provide its sample to the quantization circuit 210 and the first sample and hold circuit 404 of the second channel 216 samples the received analog signal; in a third cycle the first sample and hold circuit 404 of the second channel 216 provides its sample to the quantization circuit 210 and the first sample and hold circuit 406 of the third channel 218 samples the received analog signal; and in a fourth cycle the first sample and hold circuit 406 of the third channel 218 provides its sample to the quantization circuit 210 and the first sample and hold circuit 404 of the first channel 214 samples the received analog signal; and so on.
  • the quantization circuit 210 receives a sample from one of the three or more channels in each cycle. This is summarized in Table 1. Table 1
  • the second sample and hold circuit 408, 410, 412 of each channel 214, 216, 218 is configured to sample the received analog signal in the same cycle as the first sample and hold circuit 402, 404, 406 of the same channel 214, 216, 218, and hold the sample at least until the second cycle after the received signal is sampled.
  • the sample is provided by the second sample and hold circuit 408, 410, 412 to the amplification circuit 212 where an amplified residue signal is generated therefor.
  • the second sample and hold circuits 408, 410, 412 are configured to sample the received analog signal in the same cycle as the first sample and hold circuits 402, 404, 406 of the same channel 214, 216, 218, the second sample and hold circuits 408, 410, 412 are also configured to work in an alternating manner so that only one of the second and sample and hold circuits 408, 410, 412 samples the received analog signal in any cycle.
  • the second sample and hold circuit 408 of the first channel 214 may sample the received analog signal; in a second cycle the second sample and hold circuit 410 of the second channel 216 samples the received analog signal; in a third cycle the second sample and hold circuit 408 of the first channel 214 provides its sample to the amplification circuit 212 and the second sample and hold circuit 412 of the third channel 218 samples the received analog signal; in a fourth cycle the second sample and hold circuit 410 of the second channel 216 provides its sample to the amplification circuit 212 and the second sample and hold circuit 408 of the first channel 214 samples the received analog signal; in a fifth cycle the second sample and hold circuit 412 of the third channel 218 provides its sample to the amplification circuit 212 and the second sample and hold circuit 410 of the second channel 216 samples the received analog signal; and so on.
  • the amplification circuit 212 receives a sample from one of the three or more channels in each cycle. This is summarized in
  • FIG. 4 illustrates example implementations for the input sample circuit, the quantization circuit and the amplification circuit.
  • Each of these circuits are independent of each other thus the example implementation of one type of circuit shown in FIG. 4 may be used not only with the example implementations of the other types of circuits shown in FIG. 4 but with other suitable implementations of those circuits.
  • the example implementation of the input sample circuit described with respect to FIG. 4 may be used with a different implementation of the amplification circuit than that shown and described with respect to FIG. 4.
  • each sample and hold circuit 402, 404, 406, 408, 410, 412 comprises a first switch network, a capacitor network, and a second switch network.
  • FIG. 5 illustrates an example implementation of the sample and hold circuits 402, 404, 406, 408, 410, 412 of FIG. 4.
  • each sample and hold circuit 402, 404, 406, 408, 410, 412 comprises a first switch network, a capacitor network, and a second switch network.
  • FIG. 5 illustrates an example implementation of the sample and hold circuits 402, 404, 406, 408, 410, 412 of FIG. 4.
  • the first sample and hold circuit 402 of the first channel 214 comprises a first switch network SN1 , a capacitor network CN1 and a second switch network SN2;
  • the first sample and hold circuit 404 of the second channel 216 comprises a first switch network SN3, a capacitor network CN2 and a second switch network SN4;
  • the first sample and hold circuit 406 of the third channel 218 comprises a first switch network SN5, a capacitor network CN3 and a second switch network SN6.
  • the second sample and hold circuit 408 of the first channel 214 comprises a first switch network SN7, a capacitor network CN4, and a second switch network SN8;
  • the second sample and hold circuit 410 of the second channel 216 comprises a first switch network SN9, a capacitor network CN5 and a second switch network SN10;
  • the second sample and hold circuit 412 of the third channel 218 comprises a first switch network SN1 1 , a capacitor network CN6 and a second switch network SN12.
  • Each switch network comprises one or more switches and each capacitor network comprises one or more capacitors.
  • each sample and hold circuit receives the analog signal as input, when the one or more capacitors of a capacitor network CN1 , CN2, CN3, CN4, CN5, CN6 is/are charged the one or more capacitors of the capacitor network CN1 , CN2, CN3, CN4, CN5, CN6 is/are charged to a value (e.g. voltage) corresponding to the received analog signal at that time.
  • a value e.g. voltage
  • the capacitor network When the one or more capacitors of a capacitor network CN1 , CN2, CN3, CN4, CN5, CN6 is/are discharged the capacitor network outputs the captured value (e.g. voltage) of the received analog signal. In other words, when discharged, the one or more capacitors of a capacitor network CN1 , CN2, CN3, CN4, CN5, CN6 output the sampled value.
  • the captured value e.g. voltage
  • the channels 214, 216, 218 are configured to operate in an alternating manner such that only one channel samples the received analog signal in a cycle. Where there are three channels this results in each channel sampling the received analog signal every third cycle.
  • the first switch network SN1 , SN7 of the first and second sample and hold circuits 402, 408 of the first channel 214 may be enabled in a first cycle;
  • the first switch networks SN3, SN9 of the first and second sample and hold circuits 404, 410 of the second channel 216 may be enabled in a second cycle;
  • the first switch networks SN5, SN1 1 of the first and second sample and hold circuits 406, 412 of the third channel 218 may be enabled in a third cycle; and so on.
  • the output of the first sample and hold circuit 402, 404, 406 of each channel 214, 216, 218 is coupled to the input of the quantization circuit 210 (e.g. sub- ADC 220).
  • the quantization circuit 210 e.g. sub- ADC 220.
  • the first sample and hold circuits 402, 404, 406 are configured to provide the captured sample to the quantization circuit 210 in the cycle immediately following the cycle in which the sample was captured (e.g.
  • each first sample and hold circuit 402, 404, 406 may be enabled in the cycle immediately following the cycle in which the capacitors(s) of the corresponding capacitor network CN1 , CN2, CN3 was/were charged.
  • the second sample and hold circuit 408, 410, 412 of each channel 214, 216, 218 is coupled to the input of the amplification circuit 212 (e.g. the MDAC circuit).
  • the amplification circuit 212 e.g. the MDAC circuit.
  • the second sample and hold circuits 408, 410, 412 are configured to provide the captured sample to the amplification circuit 212 in the cycle two cycles after the cycle in which the sample was captured (e.g.
  • each second sample and hold circuit 408, 410, 412 may be enabled in the cycle that is two cycles after the cycle in which the capacitor(s) of the corresponding capacitor network was/were charged.
  • Each switch network may be enabled by one or more control signals (e.g. a clock signal).
  • the first switch networks SN1 , SN7 of the first and second sample and hold circuits of the first channel 214 may be controlled by a sample channel 1 signal which causes the one or more capacitors of the corresponding capacitor networks CN1 , CN4 to be charged by the received analog signal every third cycle;
  • the first switch networks SN3, SN8 of the first and second sample and hold circuits of the second channel 216 may be controlled by a sample channel 2 signal which is offset from the sample channel 1 signal by one cycle which causes the one or more capacitors of the corresponding capacitor networks CN2 and CN5 to be charged by the received analog signal every third cycle;
  • the first switch networks SN5, SN9 of the first and second sample and hold circuits of the third channel 218 may be controlled by a sample channel 3 signal which causes the one or more capacitors of the corresponding capacitor networks CN3 and CN6 to be charged by the received analog signal every third cycle.
  • the second switch networks SN2, SN4, SN6 of the first sample and hold circuits 402, 404, 406 of the first, second and third channels 214, 216, 218 may be controlled by Q
  • the second switch networks SN8, SN10, SN12 of the second sample and hold circuits 408, 410, 412 of the first, second and third channels 214, 216, 218 may be controlled by A Channel 1 , 2 and 3 signals respectively which cause the one or more capacitors of the corresponding capacitor network CN4, CN5, CN6 to be discharged two cycles after the one or more capacitors of the capacitor network CN4, CN5, CN6 was/were charged (e.g. two cycles after the received analog signal was sampled).
  • the one or more capacitors of the CN2 and CN5 capacitor networks are charged, the one or more capacitors of the CN1 capacitor network is/are discharged to the quantization circuit 210, the one or more capacitors of the CN6 capacitor network is discharged to the amplification circuit 212, and the one or more capacitors of the CN4 capacitor network hold/holds its/their value.
  • the one or more capacitors of the CN3 and CN6 capacitor networks are charged by the received analog signal, the one or more capacitors of the CN2 capacitor network is/are discharged to the quantization circuit 210, the one or more capacitors of the CN4 capacitor network is/are discharged to the amplification circuit 21 1 , and the one or more capacitors of the CN5 capacitor network holds/hold its/their value.
  • FIG. 7 illustrates an example implementation of the switch and capacitor networks for a channel.
  • FIG. 7 illustrates the first and second sample and hold circuits 402 and 408 of the first channel 214.
  • the first sample and hold circuit 402 comprises a first switch S1 and a second switch S1 ' that form a first switch network SN1 , a capacitor C1 that forms a capacitor network CN1 , and a third switch S2 and a fourth switch S2' that form a second switch network SN2.
  • the second sample and hold circuit 408 comprises a first switch S7 and a second switch S7' that form a switch network SN7, a capacitor C4 that forms a capacitor network CN4, and a third switch S8 and a fourth switch S8' that forms a switch network SN8.
  • the switches of a switch network may be enabled at the same time, or one of the switches of a switch network may enabled after the other switch in the switch network. For example, in some cases S7 may be enabled after S7'.
  • switches S1 , S1 ', S7 and S7' close and charge the corresponding capacitors C1 and C4.
  • switches S1 , S1 ', S7 and S7' are open and S2 and S2' are closed so that the voltage in capacitor C1 is provided to the sub- ADC 220 which converts the voltage into an N-bit value.
  • a third cycle following the second cycle e.g.
  • switches S7 and S7' are open and switches S8 and S8' are closed such that the second analog signal (the analog signal representing the N-bit value output from the sub-ADC 220) is connected to C4 which causes the second sample and hold circuit 408 to act as a subtraction circuit to output the residue (the difference between the sample value in C4 and the second analog signal (the analog signal representing the N-bit value output from the sub-ADC 220)).
  • the residue signal is then amplified by the amplifier 226 to generate the amplified residue signal for the sample in the first channel.
  • FIG. 7 illustrates the switch and capacitor networks for the first channel 214 the switch and capacitor networks of the other channels 216, 218 may be implemented in a similar manner.
  • FIG. 8 illustrates a flow diagram of an example method 800 for generating a predetermined number of bits of a digital value representing an analog signal which may be implemented by the modified non-final stage 202 of the pipelined ADC 200 of FIG. 2.
  • the received analog signal is sampled (at block 802) by one of the three channels of the input sample circuit 208.
  • the channels are selected to be the sample channel in a round-robin manner (e.g. channel 1 is selected, channel 2 is selected, channel 3 is selected, channel 1 is selected, channel 2 is selected and so on).
  • a sample from a different channel than the channel used to sample the received analog signal is quantized (at block 804) into a predetermined number of bits. For example, if channel 1 is used to sample the received analog signal then the sample from channel 3 may be quantized. Also, in the same cycle, an amplified residue signal is generated (at block 806) for a sample from a different channel than the channel used to sample the received signal or the channel that is quantized. For example, if channel 1 is used to sample the received analog signal and the sample from channel 3 is quantized, then an amplified residue signal is generated for the sample from channel 2.
  • generating a residue signal for a sample may include generating an analog signal from the predetermined number of bits generated from the quantization to generate a second analog signal, subtracting the second analog signal from the sample to generate a residue signal, and amplifying the residue signal to generate an amplified residue signal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Selon la présente invention, un convertisseur analogique-numérique en pipeline caractérisé par au moins un étage comprend au moins trois canaux d'échantillonnage. Lesdits étages comprennent un circuit d'échantillonnage d'entrée, un circuit de quantification et un circuit d'amplification. Le circuit d'échantillonnage d'entrée comprend au moins trois canaux et chaque cycle des trois canaux échantillonne le signal analogique reçu. Le circuit de quantification reçoit les échantillons d'un cycle du circuit d'échantillonnage d'entrée après qu'ils ont été générés, de telle sorte que le circuit de quantification reçoit un échantillon d'un desdits trois canaux à chaque cycle, et quantifie chaque échantillon reçu en un ou plusieurs bit(s) du mot numérique de cet échantillon. Le circuit d'amplification reçoit les échantillons de deux cycles du circuit d'échantillonnage d'entrée après qu'ils ont été générés et les bits correspondant à un cycle de cet échantillon après qu'ils ont été générés, de telle sorte que le circuit d'amplification reçoive un échantillon provenant de l'un des au moins trois canaux et des bits correspondants provenant de chaque cycle du circuit de quantification (ou d'un signal analogique représentant ces bits), et génère un signal résiduel amplifié sur la base de ce dernier.
PCT/EP2017/068251 2017-07-19 2017-07-19 Convertisseur analogique-numérique en pipeline comportant au moins trois canaux d'échantillonnage WO2019015751A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/EP2017/068251 WO2019015751A1 (fr) 2017-07-19 2017-07-19 Convertisseur analogique-numérique en pipeline comportant au moins trois canaux d'échantillonnage
CN201780093363.6A CN111295843B (zh) 2017-07-19 2017-07-19 具有至少三条采样信道的流水线模数转换器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2017/068251 WO2019015751A1 (fr) 2017-07-19 2017-07-19 Convertisseur analogique-numérique en pipeline comportant au moins trois canaux d'échantillonnage

Publications (1)

Publication Number Publication Date
WO2019015751A1 true WO2019015751A1 (fr) 2019-01-24

Family

ID=59366445

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2017/068251 WO2019015751A1 (fr) 2017-07-19 2017-07-19 Convertisseur analogique-numérique en pipeline comportant au moins trois canaux d'échantillonnage

Country Status (2)

Country Link
CN (1) CN111295843B (fr)
WO (1) WO2019015751A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100103009A1 (en) * 2008-10-29 2010-04-29 Kabushiki Kaisha Toshiba A/d converter and random-noise reducing method for a/d converters
US8730073B1 (en) * 2012-12-18 2014-05-20 Broadcom Corporation Pipelined analog-to-digital converter with dedicated clock cycle for quantization

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3851870B2 (ja) * 2002-12-27 2006-11-29 株式会社東芝 可変分解能ａ／ｄ変換器
US7075471B1 (en) * 2005-02-11 2006-07-11 Teranetics, Inc. Double-sampled, time-interleaved analog to digital converter
CN101552609B (zh) * 2009-02-12 2012-09-26 苏州通创微芯有限公司 一种流水线模数转换器
CN102025373B (zh) * 2009-09-16 2012-06-13 复旦大学 一种数字后台校准电路
CN102006073B (zh) * 2010-12-24 2012-08-01 复旦大学 一种快速收敛多通道时间交织模数转换器及其校准系统
US8487803B1 (en) * 2012-01-23 2013-07-16 Freescale Semiconductor, Inc. Pipelined analog-to-digital converter having reduced power consumption
JP5893591B2 (ja) * 2013-08-14 2016-03-23 旭化成エレクトロニクス株式会社 サンプルホールド回路のキャリブレーション方法、キャリブレーション装置、およびサンプルホールド回路
CN105049046B (zh) * 2015-08-20 2018-11-20 西安启微迭仪半导体科技有限公司 一种时间交织流水级模数转换器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100103009A1 (en) * 2008-10-29 2010-04-29 Kabushiki Kaisha Toshiba A/d converter and random-noise reducing method for a/d converters
US8730073B1 (en) * 2012-12-18 2014-05-20 Broadcom Corporation Pipelined analog-to-digital converter with dedicated clock cycle for quantization

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JIANGFENG WU ET AL: "A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 48, no. 8, 1 August 2013 (2013-08-01), pages 1818 - 1828, XP011520799, ISSN: 0018-9200, DOI: 10.1109/JSSC.2013.2259013 *

Also Published As

Publication number Publication date
CN111295843A (zh) 2020-06-16
CN111295843B (zh) 2022-05-10

Similar Documents

Publication Publication Date Title
US7551114B2 (en) Reducing power consumption in the early stages of a pipeline sub-ADC used in a time-interleaved ADC
US7978117B2 (en) Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same
US5710563A (en) Pipeline analog to digital converter architecture with reduced mismatch error
KR101140349B1 (ko) 다단 연속 근사 레지스터 아날로그 디지털 변환기
US8269657B2 (en) Background calibration of offsets in interleaved analog to digital converters
US7224306B2 (en) Analog-to-digital converter in which settling time of amplifier circuit is reduced
US8248289B2 (en) Power and area efficient interleaved ADC
US9900023B1 (en) Multi-stage delta-sigma pipelined successive approximation register analog-to-digital converter
US8497789B2 (en) Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
CN110022157B (zh) 信号处理装置和δ-σ调制器
US8466823B2 (en) Cascade analog-to-digital converting system
US7002507B2 (en) Pipelined and cyclic analog-to-digital converters
US6285309B1 (en) Nested pipelined analog-to-digital converter
US7821436B2 (en) System and method for reducing power dissipation in an analog to digital converter
JP2009290455A (ja) Ｄｅｍシステム、デルタシグマａ／ｄ変換器、及び受信機
US7573417B2 (en) Multi-bit per stage pipelined analog to digital converters
US8274419B2 (en) Analog-digital converter with pipeline architecture associated with a programmable gain amplifier
KR101141552B1 (ko) 파이프라인 아날로그 디지털 변환기
KR101141551B1 (ko) 파이프라인 아날로그-디지털 변환기
US6995703B2 (en) Analog-to-digital converting circuit and image processing circuit cyclically repeating AD conversion
CN111295843B (zh) 具有至少三条采样信道的流水线模数转换器
CN106788437B (zh) 流水线型模数转换器及提高模数转换器的采样速率的方法
US7948410B2 (en) Multibit recyclic pipelined ADC architecture
US7728751B2 (en) Pipelined converter
KR20110090669A (ko) 축차근사 레지스터형 아날로그-디지털 변환기

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17740759

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17740759

Country of ref document: EP

Kind code of ref document: A1