WO2019015076A1 - 显示面板的驱动装置 - Google Patents

显示面板的驱动装置 Download PDF

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Publication number
WO2019015076A1
WO2019015076A1 PCT/CN2017/102466 CN2017102466W WO2019015076A1 WO 2019015076 A1 WO2019015076 A1 WO 2019015076A1 CN 2017102466 W CN2017102466 W CN 2017102466W WO 2019015076 A1 WO2019015076 A1 WO 2019015076A1
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WO
WIPO (PCT)
Prior art keywords
diode
area
display panel
driving device
chip
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Application number
PCT/CN2017/102466
Other languages
English (en)
French (fr)
Inventor
陈猷仁
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Priority to US16/632,355 priority Critical patent/US11322931B2/en
Publication of WO2019015076A1 publication Critical patent/WO2019015076A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a driving device for a display panel.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display is one of the main types of flat panel display, and has become an important display platform in modern IT and video products.
  • the main driving principle of the thin film transistor liquid crystal display is that the system motherboard connects the R/G/B compression signal, the control signal and the power through the wire to the connector on the printed circuit board (PCB), and the data passes through the printed circuit.
  • the on-board timing controller (TCON Timing Controller) chip After the on-board timing controller (TCON Timing Controller) chip is processed, the printed circuit board passes through the S-COF Source-Chip on Film and the gate drive chip (G-COF Gate-Chip on Film). ) is connected to the display area so that the display obtains the required power and signal.
  • the electrostatic discharge protection capability of the component is increased.
  • the electrostatic discharge protection capability of the chip is proportional to the area of the electrostatic discharge diode, which causes the area of the electrostatic discharge diode to rise, resulting in an increase in the cost of the chip.
  • the present disclosure provides a driving device for a display panel that not only improves the electrostatic discharge protection capability of the chip but also controls the cost.
  • a driving device for a display panel includes a protection circuit, and the protection circuit includes:
  • the plurality of first diodes are disposed in parallel corresponding to the plurality of chip input ends, and the first diode negative electrode is connected to the chip input end;
  • a cathode of the third diode is connected to a cathode of the first diode, and the third The anode of the pole tube is grounded, the area of the third diode is larger than the area of the first diode, and the number of the third diode is smaller than the number of the first diode.
  • the area of the third diode is greater than or equal to 10 times the area of the first diode.
  • the protection circuit includes a first diode region and a third diode region, the first diode region including a plurality of first diodes connected in parallel, the third The diode region is a third diode.
  • the protection circuit further includes a second diode, the first diode being connected to the third diode through the second diode; and the positive connection of the second diode The anode of the first diode; the cathode of the second diode is connected to the cathode of the third diode.
  • the reverse breakdown voltage value of the second diode is greater than the reverse breakdown voltage value of the first diode and the third diode.
  • the reverse breakdown voltage of the first diode and/or the third diode is 18V-25V, and the reverse breakdown voltage of the second diode is greater than 30V.
  • the area of the first diode is equal to the area of the second diode.
  • the protection circuit includes a first diode region, a second diode region, and a third diode region, the first diode region including a plurality of first diodes connected in parallel a second diode region comprising a second diode or a plurality of second diodes connected in parallel, the third diode region being a third diode; the second diode The negative electrode of the tube is connected to the negative electrode of the third diode.
  • the plurality of second diodes are corresponding to a plurality of first diodes, and the cathodes of the plurality of second diodes are all connected to a cathode of the third diode.
  • the driving device of the display panel is configured to drive the display panel, the display panel includes a display area and a non-display area located around the display area; the driving device has a plurality of driving chips
  • the protection circuit is located in at least one of the plurality of driving chips; the plurality of driving chips are located on a non-display area on the same side of the display area.
  • the plurality of driving chips have a plurality of source driving chips and at least one gate driving chip.
  • the protection circuit is disposed within the source driver chip proximate to the The position of the source drive chip input.
  • the protection circuit is disposed in the gate drive chip at a position close to the input end of the gate drive chip.
  • a driving device for a display panel includes a protection circuit, and the protection circuit includes:
  • the first diode region includes a plurality of first diodes, and the plurality of first diodes are disposed in parallel corresponding to the plurality of chip input ends, the first diode anode Connecting the chip input terminal;
  • the second diode region includes a second diode, an anode of the second diode is coupled to a positive electrode of the first diode, and the second diode An area equal to the area of the first diode;
  • the third diode region including a third diode, a cathode of the third diode connected to a cathode of the second diode, the third diode
  • the positive pole is grounded, and the area of the third diode is larger than the area of the first diode;
  • the reverse breakdown voltage value of the second diode is greater than the reverse breakdown voltage value of the first diode and the third diode.
  • the reverse breakdown voltage value of the second diode is greater than the reverse breakdown voltage value of the first diode and the third diode.
  • the reverse breakdown voltage of the first diode and/or the third diode is 18V-25V, and the reverse breakdown voltage of the second diode is greater than 30V.
  • a driving device for a display panel comprising a protection circuit, the protection circuit comprising:
  • the plurality of first diodes are disposed in parallel corresponding to the plurality of chip input ends, and the first diode negative electrode is connected to the chip input end;
  • an anode of the second diode is connected to a positive pole of the first diode, and an area of the second diode is equal to an area of the first diode;
  • a cathode of the third diode is connected to a cathode of the second diode, a cathode of the third diode is grounded, and an area of the third diode is greater than or equal to the first 10 times the area of the diode;
  • the reverse breakdown voltage value of the second diode is greater than the reverse breakdown voltage value of the first diode and the third diode.
  • the driving device of the display panel is configured to drive the display panel, the display panel includes a display area and a non-display area located around the display area; the driving device has a plurality of driving chips
  • the protection circuit is located in at least one of the plurality of driving chips; the plurality of driving chips are located on a non-display area on the same side of the display area.
  • the plurality of driving chips have a plurality of source driving chips and at least one gate driving chip.
  • the driving device comprises a protection circuit, wherein the protection circuit comprises a chip input end, a first diode and a third diode; wherein the first diode negative electrode is connected to the chip input end; the third level The cathode of the tube is connected to the anode of the first diode, the anode of the third diode is grounded, and the area of the third diode is larger than the area of the first diode.
  • the third diode has a large electrostatic discharge protection capability. When the input end of the chip has an electrostatic discharge signal, the energy of the electrostatic discharge signal reverses the high electrostatic discharge after the first diode is reversely broken down.
  • the third diode of protection capability is finally transmitted to the ground to improve the protection against electrostatic discharge.
  • the number of the third diodes is smaller than the number of the first diodes, reducing the number of second diodes in the chip, effectively reducing the total area of the diodes in the chip, and thus controlling the cost.
  • FIG. 1 is a schematic diagram of a protection circuit of a driving device of a display panel in an embodiment
  • FIG. 2 is a schematic diagram of a protection circuit in another embodiment
  • FIG. 3 is a schematic diagram of a protection circuit in still another embodiment
  • FIG. 4 is a diagram showing a driving architecture of a display device in an embodiment
  • FIG. 5 is a diagram showing a drive architecture of a display device in another embodiment.
  • 1 is a schematic diagram of a protection circuit of a driving device of a display panel, the protection circuit including a plurality of chip input terminals, a plurality of first diodes D1 and third diodes D3.
  • the plurality of first diodes D1 are arranged in parallel corresponding to the input ends of the plurality of chips, the negative pole of the first diode D1 is connected to the input end of the chip; the negative pole of the third diode D3 is connected to the positive pole of the first diode D1, and the third The anode of the diode D3 is grounded, the area of the third diode D3 is larger than the area of the first diode D1, and the number of the third diode D3 is smaller than the number of the first diode D1.
  • the third diode D3 has a large area with high electrostatic discharge protection capability.
  • the energy of the electrostatic discharge signal is reversely broken after the first diode D1 is reversely broken down.
  • the third diode D3 of the electrostatic discharge protection capability is finally conducted to the ground to improve the protection against electrostatic discharge.
  • the number of the third diodes D3 is smaller than the number of the first diodes D1, and the number of the third diodes D3 in the chip is reduced, thereby effectively reducing the total area of the diodes in the chip, thereby controlling the cost.
  • the third diode D3 can be provided with one, two, three, etc., and with a smaller third diode D3, the size of the chip can be reduced, and the cost can be reduced.
  • the protection circuit is mainly disposed in the source driving chip, and the source driving chip and the gate driving chip cooperate to drive the display sub-pixels in the display panel.
  • the first diode D1 is disposed corresponding to the chip input end requiring electrostatic discharge protection, and then one or more third diodes D3 having a large area are disposed in the chip.
  • the first diode D1 and the third diode D3 are both internal to the chip input terminal.
  • the area of the third diode may be set to be greater than 5 times the area of the first diode. In order to obtain better electrostatic discharge protection capability, the area of the third diode may be set to be larger than the first diode. 8 times, 10 times, 15 times, 20 times, etc. of the area of the tube. In order to obtain better electrostatic discharge protection capability while taking into account cost, the area of the third diode can be set equal to 10 times the area of the first diode.
  • the protection circuit includes a first diode region 100 and a third diode region, the first diode region 100 includes a plurality of first diodes D1 connected in parallel, and the third diode region is a third Diode D3.
  • the plurality of first diodes D1 connected to the plurality of input ends of the protection circuit share a large diode D3 with a large area of high electrostatic discharge protection capability, thereby realizing the protection of the electrostatic discharge protection capability of the protection circuit and effectively controlling the cost. rise.
  • the number of first diodes D1 in the first diode region 100 corresponds to the number of input terminals of the chip, and the area of the first diode region 100 is the sum of the areas of the plurality of first diodes D1.
  • the total area of the first area and the third area is smaller than the area of the first area of the conventional design, that is, the area of each of the first diodes in the conventional first area is made smaller, the first area becomes smaller, and then Adding a large area of the third diode, so that the total area of the plurality of first diodes and the third diode is smaller than the total area of the plurality of first diodes of the conventional design, so that not only each input end is realized ESD protection capabilities have been improved, and the total footprint has been reduced, saving costs.
  • the protection circuit further includes a second diode D2.
  • the first diode D1 passes through the second The pole tube D2 is connected to the third diode D3; the anode of the second diode D2 is connected to the anode of the first diode D1; and the cathode of the second diode D2 is connected to the cathode of the third diode D3.
  • the input end is isolated by the reverse second diode D2, and the electrostatic discharge energy is not backfilled to the input end, but reversely breaks through the third diode D3 of high electrostatic discharge protection capability, and finally is conducted to the ground. .
  • the reverse breakdown voltage value of the second diode is greater than the reverse breakdown voltage value of the first diode and the third diode.
  • the first diode and the third diode are designed to have a lower reverse breakdown voltage value; the second diode has a higher reverse breakdown voltage value; when the input terminal has an electrostatic discharge signal, After the reverse breakdown of the first diode, the energy of the electrostatic discharge is positively passed through its corresponding second diode. At this time, because the reverse breakdown voltage of the second diode is higher, the electrostatic discharge energy does not Instead of refilling the input, it reverses the third diode of high electrostatic discharge protection and eventually conducts to ground. Finally, it plays the role of electrostatic discharge protection.
  • the reverse breakdown voltages of the first diode and the third diode are set as needed, for example, the reverse breakdown voltage of the first diode can be set to 18V, 20V, 22V, 25V, etc., third The reverse breakdown voltage of the diode can be set to 18V, 20V, 22V, 25V.
  • the reverse breakdown voltage of the first diode and the third diode can be set to the same or different, such as the third two.
  • the reverse breakdown voltage of the pole tube is less than the reverse breakdown voltage of the first diode, and the energy that facilitates the electrostatic discharge is conducted to the ground through the third diode.
  • the reverse breakdown voltage of the second diode is set as needed, and may be set to be greater than 30V, or may be set to be greater than 40V.
  • the area of the first diode is equal to the area of the second diode. Convenient for production. Of course, the area of the first diode may not be equal to the area of the second diode, and may be set as needed.
  • the protection circuit includes a first diode region 100, a second diode region 200, and a third diode region, and the first diode region 100 includes a plurality of first two in parallel The diode D1, the second diode region 200 includes a plurality of second diodes D2 connected in parallel, the third diode region is a third diode D3; the cathode of the second diode D2 is connected to the The negative pole of the triple diode D3.
  • a plurality of second diodes D2 can be provided to prevent electrostatic discharge energy from being reversed back into the chip input.
  • the plurality of second diodes D2 are disposed corresponding to the plurality of first diodes D1, and the cathodes of the plurality of second diodes D2 are all connected to the cathode of the third diode D3. It prevents the electrostatic discharge energy from being reversed back to the input terminals of each chip.
  • the first diode region 100, the second diode region 200, and the third diode region are both internal to the chip input end.
  • the total area of the first region, the second region, and the third region is smaller than the area of the first region and the second region of the conventional design, that is, the area of each of the first diodes in the conventional first region is made smaller.
  • the first region becomes smaller, and then a large area of the third diode is added, so that the total area of the plurality of first diodes and the third diode is smaller than the total area of the plurality of first diodes of the conventional design. This not only improves the ESD protection capability of each input, but also reduces the total footprint and saves costs.
  • the protection circuit includes a first diode region 100, a second diode region 200, and a third diode region, the first diode region 100 including a plurality of parallel
  • the first diode D1 the second diode region 200 includes a second diode D2
  • the third diode region is a third diode D3; the anodes of the first diode D1 are connected and The anode of the diode D2 and the cathode of the second diode D2 are connected to the cathode of the third diode D3.
  • the number of first diodes D1 in the first diode region 100 corresponds to the number of input terminals of the chip, and the area of the second diode D2 is equal to the area of the first diode D1, the first diode region 100
  • the area is the sum of the areas of the plurality of first diodes D1
  • the area of the second diode area 200 is the sum of the areas of the plurality of second diodes D2.
  • the display panel may include a display area 110 and a non-display area 120, wherein the display area 110 includes a plurality of display sub-pixels, a plurality of thin film transistors (TFTs), a plurality of data lines, and a plurality of scan lines.
  • TFTs thin film transistors
  • the driving device includes a source driving chip and a gate driving chip, and the protection circuit in any of the above embodiments is provided in the source driving chip and/or the gate driving chip.
  • the protection circuit can be disposed in the source driving chip near the input end of the source driving chip.
  • the protection circuit can be disposed in the gate driving chip at a position close to the input end of the gate driving chip.
  • the non-display area 120 is a reserved area disposed around a boundary line of the display area 110, and a plurality of source driving chips 210 are disposed in a vertical direction of the non-display area 120 for controlling the data lines and in the non-display area.
  • a plurality of gate driving chips 220 are disposed in the horizontal direction of 120 for controlling the scanning lines.
  • the display device corresponding to the source driving chip 210 is further provided with a printed circuit board 300.
  • the printed circuit board 300 is provided with a timing controller. The timing controller processes the image signal and the control signal through the source driving chip 210 and the gate driving chip. 220 is coupled to display area 110 such that display area 110 obtains the desired display signal.
  • the signal that the timing controller displays the image signal and the control signal and transmits to the display area may be a signal such as an R, G, B data signal, a clock signal, a vertical synchronization signal, and a horizontal synchronization signal.
  • the timing controller can transmit signals such as R, G, B data signals, row start signals, and latch signals to the source driving chip, and transmit the column start signal, the column clock signal, and the output enable signal to the gate driving chip. .
  • the source driver chip further includes a plurality of chip output ends, and each chip output end is connected with a data line for outputting the data signal to the one-to-one corresponding data line, and corresponding to each chip output end is provided for amplifying the data signal Operational amplifier.
  • the source driver chip further includes a controller for controlling the output current of the operational amplifier corresponding to the data signal output end.
  • the timing controller also transmits a setting signal to the controller, and the controller controls the output current of the operational amplifier according to the setting signal.
  • the gate driving chip includes a plurality of gate scanning signal output ends, and each gate scanning signal output end is connected to a gate scanning line for outputting the gate scanning signals to the one-to-one corresponding gate line scanning lines, each of the gate lines
  • the scan line is electrically connected to the gate electrode of the corresponding thin film transistor of the display sub-pixel for turning on or off the thin film transistor.
  • Each of the data lines is electrically connected to a source electrode of the corresponding thin film transistor of the display sub-pixel, and the data signal is transmitted to the display sub-pixel through the thin film transistor.
  • An operational amplifier for amplifying the signal may be provided for each of the gate scan signal outputs.
  • the gate scan line control thin film transistor when the gate scan line control thin film transistor is turned on, the data signal on the data line is transmitted to the display sub-pixel through the thin film transistor.
  • the timing controller can control the gate scan line to open a row of thin film transistors row by row, and then control the data lines to transmit the data signals to the corresponding display sub-pixels column by column; and then transmit the data signals to each of the display sub-pixels in the display area , eventually forming an image that needs to be displayed.
  • the display image signal may be an R/G/B compression signal, an R/G/B/W compression signal, or an R/G/B/Y compression signal.
  • the display panel may be a TN (Twisted Nematic), an OCB (Optically Compensated Birefringence), or a VA (Vertical Alignment) liquid crystal display panel, but is not limited thereto.
  • the display panel may be an RGB three primary color panel, an RGBW four color panel, or an RGBY four color panel, but is not limited thereto.
  • the drive panel can be a curved panel.
  • the display panel can also be, for example, an OLED display panel, a QLED display panel, a curved display panel, or other display panel.
  • the display panel may include a display area 110' and a non-display area 120', wherein the display area 110' includes a plurality of display sub-pixels, a plurality of thin film transistors (TFTs), a plurality of data lines, and a plurality of a gate line in which a plurality of display sub-pixels are arranged in a matrix, and a plurality of thin film transistors are used to drive display sub-pixels connected to the thin film transistor to display an image; a plurality of data lines are arranged in a vertical direction, and a plurality of scans are performed.
  • TFTs thin film transistors
  • the lines are arranged in a horizontal direction, and a plurality of data lines and scan lines cooperate to drive the thin film transistors to display an image.
  • the driving device includes a source driving chip and a gate driving chip, and the protection circuit in any of the above embodiments is provided in the source driving chip and/or the gate driving chip.
  • the protection circuit can be disposed in the source driving chip near the input end of the source driving chip.
  • the protection circuit can be disposed in the gate driving chip at a position close to the input end of the gate driving chip.
  • the non-display area 120' is a reserved area set around the boundary line of the display area 110', and the non-display area 120' (the non-display area 120' in the vertical direction in the figure) on the same side of the display panel is provided with A plurality of source driving chips 210' and at least one gate driving chip 220'.
  • the source driver chip 210' is used to control the data lines, and the gate driver chip 220' is used to control the scan lines.
  • the display device corresponding to the source driving chip 210' is further provided with a printed circuit board 300'.
  • the printed circuit board 300' is provided with a timing controller, and the timing controller processes the image signal and the control signal through the source driving chip 210' and The gate drive chip 220' is coupled to the display area 110' such that the display area 110' obtains the desired display signal.
  • the gate driving chip 220' and the source driving chip 210' are disposed on the non-display area 120' on the same side of the display area 110', and the gate driving chip 220' and the source driving chip 210' The same side edges of the display area 110' are arranged in parallel.
  • the display panel may be a long screen, and the gate driving chip 220' and the source driving chip 210' are sequentially disposed on the non-display area 120' of the lateral side of the display area 110' (that is, sequentially disposed along the length direction of the display area) Non-display area 120').
  • the other three sides of the non-display area 120' of the display area 110' have no reserved chip position.
  • the gate driving chip 220' and the source driving chip 210' are disposed on the non-display area 120' on the same side of the display area 110', and the source driving chip 210' and the gate driving chip 220' may be in the same state. Bonding in a fixed process, thereby reducing a bonding process, can reduce production costs while also improving production efficiency.

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Abstract

一种显示面板的驱动装置，包括设置在芯片内的保护电路，保护电路包括：多个芯片输入端；对应多个芯片输入端并联设置的多个第一二极管（D1），第一二极管（D1）负极连接芯片输入端；第三二极管（D3），第三二级管（D3）的负极连接第一二极管（D1）的正极，第三二级管（D3）的正极接地，第三二极管（D3）的面积大于第一二极管（D1）的面积，第三二极管（D3）的数量小于第一二极管（D1）的数量。

Description

显示面板的驱动装置 技术领域
本公开涉及显示技术领域，特别是涉及一种显示面板的驱动装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD Thin Film Transistor Liquid Crystal Display)是当前平板显示的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。薄膜晶体管液晶显示器主要驱动原理是，系统主板将R/G/B压缩信号、控制信号及动力通过线材与印制电路板(PCB板)上的连接器(connector)相连接，数据经过印制电路板上的时序控制器(TCON Timing Controller)芯片处理后，经印制电路板，通过源极驱动芯片(S-COF Source-Chip on Film)和栅极驱动芯片(G-COF Gate-Chip on Film)与显示区连接，从而使得显示器获得所需的电源、信号。
随着用户对于产品可靠性要求的不断提高，以及系统客户对产品品质要求的不断严苛，静电放电(ESD Electronic Static Discharge)防护等级及可靠性的要求越来越高，这就需要系统内各元件的静电放电防护能力随之提高。而芯片的静电放电防护能力与静电放电二极管的面积成正比，这就造成静电放电二极管的面积上升，造成芯片成本的增加。
公开内容
本公开提供一种既提高芯片静电放电防护能力且控制成本的显示面板的驱动装置。
一种显示面板的驱动装置，包括保护电路，所述保护电路包括：
多个芯片输入端；
多个第一二极管，所述多个第一二极管对应多个芯片输入端并联设置，所述第一二极管负极连接芯片输入端；
第三二极管，所述第三二级管的负极连接第一二极管的正极，所述第三二 极管的正极接地，所述第三二极管的面积大于第一二极管的面积，所述第三二极管的数量小于第一二极管的数量。
在其中一个实施例中，所述第三二极管的面积大于等于第一二极管的面积的10倍。
在其中一个实施例中，所述保护电路内包括第一二极管区域和第三二极管区域，所述第一二极管区域包括并联的多个第一二极管，所述第三二极管区域为一个第三二极管。
在其中一个实施例中，所述保护电路还包括第二二极管，所述第一二极管通过第二二极管与第三二极管连接；所述第二二极管的正极连接第一二极管的正极；所述第二二极管的负极连接第三二级管的负极。
在其中一个实施例中，所述第二二极管的反向击穿电压值大于第一二极管和第三二极管的反向击穿电压值。
在其中一个实施例中，所述第一二极管和/或第三二极管的反向击穿电压为18V-25V，所述第二二极管的反向击穿电压大于30V。
在其中一个实施例中，所述第一二极管的面积等于第二二极管的面积。
在其中一个实施例中，所述保护电路包括第一二极管区域、第二二极管区域和第三二极管区域，所述第一二极管区域包括并联的多个第一二极管，所述第二二极管区域包括一个第二二极管或并联的多个第二二极管，所述第三二极管区域为一个第三二极管；所述第二二极管的负极都连接于第三二极管的负极。
在其中一个实施例中，所述多个第二二极管对应多个第一二极管设置，所述多个第二二极管的负极都连接于第三二极管的负极。
在其中一个实施例中，所述显示面板的驱动装置用于驱动所述显示面板，所述显示面板包括显示区域和位于所述显示区域周边的非显示区域；所述驱动装置具有多个驱动芯片，所述保护电路位于所述多个驱动芯片中的至少其中之一内；所述多个驱动芯片位于所述显示区域同一侧的非显示区域上。
在其中一个实施例中，多个驱动芯片多个源极驱动芯片和至少一个栅极驱动芯片。
在其中一个实施例中，所述保护电路设置在所述源极驱动芯片内靠近所述 源极驱动芯片输入端的位置。
在其中一个实施例中，所述保护电路设置在所述栅极驱动芯片内靠近所述栅极驱动芯片输入端的位置。
一种显示面板的驱动装置，包括保护电路，所述保护电路包括：
多个芯片输入端；
第一二极管区域，所述第一二极管区域包括多个第一二极管，所述多个第一二极管对应多个芯片输入端并联设置，所述第一二极管负极连接芯片输入端；
第二二极管区域，所述第二二极管区域包括一个第二二极管，所述第二二极管的正极连接所述第一二极管的正极，所述第二二极管的面积等于所述第一二极管的面积；
第三二极管区域，所述第三二极管区域包括一个第三二极管，所述第三二级管的负极连接所述第二二极管的负极，所述第三二极管的正极接地，所述第三二极管的面积大于第一二极管的面积；
其中，所述第二二极管的反向击穿电压值大于第一二极管和第三二极管的反向击穿电压值。
在其中一个实施例中，所述第二二极管的反向击穿电压值大于第一二极管和第三二极管的反向击穿电压值。
在其中一个实施例中，所述第一二极管和/或第三二极管的反向击穿电压为18V-25V，所述第二二极管的反向击穿电压大于30V。
一种显示面板的驱动装置，其包括保护电路，所述保护电路包括：
多个芯片输入端；
多个第一二极管，所述多个第一二极管对应多个芯片输入端并联设置，所述第一二极管负极连接芯片输入端；
第二二极管，所述第二二极管的正极连接第一二极管的正极，所述第二二极管的面积等于所述第一二极管的面积；
第三二极管，所述第三二级管的负极连接所述第二二极管的负极，所述第三二极管的正极接地，所述第三二极管的面积大于等于第一二极管的面积的10倍；
其中，所述第二二极管的反向击穿电压值大于第一二极管和第三二极管的反向击穿电压值。
在其中一个实施例中，所述显示面板的驱动装置用于驱动所述显示面板，所述显示面板包括显示区域和位于所述显示区域周边的非显示区域；所述驱动装置具有多个驱动芯片，所述保护电路位于所述多个驱动芯片中的至少其中之一内；所述多个驱动芯片位于所述显示区域同一侧的非显示区域上。
在其中一个实施例中，多个驱动芯片多个源极驱动芯片和至少一个栅极驱动芯片。
上述显示面板的驱动装置中，该驱动装置包括保护电路，保护电路包括芯片输入端、第一二极管和第三二极管；其中第一二极管负极连接芯片输入端；第三二级管的负极连接第一二极管的正极，第三二极管的正极接地，第三二极管的面积大于第一二极管的面积。第三二极管面积大具有较高的静电放电防护能力，当芯片输入端有静电放电信号，使得第一二极管反向击穿后，静电放电信号的能量再反向击穿高静电放电防护能力的第三二极管，最终传导至地，起到提高静电放电防护的作用。其中第三二极管的数量小于第一二极管的数量，减少芯片内第二二极管的数量，有效减小芯片内二极管的总面积，进而控制成本。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的显示面板的驱动装置的保护电路的示意图；
图2为另一实施例中的保护电路的示意图；
图3为又一实施例中的保护电路的示意图；
图4为一实施例中的显示装置的驱动架构图；
图5为另一实施例中的显示装置的驱动架构图。
具体实施方式
为了使本公开的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本公开进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本公开，并不用于限定本公开。
图1为显示面板的驱动装置的保护电路的示意图，该保护电路包括多个芯片输入端、多个第一二极管D1和第三二极管D3。其中多个第一二极管D1对应多个芯片输入端并联设置，第一二极管D1负极连接芯片输入端；第三二级管D3的负极连接第一二极管D1的正极，第三二极管D3的正极接地，第三二极管D3的面积大于第一二极管D1的面积，第三二极管D3的数量小于第一二极管D1的数量。
第三二极管D3面积大具有较高的静电放电防护能力，当芯片输入端有静电放电信号，使得第一二极管D1反向击穿后，静电放电信号的能量再反向击穿高静电放电防护能力的第三二极管D3，最终传导至地，起到提高静电放电防护的作用。其中第三二极管D3的数量小于第一二极管D1的数量，减少芯片内第三二极管D3的数量，有效减小芯片内二极管的总面积，进而控制成本。如第三二极管D3可以设置1个、2个、3个等，用较少的第三二极管D3，可以缩小芯片的体积，减小成本。该保护电路主要设置在源极驱动芯片内，源极驱动芯片和栅极驱动芯片配合驱动显示面板中的显示子像素。
根据需要对应需静电放电防护的芯片输入端设置第一二极管D1，然后在芯片内设置一个或多个面积大的第三二极管D3。第一二极管D1、第三二极管D3均为芯片内部靠近芯片输入端。
进一步地，第三二极管的面积可以设置为大于第一二极管的面积的5倍，为了获取更好的静电放电防护能力，第三二极管的面积可以设置为大于第一二极管的面积的8倍、10倍、15倍、20倍等。为了获取更好的静电放电防护能力同时考虑到成本，第三二极管的面积可以设置为等于第一二极管的面积的10倍。
具体的，保护电路包括第一二极管区域100和第三二极管区域，第一二极管区域100包括并联的多个第一二极管D1，第三二极管区域为一个第三二极管 D3。保护电路的多个输入端连接的多个第一二极管D1共用一个大面积高静电放电防护能力的第三二极管D3，实现保护电路静电放电防护能力提升的同时，有效的控制成本的上升。第一二极管区域100内的第一二极管D1的数量对应芯片输入端的数量设置，第一二极管区域100的面积为多个第一二极管D1的面积总和。第一区域和第三区域的总面积小于传统设计的第一区域的面积，即将传统的第一区域中的每个第一二极管的面积都变小一点，则第一区域变小，然后增加一个大面积的第三二极管，使多个第一二极管和第三二极管的总面积小于传统设计的多个第一二极管的总面积，如此不仅实现每条输入端的ESD防护能力都提升了，而总的占用面积变小，节约成本。
图2为另一实施例中保护电路的示意图，本实施例与上述实施例的主要区别在于，该保护电路还包括第二二极管D2，具体的，第一二极管D1通过第二二极管D2与第三二极管D3连接；第二二极管D2的正极连接第一二极管D1的正极；第二二极管D2的负极连接第三二级管D3的负极。利用反向第二二极管D2对输入端进行隔绝，静电放电能量不会反灌回输入端，而是反向击穿高静电放电防护能力的第三二极管D3，并最终传导至地。
其中，第二二极管的反向击穿电压值大于第一二极管和第三二极管的反向击穿电压值。第一二极管与第三二极管在设计时，设计其反向击穿电压值较低；第二二极管的反向击穿电压值较高；当输入端有静电放电信号，使得第一二极管反向击穿后，静电放电的能量正向通过其对应的第二二极管，此时因为第二二极管的反向击穿电压值较高，静电放电能量不会反灌回输入端，而是反向击穿高静电放电防护能力的第三二极管，并最终传导至地。最终起到静电放电防护的作用。具体的，第一二极管和第三二极管的反向击穿电压根据需要设置，如第一二极管的反向击穿电压可以设置为18V、20V、22V、25V等，第三二极管的反向击穿电压可以设置为18V、20V、22V、25V，第一二极管和第三二极管的反向击穿电压可以设置为一样也可以不一样，如第三二极管的反向击穿电压小于第一二极管的反向击穿电压，有利于静电放电的能量通过第三二极管传导到地。第二二极管的反向击穿电压根据需要设置，如可以设置为大于30V，也可以设置为大于40V。
进一步地，第一二极管的面积等于第二二极管的面积。方便生产。当然第一二极管的面积也可以不等于第二二极管的面积，可以根据需要进行设定。
具体的，如图2所示，保护电路包括第一二极管区域100、第二二极管区域200和第三二极管区域，第一二极管区域100包括并联的多个第一二极管D1，第二二极管区域200包括并联的多个第二二极管D2，第三二极管区域为一个第三二极管D3；第二二极管D2的负极都连接于第三二极管D3的负极。可以设置多个第二二极管D2起到防止静电放电能量通过反灌回芯片输入端。进一步地，多个第二二极管D2对应多个第一二极管D1设置，多个第二二极管D2的负极都连接于第三二极管D3的负极。起到防止静电放电能量通过反灌回各个芯片输入端。其中第一二极管区域100、第二二极管区域200和第三二极管区域均为芯片内部靠近芯片输入端处。第一区域、第二区域和第三区域的总面积小于传统设计的第一区域和第二区域的面积，即将传统的第一区域中的每个第一二极管的面积都变小一点，则第一区域变小，然后增加一个大面积的第三二极管，使多个第一二极管和第三二极管的总面积小于传统设计的多个第一二极管的总面积，如此不仅实现每条输入端的ESD防护能力都提升了，而总的占用面积变小，节约成本。
在一个实施例中，如图3所示，保护电路包括第一二极管区域100、第二二极管区域200和第三二极管区域，第一二极管区域100包括并联的多个第一二极管D1，第二二极管区域200包括一个第二二极管D2，第三二极管区域为一个第三二极管D3；第一二极管D1的正极都连接与第二二极管D2的正极，第二二极管D2的负极连接于第三二极管D3的负极。通过设置一个第二二极管D2起到防止静电放电能量通过反灌回芯片输入端。其中第一二极管区域100、第二二极管区域200和第三二极管区域均为芯片内部靠近芯片输入端处。
第一二极管区域100内的第一二极管D1的数量对应芯片输入端的数量设置，第二二极管D2的面积等于第一二极管D1的面积，第一二极管区域100的面积为多个第一二极管D1的面积总和，第二二极管区域200的面积为多个第二二极管D2的面积总和。
图4为一种显示装置的驱动架构图，该显示装置包括显示面板以及上述任 一实施方式中的驱动装置。具体的，该显示面板可以包括显示区域110和非显示区域120，其中，显示区域110包括多个显示子像素、多个薄膜晶体管(TFT)、多条数据线(Data line)和多条扫描线(Gate line)，其中多个显示子像素呈矩阵排列，多个薄膜晶体管用于驱动与薄膜晶体管连接的显示子像素以显示图像；多条数据线呈竖直方向设置，多条扫描线呈水平方向设置，多条数据线和扫描线配合驱动薄膜晶体管以显示图像。驱动装置包括源极驱动芯片、栅极驱动芯片，源极驱动芯片和/或栅极驱动芯片内设有上述任一实施方式中的保护电路。该保护电路可以设置在源极驱动芯片内靠近源极驱动芯片输入端的位置，同样的，该保护电路可以设置在栅极驱动芯片内靠近栅极驱动芯片输入端的位置。
非显示区域120为围绕显示区域110的边界线设置的预留的区域，在非显示区域120的竖直方向上设置有多个源极驱动芯片210，用来控制数据线，以及在非显示区域120的水平方向上的设置多个栅极驱动芯片220，用来控制扫描线。显示装置对应源极驱动芯片210还设有印刷电路板300，印刷电路板300上设有时序控制器，时序控制器将显示图像信号、控制信号处理后通过源极驱动芯片210和栅极驱动芯片220与显示区域110连接，从而使得显示区域110获得所需的显示信号。
其中，时序控制器将显示图像信号、控制信号处理后传输给显示区域的信号可以是R、G、B数据信号、时钟信号、垂直同步信号和水平同步信号等信号。时序控制器可以将R、G、B数据信号、行起始信号、锁存信号等信号传送给源极驱动芯片，将列起始信号、列时钟信号与输出使能信号传送给栅极驱动芯片。
源极驱动芯片还包括多个芯片输出端，每个芯片输出端连接一条数据线，用于将数据信号输出至一一对应的数据线，对应每一个芯片输出端设置有用于将数据信号进行放大的运算放大器。源极驱动芯片内还包括控制器，该控制器用于控制数据信号输出端对应的运算放大器的输出电流大小。其中，时序控制器还传输设定信号至控制器，控制器根据该设定信号控制运算放大器的输出电流大小。
栅极驱动芯片包括多个栅扫描信号输出端，每个栅扫描信号输出端连接一条栅极扫描线，用于将栅扫描信号输出至一一对应的栅线扫描线，每一条栅线 扫描线与对应的显示子像素的薄膜晶体管的栅电极电性连接，用于打开或关闭薄膜晶体管。每一条数据线与对应的显示子像素的薄膜晶体管的源电极电性连接，通过薄膜晶体管将数据信号传输至显示子像素。对应每一个栅扫描信号输出端可以设置有用于将信号进行放大的运算放大器。具体的，当栅极扫描线控制薄膜晶体管打开时，数据线上的数据信号通过薄膜晶体管传输至显示子像素。时序控制器可以控制栅极扫描线逐行打开一行的薄膜晶体管，再控制数据线将数据信号逐列传输至对应的显示子像素；进而将将数据信号传输给显示区域内每一个的显示子像素，最终形成需要显示的图像。
上述显示图像信号可以是R/G/B压缩信号，也可以是R/G/B/W压缩信号，也可以是R/G/B/Y压缩信号。
该显示面板可以为TN(Twisted Nematic，扭曲向列)、OCB(Optically Compensated Birefringence，光学补偿弯曲排列)、VA(Vertical Alignment，垂直配向)型液晶显示面板，但并不限于此。该显示面板可以为RGB三原色面板、RGBW四色面板或者RGBY四色面板，但并不限于此。该驱动面板可以为曲面面板。
在某些实施方式中，显示面板还可例如为OLED显示面板、QLED显示面板、曲面显示面板或其他显示面板。
图5为另一种显示装置的驱动架构图，该显示装置与上述显示装置相似，包括显示面板以及上述任一实施方式中的驱动装置。具体的，该显示面板可以包括显示区域110’和非显示区域120’，其中，显示区域110’包括多个显示子像素、多个薄膜晶体管(TFT)、多条数据线(Data line)和多条扫描线(Gate line)，其中多个显示子像素呈矩阵排列，多个薄膜晶体管用于驱动与薄膜晶体管连接的显示子像素以显示图像；多条数据线呈竖直方向设置，多条扫描线呈水平方向设置，多条数据线和扫描线配合驱动薄膜晶体管以显示图像。驱动装置包括源极驱动芯片、栅极驱动芯片，源极驱动芯片和/或栅极驱动芯片内设有上述任一实施方式中的保护电路。该保护电路可以设置在源极驱动芯片内靠近源极驱动芯片输入端的位置，同样的，该保护电路可以设置在栅极驱动芯片内靠近栅极驱动芯片输入端的位置。
非显示区域120’为围绕显示区域110’的边界线设置的预留的区域，在显示面板的同一侧的非显示区域120’(如图中竖直方向上的非显示区域120’)设置有多个源极驱动芯片210’和至少一个栅极驱动芯片220’。源极驱动芯片210’用来控制数据线，栅极驱动芯片220’用来控制扫描线。显示装置对应源极驱动芯片210’还设有印刷电路板300’，印刷电路板300’上设有时序控制器，时序控制器将显示图像信号、控制信号处理后通过源极驱动芯片210’和栅极驱动芯片220’与显示区域110’连接，从而使得显示区域110’获得所需的显示信号。
在本实施例中，栅极驱动芯片220’和源极驱动芯片210’设置在显示区域110’的同一侧的非显示区域120’上，并且栅极驱动芯片220’和源极驱动芯片210’沿显示区域110’的同一侧边依次并列设置。显示面板可为长条屏，栅极驱动芯片220’和源极驱动芯片210’依次设置在显示区域110’的横向侧的非显示区域120’上(也即沿显示区的长度方向依次设置在非显示区域120’上)。显示区域110’的其他三侧的非显示区域120’则无预留芯片的位置。如图5中的显示区域110’的其他三侧的非显示区域120’上均无需设置控制芯片，从而使得对应区域的非显示区域120’的宽度可按照需求缩小到预定尺寸，以实现窄边框的发展需求。同时，栅极驱动芯片220’和源极驱动芯片210’设置在显示区域110’的同一侧的非显示区域120’上，源极驱动芯片210’和栅极驱动芯片220’可以在同一道邦定工序中进行邦定，进而减少一道邦定工序，可以降低制作成本同时还可以提高生产效率。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对公开专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (19)

  1. 一种显示面板的驱动装置，其包括保护电路，所述保护电路包括：
    多个芯片输入端；
    多个第一二极管，所述多个第一二极管对应多个芯片输入端并联设置，所述第一二极管负极连接芯片输入端；
    第三二极管，所述第三二级管的负极连接第一二极管的正极，所述第三二极管的正极接地，所述第三二极管的面积大于第一二极管的面积，所述第三二极管的数量小于第一二极管的数量。
  2. 根据权利要求1所述的显示面板的驱动装置，其特征在于，所述第三二极管的面积大于等于第一二极管的面积的10倍。
  3. 根据权利要求1所述的显示面板的驱动装置，其中，所述保护电路内包括第一二极管区域和第三二极管区域，所述第一二极管区域包括并联的多个第一二极管，所述第三二极管区域为一个第三二极管。
  4. 根据权利要求1所述的显示面板的驱动装置，其中，所述保护电路还包括第二二极管，所述第一二极管通过第二二极管与第三二极管连接；所述第二二极管的正极连接第一二极管的正极；所述第二二极管的负极连接第三二级管的负极。
  5. 根据权利要求4所述的显示面板的驱动装置，其中，所述第二二极管的反向击穿电压值大于第一二极管和第三二极管的反向击穿电压值。
  6. 根据权利要求5所述的显示面板的驱动装置，其中，所述第一二极管和/或第三二极管的反向击穿电压为18V-25V，所述第二二极管的反向击穿电压大于30V。
  7. 根据权利要求4所述的显示面板的驱动装置，其中，所述第一二极管的面积等于第二二极管的面积。
  8. 根据权利要求4所述的显示面板的驱动装置，其中，所述保护电路包括第一二极管区域、第二二极管区域和第三二极管区域，所述第一二极管区域包括并联的多个第一二极管，所述第二二极管区域包括一个第二二极管或并联的多个第二二极管，所述第三二极管区域为一个第三二极管；
    所述第二二极管的负极都连接于第三二极管的负极。
  9. 根据权利要求8所述的显示面板的驱动装置，其中，所述多个第二二极管对应多个第一二极管设置，所述多个第二二极管的负极都连接于第三二极管的负极。
  10. 根据权利要求1所述的显示面板的驱动装置，其中，所述显示面板的驱动装置用于驱动所述显示面板，所述显示面板包括显示区域和位于所述显示区域周边的非显示区域；所述驱动装置具有多个驱动芯片，所述保护电路位于所述多个驱动芯片中的至少其中之一内；所述多个驱动芯片位于所述显示区域同一侧的非显示区域上。
  11. 根据权利要求10所述的显示面板的驱动装置，其中，多个驱动芯片多个源极驱动芯片和至少一个栅极驱动芯片。
  12. 根据权利要求11所述的显示面板的驱动装置，其中，所述保护电路设置在所述源极驱动芯片内靠近所述源极驱动芯片输入端的位置。
  13. 根据权利要求11所述的显示面板的驱动装置，其中，所述保护电路设置在所述栅极驱动芯片内靠近所述栅极驱动芯片输入端的位置。
  14. [根据细则91更正 24.10.2017]
    一种显示面板的驱动装置，包括保护电路，其中，所述保护电路包括：
    多个芯片输入端；
    第一二极管区域，所述第一二极管区域包括多个第一二极管，所述多个第一二极管对应多个芯片输入端并联设置，所述第一二极管负极连接芯片输入端；
    第二二极管区域，所述第二二极管区域包括一个第二二极管，所述第二二极管的正极连接所述第一二极管的正极，所述第二二极管的面积等于所述第一二极管的面积；
    第三二极管区域，所述第三二极管区域包括一个第三二极管，所述第三二级管的负极连接所述第二二极管的负极，所述第三二极管的正极接地，所述第三二极管的面积大于第一二极管的面积；
    其中，所述第二二极管的反向击穿电压值大于第一二极管和第三二极管的反向击穿电压值。
  15. [根据细则91更正 24.10.2017]　
    根据权利要求15所述的显示面板的驱动装置，其中，所述第二二极管的反向击穿电压值大于第一二极管和第三二极管的反向击穿电压值。
  16. [根据细则91更正 24.10.2017]　
    根据权利要求16所述的显示面板的驱动装置，其中，所述第一二极管和/或第三二极管的反向击穿电压为18V-25V，所述第二二极管的反向击穿电压大于30V。
  17. [根据细则91更正 24.10.2017]
    一种显示面板的驱动装置，其包括保护电路，所述保护电路包括：
    多个芯片输入端；
    多个第一二极管，所述多个第一二极管对应多个芯片输入端并联设置，所述第一二极管负极连接芯片输入端；
    第二二极管，所述第二二极管的正极连接第一二极管的正极，所述第二二极管的面积等于所述第一二极管的面积；
    第三二极管，所述第三二级管的负极连接所述第二二极管的负极，所述第三二极管的正极接地，所述第三二极管的面积大于等于第一二极管的面积的10倍；
    其中，所述第二二极管的反向击穿电压值大于第一二极管和第三二极管的反向击穿电压值。
  18. [根据细则91更正 24.10.2017]　
    根据权利要求18所述的显示面板的驱动装置，其中，所述显示面板的驱动装置用于驱动所述显示面板，所述显示面板包括显示区域和位于所述显示区域周边的非显示区域；所述驱动装置具有多个驱动芯片，所述保护电路位于所述多个驱动芯片中的至少其中之一内；所述多个驱动芯片位于所述显示区域同一侧的非显示区域上。
  19. [根据细则91更正 24.10.2017]　
    根据权利要求19所述的显示面板的驱动装置，其中，多个驱动芯片多个源极驱动芯片和至少一个栅极驱动芯片。
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