WO2019011064A1 - 显示屏电源控制方法、装置、存储介质及电子设备 - Google Patents

显示屏电源控制方法、装置、存储介质及电子设备 Download PDF

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Publication number
WO2019011064A1
WO2019011064A1 PCT/CN2018/088248 CN2018088248W WO2019011064A1 WO 2019011064 A1 WO2019011064 A1 WO 2019011064A1 CN 2018088248 W CN2018088248 W CN 2018088248W WO 2019011064 A1 WO2019011064 A1 WO 2019011064A1
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Prior art keywords
power
power supply
voltage
driving chip
management module
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Ceased
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PCT/CN2018/088248
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English (en)
French (fr)
Chinese (zh)
Inventor
王玉青
王峥
张小宝
葛明伟
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Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Priority to KR1020197020759A priority Critical patent/KR102230031B1/ko
Priority to US16/328,287 priority patent/US11282908B2/en
Priority to JP2019537080A priority patent/JP7030817B2/ja
Priority to EP18832593.0A priority patent/EP3553768B1/en
Publication of WO2019011064A1 publication Critical patent/WO2019011064A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display power control method, apparatus, storage medium, and electronic device.
  • a TFT (Thin Film Transistor) display is a mainstream display device on various types of notebook computers and desktop computers. Each pixel on the display screen is driven by a thin film transistor integrated behind the pixel.
  • a TFT type display usually includes a driver chip and a screen body. The driving chip is used to control the working state of the thin film transistor, thereby causing the screen to display the corresponding image.
  • the traditional TFT display will have a black screen phenomenon when it is rebooted or hibernated, and the performance of the driver chip directly affects the display effect of the screen. Therefore, how to improve the performance of the driver chip is an urgent problem to be solved.
  • a display power supply control method is applied to a TFT display screen;
  • the TFT display screen includes a driving chip and a screen body;
  • the driving chip is used to control the screen body to display a corresponding image, and the screen body utilizes a film
  • the transistor controls the pixel; the method includes:
  • the power supply to the driver chip is continuously supplied.
  • the driving chip includes a power management module; and, after receiving the startup signal, controlling the power of the driving chip to be powered according to a setting rule to reduce the output of the driving chip.
  • the steps for the probability of a voltage abnormality are:
  • the power supply voltage of the power management module is controlled to be powered up according to a set rule to reduce the probability that the gate drive negative voltage output by the driving chip is abnormally raised.
  • the power supply voltage of the power management module is controlled to be powered up according to a set rule to reduce an abnormal increase in a gate drive negative voltage output by the driving chip.
  • the steps of the probability of a phenomenon include:
  • the power supply voltage of the power management module is controlled to rise to the first level.
  • the first level is between 2.5V and 4.8V; preferably, the first time period is between 8ms and 12ms; preferably, the first time period is 10ms
  • the second time period is between 8 ms and 12 ms; preferably, the second time period is 10 ms.
  • the second level is between 1V and 2.2V.
  • the driving chip includes a power management module and a digital circuit; and, after receiving the startup signal, controlling power of the driving chip to be powered according to a setting rule to reduce the driving
  • the steps of the probability that the voltage output from the chip is abnormal include:
  • the power supply voltage of the digital circuit is controlled to be powered up after a third period of time; preferably, the third time period is between 90 ms and 110 ms; preferably, the third time period is 100 ms.
  • the step of controlling the power supply voltage of the digital circuit after the third period of time to power up is:
  • the power supply voltage of the power management module is stepped down in the driving chip, the power supply voltage of the digital circuit is controlled to be powered on;
  • the step of controlling the power supply voltage of the digital circuit to be powered up is: the power source is set in the driving chip The power supply voltage of the management module is reduced to a first voltage, and after the first voltage is lowered to the second voltage, the power supply voltage of the digital circuit is controlled to be powered; wherein the second voltage is used by the power management module a reference voltage; preferably, the first voltage is a voltage generated by a charge pump in the power management module. .
  • a display power control device is applied to a TFT display screen;
  • the TFT display screen includes a driving chip and a screen body;
  • the driving chip is used to control the screen body to display a corresponding image, and the screen body utilizes a film
  • the transistor controls the pixel;
  • the device includes:
  • a power-on control module configured to: after receiving the startup signal, control the power of the driving chip to be powered according to a setting rule, so as to reduce a probability that the voltage output by the driving chip is abnormal;
  • a normal power supply module is configured to continuously supply power to the driving chip.
  • a storage medium is applied to a TFT display screen; the TFT display screen includes a power chip, a driving chip and a screen; the storage medium is located in the power chip, and a program is stored, the program is powered by the power source.
  • the power supply to the driver chip is continuously supplied.
  • An electronic device includes a power chip, a driver chip and a screen; the power chip includes a memory and a processor, wherein the memory stores a program, when the program is executed by the processor, causing the processor to execute The following steps:
  • the power supply to the driver chip is continuously supplied.
  • the power of the control driver chip is powered up according to the setting rule to reduce the probability that the voltage output by the driver chip is abnormal. Since the power supply of the driving chip directly determines the performance of the voltage output by the driving chip to the screen body, and the power supply is prone to fluctuation when it is powered on, the quality of the voltage outputted by the driving chip can be improved by improving the power-on condition of the driving chip. Thereby reducing the probability of a black screen on the screen and improving the display performance of the display.
  • FIG. 1 is a flow chart of a display power control method provided by an embodiment
  • FIG. 3 is a flow chart showing another embodiment of step S100 of the display power supply control method of the embodiment shown in FIG. 1;
  • FIG. 4 is a flow chart of one specific power-on mode of the driving chip in the display power supply control method of the embodiment shown in FIG. 3;
  • FIG. 5 is a block diagram of a display power control device provided by another embodiment
  • FIG. 6 is a block diagram of one embodiment of a power-on control module of the display power control device of the embodiment shown in FIG. 5;
  • FIG. 7 is a block diagram of another embodiment of a power-on control module of the display power control device of the embodiment shown in FIG. 5.
  • Embodiments of the present invention provide a display power supply control method for a TFT type display screen.
  • the TFT display includes a power chip, a driver chip, and a screen body.
  • the screen body uses a thin film transistor to control pixels.
  • the screen body includes, for example, a pixel matrix, a row driving circuit, and a column driving circuit.
  • the pixel matrix includes a plurality of pixels and a plurality of pixel driving circuits, each of which is controlled by a pixel driving circuit.
  • the row driver circuit transmits a scan signal to each pixel drive circuit through a row (scan) address bus.
  • the column driver circuit transmits a data signal to each pixel driving circuit through a column (data) address bus.
  • the driver chip is used to control the screen to display the corresponding image.
  • the driving chips are electrically connected to the row driving circuit and the column driving circuit, respectively, and are responsible for functions such as data processing, transmission, and control signal transmission of the entire display screen.
  • the driver chip is composed of, for example, a single chip microcomputer (or FPGA) and peripheral circuits.
  • a power chip is used to power the driver chip.
  • the display power supply control method provided by the embodiment can be performed by a power chip.
  • the display power control method provided by the embodiment includes the following content.
  • Step S100 after receiving the start signal, control the power of the driving chip to be powered up according to the setting rule to reduce the probability that the voltage outputted by the driving chip is abnormal.
  • the start signal is, for example, a signal generated after the power is turned on or the sleep is awakened.
  • the power source of the driver chip refers to the power source input from the power chip to the driver chip.
  • the voltage outputted by the driving chip includes, for example, a gate driving positive voltage VGH and a gate driving negative voltage VGL.
  • the driver chip includes, for example, a digital circuit and an analog circuit as described below.
  • the digital circuit includes, for example, an input/output interface and a timing control module (ie, a TCON module).
  • the input and output interfaces have a high speed parallel bus interface and a serial peripheral interface.
  • the timing control module performs functions such as data processing in the SPI interface and the RGB interface and timing control of some modules in the driver chip.
  • the analog circuit includes, for example, a power management module and a pixel driving module.
  • the power management module provides voltage for scanning signals of various parts in the driving chip and the display screen.
  • the power management module includes, for example, a reference voltage source, a charge pump, and an LDO (low dropout regulator).
  • the pixel driving module includes, for example, a source driving module, a gate driving module, and a gamma correction module.
  • the source driving module outputs the gray voltage to the column driving circuit in the screen body.
  • the gate driving module outputs a scan signal (for example, including a gate driving positive voltage VGH and a gate driving negative voltage VGL) to the row driving circuit.
  • the gamma correction module is used to supply the gray voltage to the source driver module, and the change of the binary code to the gray voltage can be realized by adjusting the gamma curve.
  • the power source of the driving chip includes, for example, the power supply voltage VCI of the power management module and the power supply voltage of the digital circuit. Since the power supply is prone to fluctuations when it is powered on, the voltage outputted by the driver chip fluctuates abnormally, which causes a black screen on the display screen. Therefore, by improving the power-on mode of the power supply of the driver chip, the screen body can be reduced to some extent. The probability of a black screen.
  • step S200 the driving chip is continuously powered normally.
  • the power chip supplies power to the driving chip according to normal requirements, so that the TFT display screen operates normally.
  • the Improving the power-on condition of the driver chip power supply can improve the quality of the output signal of the driver chip, thereby reducing the probability of a black screen on the screen and improving the display performance of the display.
  • the above driver chip includes a power management module. Moreover, in the above step S100, after receiving the start signal, the power supply voltage of the control power management module is powered up according to the setting rule, so as to reduce the probability that the gate drive negative voltage VGL outputted by the driving chip is abnormally raised.
  • the gate driving negative voltage VGL is obtained by stepping down the power supply voltage VCI of the power management module.
  • the gate drive negative voltage VGL is abnormally raised, which means that the gate drive negative voltage VGL will be higher than the normal voltage range.
  • the range of the gate drive negative voltage VGL under normal conditions is (-7V, 0V).
  • the gate driving negative voltage VGL rises to 0.6 V it is considered that the abnormality is raised.
  • the voltage fluctuation may exceed the normal range, causing the gate drive negative voltage VGL to be abnormally raised.
  • the driver chip appears Latch.
  • the Up phenomenon that is, the voltage output from the driver chip is abnormally high, resulting in abnormal operation of the thin film transistor. Since the gate driving negative voltage VGL directly controls the operation of the thin film transistor, abnormality of the voltage causes the thin film transistor to be turned on, thereby generating a black screen.
  • the gate drive negative voltage VGL can be reduced to be abnormally high. The probability.
  • step S100 may include the following content, please refer to FIG. 2 .
  • Step S111 after receiving the start signal, the power supply voltage VCI of the control power management module is normally powered up to a first level.
  • the first level may be a normal supply voltage of the power management module, for example, between 2.5V and 4.8V.
  • the first level is 3.3V.
  • Step S112 after the first period of time, the power supply voltage VCI of the control power management module is lowered to the second level.
  • the second level is lower than the first level.
  • the first time period is related to the Transient Response characteristic of the power chip.
  • the first time period is between 8 ms and 12 ms, for example 10 ms.
  • the size of the second level at least ensures that the size of the gate drive negative voltage VGL does not cause a black screen problem in the screen.
  • the second level is, for example, between 1V and 2.2V.
  • the second level is, for example, 1.8V, at which time the corresponding gate drive negative voltage VGL is less than 0.4V.
  • the power chip can step down the first level by a charge pump or other circuit capable of implementing a buck to generate a second level to provide a second level to the power management module in step S112.
  • Step S113 after the second period of time, the power supply voltage VCI of the control power management module is raised to the first level.
  • the second time period is related to the Transient Response characteristic of the power chip.
  • the second time period is between 8 ms and 12 ms, for example 10 ms.
  • the power chip can also boost the second level to the first level again using a charge pump or other circuit capable of implementing a buck, and provide a first level to the power management module in step S113.
  • the specific implementation manner described above optimizes the power-on mode (ie, adopting a high-low-high level) mode of the power supply voltage VCI of the power management module, thereby reducing the probability of a black screen appearing on the screen.
  • the foregoing step S100 may specifically adopt another manner to reduce the probability that the voltage output by the driving chip is abnormal.
  • the above driving chip includes the above power management module and the above digital circuit.
  • the above step S100 specifically includes the following content, please refer to FIG. 3.
  • Step S121 after receiving the start signal, control the power supply voltage VCI of the power management module to be powered on.
  • Step S122 after the third period of time, the power supply voltage of the digital circuit is controlled to be powered on.
  • the power supply voltage VCI of the power management module and the power supply voltage of the digital circuit are sequentially adjusted, that is, the power supply voltage VCI of the power management module is first powered on, and after the third time period, the digital circuit is controlled. Powering up the supply voltage allows the digital circuitry to be protected from interference from VCI-related circuits (such as buck-boost circuits in the power management module) (such as electromagnetic interference) to ensure proper operation of the digital circuitry. Since the digital circuit is the core control circuit of the driving chip, the reliability of the driving chip operation can be improved, the probability of abnormality of the voltage outputted by the driving chip is reduced, and the probability of a black screen appearing on the display screen is reduced. Specifically, the third time period is between 90 ms and 110 ms, for example 100 ms.
  • the supply voltage of the digital circuit is, for example, the voltage VDDIO of the input/output interface.
  • the power supply voltage DVDD of the timing control module is stepped down by the voltage VDDIO of the input/output interface. At this time, after the voltage VDDIO of the input/output interface is controlled, the power is turned on, and in the case of no interference, it can be ensured that the power supply voltage of the timing control module is less than the set voltage threshold (for example, 1.4V), that is, the timing control module can work normally.
  • the set voltage threshold for example, 1.4V
  • the step S122 may be specifically: after the power supply voltage VCI of the power management module is stepped down in the driving chip, the power supply voltage of the digital circuit is controlled to be powered on.
  • stepping down the power supply voltage VCI of the power management module gradually reduces the power supply voltage VCI of the power management module to one or more voltages. Moreover, when the time elapsed by the entire step-down process of the power supply voltage VCI of the power management module reaches the third time period, the power supply voltage of the control data circuit is powered on.
  • the step-down process of the power supply voltage of the power management module can be implemented by a charge pump or other circuit that can implement a step-down.
  • the step of controlling the power supply voltage of the digital circuit to be powered up is: reducing the power supply voltage VCI of the power management module to the first in the driving chip. After the voltage is lowered to the second voltage, the power supply voltage of the digital circuit is controlled to be powered.
  • the second voltage is, for example, a reference voltage VREF used by the power management module.
  • the power supply voltage VCI of the power management module is reduced to the first voltage, and then the first voltage is lowered to the second voltage, and the total elapsed time is the third time period.
  • the rising edge of the charge pump in the driving chip, the duration of the falling edge, or the number of instructions executed by the timing control module can be adjusted to control the power supply voltage VCI of the power management module to be reduced to the first voltage, and then the first The time during which the voltage is reduced to the second voltage is a total of the third time period described above.
  • the first voltage is VCL, which is a voltage generated by a charge pump in the power management module.
  • VCL is a voltage generated by a charge pump in the power management module.
  • the power supply voltage VCI of the power management module may be reduced to a first voltage by a charge pump and then decreased by a first voltage to a second voltage.
  • FIG. 4 for the power-on condition of each voltage in the driving chip.
  • the power supply voltage VCI of the power management module when the power supply voltage VCI of the power management module is powered on, on the one hand, the power supply voltage VCI of the power management module maintains its own voltage level, and the voltage AVDD (ie, the power supply of the gamma correction module and the power management module)
  • the voltages are matched to each other and boosted by a charge pump or other circuit that can be stepped down to generate a gate drive positive voltage VGH.
  • the size of VGH is, for example, AVDD+VCI, 2AVDD, 2AVDD+VCI, or 3AVDD.
  • the power supply voltage VCI of the power management module can be stepped down by a charge pump or other circuit that can be stepped down, and reduced to the first voltage VCL.
  • the process in which the power supply voltage VCI of the power management module maintains its own voltage level and the power supply voltage VCI of the power management module are reduced to the first voltage VCL are simultaneously performed.
  • the first voltage VCL can be stepped down with the voltage AVDD to generate the gate driving negative voltage VGL, and the first voltage VCL is further stepped down.
  • a second voltage is obtained (such as VREF described above).
  • the time elapsed from the power-on of the VCI to the falling of VREF in the dashed box is the third time period described above.
  • the supply voltage to the digital circuit is powered up.
  • FIG. 1 to FIG. 3 are schematic flowcharts of a method according to an embodiment of the present invention. It should be understood that although the various steps in the flowcharts of FIGS. 1 through 3 are sequentially displayed as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Except as explicitly stated herein, the execution of these steps is not strictly limited, and may be performed in other sequences. Moreover, at least some of the steps in FIGS.
  • 1 to 3 may include a plurality of sub-steps or stages, which are not necessarily performed at the same time, but may be executed at different times, and the execution order thereof is also It is not necessarily performed sequentially, but may be performed alternately or alternately with at least a portion of other steps or sub-steps or stages of other steps.
  • the TFT display screen includes a driving chip and a screen body.
  • the driving chip is configured to control the screen to display a corresponding image, and the screen body controls pixels by using a thin film transistor.
  • the display power control device includes the following, please refer to Figure 5.
  • the power-on control module 100 is configured to control the power of the driving chip to be powered according to a setting rule after receiving the startup signal, so as to reduce the probability that the voltage output by the driving chip is abnormal.
  • the normal power supply module 200 is configured to continuously supply power to the driving chip.
  • the driver chip includes a power management module.
  • the power-on control module 100 is configured to: after receiving the startup signal, control the power supply voltage of the power management module to be powered up according to the setting rule, so as to reduce the abnormality of the gate driving negative voltage output by the driving chip. The probability of a phenomenon.
  • the power-on control module 100 includes the following content, please refer to FIG. 6:
  • the first power-on unit 110 is configured to control the power supply voltage of the power management module to be normally powered up to a first level after receiving the startup signal.
  • the second power-on unit 120 is configured to control the power supply voltage of the power management module to decrease to a second level after the first period of time.
  • the second level is lower than the first level.
  • the third power-on unit 130 is configured to control the power supply voltage of the power management module to rise to the first level after the second period of time.
  • the first level is between 2.5V and 4.8V.
  • the first time period is between 8 ms and 12 ms.
  • the first time period is 10 ms.
  • the second time period is between 8 ms and 12 ms.
  • the second period of time is 10 ms.
  • the second level is between 1V and 2.2V.
  • the driver chip includes a power management module and a digital circuit.
  • the power-on control module 100 includes the following contents, please refer to FIG. 7:
  • the power-on unit 140 is configured to control the power-on voltage of the power management module to be powered on after receiving the startup signal.
  • the digital power-on unit 150 is configured to control the power supply voltage of the digital circuit to be powered after the third period of time.
  • the third time period is between 90ms and 110ms.
  • the third time period is 100 ms.
  • the digital power-on unit 150 is configured to control the power supply voltage of the digital circuit to be powered up after stepping down the power supply voltage of the power management module in the driving chip.
  • the digital power-on unit 150 is configured to reduce the power supply voltage of the power management module to a first voltage in the driving chip, and then control the digital circuit after lowering the first voltage to a second voltage.
  • the supply voltage is powered up.
  • the second voltage is a reference voltage used by the power management module.
  • the first voltage is a voltage generated by a charge pump in the power management module.
  • the display power supply control device provided by the present embodiment corresponds to the display power supply control method of the above embodiment, and details are not described herein again.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or the like.
  • This storage medium is applied to a TFT type display screen.
  • the TFT type display screen includes a power chip, a driving chip and a screen body.
  • the storage medium is located in the power chip, and the storage medium stores a program, and when the program is executed by a processor in the power chip, the following steps are implemented:
  • the power supply to the driver chip is continuously supplied.
  • the electronic device includes a power chip, a driver chip, and a screen body.
  • the power chip includes a memory and a processor, and the memory stores a program, and when the program is executed by the processor, the processor performs the following steps:
  • the power supply to the driver chip is continuously supplied.

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  • Crystallography & Structural Chemistry (AREA)
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PCT/CN2018/088248 2017-07-13 2018-05-24 显示屏电源控制方法、装置、存储介质及电子设备 Ceased WO2019011064A1 (zh)

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KR1020197020759A KR102230031B1 (ko) 2017-07-13 2018-05-24 디스플레이 파워 서플라이를 위한 제어 방법, 제어 장치, 저장 매체 및 전자 장치
US16/328,287 US11282908B2 (en) 2017-07-13 2018-05-24 Control methods and control devices for display power supply
JP2019537080A JP7030817B2 (ja) 2017-07-13 2018-05-24 ディスプレイ電源制御方法、装置、記録媒体及び電子機器
EP18832593.0A EP3553768B1 (en) 2017-07-13 2018-05-24 Method and apparatus for controlling power source of display screen, and storage medium and electronic device

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EP3553768A1 (en) 2019-10-16
TWI662527B (zh) 2019-06-11
US11282908B2 (en) 2022-03-22
EP3553768A4 (en) 2019-11-27
CN109256075A (zh) 2019-01-22
TW201832199A (zh) 2018-09-01
JP2020503567A (ja) 2020-01-30
KR102230031B1 (ko) 2021-03-22
KR20190091358A (ko) 2019-08-05
EP3553768B1 (en) 2022-06-29
JP7030817B2 (ja) 2022-03-07
US20210280651A1 (en) 2021-09-09
CN109256075B (zh) 2020-08-25

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