WO2019011064A1 - 显示屏电源控制方法、装置、存储介质及电子设备 - Google Patents

显示屏电源控制方法、装置、存储介质及电子设备 Download PDF

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Publication number
WO2019011064A1
WO2019011064A1 PCT/CN2018/088248 CN2018088248W WO2019011064A1 WO 2019011064 A1 WO2019011064 A1 WO 2019011064A1 CN 2018088248 W CN2018088248 W CN 2018088248W WO 2019011064 A1 WO2019011064 A1 WO 2019011064A1
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Prior art keywords
power
power supply
voltage
driving chip
management module
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PCT/CN2018/088248
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English (en)
French (fr)
Inventor
王玉青
王峥
张小宝
葛明伟
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昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to EP18832593.0A priority Critical patent/EP3553768B1/en
Priority to KR1020197020759A priority patent/KR102230031B1/ko
Priority to US16/328,287 priority patent/US11282908B2/en
Priority to JP2019537080A priority patent/JP7030817B2/ja
Publication of WO2019011064A1 publication Critical patent/WO2019011064A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display power control method, apparatus, storage medium, and electronic device.
  • a TFT (Thin Film Transistor) display is a mainstream display device on various types of notebook computers and desktop computers. Each pixel on the display screen is driven by a thin film transistor integrated behind the pixel.
  • a TFT type display usually includes a driver chip and a screen body. The driving chip is used to control the working state of the thin film transistor, thereby causing the screen to display the corresponding image.
  • the traditional TFT display will have a black screen phenomenon when it is rebooted or hibernated, and the performance of the driver chip directly affects the display effect of the screen. Therefore, how to improve the performance of the driver chip is an urgent problem to be solved.
  • a display power supply control method is applied to a TFT display screen;
  • the TFT display screen includes a driving chip and a screen body;
  • the driving chip is used to control the screen body to display a corresponding image, and the screen body utilizes a film
  • the transistor controls the pixel; the method includes:
  • the power supply to the driver chip is continuously supplied.
  • the driving chip includes a power management module; and, after receiving the startup signal, controlling the power of the driving chip to be powered according to a setting rule to reduce the output of the driving chip.
  • the steps for the probability of a voltage abnormality are:
  • the power supply voltage of the power management module is controlled to be powered up according to a set rule to reduce the probability that the gate drive negative voltage output by the driving chip is abnormally raised.
  • the power supply voltage of the power management module is controlled to be powered up according to a set rule to reduce an abnormal increase in a gate drive negative voltage output by the driving chip.
  • the steps of the probability of a phenomenon include:
  • the power supply voltage of the power management module is controlled to rise to the first level.
  • the first level is between 2.5V and 4.8V; preferably, the first time period is between 8ms and 12ms; preferably, the first time period is 10ms
  • the second time period is between 8 ms and 12 ms; preferably, the second time period is 10 ms.
  • the second level is between 1V and 2.2V.
  • the driving chip includes a power management module and a digital circuit; and, after receiving the startup signal, controlling power of the driving chip to be powered according to a setting rule to reduce the driving
  • the steps of the probability that the voltage output from the chip is abnormal include:
  • the power supply voltage of the digital circuit is controlled to be powered up after a third period of time; preferably, the third time period is between 90 ms and 110 ms; preferably, the third time period is 100 ms.
  • the step of controlling the power supply voltage of the digital circuit after the third period of time to power up is:
  • the power supply voltage of the power management module is stepped down in the driving chip, the power supply voltage of the digital circuit is controlled to be powered on;
  • the step of controlling the power supply voltage of the digital circuit to be powered up is: the power source is set in the driving chip The power supply voltage of the management module is reduced to a first voltage, and after the first voltage is lowered to the second voltage, the power supply voltage of the digital circuit is controlled to be powered; wherein the second voltage is used by the power management module a reference voltage; preferably, the first voltage is a voltage generated by a charge pump in the power management module. .
  • a display power control device is applied to a TFT display screen;
  • the TFT display screen includes a driving chip and a screen body;
  • the driving chip is used to control the screen body to display a corresponding image, and the screen body utilizes a film
  • the transistor controls the pixel;
  • the device includes:
  • a power-on control module configured to: after receiving the startup signal, control the power of the driving chip to be powered according to a setting rule, so as to reduce a probability that the voltage output by the driving chip is abnormal;
  • a normal power supply module is configured to continuously supply power to the driving chip.
  • a storage medium is applied to a TFT display screen; the TFT display screen includes a power chip, a driving chip and a screen; the storage medium is located in the power chip, and a program is stored, the program is powered by the power source.
  • the power supply to the driver chip is continuously supplied.
  • An electronic device includes a power chip, a driver chip and a screen; the power chip includes a memory and a processor, wherein the memory stores a program, when the program is executed by the processor, causing the processor to execute The following steps:
  • the power supply to the driver chip is continuously supplied.
  • the power of the control driver chip is powered up according to the setting rule to reduce the probability that the voltage output by the driver chip is abnormal. Since the power supply of the driving chip directly determines the performance of the voltage output by the driving chip to the screen body, and the power supply is prone to fluctuation when it is powered on, the quality of the voltage outputted by the driving chip can be improved by improving the power-on condition of the driving chip. Thereby reducing the probability of a black screen on the screen and improving the display performance of the display.
  • FIG. 1 is a flow chart of a display power control method provided by an embodiment
  • FIG. 3 is a flow chart showing another embodiment of step S100 of the display power supply control method of the embodiment shown in FIG. 1;
  • FIG. 4 is a flow chart of one specific power-on mode of the driving chip in the display power supply control method of the embodiment shown in FIG. 3;
  • FIG. 5 is a block diagram of a display power control device provided by another embodiment
  • FIG. 6 is a block diagram of one embodiment of a power-on control module of the display power control device of the embodiment shown in FIG. 5;
  • FIG. 7 is a block diagram of another embodiment of a power-on control module of the display power control device of the embodiment shown in FIG. 5.
  • Embodiments of the present invention provide a display power supply control method for a TFT type display screen.
  • the TFT display includes a power chip, a driver chip, and a screen body.
  • the screen body uses a thin film transistor to control pixels.
  • the screen body includes, for example, a pixel matrix, a row driving circuit, and a column driving circuit.
  • the pixel matrix includes a plurality of pixels and a plurality of pixel driving circuits, each of which is controlled by a pixel driving circuit.
  • the row driver circuit transmits a scan signal to each pixel drive circuit through a row (scan) address bus.
  • the column driver circuit transmits a data signal to each pixel driving circuit through a column (data) address bus.
  • the driver chip is used to control the screen to display the corresponding image.
  • the driving chips are electrically connected to the row driving circuit and the column driving circuit, respectively, and are responsible for functions such as data processing, transmission, and control signal transmission of the entire display screen.
  • the driver chip is composed of, for example, a single chip microcomputer (or FPGA) and peripheral circuits.
  • a power chip is used to power the driver chip.
  • the display power supply control method provided by the embodiment can be performed by a power chip.
  • the display power control method provided by the embodiment includes the following content.
  • Step S100 after receiving the start signal, control the power of the driving chip to be powered up according to the setting rule to reduce the probability that the voltage outputted by the driving chip is abnormal.
  • the start signal is, for example, a signal generated after the power is turned on or the sleep is awakened.
  • the power source of the driver chip refers to the power source input from the power chip to the driver chip.
  • the voltage outputted by the driving chip includes, for example, a gate driving positive voltage VGH and a gate driving negative voltage VGL.
  • the driver chip includes, for example, a digital circuit and an analog circuit as described below.
  • the digital circuit includes, for example, an input/output interface and a timing control module (ie, a TCON module).
  • the input and output interfaces have a high speed parallel bus interface and a serial peripheral interface.
  • the timing control module performs functions such as data processing in the SPI interface and the RGB interface and timing control of some modules in the driver chip.
  • the analog circuit includes, for example, a power management module and a pixel driving module.
  • the power management module provides voltage for scanning signals of various parts in the driving chip and the display screen.
  • the power management module includes, for example, a reference voltage source, a charge pump, and an LDO (low dropout regulator).
  • the pixel driving module includes, for example, a source driving module, a gate driving module, and a gamma correction module.
  • the source driving module outputs the gray voltage to the column driving circuit in the screen body.
  • the gate driving module outputs a scan signal (for example, including a gate driving positive voltage VGH and a gate driving negative voltage VGL) to the row driving circuit.
  • the gamma correction module is used to supply the gray voltage to the source driver module, and the change of the binary code to the gray voltage can be realized by adjusting the gamma curve.
  • the power source of the driving chip includes, for example, the power supply voltage VCI of the power management module and the power supply voltage of the digital circuit. Since the power supply is prone to fluctuations when it is powered on, the voltage outputted by the driver chip fluctuates abnormally, which causes a black screen on the display screen. Therefore, by improving the power-on mode of the power supply of the driver chip, the screen body can be reduced to some extent. The probability of a black screen.
  • step S200 the driving chip is continuously powered normally.
  • the power chip supplies power to the driving chip according to normal requirements, so that the TFT display screen operates normally.
  • the Improving the power-on condition of the driver chip power supply can improve the quality of the output signal of the driver chip, thereby reducing the probability of a black screen on the screen and improving the display performance of the display.
  • the above driver chip includes a power management module. Moreover, in the above step S100, after receiving the start signal, the power supply voltage of the control power management module is powered up according to the setting rule, so as to reduce the probability that the gate drive negative voltage VGL outputted by the driving chip is abnormally raised.
  • the gate driving negative voltage VGL is obtained by stepping down the power supply voltage VCI of the power management module.
  • the gate drive negative voltage VGL is abnormally raised, which means that the gate drive negative voltage VGL will be higher than the normal voltage range.
  • the range of the gate drive negative voltage VGL under normal conditions is (-7V, 0V).
  • the gate driving negative voltage VGL rises to 0.6 V it is considered that the abnormality is raised.
  • the voltage fluctuation may exceed the normal range, causing the gate drive negative voltage VGL to be abnormally raised.
  • the driver chip appears Latch.
  • the Up phenomenon that is, the voltage output from the driver chip is abnormally high, resulting in abnormal operation of the thin film transistor. Since the gate driving negative voltage VGL directly controls the operation of the thin film transistor, abnormality of the voltage causes the thin film transistor to be turned on, thereby generating a black screen.
  • the gate drive negative voltage VGL can be reduced to be abnormally high. The probability.
  • step S100 may include the following content, please refer to FIG. 2 .
  • Step S111 after receiving the start signal, the power supply voltage VCI of the control power management module is normally powered up to a first level.
  • the first level may be a normal supply voltage of the power management module, for example, between 2.5V and 4.8V.
  • the first level is 3.3V.
  • Step S112 after the first period of time, the power supply voltage VCI of the control power management module is lowered to the second level.
  • the second level is lower than the first level.
  • the first time period is related to the Transient Response characteristic of the power chip.
  • the first time period is between 8 ms and 12 ms, for example 10 ms.
  • the size of the second level at least ensures that the size of the gate drive negative voltage VGL does not cause a black screen problem in the screen.
  • the second level is, for example, between 1V and 2.2V.
  • the second level is, for example, 1.8V, at which time the corresponding gate drive negative voltage VGL is less than 0.4V.
  • the power chip can step down the first level by a charge pump or other circuit capable of implementing a buck to generate a second level to provide a second level to the power management module in step S112.
  • Step S113 after the second period of time, the power supply voltage VCI of the control power management module is raised to the first level.
  • the second time period is related to the Transient Response characteristic of the power chip.
  • the second time period is between 8 ms and 12 ms, for example 10 ms.
  • the power chip can also boost the second level to the first level again using a charge pump or other circuit capable of implementing a buck, and provide a first level to the power management module in step S113.
  • the specific implementation manner described above optimizes the power-on mode (ie, adopting a high-low-high level) mode of the power supply voltage VCI of the power management module, thereby reducing the probability of a black screen appearing on the screen.
  • the foregoing step S100 may specifically adopt another manner to reduce the probability that the voltage output by the driving chip is abnormal.
  • the above driving chip includes the above power management module and the above digital circuit.
  • the above step S100 specifically includes the following content, please refer to FIG. 3.
  • Step S121 after receiving the start signal, control the power supply voltage VCI of the power management module to be powered on.
  • Step S122 after the third period of time, the power supply voltage of the digital circuit is controlled to be powered on.
  • the power supply voltage VCI of the power management module and the power supply voltage of the digital circuit are sequentially adjusted, that is, the power supply voltage VCI of the power management module is first powered on, and after the third time period, the digital circuit is controlled. Powering up the supply voltage allows the digital circuitry to be protected from interference from VCI-related circuits (such as buck-boost circuits in the power management module) (such as electromagnetic interference) to ensure proper operation of the digital circuitry. Since the digital circuit is the core control circuit of the driving chip, the reliability of the driving chip operation can be improved, the probability of abnormality of the voltage outputted by the driving chip is reduced, and the probability of a black screen appearing on the display screen is reduced. Specifically, the third time period is between 90 ms and 110 ms, for example 100 ms.
  • the supply voltage of the digital circuit is, for example, the voltage VDDIO of the input/output interface.
  • the power supply voltage DVDD of the timing control module is stepped down by the voltage VDDIO of the input/output interface. At this time, after the voltage VDDIO of the input/output interface is controlled, the power is turned on, and in the case of no interference, it can be ensured that the power supply voltage of the timing control module is less than the set voltage threshold (for example, 1.4V), that is, the timing control module can work normally.
  • the set voltage threshold for example, 1.4V
  • the step S122 may be specifically: after the power supply voltage VCI of the power management module is stepped down in the driving chip, the power supply voltage of the digital circuit is controlled to be powered on.
  • stepping down the power supply voltage VCI of the power management module gradually reduces the power supply voltage VCI of the power management module to one or more voltages. Moreover, when the time elapsed by the entire step-down process of the power supply voltage VCI of the power management module reaches the third time period, the power supply voltage of the control data circuit is powered on.
  • the step-down process of the power supply voltage of the power management module can be implemented by a charge pump or other circuit that can implement a step-down.
  • the step of controlling the power supply voltage of the digital circuit to be powered up is: reducing the power supply voltage VCI of the power management module to the first in the driving chip. After the voltage is lowered to the second voltage, the power supply voltage of the digital circuit is controlled to be powered.
  • the second voltage is, for example, a reference voltage VREF used by the power management module.
  • the power supply voltage VCI of the power management module is reduced to the first voltage, and then the first voltage is lowered to the second voltage, and the total elapsed time is the third time period.
  • the rising edge of the charge pump in the driving chip, the duration of the falling edge, or the number of instructions executed by the timing control module can be adjusted to control the power supply voltage VCI of the power management module to be reduced to the first voltage, and then the first The time during which the voltage is reduced to the second voltage is a total of the third time period described above.
  • the first voltage is VCL, which is a voltage generated by a charge pump in the power management module.
  • VCL is a voltage generated by a charge pump in the power management module.
  • the power supply voltage VCI of the power management module may be reduced to a first voltage by a charge pump and then decreased by a first voltage to a second voltage.
  • FIG. 4 for the power-on condition of each voltage in the driving chip.
  • the power supply voltage VCI of the power management module when the power supply voltage VCI of the power management module is powered on, on the one hand, the power supply voltage VCI of the power management module maintains its own voltage level, and the voltage AVDD (ie, the power supply of the gamma correction module and the power management module)
  • the voltages are matched to each other and boosted by a charge pump or other circuit that can be stepped down to generate a gate drive positive voltage VGH.
  • the size of VGH is, for example, AVDD+VCI, 2AVDD, 2AVDD+VCI, or 3AVDD.
  • the power supply voltage VCI of the power management module can be stepped down by a charge pump or other circuit that can be stepped down, and reduced to the first voltage VCL.
  • the process in which the power supply voltage VCI of the power management module maintains its own voltage level and the power supply voltage VCI of the power management module are reduced to the first voltage VCL are simultaneously performed.
  • the first voltage VCL can be stepped down with the voltage AVDD to generate the gate driving negative voltage VGL, and the first voltage VCL is further stepped down.
  • a second voltage is obtained (such as VREF described above).
  • the time elapsed from the power-on of the VCI to the falling of VREF in the dashed box is the third time period described above.
  • the supply voltage to the digital circuit is powered up.
  • FIG. 1 to FIG. 3 are schematic flowcharts of a method according to an embodiment of the present invention. It should be understood that although the various steps in the flowcharts of FIGS. 1 through 3 are sequentially displayed as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Except as explicitly stated herein, the execution of these steps is not strictly limited, and may be performed in other sequences. Moreover, at least some of the steps in FIGS.
  • 1 to 3 may include a plurality of sub-steps or stages, which are not necessarily performed at the same time, but may be executed at different times, and the execution order thereof is also It is not necessarily performed sequentially, but may be performed alternately or alternately with at least a portion of other steps or sub-steps or stages of other steps.
  • the TFT display screen includes a driving chip and a screen body.
  • the driving chip is configured to control the screen to display a corresponding image, and the screen body controls pixels by using a thin film transistor.
  • the display power control device includes the following, please refer to Figure 5.
  • the power-on control module 100 is configured to control the power of the driving chip to be powered according to a setting rule after receiving the startup signal, so as to reduce the probability that the voltage output by the driving chip is abnormal.
  • the normal power supply module 200 is configured to continuously supply power to the driving chip.
  • the driver chip includes a power management module.
  • the power-on control module 100 is configured to: after receiving the startup signal, control the power supply voltage of the power management module to be powered up according to the setting rule, so as to reduce the abnormality of the gate driving negative voltage output by the driving chip. The probability of a phenomenon.
  • the power-on control module 100 includes the following content, please refer to FIG. 6:
  • the first power-on unit 110 is configured to control the power supply voltage of the power management module to be normally powered up to a first level after receiving the startup signal.
  • the second power-on unit 120 is configured to control the power supply voltage of the power management module to decrease to a second level after the first period of time.
  • the second level is lower than the first level.
  • the third power-on unit 130 is configured to control the power supply voltage of the power management module to rise to the first level after the second period of time.
  • the first level is between 2.5V and 4.8V.
  • the first time period is between 8 ms and 12 ms.
  • the first time period is 10 ms.
  • the second time period is between 8 ms and 12 ms.
  • the second period of time is 10 ms.
  • the second level is between 1V and 2.2V.
  • the driver chip includes a power management module and a digital circuit.
  • the power-on control module 100 includes the following contents, please refer to FIG. 7:
  • the power-on unit 140 is configured to control the power-on voltage of the power management module to be powered on after receiving the startup signal.
  • the digital power-on unit 150 is configured to control the power supply voltage of the digital circuit to be powered after the third period of time.
  • the third time period is between 90ms and 110ms.
  • the third time period is 100 ms.
  • the digital power-on unit 150 is configured to control the power supply voltage of the digital circuit to be powered up after stepping down the power supply voltage of the power management module in the driving chip.
  • the digital power-on unit 150 is configured to reduce the power supply voltage of the power management module to a first voltage in the driving chip, and then control the digital circuit after lowering the first voltage to a second voltage.
  • the supply voltage is powered up.
  • the second voltage is a reference voltage used by the power management module.
  • the first voltage is a voltage generated by a charge pump in the power management module.
  • the display power supply control device provided by the present embodiment corresponds to the display power supply control method of the above embodiment, and details are not described herein again.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or the like.
  • This storage medium is applied to a TFT type display screen.
  • the TFT type display screen includes a power chip, a driving chip and a screen body.
  • the storage medium is located in the power chip, and the storage medium stores a program, and when the program is executed by a processor in the power chip, the following steps are implemented:
  • the power supply to the driver chip is continuously supplied.
  • the electronic device includes a power chip, a driver chip, and a screen body.
  • the power chip includes a memory and a processor, and the memory stores a program, and when the program is executed by the processor, the processor performs the following steps:
  • the power supply to the driver chip is continuously supplied.

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Abstract

一种显示屏电源控制方法、装置、存储介质及电子设备，应用于TFT式显示屏；TFT式显示屏包括驱动芯片及屏体；驱动芯片用于控制屏体显示相应图像，且屏体利用薄膜晶体管控制像素；方法包括：在接收到启动信号后，控制驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率；持续对驱动芯片正常供电。由于驱动芯片的电源直接决定驱动芯片向屏体输出的电压的性能，而且电源刚上电时容易出现波动的情况，因此通过改善驱动芯片的上电情况，可以提高驱动芯片输出的电压的质量，从而减小屏体出现黑屏的概率，提高显示屏的显示性能。

Description

显示屏电源控制方法、装置、存储介质及电子设备 技术领域
本发明涉及显示技术领域，特别是涉及一种显示屏电源控制方法、装置、存储介质及电子设备。
背景技术
TFT(Thin Film Transistor，薄膜晶体管)式显示屏是各类笔记本电脑和台式机上的主流显示设备，该类显示屏上的每个像素点都是由集成在像素点后面的薄膜晶体管来驱动。TFT式显示屏通常包括驱动芯片及屏体。其中，驱动芯片用于控制薄膜晶体管的工作状态，进而使屏体显示相应图像。传统的TFT式显示屏在重新开机或休眠唤醒时会出现黑屏现象，而驱动芯片的工作性能直接影响屏体的显示效果，因此如何改善驱动芯片的性能是亟待解决的问题。
发明内容
基于此，有必要针对如何改善TFT式显示屏驱动芯片的性能的问题，提供一种显示屏电源控制方法、装置、存储介质及电子设备。
一种显示屏电源控制方法，应用于TFT式显示屏；所述TFT式显示屏包括驱动芯片及屏体；所述驱动芯片用于控制所述屏体显示相应图像，且所述屏体利用薄膜晶体管控制像素；所述方法包括：
在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率；
持续对所述驱动芯片正常供电。
在其中一个实施例中，所述驱动芯片包括电源管理模块；并且，所述在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率的步骤为：
在接收到启动信号后，控制所述电源管理模块的供电电压按照设定规则上电，以减小所述驱动芯片输出的栅极驱动负电压发生异常抬高现象的概率。
在其中一个实施例中，所述在接收到启动信号后，控制所述电源管理模块的供电电压按照设定规则上电，以减小所述驱动芯片输出的栅极驱动负电压发生异常抬高现象的概率的步骤包括：
在接收到启动信号后，控制所述电源管理模块的供电电压正常上电至第一电平；
经过第一时间段后控制所述电源管理模块的供电电压降至第二电平；所述第二电平低于所述第一电平；
经过第二时间段后控制所述电源管理模块的供电电压再升至所述第一电平。
在其中一个实施例中，所述第一电平介于2.5V至4.8V之间；优选地，所述第一时间段介于8ms至12ms之间；优选地，所述第一时间段为10ms；优选地，所述第二时间段介于8ms至12ms之间；优选地，所述第二时间段为10ms。
在其中一个实施例中，所述第二电平介于1V至2.2V之间。
在其中一个实施例中，所述驱动芯片包括电源管理模块及数字电路；并且，所述在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率的步骤包括：
在接收到启动信号后，控制所述电源管理模块的供电电压上电；
经过第三时间段后控制所述数字电路的供电电压上电；优选地，所述第三时间段介于90ms至110ms之间；优选地，所述第三时间段为100ms。
在其中一个实施例中，所述经过第三时间段后控制所述数字电路的供电电压上电的步骤为：
在所述驱动芯片内将所述电源管理模块的供电电压进行逐步降压后，控制所述数字电路的供电电压上电；
优选地，所述在所述驱动芯片内将所述电源管理模块的供电电压进行逐步降压后，控制所述数字电路的供电电压上电的步骤为：在所述驱动芯片内将所述电源管理模块的供电电压降低至第一电压，再将所述第一电压降低至第二电压后，控制所述数字电路的供电电压上电；其中，所述第二电压为所述电源管理模块采用的参考电压；优选地，所述第一电压为所述电源管理模块内电荷泵产生的电压。。
一种显示屏电源控制装置，应用于TFT式显示屏；所述TFT式显示屏包括驱动芯片及屏体；所述驱动芯片用于控制所述屏体显示相应图像，且所述屏体利用薄膜晶体管控制像素； 所述装置包括：
上电控制模块，用于在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率；
正常供电模块，用于持续对所述驱动芯片正常供电。
一种存储介质，应用于TFT式显示屏；所述TFT式显示屏包括电源芯片、驱动芯片及屏体；所述存储介质位于所述电源芯片内，并存储有程序，该程序被所述电源芯片内的处理器执行时实现以下步骤：
在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率；
持续对所述驱动芯片正常供电。
一种电子设备，包括电源芯片、驱动芯片和屏体；所述电源芯片包括存储器和处理器，所述存储器中储存有程序，所述程序被所述处理器执行时，使得所述处理器执行以下步骤：
在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率；
持续对所述驱动芯片正常供电。
上述显示屏电源控制方法、装置、存储介质及电子设备中，在接收到启动信号后，控制驱动芯片的电源按照设定规则上电，以减小驱动芯片输出的电压发生异常的概率。由于驱动芯片的电源直接决定驱动芯片向屏体输出的电压的性能，而且电源刚上电时容易出现波动的情况，因此通过改善驱动芯片的上电情况，可以提高驱动芯片输出的电压的质量，从而减小屏体出现黑屏的概率，提高显示屏的显示性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施方式提供的显示屏电源控制方法的流程图；
图2为图1所示实施方式的显示屏电源控制方法的步骤S100的其中一个实施例的流程 图；
图3为图1所示实施方式的显示屏电源控制方法的步骤S100的另一个实施例的流程图；
图4为图3所示实施例的显示屏电源控制方法中驱动芯片的其中一种具体上电方式的流程图；
图5为另一实施方式提供的显示屏电源控制装置的框图；
图6为图5所示实施方式的显示屏电源控制装置的上电控制模块的其中一个实施例的框图；
图7为图5所示实施方式的显示屏电源控制装置的上电控制模块的另一个实施例的框图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于发明的技术领域的技术人员通常理解的含义相同。本文中在发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本发明。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本发明的实施方式提供了一种显示屏电源控制方法，应用于TFT式显示屏。TFT式显示屏包括电源芯片、驱动芯片及屏体。其中，屏体利用薄膜晶体管控制像素。屏体例如包括像素矩阵、行驱动电路及列驱动电路。像素矩阵包括多个像素及多个像素驱动电路，每一个像素由一个像素驱动电路控制。行驱动电路通过行(扫描)地址总线向各像素驱动电路发送扫描信号。列驱动电路通过列(数据)地址总线向各像素驱动电路发送数据信号。驱动芯片用于控制屏体显示相应图像。驱动芯片分别与行驱动电路、列驱动电路电连接，其负责整个显示屏的数据处理、传送、控制信号的发出等功能。驱动芯片例如由单片机(或FPGA)及外围电路构成。电源芯片(Power IC)用于向驱动芯片供电。本实施方式提供的显示屏电源控制方法可以电源芯片来执行。
请参考图1，本实施方式提供的显示屏电源控制方法包括以下内容。
步骤S100，在接收到启动信号后，控制驱动芯片的电源按照设定规则上电，以减小驱动 芯片输出的电压发生异常的概率。
其中，启动信号例如为在开机或休眠被唤醒后产生的信号。驱动芯片的电源是指由电源芯片向驱动芯片输入的电源。驱动芯片输出的电压例如包括栅极驱动正电压VGH、栅极驱动负电压VGL。驱动芯片输出的电压发生异常后，就会导致屏体的薄膜晶体管工作异常，从而导致屏体发生黑屏。
驱动芯片例如包括数字电路和模拟电路，如下所述。
其中，数字电路例如包括输入输出接口及时序控制模块(即TCON模块)。输入输出接口有高速并行总线接口及串行外围接口。时序控制模块例如完成SPI接口和RGB接口中数据处理以及驱动芯片中部分模块的时序控制的功能。
模拟电路例如包括电源管理模块及像素驱动模块。其中，电源管理模块为驱动芯片内的各部分及显示屏的扫描信号提供电压，电源管理模块例如包括基准电压源、电荷泵、LDO(low dropout regulator，低压差线性稳压器)。像素驱动模块例如包括源极驱动模块、栅极驱动模块及gamma校正模块。其中，源极驱动模块输出灰度电压至屏体内的列驱动电路。栅极驱动模块输出扫描信号(例如包括栅极驱动正电压VGH、栅极驱动负电压VGL)至行驱动电路。gamma校正模块用于向源极驱动模块提供灰度电压，通过调节gamma曲线可实现二进制代码与灰度电压对应关系的变化。
在驱动芯片中，驱动芯片的电源例如包括上述电源管理模块的供电电压VCI、数字电路的供电电压。由于电源刚上电时容易出现波动情况，使得驱动芯片输出的电压发生异常波动，进而导致显示屏出现黑屏，因此通过改善驱动芯片的电源的上电方式，可以在一定程度上减小屏体发生黑屏的概率。
步骤S200，持续对驱动芯片正常供电。
步骤S100执行后，电源芯片按照正常的需求对驱动芯片进行供电，以使得TFT式显示屏正常运行。
综上所述，上述实施方式提供的显示屏电源控制方法中，由于驱动芯片的电源直接决定驱动芯片向屏体输出的电压的性能，而且电源刚开始上电时容易出现波动的情况，因此通过改善驱动芯片电源的上电情况，可以提高驱动芯片输出信号的质量，从而减小屏体出现黑屏的概率，提高显示屏的显示性能。
在其中一个实施例中，上述驱动芯片包括电源管理模块。并且，上述步骤S100为：在接 收到启动信号后，控制电源管理模块的供电电压按照设定规则上电，以减小驱动芯片输出的栅极驱动负电压VGL发生异常抬高的概率。
其中，栅极驱动负电压VGL由电源管理模块的供电电压VCI降压得到。栅极驱动负电压VGL发生异常抬高，是指栅极驱动负电压VGL会出现高于正常电压范围的情况，例如：正常情况下栅极驱动负电压VGL的范围为(-7V，0V)，而栅极驱动负电压VGL上升为0.6V时，则认为异常抬高。
在传统的TFT式显示屏中，电源管理模块的供电电压VCI刚上电后，可能出现电压波动超出正常范围的情况，导致栅极驱动负电压VGL被异常抬高，这时驱动芯片则出现Latch Up现象(即驱动芯片输出的电压异常太高，从而导致薄膜晶体管工作异常)。由于栅极驱动负电压VGL直接控制薄膜晶体管运行，因此，该电压出现异常，将会导致薄膜晶体管无法导通，进而产生黑屏。本实施例中，通过改善电源管理模块的供电电压VCI的上电情况，例如减小波动电流，以降低栅极驱动负电压VGL的幅值，从而可以降低栅极驱动负电压VGL发生异常太高的概率。
具体地，步骤S100的上述具体实现方式可以包括以下内容，请参考图2。
步骤S111，在接收到启动信号后，控制电源管理模块的供电电压VCI正常上电至第一电平。
其中，第一电平可以为电源管理模块的正常供电电压，例如介于2.5V至4.8V之间。可选地，第一电平为3.3V。
步骤S112，经过第一时间段后控制电源管理模块的供电电压VCI降至第二电平。第二电平低于第一电平。
其中，第一时间段与电源芯片的Transient Response(瞬态响应)特性有关。Transient Response时间越短，第一时间段越长。优选地，第一时间段介于8ms至12ms之间，例如为10ms。第二电平的大小至少可以保证栅极驱动负电压VGL的大小不会导致屏体出现黑屏问题。第二电平例如介于1V至2.2V。可选地，第二电平例如为1.8V，这时对应的栅极驱动负电压VGL小于0.4V。
具体地，电源芯片可以通过电荷泵或其他能实现降压的电路对第一电平进行降压产生第二电平，以在步骤S112中向电源管理模块提供第二电平。
步骤S113，经过第二时间段后控制电源管理模块的供电电压VCI再升至第一电平。
其中，第二时间段与电源芯片的Transient Response(瞬态响应)特性有关。Transient Response时间越短，第二时间段越长。优选地，第二时间段介于8ms至12ms之间，例如为10ms。
具体地，电源芯片同样可以利用电荷泵或其他能够实现降压的电路将第二电平再次升压至第一电平，并在步骤S113中向电源管理模块提供第一电平。
在图2所示的上述具体实现方式中，在电源管理模块的供电电压VCI正常上电后，再降低该供电电压，从而可以降低Latch Up电流，使得栅极驱动负电压VGL开始下降，直至电源管理模块的供电电压VCI降低至第二电平，可以解除Latch Up现象，之后，再重新将电源管理模块的供电电压VCI上升至第一电平，即可使驱动芯片正常运行。
因此，上述具体实现方式通过优化电源管理模块的供电电压VCI的上电方式(即采用高电平-低电平-高电平)的模式，从而可以降低屏体出现黑屏的概率。
在另一实施例中，上述步骤S100具体可以采用另一种方式来减小驱动芯片输出的电压发生异常的概率。上述驱动芯片包括上述电源管理模块及上述数字电路。并且，上述步骤S100具体包括以下内容，请参考图3。
步骤S121，在接收到启动信号后，控制电源管理模块的供电电压VCI上电。
步骤S122，经过第三时间段后控制数字电路的供电电压上电。
该实施例中，调整了电源管理模块的供电电压VCI及数字电路的供电电压的先后上电顺序，即先控制电源管理模块的供电电压VCI上电，经过第三时间段后，再控制数字电路的供电电压上电，可以使数字电路避免受到与VCI相关电路(例如电源管理模块内的升降压电路)的干扰(例如电磁干扰)，从而确保数字电路能够正常工作。由于数字电路是驱动芯片的核心控制电路，因此可以提高驱动芯片工作的可靠性，减小了驱动芯片输出的电压发生异常的概率，进而降低显示屏出现黑屏的概率。具体地，第三时间段介于90ms至110ms之间，例如为100ms。
具体地，数字电路的供电电压例如为输入输出接口的电压VDDIO。并且，时序控制模块的供电电压DVDD由输入输出接口的电压VDDIO降压得到。这时，控制输入输出接口的电压VDDIO后上电，在无干扰的情况下，可以确保时序控制模块的供电电压小于设定电压阈值(例如1.4V)，即使得时序控制模块能够正常工作。
具体地，上述步骤S122具体可以为：在驱动芯片内将电源管理模块的供电电压VCI进 行逐步降压后，控制数字电路的供电电压上电。
其中，将电源管理模块的供电电压VCI进行逐步降压，是指将电源管理模块的供电电压VCI依次逐渐降低至一个或一个以上电压。并且，当电源管理模块的供电电压VCI的整个降压过程所经历的时间达到第三时间段后，即控制数据电路的供电电压上电。具体地，电源管理模块的供电电压的降压过程可以通过电荷泵或其他可以实现降压的电路来实现。
具体地，上述在驱动芯片内将电源管理模块的供电电压VCI进行逐步降压后，控制数字电路的供电电压上电的步骤为：在驱动芯片内将电源管理模块的供电电压VCI降低至第一电压，再将第一电压降低至第二电压后，控制数字电路的供电电压上电。其中，第二电压例如为电源管理模块采用的参考电压VREF。
其中，电源管理模块的供电电压VCI降低至第一电压，再将第一电压降低至第二电压，这一过程共经历的时间为上述第三时间段。例如：可以调节驱动芯片内电荷泵上升沿、下降沿持续的时间，或者时序控制模块共执行的指令条数等方式，来控制电源管理模块的供电电压VCI降低至第一电压，再将第一电压降低至第二电压这一过程共经历的时间为上述第三时间段。
具体地，第一电压为VCL，即电源管理模块内电荷泵产生的一个电压。可选地，电源管理模块的供电电压VCI可以通过电荷泵降低至第一电压，再由第一电压降低至第二电压。
进一步地，基于图3所示的实施例，驱动芯片内各电压的上电情况请参考图4。其中，当电源管理模块的供电电压VCI上电后，一方面，电源管理模块的供电电压VCI保持自身的电压大小，并与电压AVDD(即gamma校正模块和电源管理模块内升降压电路的供电电压)相互配合，通过电荷泵或其他可以降压的电路进行升压产生栅极驱动正电压VGH。VGH的大小例如为AVDD+VCI、2AVDD、2AVDD+VCI或3AVDD。另一方面，电源管理模块的供电电压VCI可以通过电荷泵或其他可以降压的电路进行降压，并降低至第一电压VCL。其中，电源管理模块的供电电压VCI保持自身的电压大小这一过程与电源管理模块的供电电压VCI降低至第一电压VCL这一过程是同时进行的。当电源管理模块的供电电压VCI降低至第一电压VCL后，第一电压VCL一方面可以与电压AVDD配合进行降压以产生栅极驱动负电压VGL，另一方面，第一电压VCL进一步降压得到第二电压(例如上述的VREF)。在图4中，虚线框内从VCI上电到降至VREF这一过程共经历的时间为上述第三时间段。当降至VREF后(即经过第三时间段后)，数字电路的供电电压上电。
需要说明的是，图1至图3为本发明实施例的方法的流程示意图。应该理解的是，虽然图1至图3的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，其可以以其他的顺序执行。而且，图1至图3中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，其执行顺序也不必然是依次进行，而是可以与其他步骤或者其他步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
另一实施方式提供了一种显示屏电源控制装置，应用于TFT式显示屏。所述TFT式显示屏包括驱动芯片及屏体。所述驱动芯片用于控制所述屏体显示相应图像，且所述屏体利用薄膜晶体管控制像素。显示屏电源控制装置包括以下内容，请参考图5。
上电控制模块100，用于在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率。
正常供电模块200，用于持续对所述驱动芯片正常供电。
在其中一个实施例中，所述驱动芯片包括电源管理模块。并且，上电控制模块100用于在接收到启动信号后，控制所述电源管理模块的供电电压按照设定规则上电，以减小所述驱动芯片输出的栅极驱动负电压发生异常抬高现象的概率。
在其中一个实施例中，上电控制模块100包括以下内容，请参考图6：
第一上电单元110，用于在接收到启动信号后，控制所述电源管理模块的供电电压正常上电至第一电平。
第二上电单元120，用于经过第一时间段后控制所述电源管理模块的供电电压降至第二电平。所述第二电平低于所述第一电平。
第三上电单元130，用于经过第二时间段后控制所述电源管理模块的供电电压再升至所述第一电平。
在其中一个实施例中，所述第一电平介于2.5V至4.8V之间。优选地，所述第一时间段介于8ms至12ms之间。优选地，所述第一时间段为10ms。优选地，所述第二时间段介于8ms至12ms之间。优选地，所述第二时间段为10ms在其中一个实施例中，所述第二电平介于1V至2.2V之间。
在其中一个实施例中，所述驱动芯片包括电源管理模块及数字电路。并且，上电控制模 块100包括以下内容，请参考图7：
电源上电单元140，用于在接收到启动信号后，控制所述电源管理模块的供电电压上电。
数字上电单元150，用于经过第三时间段后控制所述数字电路的供电电压上电。所述第三时间段介于90ms至110ms之间。优选地，所述第三时间段为100ms。
在其中一个实施例中，数字上电单元150用于在所述驱动芯片内将所述电源管理模块的供电电压进行逐步降压后，控制所述数字电路的供电电压上电。优选地，数字上电单元150用于在所述驱动芯片内将所述电源管理模块的供电电压降低至第一电压，再将所述第一电压降低至第二电压后，控制所述数字电路的供电电压上电。其中，所述第二电压为所述电源管理模块采用的参考电压。优选地，所述第一电压为所述电源管理模块内电荷泵产生的电压。
需要说明的是，本实施方式提供的显示屏电源控制装置与上述实施方式的显示屏电源控制方法对应，这里就不再赘述。
另一实施方式提供了一种存储介质。存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)等。该存储介质应用于TFT式显示屏。所述TFT式显示屏包括电源芯片、驱动芯片及屏体。所述存储介质位于所述电源芯片内，该存储介质存储有程序，该程序被电源芯片内的处理器执行时实现以下步骤：
在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率；
持续对所述驱动芯片正常供电。
需要说明的是，本实施方式中处理器执行的步骤与上述实施方式的显示屏电源控制方法对应，这里就不再赘述。
另一实施方式提供了一种电子设备，例如手机、计算机等。该电子设备包括电源芯片、驱动芯片和屏体。所述电源芯片包括存储器和处理器，所述存储器中储存有程序，所述程序被所述处理器执行时，使得所述处理器执行以下步骤：
在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率；
持续对所述驱动芯片正常供电。
需要说明的是，本实施方式中处理器执行的步骤与上述实施方式的显示屏电源控制方法对应，这里就不再赘述。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种显示屏电源控制方法，应用于TFT式显示屏；所述TFT式显示屏包括驱动芯片及屏体；所述驱动芯片用于控制所述屏体显示相应图像，且所述屏体利用薄膜晶体管控制像素；所述方法包括：
    在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率；
    持续对所述驱动芯片正常供电。
  2. 根据权利要求1所述的方法，其中，所述驱动芯片包括电源管理模块；并且，所述在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率，包括：
    在接收到启动信号后，控制所述电源管理模块的供电电压按照设定规则上电，以减小所述驱动芯片输出的栅极驱动负电压发生异常抬高现象的概率。
  3. 根据权利要求2所述的方法，其中，所述在接收到启动信号后，控制所述电源管理模块的供电电压按照设定规则上电，以减小所述驱动芯片输出的栅极驱动负电压发生异常抬高现象的概率，包括：
    在接收到启动信号后，控制所述电源管理模块的供电电压正常上电至第一电平；
    经过第一时间段后控制所述电源管理模块的供电电压降至第二电平；所述第二电平低于所述第一电平；
    经过第二时间段后控制所述电源管理模块的供电电压再升至所述第一电平。
  4. 根据权利要求3所述的方法，其中，所述第一电平介于2.5V至4.8V之间。
  5. 根据权利要求4所述的方法，其中，所述第一时间段介于8ms至12ms之间。
  6. 根据权利要求4所述的方法，其中，所述第一时间段为10ms。
  7. 根据权利要求3所述的方法，其中，所述第二电平介于1V至2.2V之间。
  8. 根据权利要求1所述的方法，其中，所述驱动芯片包括电源管理模块及数字电路；并且，所述在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率，包括：
    在接收到启动信号后，控制所述电源管理模块的供电电压上电；
    经过第三时间段后控制所述数字电路的供电电压上电。
  9. 根据权利要求8所述的方法，其中，所述第三时间段介于90ms至110ms之间。
  10. 根据权利要求8所述的方法，其中，所述第三时间段为100ms。
  11. 根据权利要求8所述的方法，其中，所述经过第三时间段后控制所述数字电路的供电电压上电的步骤为：
    在所述驱动芯片内将所述电源管理模块的供电电压进行逐步降压后，控制所述数字电路的供电电压上电。
  12. 根据权利要求8所述的方法，其中，所述在所述驱动芯片内将所述电源管理模块的供电电压进行逐步降压后，控制所述数字电路的供电电压上电的步骤为：在所述驱动芯片内将所述电源管理模块的供电电压降低至第一电压，再将所述第一电压降低至第二电压后，控制所述数字电路的供电电压上电；其中，所述第二电压为所述电源管理模块采用的参考电压；优选地，所述第一电压为所述电源管理模块内电荷泵产生的电压。
  13. 一种显示屏电源控制装置，应用于TFT式显示屏；所述TFT式显示屏包括驱动芯片及屏体；所述驱动芯片用于控制所述屏体显示相应图像，且所述屏体利用薄膜晶体管控制像素；其中，所述装置包括：
    上电控制模块，用于在接收到启动信号后，控制所述驱动芯片的电源按照设定规则上电，以减小所述驱动芯片输出的电压发生异常的概率；
    正常供电模块，用于持续对所述驱动芯片正常供电。
  14. 根据权利要求13所述的显示屏电源控制装置，其中，所述驱动芯片包括电源管理模块及数字电路，当所述电源管理模块的供电电压逐步降压后，所述数字电路的供电电压上电。
  15. 一种电子设备，包括电源芯片、驱动芯片和屏体；所述电源芯片包括存储器和处理器，所述存储器中储存有程序，其中，所述程序被所述处理器执行时，使得所述处理器执行如权利要求1～12任一项所述的方法。
  16. 一种存储介质，应用于TFT式显示屏；所述TFT式显示屏包括电源芯片、驱动芯片及屏体；所述存储介质位于所述电源芯片内，并存储有程序，其特征在于，该程序被所述电源芯片内的处理器执行如权利要求1～12任一项所述的方法。
PCT/CN2018/088248 2017-07-13 2018-05-24 显示屏电源控制方法、装置、存储介质及电子设备 WO2019011064A1 (zh)

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