WO2019003589A1 - Dispositif à semi-conducteur et son procédé de production - Google Patents

Dispositif à semi-conducteur et son procédé de production Download PDF

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WO2019003589A1
WO2019003589A1 PCT/JP2018/015795 JP2018015795W WO2019003589A1 WO 2019003589 A1 WO2019003589 A1 WO 2019003589A1 JP 2018015795 W JP2018015795 W JP 2018015795W WO 2019003589 A1 WO2019003589 A1 WO 2019003589A1
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gate electrode
insulating film
semiconductor device
power transistor
gate
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PCT/JP2018/015795
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English (en)
Japanese (ja)
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慎太郎 佐藤
悠佳 清水
佐川　雅一
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株式会社日立パワーデバイス
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L29/12—
    • H01L29/78—

Definitions

  • the present invention relates to, for example, a semiconductor device using silicon carbide (SiC) and a technique effective when applied to a manufacturing technique thereof.
  • SiC silicon carbide
  • JP 2010-212636 A when a positive bias is applied to the gate electrode by introducing a conductive impurity only to the central portion of the gate electrode made of a polysilicon film, A technique is described which extends the depletion layer generated at the end to reduce the electric field in the vicinity of the end of the gate electrode.
  • SiC 4H-type silicon carbide
  • An object of the present invention is to improve the performance of a semiconductor device including a power transistor by reducing the leak current of a power transistor using silicon carbide.
  • the semiconductor device in one embodiment includes a power transistor formed on an epitaxial layer containing silicon carbide as a main component.
  • the power transistor includes a gate insulating film formed on the epitaxial layer, a gate electrode formed on the gate insulating film and containing a conductive impurity, and a first insulating film formed on the sidewall of the gate electrode. And a second insulating film formed to cover the gate electrode and the first insulating film.
  • the density of the first insulating film is higher than the density of the second insulating film.
  • the first insulating film contains the conductive impurity at an impurity concentration of 1/100 or less of the maximum impurity concentration of the conductive impurity contained in the gate electrode.
  • the performance of a semiconductor device including a power transistor using silicon carbide can be improved.
  • FIG. 1 It is a block diagram which shows an example of the three-phase motor system (power converter device) applied to a rail vehicle. It is a circuit diagram which shows the circuit structure of the converter and inverter which are shown in FIG. It is the figure which took out a part of 3 phase inverter. It is a figure explaining the mechanism of a "false ⁇ ". It is a figure explaining "false ⁇ ". It is a figure explaining the short circuit by "a false positive”. It is a figure explaining the prevention measures of a "false eclipse”. It is a figure explaining the prevention measures of a "false eclipse”. It is a figure explaining the room for improvement which the present inventor found.
  • FIG. 15 is a cross-sectional view showing the manufacturing process of the SiC power MOSFET continued from FIG. 14; FIG.
  • FIG. 16 is a cross-sectional view showing the manufacturing process of the SiC power MOSFET continued from FIG. 15;
  • FIG. 17 is a cross-sectional view showing the manufacturing process of the SiC power MOSFET continued from FIG. 16;
  • FIG. 18 is a cross-sectional view showing the manufacturing process of the SiC power MOSFET continued from FIG. 17;
  • FIG. 19 is a cross-sectional view showing the manufacturing process of the SiC power MOSFET continued from FIG. 18;
  • FIG. 20 is a cross-sectional view showing the manufacturing process of the SiC power MOSFET continued from FIG. 19;
  • FIG. 21 is a cross-sectional view showing the manufacturing process of the SiC power MOSFET continued from FIG. 20; It is a figure explaining modification 1. It is a figure explaining modification 2.
  • the wide band gap semiconductor material refers to a semiconductor material having a band gap larger than that of silicon (1.12 eV), for example, silicon carbide (2.20 to 3.02 eV), Gallium nitride (3.39 eV), diamond (5.47 eV) and the like are included.
  • the wide band gap semiconductor device refers to a semiconductor device using such a wide band gap semiconductor material as a substrate.
  • FIG. 1 is a block diagram showing an example of a three-phase motor system (power conversion device) applied to, for example, a railway vehicle.
  • electric power is supplied from the overhead wire RT to the railcar via the pantograph PG.
  • the high voltage AC voltage supplied from the overhead wire RT is, for example, 25 kV or 15 kV.
  • the high voltage AC voltage supplied from the overhead wire RT to the railcar via the pantograph PG is stepped down to, for example, 3.3 kV AC voltage by the insulating main transformer MTR.
  • the stepped-down AC voltage is forwardly converted to a DC voltage (3.3 kV) by converter CON.
  • the DC voltage converted by converter CON is converted into a three-phase AC voltage 120 degrees out of phase by inverter INV via capacitor CL.
  • the three-phase AC voltage converted by the inverter INV is supplied to the three-phase motor MT.
  • the wheels WHL can be rotated, whereby the railway vehicle can be traveled.
  • FIG. 2 is a circuit diagram showing a circuit configuration of converter CON and inverter INV shown in FIG.
  • each of converter CON and inverter INV is formed of six power transistors Q and six free wheeling diodes FRD.
  • an upper arm (high side switch) and a lower arm (low side switch) are provided corresponding to each of the three phases (U phase, V phase, W phase).
  • Each of the lower arms is composed of one power transistor Q and one free wheeling diode FRD connected in parallel with each other.
  • the free wheeling diode FRD functions as, for example, a rectifying element that allows a return current due to an inductance included in the three-phase motor MT.
  • power semiconductor elements such as the power transistor Q and the free wheel diode FRD are used as main components having a switching function and a rectifying function.
  • IGBT Insulated Gate Bipolar Transistor
  • Si silicon
  • pn junction diode using silicon as a substrate material
  • the wide band gap semiconductor material has a higher breakdown electric field strength than silicon due to the larger band gap than silicon. That is, in a power semiconductor device using a wide band gap semiconductor material, the thickness of the drift layer (epitaxial layer) is thinner than that of a power semiconductor device using silicon as a substrate material because the dielectric breakdown electric field strength is higher than that of silicon. Even if the pressure resistance can be secured.
  • the on resistance can be reduced by reducing the thickness of the drift layer. That is, in a power semiconductor device using a wide band gap semiconductor material as a substrate material, there is obtained an advantage that it is possible to achieve a balance between ensuring the breakdown voltage and reducing the on-resistance, which are in a trade-off relationship.
  • SiC silicon carbide
  • GaN gallium nitride
  • diamond diamond and the like
  • SiC silicon carbide
  • SiN gallium nitride
  • SiC which is a wide band gap semiconductor material, has a dielectric breakdown electric field strength higher by about an order of magnitude than silicon, it is possible to reduce the on-resistance of the power semiconductor element. This is because, as described above, when the dielectric breakdown electric field strength is high, the withstand voltage can be ensured even in a thin drift layer (epitaxial layer), and the on resistance can be reduced by thinning the drift layer. Furthermore, since the thermal conductivity of SiC is about three times that of silicon and is excellent in semiconductor physical properties even at high temperatures, it is also suitable for use at high temperatures.
  • SiC-pn junction diode a pn junction diode using silicon as a substrate material as a free wheel diode FRD as a rectifying element among switching elements and rectifying elements as components of the inverter INV
  • SiC Development has been preceded by replacing it with a pn junction diode (hereinafter referred to as a SiC-pn junction diode) using as a substrate material.
  • SiC-MOSFET power MOSFET using SiC as a substrate material
  • SiC-MOSFET power MOSFET
  • the SiC-MOSFET has a high breakdown voltage per device as compared to the Si-IGBT, so the number of parts can be reduced.
  • the size (volume) of the three-phase motor system can be reduced. This can reduce the floor of a railway vehicle, for example, by miniaturizing underfloor components including a three-phase motor system.
  • a space in which storage battery SB see FIG.
  • the improvement of the performance of the power conversion device represented by the inverter INV is achieved by devising to improve the performance of the SiC-MOSFET.
  • the purpose is to The technical idea in the present embodiment in which a device for SiC-MOSFET is applied will be described below. First, room for improvement, which is a premise for considering the technical idea in the present embodiment, will be described, and then, the technical idea in the present embodiment will be described. ⁇ Consideration of improvement>
  • FIG. 3 is a diagram showing a part of the three-phase inverter.
  • a power transistor Q1 forming a high side switch (upper arm) and a power transistor Q2 forming a low side switch (lower arm) are connected in series between the power supply terminal VT and the ground terminal GT.
  • One leg is illustrated.
  • FIG. 3 also shows a second leg in which a power transistor Q3 constituting a high side switch (upper arm) and a power transistor Q4 constituting a low side switch (lower arm) are connected in series.
  • the power transistor Q1 and the power transistor Q4 are turned on, while the power transistor Q2 and the power transistor Q3 are turned off.
  • current can flow in the path of power supply terminal VT ⁇ turned on power transistor Q1 ⁇ load motor MT ⁇ turned on power transistor Q4 ⁇ ground terminal GT.
  • a certain motor MT can be driven.
  • the power supply terminal VT and the ground terminal GT are short-circuited, whereby a large current indicated by a thick arrow flows between the power supply terminal VT and the ground terminal GT. Then, when a large current flows between the power supply terminal VT and the ground terminal GT, the power conversion device including the three-phase inverter generates heat and leads to destruction. From the above, from the viewpoint of improving the reliability of the power conversion device composed of the three-phase inverter, it is necessary to take measures to suppress the “false arcing”.
  • a countermeasure is taken to change the gate voltage V2 of the power transistor Q2 to be turned off from “-8 V" to "-15 V". That is, a measure is taken to increase the absolute value of the negative voltage applied to the gate electrode of the power transistor Q to be turned off.
  • the margin for reaching the threshold voltage becomes large. From this, it is difficult to cause "misfires" of the power transistor Q2, and it is possible to suppress a short circuit between the power supply terminal VT and the ground terminal GT.
  • FIG. 9 is a diagram for explaining the room for improvement found by the present inventor.
  • FIG. 9 shows a schematic cross-sectional structure of a so-called vertical power transistor.
  • the power transistor is formed in an epitaxial layer EPI formed of an n-type semiconductor layer.
  • a well region WL formed of a p-type semiconductor layer is formed in epitaxial layer EPI, and source region SR and body contact region BC are formed on the surface of well region WL. It is formed.
  • the source region is formed of an n-type semiconductor region
  • the body contact region BC is formed of a p-type semiconductor region having a higher impurity concentration than the well region WL.
  • the gate insulating film GOX is formed over the surface of the epitaxial layer EPI, the surface of the well region WL, and the surface of the source region SR. Furthermore, the gate electrode GE is formed over the gate insulating film GOX, and the interlayer insulating film IL is formed over the gate electrode GE and over the gate insulating film GOX.
  • the concentration of the electric field at the end of the gate electrode GE is alleviated, and the increase in leakage current due to the concentration of the electric field is less likely to be apparent.
  • a negative voltage is applied to the gate electrode GE, a depletion layer as in the case of applying a positive voltage to the gate electrode GE does not occur, and therefore the relaxation effect of electric field concentration by the depletion layer can not be expected. Therefore, the leak current between the gate electrode GE and the semiconductor substrate is particularly manifested when a negative voltage is applied to the gate electrode GE.
  • FIG. 10 is a view schematically showing a potential barrier by the gate insulating film when the electric field strength in the gate insulating film is small.
  • a negative voltage is applied to the gate electrode, electrons are accumulated in the gate electrode. Then, when the electrons present in the gate electrode escape to the substrate side, a leak current is generated. In this case, the electrons present in the gate electrode need to tunnel through the potential barrier having a width of “L1”.
  • the inclination of the potential barrier by the gate insulating film is gentle when the electric field strength is small. For this reason, the width "L1" of the potential barrier is large, and the probability that electrons present in the gate electrode tunnel through the potential barrier by the gate insulating film is low. This means that the electron current (FN tunneling current) flowing from the gate electrode to the substrate is reduced, in other words, the leakage current flowing from the substrate to the gate electrode is reduced.
  • FIG. 11 is a view schematically showing a potential barrier by the gate insulating film when the electric field strength in the gate insulating film is increased.
  • FIG. 11 when the electrons present in the gate electrode are leaked to the substrate side, a leak current is generated. In this case, the electrons present in the gate electrode need to tunnel through the potential barrier of width “L2”. is there.
  • the inclination of the potential barrier by the gate insulating film is steep when the electric field strength is large. Therefore, the potential barrier width "L2" is smaller than the potential barrier width "L1” in FIG.
  • the probability that electrons present in the gate electrode tunnel through the potential barrier of the gate insulating film is high. This means that the electron current (FN tunneling current) flowing from the gate electrode to the substrate increases, in other words, the leakage current flowing from the substrate to the gate electrode increases.
  • the epitaxial layer made of silicon carbide is not easily oxidized, there is a situation where it is difficult to use light oxidation after forming the gate electrode.
  • a gate insulating film is formed on the epitaxial layer, and then a gate electrode is formed on the gate insulating film, followed by light oxidation. Since the silicon oxide film is formed at the end of the gate electrode by this light oxidation, the thickness of the substantial gate insulating film at the end of the gate electrode is increased, thereby suppressing the electric field concentration at the end of the gate electrode it can.
  • This light oxidation increases the thickness of the substantial gate insulating film at the end of the gate electrode because oxygen molecules and oxygen-containing molecules pass through the gate insulating film and the epitaxial layer made of silicon is oxidized. It is from.
  • the epitaxial layer made of silicon carbide even if oxygen molecules or molecules containing oxygen pass through the gate insulating film by light oxidation, the epitaxial layer made of silicon carbide is not oxidized.
  • the thickness of the substantial gate insulating film in the portion does not increase. That is, in the power transistor using silicon, by performing light oxidation, the thickness of the substantial gate insulating film at the end of the gate electrode can be increased. As a result, electric field concentration at the end of the gate electrode can be suppressed.
  • step bunching refers to a step that occurs when epitaxially growing silicon carbide.
  • a step flow growth method is used as an epitaxial growth technique of silicon carbide. In this step flow growth method, for example, with respect to a surface introduced with an offset angle (off angle) of several degrees (for example, 4 degrees or 8 degrees) from the ⁇ 0001 ⁇ plane, in order to realize good epitaxial growth. It is a method of performing epitaxial growth.
  • the thickness of the gate insulating film tends to be thinner than that of the power transistor using silicon, and the reduction in thickness of the gate insulating film causes the electric field strength applied to the inside of the gate insulating film. growing.
  • the epitaxial layer made of silicon carbide there is a fine step called "step bunching", and silicon carbide is used due to dangling bonds and carbon atoms remaining in the gate insulating film.
  • the electron mobility of the channel is lower than that of the power transistor using silicon. Therefore, in the power transistor using silicon carbide, the channel resistance is larger than that of the power transistor using silicon.
  • the channel resistance is reduced by increasing the gate capacitance by decreasing the thickness of the gate insulating film and increasing the electron density generated in the channel. Has been done. For this reason, the power transistor using silicon carbide tends to have a thinner gate insulating film than the power transistor using silicon. As a result, as a result of the increase of the electric field strength inside the gate insulating film, the increase of the leak current particularly at the end of the gate electrode becomes apparent.
  • FIG. 12 is a diagram showing a device structure which suppresses an increase in the leak current at the end of the gate electrode in the power transistor using silicon carbide.
  • an insulating film OXF is provided to cover the gate electrode GE.
  • the insulating film OXF is made of, for example, a silicon oxide film formed by a thermal oxidation method, and CVD (Chemical Vapor Deposition) is provided. Film having a density higher than that of the interlayer insulating film IL made of a silicon oxide film formed by the above method.
  • the inventor has found that it is not sufficient to just form the dense insulating film OXF on the side wall of the gate electrode GE in order to reduce the leakage current at the end of the gate electrode GE. . That is, the inventor has newly found that the leak current when a negative voltage is applied to the gate electrode GE strongly depends on the film quality of the insulating film OXF formed on the side wall of the gate electrode GE.
  • the reason why the n-type impurity is introduced into the inside of the insulating film OXF is as follows. That is, although the gate electrode GE is formed of a polysilicon film, high concentration n-type impurities are introduced into the polysilicon film in order to reduce the resistance of the gate electrode GE. Therefore, for example, the n-type impurity is diffused from the inside of the polysilicon film to the inside of the insulating film OXF formed on the sidewall of the gate electrode GE by the heat treatment for activating the n-type impurity introduced into the polysilicon film. Do. As a result, n-type impurities are introduced also into the inside of the insulating film OXF.
  • the leakage current at the end of the gate electrode GE is increased by the following two mechanisms.
  • the first mechanism will be described. For example, when an n-type impurity is introduced into silicon, a donor level due to the n-type impurity is formed immediately below the conduction band of silicon. On the other hand, even when an n-type impurity is introduced into the insulating film OXF, a trap level (mid gap level) resulting from the n-type impurity is formed at the same energy level as the above-described donor level. Because the band gap of the insulating film OXF is much larger than the band gap of silicon, in silicon, the energy level formed in the vicinity immediately below the conduction band is in the center of the band gap in the insulating film OXF.
  • the film OXF also enables excitation of electrons from the valence band to the conduction band. As a result, the electrons excited in the conduction band recombine with the holes in the valence band, whereby the leak current in the insulating film OXF is increased.
  • the n-type impurity introduced into the insulating film OXF may be ionized.
  • the interface between the gate electrode GE and the insulating film OXF is For example, as in the case of the gate insulating film shown in FIG. 11, a steep potential barrier is generated. With such a steep potential barrier, for example, as shown in FIG. 11, the width "L2" of the potential barrier becomes smaller, so that the FN tunneling current becomes easier to flow, and this FN tunneling current becomes a leakage current. .
  • the high concentration of the n-type impurity contained in the insulating film OXF means that the ionized n-type impurity is increased accordingly. Therefore, when a high concentration of n-type impurity is introduced into the insulating film OXF, a sharper potential barrier is generated at the interface between the gate electrode GE and the insulating film OXF, which causes the FN tunneling current ( Leakage current) increases.
  • the n-type is formed inside the insulating film OXF formed on the side wall of the gate electrode GE. If the impurity phosphorus is contained at a high concentration, the leakage current at the end of the gate electrode GE can not be reduced.
  • FIG. 13 is a cross-sectional view of main parts of the SiC power MOSFET according to the present embodiment.
  • a substrate 1S mainly composed of n + -type SiC is formed on the surface (first main surface) of a substrate 1S mainly composed of silicon carbide (SiC) and made of n + -type SiC.
  • An n -- type epitaxial layer EPI drift layer mainly composed of silicon carbide (SiC) having a low impurity concentration is also formed.
  • the thickness of this n ⁇ -type epitaxial layer EPI is, for example, about 5 ⁇ m to 20 ⁇ m, and has an offset angle (off angle) of, for example, 4 degrees or 8 degrees.
  • main component refers to the material component contained most in the constituent materials constituting the member, for example, "epitaxial layer containing silicon carbide as the main component” Means that the epitaxial layer contains the most silicon carbide.
  • the intention of using the term “main component” in the present specification is, for example, to express that the epitaxial layer is basically composed of silicon carbide, but does not exclude the case where other impurities are contained. Used for
  • a p-type well region (body region) WL having a predetermined depth from the surface of the n ⁇ -type epitaxial layer EPI is formed. Furthermore, in the p-type well region WL, the n + -type source region has a predetermined depth from the surface of the n ⁇ -type epitaxial layer EPI and is separated from the end of the p-type well region WL. SR is formed. The source region SR has a structure different from the LDD structure.
  • the depth from the surface of the epitaxial layer EPI of the p-type well region WL is, for example, about 0.5 ⁇ m to 2.0 ⁇ m.
  • the depth from the surface of the epitaxial layer EPI of the n + -type source region SR is, for example, about 0.1 ⁇ m to 0.4 ⁇ m.
  • p ++ type body contact region BC having a predetermined depth from the surface of n - type epitaxial layer EPI and fixing the potential of p type well region WL in p type well region WL Is formed.
  • the depth from the surface of the epitaxial layer EPI of the p ++ -type body contact region BC is, for example, about 0.05 ⁇ m to 0.2 ⁇ m.
  • a back surface silicide layer BSL is formed on the back surface (second main surface) of the substrate 1S, and a back surface electrode BE is formed in contact with the back surface silicide layer BSL.
  • - and “+” is a code conductivity type expressed relative impurity concentrations of the n-type or p-type, for example, “n -”, “n”, “n +”, “n ++ "Indicates that the impurity concentration of the n-type impurity is increased in the order of".
  • the preferable range of the impurity concentration of the substrate 1S made of n + -type SiC is, for example, 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3
  • the preferable range of the impurity concentration of the n ⁇ -type epitaxial layer EPI is For example, it is 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the preferable range of the impurity concentration of the p ++ type body contact region BC is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3
  • the preferable range of the impurity concentration of the p-type well region WL is For example, it is 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3
  • a preferable range of the impurity concentration of the n + -type source region SR is, for example, 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3
  • the impurity concentration of the n-type impurity (phosphorus) contained in the gate electrode GE is 10 20 / cm 3 or more.
  • a gate insulating film GOX is formed on the surface of the substrate 1S in a region continuing from the source region SR to the epitaxial layer EPI via the well region WL.
  • a gate made of a polysilicon film is in contact with the gate insulating film GOX.
  • An electrode GE is formed.
  • the conductivity type of the polysilicon film forming the gate electrode GE is, for example, n + -type.
  • the gate electrode GE is covered with, for example, an insulating film OXF made of a silicon oxide film formed by a thermal oxidation method.
  • an interlayer insulating film IL made of, for example, a silicon oxide film formed by a CVD method is formed in contact with the insulating film OXF.
  • the density of the insulating film OXF is higher than the density of the interlayer insulating film IL. Further, the film thickness of the insulating film OXF is thinner than the film thickness of the interlayer insulating film IL.
  • the insulating film OXF is formed on the side wall of the gate electrode GE, but the insulating film OXF is not a sidewall spacer for forming the source region SR into a so-called LDD structure, and reduces leakage current at the end of the gate electrode GE
  • the membrane has the function of In particular, in the SiC power MOSFET in the present embodiment, the source region SR does not have an LDD structure, and therefore no sidewall spacer is provided.
  • the insulating film OXF in the present embodiment is a dense film having a high insulation resistance as compared with a general sidewall spacer.
  • the insulating film OXF in the present embodiment is a silicon oxide film formed by a thermal oxidation method, for example, a common sidewall spacer is a silicon oxide film formed by a CVD method. It differs in some respects.
  • the film thickness of the insulating film OXF is larger than the film thickness of the gate insulating film GOX. In the SiC power MOSFET according to the present embodiment, the thickness of the gate insulating film GOX is 80 nm or less.
  • n + -type source region SR and the p ++ -type body contact region BC are exposed, and the metal silicide layer SL is formed on these surfaces. It is formed.
  • a part of the n + -type source region SR and the p ++ -type body contact region BC are electrically connected to the source electrode SE through the metal silicide layer SL.
  • the substrate 1S is electrically connected to the back surface electrode (drain electrode) BE via the back surface silicide layer BSL.
  • a gate potential is externally applied to the gate electrode GE
  • a source potential is externally applied to the source electrode SE
  • a drain potential is externally applied to the drain electrode DE.
  • the SiC power MOSFET configured in this way is used, for example, as power transistors Q1 to Q4 shown in FIG.
  • a first voltage (+15 V) equal to or higher than the threshold voltage is applied to the gate electrode of the SiC power MOSFET.
  • a second voltage (-15 V) having the same absolute value as the first voltage and having the opposite polarity to the first voltage is applied to the gate electrode of the SiC power MOSFET Be done.
  • the semiconductor device in the present embodiment includes a SiC power MOSFET formed on an epitaxial layer EPI containing silicon carbide (SiC) as a main component.
  • the SiC power transistor includes a gate insulating film GOX formed on the epitaxial layer EPI, a gate electrode GE formed on the gate insulating film GOX, and containing an n-type impurity (conductive type impurity), and a gate An insulating film OXF formed on the side wall of the electrode GE, and an interlayer insulating film IL formed to cover the gate electrode GE and the insulating film OXF are provided.
  • the density of the insulating film OXF is higher than the density of the interlayer insulating film IL.
  • the insulating film OXF contains an n-type impurity (conductive impurity) at an impurity concentration of 1/100 or less of the maximum impurity concentration of the n-type impurity (conductive impurity) contained in the gate electrode GE.
  • the structural feature of this embodiment is, for example, that the impurity concentration of the n-type impurity (phosphorus) introduced in the insulating film OXF formed on the side wall of the gate electrode GE in FIG.
  • the point is 1/100 or less of the maximum impurity concentration of the n-type impurity (phosphorus) contained therein.
  • the maximum impurity concentration of the n-type impurity contained in the gate electrode GE is on the order of 10 20 / cm 3 or more, of the n-type impurity (phosphorus) contained in the insulating film OXF
  • the impurity concentration is in the order of 10 18 / cm 3 or less.
  • the SiC power MOSFET in the present embodiment it is possible to reduce the leak current at the end portion of the gate electrode GE which is a critical point. As a result, the reliability of the power conversion device using the SiC power MOSFET in the present embodiment can be improved.
  • the insulating film OXF in the present embodiment is formed of a silicon oxide film formed by a thermal oxidation method, and is, for example, denser and insulating than the interlayer insulating film IL which is a silicon oxide film formed by a CVD method. It is a highly resistant membrane. For this reason, according to the SiC power MOSFET in the present embodiment, it is considered that the leakage current at the end of the gate electrode GE can be reduced.
  • the inside of the insulating film OXF formed on the side wall of the gate electrode GE is an n-type impurity If phosphorus is contained at a high concentration, it is impossible to reduce the leakage current at the end of the gate electrode GE.
  • the impurity concentration of the n-type impurity (phosphorus) introduced in the insulating film OXF formed on the side wall of the gate electrode GE is equal to that of the gate electrode GE.
  • the SiC power MOSFET in the present embodiment the impurity concentration of the n-type impurity (phosphorus) introduced to the insulating film OXF formed on the side wall of the gate electrode GE is low, and thus dense and insulating resistance
  • the advantages of the silicon oxide film formed by the thermal oxidation method, that is, an excellent film can be maximized. Therefore, according to the SiC power MOSFET in the present embodiment, the leak current at the end of gate electrode GE can be reduced.
  • the maximum impurity concentration of the n-type impurity contained in the gate electrode GE is on the order of 10 20 / cm 3 or more.
  • the impurity concentration of the n-type impurity (phosphorus) introduced to insulating film OXF formed on the sidewall of gate electrode GE is contained in gate electrode GE. It is intended to reduce the leakage current at the end of the gate electrode GE while securing the reduction of the resistance of the gate electrode GE by the feature that it is 1/100 or less of the maximum impurity concentration of the n-type impurity (phosphorus) it can.
  • the feature point in the present embodiment is an excellent technical idea in that it is compatible with the reduction of resistance in the gate electrode GE and the reduction of the leak current at the end of the gate electrode GE. As described above, according to the structural feature point in the present embodiment, it has great utility in that both improvement in the reliability and performance of the power conversion device can be improved. ⁇ Method of manufacturing SiC power MOSFET>
  • the SiC power MOSFET in the present embodiment is configured as described above, and a method of manufacturing the same will be described below with reference to the drawings.
  • a substrate 1S mainly comprising an n + -type 4H—SiC substrate is prepared.
  • An n-type impurity is introduced into the substrate 1S.
  • the n-type impurity is, for example, nitrogen (N).
  • the impurity concentration of the n-type impurity is, for example, 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 It is in the range of 21 cm -3 .
  • the substrate 1S made of an n + -type SiC substrate has both the Si surface and the C surface, the surface of the substrate 1S may be either the Si surface or the C surface.
  • an n ⁇ -type epitaxial layer EPI mainly composed of silicon carbide is formed on the surface (first main surface) of the substrate 1S by epitaxial growth.
  • the n ⁇ -type epitaxial layer EPI may be formed by ion implantation.
  • An n-type impurity lower than the impurity concentration of the substrate 1S is introduced into the n ⁇ -type epitaxial layer EPI.
  • the impurity concentration of the n ⁇ -type epitaxial layer EPI depends on the device rating of the SiC power MOSFET, and is, for example, in the range of 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the thickness of the n ⁇ -type epitaxial layer EPI is, for example, 5 ⁇ m to 20 ⁇ m.
  • a first resist pattern is formed on the surface of the n ⁇ -type epitaxial layer EPI. Then, the first resist pattern as a mask, n - -type epitaxial layer p-type impurities in EPI, for example, by aluminum atoms to (Al) ion implantation, n - p-type well region -type epitaxial layer EPI Form WL.
  • the depth from the surface of the epitaxial layer EPI of the p-type well region WL is, for example, about 0.5 ⁇ m to 2.0 ⁇ m.
  • the impurity concentration of the p-type well region WL is, for example, in the range of 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • a second resist pattern is formed on the surface of the n ⁇ -type epitaxial layer EPI.
  • ions of an n-type impurity such as nitrogen atoms (N) or phosphorus atoms (P) are implanted into the p-type well region WL to form p-type well regions WL.
  • An n + -type source region SR is formed.
  • the depth from the surface of the epitaxial layer EPI of the n + -type source region SR is, for example, about 0.1 ⁇ m to 0.4 ⁇ m.
  • n-type impurity ion-implanted into the p-type well region WL a nitrogen atom (N) or a phosphorus atom (P) is exemplified, but the depth from the surface of the epitaxial layer EPI of the n + -type source region SR In order to make it shallow, any n-type impurity that can easily form a shallow junction may be used.
  • a mixture gas of (PF), phosphorus difluoride (PF 2 ), or phosphorus trifluoride (PF 3 ), or the above-described gas species may be used.
  • the impurity concentration of the n + -type source region SR is, for example, in the range of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
  • a third resist pattern is formed on the surface of the n ⁇ -type epitaxial layer EPI.
  • the opening region is provided only in the region where the p ++ -type body contact region BC is formed in the subsequent step.
  • ions of a p-type impurity such as aluminum atoms (Al) are implanted into the p-type well region WL to form a p ++ -type body contact region in the p-type well region WL.
  • the depth from the surface of the epitaxial layer EPI of the p ++ -type body contact region BC is, for example, about 0.05 to 0.2 ⁇ m.
  • the impurity concentration of the p ++ type body contact region BC is, for example, in the range of 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the gate insulating film GOX is, for example, a silicon oxide film (SiO 2 film) formed by thermally oxidizing the substrate 1S, or a silicon oxide film formed by thermal CVD (Chemical Vapor Deposition), or silicon nitride It consists of a film (SiN film) and a silicon oxynitride film (SiON film).
  • the thickness of the gate insulating film GOX is, for example, about 0.01 ⁇ m to 0.10 ⁇ m.
  • the non-doped polysilicon film PF in which the conductive impurity is not introduced is formed.
  • the polysilicon film PF is formed by depositing a polycrystalline film by the CVD method or depositing an amorphous film by the CVD method, and forming the film by annealing at a temperature of about 700 to 900 ° C. to crystallize it. Do.
  • a fourth resist pattern is formed on the polysilicon film PF. Then, using the fourth resist pattern as a mask, the polysilicon film PF is processed by dry etching to form the gate electrode GE made of the polysilicon film PF.
  • an insulating film OXF made of a silicon oxide film is formed on the surface of the gate electrode GE made of a polysilicon film, for example, by a thermal oxidation method of heating the substrate 1S at about 1000.degree.
  • a resist pattern PR is formed having an opening OP which opens.
  • an n-type impurity (phosphorus) is introduced into the gate electrode GE by an ion implantation method using the resist pattern PR as a mask.
  • the substrate 1S is heated to about 800 ° C. to activate the n-type impurity (phosphorus) introduced into the gate electrode GE.
  • the surface of the n ⁇ -type epitaxial layer EPI is oxidized by, eg, plasma CVD so as to cover the gate insulating film GOX and the insulating film OXF.
  • An interlayer insulating film IL made of a silicon film is formed.
  • a fifth resist pattern is formed on the interlayer insulating film IL.
  • the interlayer insulating film IL and the gate insulating film GOX are processed by dry etching to reach a part of the n + -type source region SR and the p ++ -type body contact region BC. Form a hole CNT.
  • each of a part of n + -type source region SR exposed at the bottom of contact hole CNT and a body contact region BC of p ++ -type The metal silicide layer SL is formed on the surface of
  • the inside (side and bottom) of the interlayer insulating film IL and the contact hole CNT is covered on the surface of the n ⁇ -type epitaxial layer EPI, for example
  • a first metal film made of a nickel film (Ni film) is deposited by sputtering.
  • the thickness of the first metal film is, for example, about 0.05 ⁇ m.
  • a heat treatment at 500 to 900 ° C.
  • a silicide layer SL is formed on part of the n + -type source region SR exposed at the bottom of the contact hole CNT and on the surface of the p ++ -type body contact region BC. Then, the unreacted first metal film is removed by wet etching. For example, sulfuric acid / hydrogen peroxide is used in the wet etching method.
  • a second metal film is deposited on the back surface of the substrate 1S by, for example, a sputtering method.
  • the thickness of the second metal film is, for example, about 0.1 ⁇ m.
  • the second metal film and the substrate 1S are reacted by heat treatment at 800 to 1200 ° C. to form a back surface silicide layer BSL on the back surface side of the substrate 1S.
  • a back surface electrode BE drain electrode
  • the thickness of the back surface electrode BE is, for example, about 0.4 ⁇ m.
  • the interlayer insulating film IL is processed by a dry etching method using a resist pattern as a mask to form an opening reaching the gate electrode GE.
  • the third metal film is deposited on the interlayer insulating film IL including the inside of the opening (not shown) reaching GE.
  • the third metal film is formed of, for example, a laminated film of a titanium film (Ti film), a titanium nitride film (TiN film), and an aluminum film (Al film).
  • the thickness of the aluminum film is preferably, for example, 2.0 ⁇ m or more.
  • the third metal film is processed to be electrically connected to the source electrode SE electrically connected to a part of the n + -type source region SR via the metal silicide layer SL and to the gate electrode GE.
  • a gate electrode wiring (not shown) is formed.
  • external wirings are electrically connected to the gate electrode GE, the source electrode SE, and the back surface electrode BE (drain electrode), respectively.
  • the SiC power MIOSFET in the present embodiment can be manufactured. ⁇ Features of the manufacturing method in the embodiment>
  • the first feature of the manufacturing method according to the present embodiment is, for example, the surface of a non-doped polysilicon film not doped with n-type impurities constituting gate electrode GE by using a thermal oxidation method in FIG.
  • the point is to form an insulating film OXF made of a silicon oxide film.
  • the non-doped polysilicon film since the non-doped polysilicon film is used, the n-type impurity is not introduced into the inside of the insulating film OXF formed by the thermal oxidation method.
  • the polysilicon film PF when forming the polysilicon film PF over the gate insulating film GOX, it is also conceivable to form the polysilicon film PF into which an n-type impurity is introduced.
  • the n-type impurity is already introduced into the gate electrode GE shown in FIG. 16 at this high impurity concentration. Therefore, the n-type impurity can be introduced into the gate electrode GE at a high concentration of impurity concentration without adding a process of introducing the n-type impurity into the gate electrode GE anew. The resistance of the electrode GE can be reduced.
  • the n-type impurity introduced into the gate electrode GE is diffused to the inside of the insulating film OXF by the high temperature heat treatment performed when forming the insulating film OXF on the side wall of the gate electrode GE. Resulting in. As a result, a high concentration n-type impurity is introduced into the inside of the insulating film OXF, which causes an increase in the leakage current at the end of the gate electrode GE.
  • the non-doped polysilicon film PF in which the n-type impurity is not introduced is formed instead of the polysilicon film PF in which the n-type impurity is previously introduced.
  • the insulating film OXF made of a silicon oxide film is formed on the surface of the non-doped polysilicon film PF by heat treatment at a high temperature by a thermal oxidation method.
  • the n-type impurity is diffused from the polysilicon film PF by the subsequent high temperature heat treatment to form the insulating film OXF. It can be effectively suppressed that the n-type impurity is introduced to the inside. As a result, in the present embodiment, it is possible to prevent the high concentration of the n-type impurity from being mixed into the insulating film OXF which causes an increase in the leak current at the end portion of the gate electrode GE. However, in this case, since the n-type impurity is not introduced into the gate electrode GE, the resistance of the gate electrode GE becomes high resistance as it is.
  • an n-type impurity is introduced into the gate electrode GE at a high concentration of impurities in an ion implantation step different from the step of forming the polysilicon film.
  • an n-type impurity is introduced into the entire gate electrode GE, the heat treatment for activating the subsequent n-type impurity from the gate electrode GE to the inside of the insulating film OXF formed on the side wall of the gate electrode GE.
  • the n-type impurity is easily diffused, which causes the n-type impurity to be mixed into the insulating film OXF at a high concentration of impurity concentration.
  • a device for suppressing the mixing of the n-type impurity into the inside of the insulating film OXF is performed, and this device point is a second feature point in the manufacturing method in the present embodiment. .
  • the 2nd feature point on the manufacturing method in this Embodiment will be demonstrated.
  • the second feature of the manufacturing method according to the present embodiment covers the end of the gate electrode GE and the insulating film OXF formed on the side wall of the gate electrode GE, and the gate electrode
  • n-type impurity is introduced into the inside of the gate electrode GE by ion implantation using a mask (resist pattern PR) having an opening OP for opening a partial region of the insulating film OXF formed on the upper part of GE. is there.
  • a mask resist pattern PR
  • the ion implantation step is performed since the portion of the gate electrode GE into which the n-type impurity is introduced is separated from the insulating film OXF formed on the side wall of the gate electrode GE.
  • the introduction of n-type impurities into the inside of the insulating film OXF can be suppressed. Then, since the portion of the gate electrode GE into which the n-type impurity is introduced is separated from the insulating film OXF formed on the side wall of the gate electrode GE, the n-type impurity to be performed after the ion implantation step is activated. Even if diffusion of n-type impurities occurs due to heat treatment for the conversion, mixing of n-type impurities at a high impurity concentration into the insulating film OXF formed on the side wall of the gate electrode GE is suppressed.
  • the n-type impurity concentration in the gate electrode GE is the impurity concentration of the n-type impurity introduced into the insulating film OXF formed on the side wall of the gate electrode GE. It can be made 1/100 or less of the maximum impurity concentration of impurities. As a result, according to the second feature point of the manufacturing method in the present embodiment, the n-type impurity can be introduced into the gate electrode GE with an impurity concentration sufficient to realize the reduction of the resistance of the gate electrode GE.
  • the insulating film OXF which covers the end of the gate electrode GE and the insulating film OXF formed on the side wall of the gate electrode GE and which is formed on the gate electrode GE
  • resist pattern PR as a mask which has opening OP which opens a partial area of film OXF
  • the technical idea in the above embodiment is not limited to this, and covers, for example, the end portion of the gate electrode GE and the insulating film OXF formed on the side wall of the gate electrode GE as shown in FIG.
  • a hard mask HM made of a silicon oxide film may be used as a mask having an opening OP that opens a partial region of the upper surface of the gate electrode GE.
  • the insulating film OXF exposed from the opening OP is formed of the same silicon oxide film as the hard mask HM, as shown in FIG. 22, when the opening OP is formed in the hard mask HM, the opening The insulating film OXF exposed from the bottom of the OP is also removed. ⁇ Modification 2>
  • the technical idea in the above embodiment is not limited to this, and for example, as shown in FIG. 23, after forming the hard mask HM having the opening OP, the gate electrode GE exposed from the hard mask HM An n-type impurity may be diffused from the BPSG film into the inside of the gate electrode by bringing a PSG film, which is a film containing pure n-type impurities, into contact and then performing heat treatment, for example.
  • the heat treatment in this case is at a lower temperature than the activation annealing performed after ion implantation. Therefore, it is useful in that diffusion of phosphorus (P) to the insulating film OXF formed on the side wall of the gate electrode GE can be suppressed.
  • the non-doped polysilicon film PF to which the n-type impurity is not introduced is processed to form the gate electrode GE
  • the non-doped polysilicon film PF is formed.
  • the insulating film OXF is formed on the surface of the gate electrode GE made of
  • the technical idea in the above embodiment is not limited thereto.
  • the gate is formed after forming the gate electrode GE by processing the polysilicon film PF in which the n-type impurity is introduced at a low impurity concentration.
  • the insulating film OXF may be formed on the surface of the electrode GE.
  • the insulating film OXF is lower than the case where the non-doped polysilicon film PF is used, but compared to the case where the polysilicon film PF in which the n-type impurity is introduced at a high impurity concentration is used. It is possible to suppress the mixing of n-type impurities into it.
  • the formation rate of the insulating film OXF on the surface of the gate electrode GE by the thermal oxidation method is reduced, while an n-type impurity is introduced at a low impurity concentration.
  • the formation rate of the insulating film OXF on the surface of the gate electrode GE by the thermal oxidation method can be increased.
  • the corner portion of the gate electrode GE may be configured to have a round shape. Thereby, electric field concentration at the end of the gate electrode GE can be alleviated.
  • the impurity concentration of the n-type impurity introduced into the insulating film OXF formed on the sidewall of the gate electrode GE is the same as the maximum impurity concentration of the n-type impurity contained in the gate electrode GE.
  • An increase in leakage current at the end portion of the gate electrode GE can be suppressed by the synergetic effect of the configuration of 1/100 or less and the configuration of forming the corner portion of the gate electrode GE in a round shape.
  • phosphorus (P) is taken as an example of the n-type impurity to explain the technical idea in the embodiment.
  • the technical idea in the embodiment is not limited to this, and n It can be widely applied to mold impurities.
  • arsenic (As) can be mentioned as n-type impurities other than phosphorus.
  • arsenic is heavier than phosphorus and is difficult to diffuse, applying the technical idea in the above embodiment further reduces the impurity concentration of the n-type impurity (arsenic) mixed in the insulating film OXF. Can.
  • the embodiment has described the embodiment in which the n-type impurity represented by phosphorus is introduced to the gate electrode GE of the SiC power MOSFET, the technical idea in the embodiment is not limited thereto, and the SiC power MOSFET The present invention can also be applied to a mode in which a p-type impurity represented by boron (B) is introduced into the gate electrode GE.
  • B boron
  • the threshold voltage can be increased by introducing a p-type impurity into the gate electrode GE. This means that it is possible to suppress "false points". This is because, for example, as can be seen also from FIG. 5, the “capacitance” occurs when the gate voltage V 2 of the SiC power transistor to be turned off exceeds the threshold voltage due to capacitive coupling. If it is high, the gate voltage V2 of the SiC power transistor to be turned off is unlikely to exceed the threshold voltage.
  • the p-type impurity mixed in the insulating film OXF formed on the side wall of the gate electrode GE may cause an increase in the leakage current at the end of the gate electrode GE.
  • the first mechanism described in the section “ ⁇ New Findings Found by the Inventor >>” is as follows. That is, the level of the p-type impurity (acceptor level) is at a position where the energy level is lower than the level of the n-type impurity (donor level). This means that, in the band gap of the insulating film OXF, a trap level caused by the p-type impurity is formed at a position lower in energy level than the trap level caused by the n-type impurity.
  • the first mechanism described in the section of “ ⁇ New information found by the present inventor >>” is as follows. That is, since the n-type impurity has a positive charge and electrons are stored by applying a negative voltage to the gate electrode GE, for example, the interface between the gate electrode GE and the insulating film OXF is, for example, Similar to the gate insulating film shown in FIG. 11, a sharp potential barrier is generated. With such a steep potential barrier, for example, as shown in FIG. 11, the width "L2" of the potential barrier becomes smaller, so that the FN tunneling current becomes easier to flow, and this FN tunneling current becomes a leakage current. .
  • the p-type impurity since the p-type impurity has a negative charge, the inclination of the potential barrier formed at the interface between the gate electrode GE and the insulating film OXF is rather gentle. And, since electrons are not accumulated by applying a positive voltage to the gate electrode GE, it becomes difficult for the FN tunnel current to flow.
  • the increase of the leak current due to the first mechanism and the second mechanism described above is a configuration in which the p-type impurity is mixed in the insulating film OXF rather than the configuration in which the n-type impurity is mixed in the insulating film OXF.
  • the impurity concentration of the p-type impurity contained in the insulating film OXF is the maximum impurity concentration of the p-type impurity contained in the gate electrode GE. Even in the configuration of not more than 1/10 of the above, the increase of the leak current at the end of the gate electrode GE can be sufficiently suppressed.
  • the power transistor is A gate insulating film formed on the epitaxial layer;
  • the semiconductor device, wherein the first insulating film contains a p-type impurity at an impurity concentration of 1/10 or less of the maximum impurity concentration of the p-type impurity contained in the gate electrode.

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Abstract

La présente invention réduit un courant de fuite dans un transistor de puissance qui utilise du carbure de silicium, d'où une amélioration des performances d'un dispositif à semi-conducteur comportant le transistor de puissance. Le dispositif à semi-conducteur comprend un transistor de puissance formé sur une couche épitaxiale (EPI) contenant du carbure de silicium comme constituant principal. Ce transistor de puissance comprend un film isolant (OXF) formé sur une paroi latérale d'une électrode grille (GE), et un film d'isolation intercouche (IL) formé de manière à recouvrir l'électrode grille (GE) et le film isolant (OXF). La densité du film isolant (OXF) est supérieure à la densité du film d'isolation intercouche (IL). De plus, le film d'isolation (OXF) contient des impuretés conductrices à une concentration d'impuretés inférieure ou égale à 1/100 de la concentration d'impuretés maximale des impuretés conductrices contenues dans l'électrode grille (GE).
PCT/JP2018/015795 2017-06-27 2018-04-17 Dispositif à semi-conducteur et son procédé de production WO2019003589A1 (fr)

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JP7436950B2 (ja) * 2019-09-20 2024-02-22 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法

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JPH0766421A (ja) * 1993-08-31 1995-03-10 Ryoden Semiconductor Syst Eng Kk 薄膜トランジスタとその製造方法
JP2006100679A (ja) * 2004-09-30 2006-04-13 Ricoh Co Ltd 半導体装置
JP2014175471A (ja) * 2013-03-08 2014-09-22 Sumitomo Electric Ind Ltd 炭化珪素半導体装置およびその製造方法
JP2015177073A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置およびその製造方法

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JPH0766421A (ja) * 1993-08-31 1995-03-10 Ryoden Semiconductor Syst Eng Kk 薄膜トランジスタとその製造方法
JP2006100679A (ja) * 2004-09-30 2006-04-13 Ricoh Co Ltd 半導体装置
JP2014175471A (ja) * 2013-03-08 2014-09-22 Sumitomo Electric Ind Ltd 炭化珪素半導体装置およびその製造方法
JP2015177073A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594030A (zh) * 2021-07-27 2021-11-02 中国科学院微电子研究所 一种场效应晶体管器件的栅极结构制作方法及场效应晶体管器件

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