WO2018233272A1 - 孔连接层的制作方法、线路板的制作方法及线路板 - Google Patents

孔连接层的制作方法、线路板的制作方法及线路板 Download PDF

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Publication number
WO2018233272A1
WO2018233272A1 PCT/CN2017/120094 CN2017120094W WO2018233272A1 WO 2018233272 A1 WO2018233272 A1 WO 2018233272A1 CN 2017120094 W CN2017120094 W CN 2017120094W WO 2018233272 A1 WO2018233272 A1 WO 2018233272A1
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WIPO (PCT)
Prior art keywords
sub
layer
board
boards
dielectric layer
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Application number
PCT/CN2017/120094
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English (en)
French (fr)
Inventor
廉泽阳
吴森
李艳国
陈蓓
Original Assignee
广州兴森快捷电路科技有限公司
深圳市兴森快捷电路科技股份有限公司
宜兴硅谷电子科技有限公司
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Application filed by 广州兴森快捷电路科技有限公司, 深圳市兴森快捷电路科技股份有限公司, 宜兴硅谷电子科技有限公司 filed Critical 广州兴森快捷电路科技有限公司
Priority to US16/642,186 priority Critical patent/US11083091B2/en
Publication of WO2018233272A1 publication Critical patent/WO2018233272A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047—Drilling of holes

Definitions

  • the invention relates to the technical field of printed circuit boards, in particular to a method for manufacturing a hole connecting layer, a method for manufacturing the circuit board and a circuit board.
  • the Via bond process is a Z-direction inter-layer random interconnect technique.
  • the upper sub-board is bonded and pressed through the intermediate receiving layer to realize the high-level number, and the interconnection is electrically connected by a conductive medium.
  • the advantage of this technology is that it is simple to make and can be used to make super high-rise boards.
  • the conventional Via bond process still has defects: when the daughter board is fabricated on a POFV (plated on filled via) process, the copper thickness and uniformity of the outer layer of the daughter board are difficult to control, and the average control is in the range of 30 ⁇ m to 40 ⁇ m. , the range is ⁇ 5 ⁇ m. Therefore, the prepreg flow between the daughter board and the daughter board needs to meet the double-sided filling requirements. At the same time, in order to prevent the conductive medium from being squeezed and dissipated, the prepreg of the intermediate receiving layer generally needs to use a low fluidity. Therefore, the traditional Via bond technology has contradictory requirements for the fluidity of the prepreg. How to ensure that the conductive medium is not squeezed and dispersed while satisfying the filling requirements is an urgent problem to be solved.
  • the present invention overcomes the defects of the prior art, and provides a method for manufacturing a hole connecting layer, a method for manufacturing a circuit board, and a circuit board, which can meet the requirement of double-sided filling and improve two adjacent sub-boards.
  • the bonding strength can control the fluidity of the hole connecting layer, prevent the glue from being excessively large, break the hole shape of the receiving hole, and ensure that the conductive medium is not squeezed and scattered.
  • a method for manufacturing a hole connecting layer wherein at least two sub-boards stacked one above another, the hole connecting layer is disposed between two adjacent sub-boards, comprising the steps of: facing one of the sub-boards adjacent to each other One side of one of the daughter boards is attached with a first insulating medium layer for press-bonding; the first insulating medium layer on the daughter board is press-bonded; the first insulating medium after press-cure curing a second insulating medium layer for press-bonding is attached to the layer, and a side of the second insulating medium layer facing away from the first insulating medium layer is used for bonding with another adjacent sub-board; a first receiving hole is formed in the first insulating medium layer, and a second receiving hole is formed in the second insulating medium layer, wherein the first receiving hole and the second receiving hole are disposed opposite to each other; The hole and the second receiving hole are filled with a conductive medium to complete the fabrication of the hole connecting layer, wherein each of the daughter boards is electrically connected to the
  • the first insulating medium layer is attached to one of the daughter boards, and the filling material of the daughter board is satisfied by the first insulating medium layer. Then, the first insulating medium is laminated and cured, and a second insulating medium layer is attached to the first insulating dielectric layer after press-bonding. The second insulating dielectric layer is used to press-fit another sub-board.
  • one of the sub-boards is filled by the first insulating medium layer, and the second sub-board is filled by the second insulating medium layer, thereby ensuring sufficient filling during pressing. the amount.
  • the first insulating medium layer has been pressed and cured, and is not melt-softened and softened during the subsequent pressing, and basically no flow occurs, so
  • the fluidity of the hole connecting layer according to the embodiment of the present invention is basically derived from a single second insulating medium layer, and the hole connecting layer can be controlled to have a small fluidity.
  • the method for fabricating the hole connecting layer of the present invention fully satisfies the requirement of double-sided filling, improves the bonding strength between adjacent sub-plates, and controls the hole connecting layer to have a small flow. To prevent the glue from being too large, destroy the hole shape of the receiving hole, and ensure that the conductive medium is not squeezed and dissipated.
  • the aperture of the first receiving hole is smaller than or equal to the aperture of the conductive through hole of two adjacent sub-boards; the aperture of the second receiving hole is less than or equal to the conductivity of two adjacent sub-boards The aperture of the through hole.
  • the first receiving hole and the second receiving hole of the smaller aperture are provided to reduce the impedance during signal transmission, and to reduce fluctuations and losses during signal transmission.
  • the conductive medium is a conductive resin
  • the conductive resin contains a metal alloy containing particles of copper, tin, antimony, etc., and the metal tin and antimony particles are melted by heat to melt the metal copper during lamination heating.
  • the particles and the pads on the daughter board are soldered together to achieve conduction and fixed connection of the two adjacent sub-boards.
  • the first insulating dielectric layer is a thermosetting first prepreg, thereby ensuring that after the laminate is cured, the first insulating dielectric layer is not melted by the factor plate and is again melted by heat, thereby achieving control hole connection. The effect of the fluidity of the layer.
  • the second insulating dielectric layer comprises a second prepreg and a protective layer on the second prepreg.
  • the method further comprises the step of: removing the protective film. Providing a protective film prevents damage to the dielectric layer during subsequent fabrication of the receiving holes.
  • the hole connection layer has a flow distance of 25 mil to 200 mil, which ensures that the conductive medium is not squeezed and scattered, thereby ensuring the safety and reliability of the circuit board.
  • the technical solution further provides a method for manufacturing a circuit board, comprising the steps of: preparing a daughter board, the number of the daughter boards is at least two, and at least two of the daughter boards are sequentially arranged from top to bottom, wherein One side of each of the fabricated sub-boards facing the adjacent one of the sub-boards is provided with a pad layer, and the pad layer is provided in one-to-one correspondence with the conductive via holes on the sub-boards a pad; in the two adjacent daughter boards, the hole connection layer is formed by the above-described method of manufacturing the hole connection layer; all of the daughter boards are laminated to form a mother board.
  • a pad layer is disposed on each of the sub-boards to be bonded, and each layer of each sub-board extends through the conductive vias to the pads on the pad layer, and then through the via connection layer.
  • the conductive medium is electrically connected to the layers of the other sub-board. During the pressing process, the hole connecting layer bonds the two sub-plates adjacent to each other.
  • the pad layer Since the upper and lower sides of the hole connection layer are butted to the pad layer of the sub-board, the pad layer only has a pad (wireless path), and the rest are copper-free areas, thereby reducing the residual copper ratio, thereby reducing the difficulty of filling, further It is ensured that the double-sided filling is sufficient, the bonding strength between the sub-boards is enhanced, and the delamination caused by the insufficient bonding of the sub-board wiring layer directly to the insulating dielectric layer is avoided.
  • the present invention also effectively prevents the pad from being directly added to the original design circuit layer, thereby avoiding the alignment space between the conductive medium on one of the daughter boards and the pad on the other of the daughter boards during the docking process of the daughter board. Insufficient is easy to cause short circuit of the circuit board.
  • the daughter boards are sequentially disposed from top to bottom to form a daughter board group, the daughter board group includes two end daughter boards at both ends, and the step of fabricating the daughter board includes a production end
  • the step of manufacturing the tip sub-board includes the steps of: preparing two copper foils, a plurality of copper clad laminates, and a plurality of third prepreg, each of the two opposite sides of the copper clad plate being provided with a circuit layer; Forming a pre-pressing plate in the order of copper foil, a plurality of copper clad laminates, and copper foil, wherein at least one of the third prepreg is disposed between two adjacent copper clad laminates, and two of the copper foils are At least one of the third prepreg is also disposed between the copper clad plates; the pre-pressing plate is pressed to form a plywood; a conductive through hole is formed on the ply plate; and a line is etched on one of the copper foils Forming a surface wiring
  • the number of copper foil layers (including the number of circuit layers and the number of pad layers) on each of the terminal sub-boards is even, so that the laminated structure of the sub-board is symmetrical to avoid warping.
  • the number of the daughter boards is at least three
  • the daughter board group further includes an intermediate daughter board between the two end daughter boards
  • the step of fabricating the daughter board further includes making a middle child a step of forming a middle sub-board, comprising the steps of: preparing two copper foils, a plurality of copper clad laminates, and a plurality of third prepreg, each of the opposite sides of the copper clad plate being provided with a circuit layer; a copper foil, a plurality of copper clad laminates, and a copper foil are sequentially laminated to form a pre-pressing plate, wherein at least one of the third prepreg is disposed between two adjacent copper clad plates, and the two copper foils are At least one of the third prepreg is also disposed between the copper clad laminates; the pre-pressing plate is pressed to form a plywood; the conductive through holes are formed on the plywood; and the solder is etched on the two copper foils Forming the pad layer to complete the fabrication of
  • the number of copper foil layers on each of the intermediate sub-boards is even, so that the laminated structure of the sub-boards is symmetrical to avoid warping.
  • the pad layer is disposed on both sides of the middle sub-board, so as to ensure the difficulty of filling the glue when docking with the two sub-boards on the upper and lower sides.
  • the technical solution further provides a circuit board, comprising a hole connection layer and at least two sub-boards, at least two of the sub-boards are sequentially stacked from top to bottom, and two adjacent sub-boards are disposed between a hole connecting layer, the hole connecting layer comprising a first insulating dielectric layer pre-pressed and cured on one of the sub-boards and a second insulating dielectric layer disposed on the first insulating dielectric layer, the second insulating layer
  • the dielectric layer is used for bonding to the adjacent one of the sub-boards during the press-forming process, the first insulating medium layer is provided with a first receiving hole, and the second insulating medium layer is provided with a second
  • the receiving hole is provided with a conductive medium in the first receiving hole and the second receiving hole, and one of the two adjacent sub-boards is electrically connected to the other sub-board through the conductive medium.
  • the circuit board of the embodiment of the invention comprises a novel hole connection layer, so that it can meet the requirement of double-sided glue filling, improve the bonding strength of two adjacent sub-boards, and control the fluidity of the hole connection layer to prevent The glue is too large, destroying the hole shape of the receiving hole, and ensuring that the conductive medium is not squeezed and scattered.
  • FIG. 1 is a flow chart of a method for fabricating a hole connection layer according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method for manufacturing a circuit board according to an embodiment of the present invention
  • FIG. 3 is a flowchart of fabricating a daughter board according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of fabricating a header sub-board according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of manufacturing a middle sub-board according to an embodiment of the present invention.
  • FIG. 6 is a schematic exploded view of a circuit board according to an embodiment of the invention.
  • FIG. 7 is a schematic structural diagram of a circuit board according to an embodiment of the present invention.
  • FIG. 8 is a schematic exploded view of a circuit board according to another embodiment of the present invention.
  • the mother board is generally formed by laminating at least two sub-boards 100 stacked in this order, and a via bond layer is disposed between the adjacent two sub-boards 100.
  • the method for manufacturing the hole connecting layer of the present invention comprises the following steps:
  • a first insulating dielectric layer 200 for press-bonding is attached to one side of one of the sub-boards 100 facing the adjacent other sub-board 100.
  • the second insulating dielectric layer 300 includes a second prepreg and a protective layer on the second prepreg, and the protective film is disposed to prevent damage to the insulating dielectric layer when the receiving hole is subsequently formed.
  • a first receiving hole is formed in the first insulating dielectric layer 200, and a second receiving hole is formed in the second insulating dielectric layer 300.
  • the first receiving hole and the second receiving hole are disposed opposite to each other.
  • the first receiving hole is drilled in the first insulating medium layer 200.
  • the second receiving hole is drilled in the second insulating medium layer 300 from the top to the bottom by laser drilling
  • the first receiving hole is drilled in the first insulating medium layer 200.
  • the conductive vias 130 on each of the daughter boards 100 are electrically connected to the conductive vias 130 of the adjacent other daughter board 100 through the conductive medium 400.
  • the first insulating dielectric layer 200 is attached to one of the sub-boards 100, and the filling requirement of the sub-board 100 is satisfied by the first insulating dielectric layer 200. Then, the first insulating dielectric layer 200 is then press-bonded and cured, and the second insulating dielectric layer 300 is attached to the first insulating dielectric layer 200 after the press-bonding. The second insulating dielectric layer 300 is used to press-fit another sub-board 100.
  • one of the sub-boards 100 is filled by the first insulating dielectric layer 200, and the second sub-board 100 is filled by the second insulating dielectric layer 300, thereby ensuring that there is Ample amount of glue. Even in the case where the copper thickness on the sub-board 100 has a large difference, the filling requirement can be satisfied, and the bonding strength between the adjacent two sub-boards 100 can be improved.
  • the first insulating medium layer 200 has been pressed and cured, and will not be soft-melted and softened during the subsequent pressing, and substantially no flow occurs.
  • the fluidity of the hole connecting layer according to the embodiment of the present invention is basically derived from the single second insulating dielectric layer 300, and the hole connecting layer can be controlled to have a small fluidity.
  • the manufacturing method of the hole connecting layer of the present invention fully satisfies the requirement of double-sided filling, improves the bonding strength between adjacent sub-boards 100, and can also control the hole connecting layer to have a smaller
  • the fluidity prevents the glue from being too large, destroys the hole shape of the receiving hole, and ensures that the conductive medium 400 is not squeezed and scattered.
  • the first insulating dielectric layer 200 is a thermosetting first prepreg, thereby ensuring that the first insulating dielectric layer 200 is not melted again by the subsequent lamination of the sub-board 100 after the laminate is cured.
  • the effect of controlling the fluidity of the connection layer of the pores is achieved.
  • the flow distance of the hole connection layer formed by the embodiment of the invention is controlled to be 25 mil to 200 mil, and the flow distance can ensure that the conductive medium 400 is not squeezed and scattered, thereby ensuring the safety and reliability of the circuit board.
  • the aperture of the first receiving hole is smaller than or equal to the aperture of the conductive through hole 130 of the two adjacent sub-boards 100; the aperture of the second receiving hole is smaller than or equal to the conductive through hole of the adjacent two sub-boards 100 The aperture of 130.
  • the first receiving hole and the second receiving hole of the smaller aperture are provided to reduce the impedance during signal transmission, and to reduce fluctuations and losses during signal transmission.
  • the conductive medium 400 is a conductive resin
  • the conductive resin contains a metal alloy containing particles of copper, tin, antimony or the like.
  • the metal tin and antimony particles are melted by heat to the metal.
  • the copper particles and the pads on the sub-board 100 are soldered together to achieve conduction and fixed connection of the upper and lower adjacent sub-boards 100.
  • the present invention also provides a method for manufacturing a circuit board, comprising the following steps:
  • each of the sub-boards 100 is provided with a pad layer on one side of the adjacent other sub-board 100 (padslayer1, padslayer2, padslayer3, padslayer4, and padslayer5 shown in FIG. 6 and FIG. 8), and each of the sub-boards 100 is Conductive through holes 130 are provided, and the conductive through holes 130 on the adjacent two sub-boards 100 are in one-to-one correspondence and are opposed to each other.
  • the pad layer is provided with pads that are in one-to-one correspondence with the conductive vias 130 on the sub-board 100 in which they are located.
  • the daughter board group includes two end daughter boards 100 at both ends, as shown in FIG. 6; when the number of the daughter boards 100 is more than two, the daughter board group
  • at least one intermediate sub-board 100 between the two end sub-boards 100 is included, as shown in FIG.
  • the pad layer is only located on one of the faces of the daughter board 100, and the other side of the daughter board 100 is the surface circuit layer (L1, L18, and attached as shown in FIG. 6). L1, L34) shown in Fig. 8.
  • the daughter board 100 is the intermediate daughter board 100, its pad layer is located on the upper and lower opposite sides of the daughter board 100.
  • circuit layer may be used instead of the above-mentioned pad layer according to actual needs.
  • the hole connection layer is formed by the method of step S210 to step S250.
  • the first insulating dielectric layer 200 covers the pad layer of the sub-board 100.
  • all of the daughter boards 100 are laminated to form a mother board as shown in FIG.
  • the conductive vias 130 on each of the daughter boards 100 are electrically connected to the conductive vias 130 of the adjacent other daughter board 100 through the conductive medium 400.
  • a pad layer is disposed on each of the sub-boards 100 to be bonded, and each layer of the circuit on each of the sub-boards 100 extends through the conductive vias 130 to the pads.
  • the pads on the layers are then electrically conducted through the conductive medium 400 on the insulating isolation layer to the various layers on the other daughter board 100.
  • the insulating dielectric layer 200 bonds the two sub-boards 100 adjacent to each other.
  • the pad layer Since the upper and lower sides of the insulating dielectric layer 200 are butted against the pad layer of the sub-board 100, the pad layer has only pads (wireless paths), and the rest are copper-free regions, thereby effectively reducing the residual copper ratio and thereby reducing the filling.
  • the present invention also effectively prevents the pad from being directly added to the original design circuit layer, thereby avoiding the interconnection between the conductive medium 400 on one of the sub-boards 100 and the pad on the other sub-board 100 during the docking process of the sub-board 100.
  • the aligning space refers to the space that can be displaced between adjacent two sub-boards 100 in the case of ensuring normal conduction
  • the short circuit of the circuit board is easily caused. Because there is a line on the original design circuit layer, the misalignment of the sub-board 100 is easy to conduct with the line, causing a short circuit.
  • step S100 when the total number of all the sub-boards 100 is two, step S100 includes only step S110 of fabricating the header sub-board 100. As shown in FIG. 4 and FIG. 6, step S110 specifically includes the following steps:
  • a pre-pressing plate is formed by sequentially stacking copper foil, a plurality of copper clad plates 110, and copper foils from top to bottom, wherein at least one of the third prepregs 120 is disposed between two adjacent copper clad laminates 110, At least one of the third prepreg 120 is also disposed between the two copper foils and the copper clad laminate 110.
  • the number of copper foil layers (including the circuit layers (L1 - L18) and the pad layers) on the terminal sub-board 100 in the embodiment of the present invention is an even number, so that the laminated structure of the sub-board 100 is symmetrical to avoid warping.
  • the phenomenon of music is an even number, so that the laminated structure of the sub-board 100 is symmetrical to avoid warping.
  • step S100 when the total number of all the sub-boards 100 is more than two, step S100 includes not only step S110 but also step S120 of making the intermediate sub-board 100. As shown in FIG. 5 and FIG. 8 , step S120 specifically includes the following steps:
  • a pre-pressing plate is formed by sequentially stacking copper foil, a plurality of copper clad plates 110, and copper foil from top to bottom, wherein at least one of the third prepreg 120 is disposed between two adjacent copper clad laminates 110, At least one of the third prepreg 120 is also disposed between the two copper foils and the copper clad laminate 110.
  • the number of copper foil layers (including the circuit layer and the pad layer) on the intermediate sub-board 100 in the embodiment of the present invention is also an even number, so that the laminated structure of the sub-board 100 is symmetrical to avoid warping.
  • the pad layer is disposed on both sides of the intermediate sub-board 100, thereby achieving docking with the sub-boards 100 on the upper and lower sides.
  • step S110 and step S120 are not limited by any person skilled in the art according to actual needs.
  • a step may be further included: symmetrically splitting the target circuit board according to the drill tape and the number of layers of the target order, thereby determining the number of the daughter boards 100.
  • This step can be used to determine the total number of daughter boards 100 to be pressed, so that the design of the daughter board 100 is simpler and only needs to be symmetrically split according to the original design of the customer.
  • the present invention further provides a circuit board manufactured by the above manufacturing method, comprising a hole connecting layer and at least two sub-boards 100, and at least two of the sub-boards 100 are sequentially stacked from top to bottom.
  • the hole connection layer is disposed between two adjacent sub-boards 100.
  • the hole connection layer includes a first insulating dielectric layer 200 pre-compressed and cured on one of the sub-boards 100 and a second insulating dielectric layer 300 disposed on the first insulating dielectric layer 200.
  • the second insulating dielectric layer 300 is used to bond with another adjacent sub-board 100 during the press-forming type.
  • the first insulating dielectric layer 200 is provided with a first receiving hole
  • the second insulating dielectric layer 300 is provided with a second receiving hole
  • the first receiving hole and the second receiving hole are respectively provided with a conductive medium 400.
  • one of the sub-boards 100 is electrically connected to the other sub-board 100 through the conductive medium 400.
  • the circuit board of the embodiment of the invention comprises a novel hole connection layer, so that it can meet the requirements of double-sided glue filling, improve the bonding strength of two adjacent sub-boards 100, and control the fluidity of the hole connection layer. Prevent the flow glue from being too large, destroy the hole type of the receiving hole, and ensure that the conductive medium is not squeezed and dissipated.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种孔连接层的制作方法、线路板的制作方法及线路板。该孔连接层的制作方法包括以下步骤：在一个子板贴附用于压合填胶的第一绝缘介质层（200）；压合固化位于子板上的第一绝缘介质层（200）；在压合固化后的第一绝缘介质层（200）上贴附用于压合填胶的第二绝缘介质层（300）；在第一绝缘介质层（200）制作第一承接孔、并在第二绝缘介质层（300）制作第二承接孔，第一承接孔和第二承接孔上下相对设置；在第一承接孔和第二承接孔内均填塞导电介质，完成孔连接层的制作。该方法形既可满足双面填胶的需求，提高相邻的两个子板的粘合强度，又可控制孔连接层的流动度，防止流胶过大，破坏承接孔的孔型，保证导电介质不被挤压和冲散。

Description

孔连接层的制作方法、线路板的制作方法及线路板 技术领域
本发明涉及印刷线路板技术领域，尤其是涉及一种孔连接层的制作方法、线路板的制作方法及线路板。
背景技术
随着通信行业的发展和建设，高层数背板已经逐渐应用开来。而随着未来各种联网消费产品的增加，必将对信息传递提出更大容量、更高速度的要求。未来的5G网络建设，必然需要可以承载更多子板、信号损耗更小、可靠性更高的背板来支撑。实现超高密度、更高层数的背板的制造技术将是未来印制电路行业的一个发展方向。
Via bond(孔连接)工艺是一种Z向层间任意互连技术。其是将先制作好的子板通过中间承接层粘接压合起来实现高层数，互连采用导电介质电连接。这种技术的好处是制作方法简单，可以实现超高层数电路板的制作。
但是，传统的Via bond工艺仍然存在缺陷：子板在制作POFV(plated on filled via，孔上电镀)工艺时，子板外层铜厚和均匀性难以控制，一般控制在均值在30μm～40μm区间，极差±5μm。，因此，子板与子板之间的半固化片流动度需满足双面填胶需求。而同时，为了防止导电介质被挤压和冲散，中间承接层的半固化片一般需要使用低流动度。因此，传统的Via bond技术对于半固化片的流动度的需求存在矛盾的地方，如何在满足填胶需求的同时保证导电介质不被挤压和冲散，是一个亟待解决的问题。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种孔连接层的制作方法、线路板的制作方法及线路板，其既可满足双面填胶的需求，提高相邻的两个子板的粘合强度，又可控制孔连接层的流动度，防止流胶过大，破坏承接孔的孔 型，保证导电介质不被挤压和冲散。
其技术方案如下：
一种孔连接层的制作方法，在上下依次层叠的至少两个子板中，相邻的两个子板之间设有所述孔连接层，包括以下步骤：在其中一个子板面向相邻的另一个子板的一面贴附用于压合填胶的第一绝缘介质层；压合固化位于所述子板上的所述第一绝缘介质层；在压合固化后的所述第一绝缘介质层上贴附用于压合填胶的第二绝缘介质层，所述第二绝缘介质层背向所述第一绝缘介质层的一面用于与相邻的另一个子板粘接；在所述第一绝缘介质层制作第一承接孔、并在所述第二绝缘介质层制作第二承接孔，所述第一承接孔和所述第二承接孔上下相对设置；在所述第一承接孔和所述第二承接孔内均填塞导电介质，完成所述孔连接层的制作，其中，每个子板通过所述导电介质与相邻的另一个子板电连接。
本发明实施例所述的孔连接层的制作方法，其在其中一个子板上贴附第一绝缘介质层，通过第一绝缘介质层来满足该子板的填胶需求。并且，之后将第一绝缘介质层压合固化，并在压合固化后的第一绝缘介质层上贴附第二绝缘介质层。第二绝缘介质层用于对另一个子板进行压合填胶。综上可知，本发明实施例通过第一绝缘介质层对其中一个子板进行填胶，并通过第二绝缘介质层来对第二个子板进行填胶，进而保证压合时具有充足的填胶量。即便是子板上铜厚有较大极差的情况下也可满足填胶需求，提高相邻的两个子板之间的粘接强度。与此同时，在各子板压合形成母板的过程中，所述的第一绝缘介质层已经压合固化，在之后的压合过程中不会热熔软化，基本不会发生流动，因此本发明实施例所述的孔连接层的流动性基本来自于单张的第二绝缘介质层，可以控制孔连接层具有较小的流动度。综上可知，本发明所述孔连接层的制作方法充分地满足了双面填胶的需求，提高了相邻子板之间的粘接强度；同时也可控制孔连接层具有较小的流动度，防止流胶过大，破坏承接孔的孔型，保证导电介质不被挤压和冲散。
下面对上述技术方案作进一步的说明：
在其中一个实施例中，所述第一承接孔的孔径小于或等于相邻的两个子板的导电通孔的孔径；所述第二承接孔的孔径小于或等于相邻的两个子板的导电通孔的孔径。通过设置较小孔径的第一承接孔和第二承接孔来减小信号传输过程中的阻抗，减少信号传输时的波动与损耗。
在其中一个实施例中，所述导电介质为导电树脂，导电树脂中含有包含金属铜、锡、铋等颗粒的金属合金，在层压受热的过程中，金属锡和铋颗粒受热融化将金属铜颗粒以及子板上的焊盘等焊接在一起，从而实现上下相邻两个子板的导通及固定连接。
在其中一个实施例中，所述第一绝缘介质层为热固性的第一半固化片，从而保证第一绝缘介质层在层压固化之后，不会因子板层压而再次受热融化，进而达到控制孔连接层的流动度的效果。
在其中一个实施例中，所述在第一绝缘介质层上贴附第二绝缘介质层的步骤中，所述第二绝缘介质层包括第二半固化片和位于所述第二半固化片上的保护层，且所述在第一绝缘介质层制作第一承接孔、并在第二绝缘介质层制作第二承接孔的步骤之后，还包括步骤：去除所述保护膜。设置保护膜可以防止在后续制作承接孔时损坏绝缘介质层。
在其中一个实施例中，所述孔连接层的流动距离为25mil～200mil，该流动距离可以保证导电介质不被挤压和冲散，保证线路板的安全可靠性。
本技术方案还提供了一种线路板的制作方法，包括以下步骤：制作子板，所述子板的数量为至少两个，至少两个所述子板由上往下依次设置，其中，所制作的每个所述子板面向相邻的另一个所述子板的一面均设有焊盘层，所述焊盘层设有与所在的子板上的导电通孔一一对应且导通的焊盘；在相邻的两个所述子板中，采用上述的孔连接层的制作方法来制作孔连接层；将所有的所述子板层压，形成母板。
本发明实施例在每个子板的待黏合面上设置一个焊盘层，每个子板上的各层线路均经过导电通孔延伸至焊盘层上的焊盘，之后再经由孔连接层上的导电介质与另一个子板上的各层线路导通。在压合的过程中，孔连接层将上下相邻 的两个子板粘接。由于孔连接层的上下两侧是与子板的焊盘层对接，焊盘层仅有焊盘(无线路)，其余均为无铜区，从而降低残铜率，进而降低填胶难度，进一步保证双面填胶充分，增强子板之间的粘接强度，避免发生子板线路层直接与绝缘介质层粘接因填胶不足而引发的分层现象。此外，本发明也有效地避免了将焊盘直接增设在原设计线路层，从而避免了在子板对接过程中，其中一子板上导电介质与另一子板上焊盘之间因对位空间不足易引发线路板短路现象。
在其中一个实施例中，至少两个所述子板由上往下依次设置形成子板组，所述子板组包括位于两端的两个端头子板，所述制作子板的步骤包括制作端头子板的步骤，所述制作端头子板的步骤包括以下步骤：准备两片铜箔、若干个覆铜板和若干个第三半固化片，每个所述覆铜板上下相对的两面均设有线路层；按照铜箔、若干个覆铜板、铜箔的顺序依次层叠形成预压板，其中，相邻的两个所述覆铜板之间设置至少一个所述第三半固化片，且两片所述铜箔与所述覆铜板之间也均设置至少一个所述第三半固化片；将所述预压板压合，形成压合板；在所述压合板上制作导电通孔；在其中一片所述铜箔上蚀刻出线路、形成表面线路层，在另一片所述铜箔上蚀刻出焊盘、形成所述焊盘层，完成所述端头子板的制作。
由上可知，每个端头子板上的铜箔层数(包括线路层的数量和焊盘层的数量)均为偶数，从而使得子板层压结构对称，避免发生翘曲现象。
在其中一个实施例中，所述子板的数量为至少三个，所述子板组还包括位于两个端头子板之间的中间子板，所述制作子板的步骤还包括制作中间子板的步骤，所述制作中间子板的步骤包括以下步骤：准备两片铜箔、若干个覆铜板和若干个第三半固化片，每个所述覆铜板上下相对的两面均设有线路层；按照铜箔、若干个覆铜板、铜箔的顺序依次层叠形成预压板，其中，相邻的两个所述覆铜板之间设置至少一个所述第三半固化片，且两片所述铜箔与所述覆铜板之间也均设置至少一个所述第三半固化片；将所述预压板压合，形成压合板；在所述压合板上制作导电通孔；在两片所述铜箔上均蚀刻出焊盘、形成所述焊盘层，完成所述中间子板的制作。
同理可知，每个中间子板上的铜箔层数均为偶数，从而使得子板层压结构对称，避免发生翘曲现象。同时，中间子板的双面均设置焊盘层，从而保证与上下两侧两个子板对接时均可降低填胶难度。
本技术方案还提供了一种线路板，包括孔连接层和至少两个子板，至少两个所述子板由上往下依次层叠设置，相邻的两个所述子板之间设有所述孔连接层，所述孔连接层包括预先压合固化于其中一个子板上的第一绝缘介质层和设于所述第一绝缘介质层上的第二绝缘介质层，所述第二绝缘介质层用于在压合成型的过程中与相邻的另一个所述子板粘接，所述第一绝缘介质层开设有第一承接孔，所述第二绝缘介质层上开设有第二承接孔，所述第一承接孔和所述第二承接孔内均设有导电介质，在相邻的两个子板中，其中一个子板通过所述导电介质与另一个子板电连接。
本发明实施例所述线路板包括新型的孔连接层，使得其既可满足双面填胶的需求，提高相邻的两个子板的粘合强度，又可控制孔连接层的流动度，防止流胶过大，破坏承接孔的孔型，保证导电介质不被挤压和冲散。
附图说明
图1为本发明实施例所述的孔连接层的制作方法的流程图；
图2为本发明实施例所述的线路板的制作方法的流程图；
图3为本发明实施例所述的制作子板的流程图；
图4为本发明实施例所述的制作端头子板的流程图；
图5为本发明实施例所述的制作中间子板的流程图；
图6为本发明一实施例所述的线路板的分解结构示意图；
图7为本发明一实施例所述的线路板的结构示意图；
图8为本发明另一实施例所述的线路板的分解结构示意图。
附图标记说明：
100、子板，110、覆铜板，120、第三半固化片，130、导电通孔，200、第一绝缘介质层，300、第二绝缘介质层，400、导电介质。
具体实施方式
为使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施方式，对本发明进行进一步的详细说明。应当理解的是，此处所描述的具体实施方式仅用以解释本发明，并不限定本发明的保护范围。
母板一般由上下依次层叠的至少两个子板100层压形成，相邻的两个子板100之间设有孔连接层(via bond层)。如图1和图6所示，本发明所述的孔连接层的制作方法，包括以下步骤：
S210，在相邻的两个子板100中，在其中一个子板100面向相邻的另一个子板100的一面贴附用于压合填胶的第一绝缘介质层200。
S220，压合固化位于所述子板100上的所述第一绝缘介质层200。
S230，在压合固化后的所述第一绝缘介质层200上贴附用于压合填胶的第二绝缘介质层300，所述第二绝缘介质层300背向所述第一绝缘介质层200的一面用于与相邻的另一个子板100粘接。
所述第二绝缘介质层300包括第二半固化片和位于所述第二半固化片上的保护层，设置保护膜可以防止在后续制作承接孔时损坏绝缘介质层。
S240，在所述第一绝缘介质层200制作第一承接孔，并在所述第二绝缘介质层300制作第二承接孔，所述第一承接孔和所述第二承接孔上下相对设置。
具体地，采用激光钻孔的方式由上往下地依次在所述第二绝缘介质层300上钻出第二承接孔后，再在所述第一绝缘介质层200钻出所述第一承接孔，保证钻孔精度和速度，有利于实现高密度的群孔加工。
S250，在所述第一承接孔和所述第二承接孔内均填塞导电介质400，并去除所述保护膜，完成所述孔连接层的制作。
其中，每个子板100上的导电通孔130通过所述导电介质400与相邻的另一个子板100的导电通孔130电连接。
本发明实施例所述的孔连接层的制作方法，其在其中一个子板100上贴附第一绝缘介质层200，通过第一绝缘介质层200来满足该子板100的填胶需求。 并且，之后将第一绝缘介质层200压合固化，并在压合固化后的第一绝缘介质层200上贴附第二绝缘介质层300。第二绝缘介质层300用于对另一个子板100进行压合填胶。综上可知，本发明实施例通过第一绝缘介质层200对其中一个子板100进行填胶，并通过第二绝缘介质层300来对第二个子板100进行填胶，进而保证压合时具有充足的填胶量。即便是子板100上铜厚有较大极差的情况下也可满足填胶需求，提高相邻的两个子板100之间的粘接强度。与此同时，在各子板100压合形成母板的过程中，所述的第一绝缘介质层200已经压合固化，在之后的压合过程中不会热熔软化，基本不会发生流动，因此本发明实施例所述的孔连接层的流动性基本来自于单张的第二绝缘介质层300，可以控制孔连接层具有较小的流动度。综上可知，本发明所述孔连接层的制作方法充分地满足了双面填胶的需求，提高了相邻子板100之间的粘接强度；同时也可控制孔连接层具有较小的流动度，防止流胶过大，破坏承接孔的孔型，保证导电介质400不被挤压和冲散。
在本实施例中，所述第一绝缘介质层200为热固性的第一半固化片，从而保证第一绝缘介质层200在层压固化之后，不会因后续子板100层压而再次受热融化，进而达到控制孔连接层的流动度的效果。本发明实施例所形成的所述孔连接层的流动距离控制为25mil～200mil，该流动距离可以保证导电介质400不被挤压和冲散，保证线路板的安全可靠性。
此外，所述第一承接孔的孔径小于或等于相邻的两个子板100的导电通孔130的孔径；所述第二承接孔的孔径小于或等于相邻的两个子板100的导电通孔130的孔径。通过设置较小孔径的第一承接孔和第二承接孔来减小信号传输过程中的阻抗，减少信号传输时的波动与损耗。
可选地，所述导电介质400为导电树脂，导电树脂中含有包含金属铜、锡、铋等颗粒的金属合金，在子板间层压受热的过程中，金属锡和铋颗粒受热融化将金属铜颗粒以及子板100上的焊盘等焊接在一起，从而实现上下相邻两个子板100的导通及固定连接。
如图2、图6至图8所示，本发明还提供了一种线路板的制作方法，包括以 下步骤：
S100，制作子板100，所述子板100的数量为至少两个，至少两个子板100由上往下依次设置。其中，每个子板100面向相邻的另一个子板100的一面设有焊盘层(附图6和图8所示的padslayer1、padslayer2、padslayer3、padslayer4及padslayer5)，且每个子板100上均设有导电通孔130，相邻的两个子板100上的导电通孔130一一对应且上下相对。所述焊盘层设有与所在的子板100上的导电通孔130一一对应且导通的焊盘。
其中，请结合图6和图8，至少两个子板100由上往下依次设置形成子板组。当子板100的数量为两个时，所述子板组则包括位于两端的两个端头子板100，如图6所示；当子板100的数量为超过两个时，则子板组除了包括两个端头子板100外，还包括位于两个端头子板100之间的至少一个中间子板100，如图8所示。当子板100为端头子板100时，其焊盘层仅位于子板100的其中一个面上，子板100的另一面则为表面线路层(附图6所示的L1、L18，以及附图8所示的L1、L34)。当子板100为中间子板100时，其焊盘层位于子板100的上下相对的两个面上。
需要说明的是，本发明实施例也可根据实际需要采用线路层代替上述的焊盘层。
S200，在相邻的两个子板100中，采用步骤S210至步骤S250的方法制作孔连接层。
其中，所述第一绝缘介质层200覆盖于所在子板100的所述焊盘层。
S300，将所有的所述子板100层压，形成母板，如图6所示。其中，每个子板100上的导电通孔130通过所述导电介质400与相邻的另一个子板100的导电通孔130电连接。
本发明实施例所述的线路板的制作方法，其通过在每个子板100的待黏合面上设置一个焊盘层，每个子板100上的各层线路均经过导电通孔130延伸至焊盘层上的焊盘，之后再经由绝缘隔离层上的导电介质400与另一个子板100上的各层线路导通。在压合的过程中，绝缘介质层200将上下相邻的两个子板 100粘接。由于绝缘介质层200的上下两侧是与子板100的焊盘层对接，焊盘层仅有焊盘(无线路)，其余均为无铜区，从而有效地降低残铜率，进而降低填胶难度，增强子板100之间的粘接强度，避免发生子板100线路层直接与绝缘介质层200粘接因填胶不足而引发的分层现象。此外，本发明也有效地避免了将焊盘直接增设在原设计线路层，从而避免了在子板100对接过程中，其中一子板100上导电介质400与另一子板100上焊盘之间因对位空间(对位空间是指在保证正常导通的情况下相邻两个子板100之间可错位移动的空间)不足易引发线路板短路现象。因为原设计线路层上有线路，子板100错位对接容易与线路导通，引发短路现象。
在其中一个实施例中，当所有的子板100总数为两个时，则步骤S100仅包括制作端头子板100的步骤S110。其中，如图4和图6所示，步骤S110具体包括以下步骤：
S111，准备两片铜箔、若干个覆铜板110和若干个第三半固化片120，每个所述覆铜板110上下相对的两面均设有线路层，如附图6所示的(L2、L3)和(L4、L5)等。
S112，按照铜箔、若干个覆铜板110、铜箔的顺序由上往下依次层叠形成预压板，其中，相邻的两个所述覆铜板110之间设置至少一个所述第三半固化片120，且两片所述铜箔与所述覆铜板110之间也均设置至少一个所述第三半固化片120。
S113，将所述预压板压合，形成压合板。
S114，在所述压合板上制作导电通孔130，包括钻孔和电镀两个工艺步骤。
S115，在其中一片所述铜箔上蚀刻出线路形成表面线路层(如图6所示的L1或L18)，在另一片所述铜箔上蚀刻出焊盘形成所述焊盘层(如图6所示的padslayer1或padslayer2)，完成所述端头子板100的制作。需要说明的是，在各个子板100之间压合的过程中，两个端头子板100对称设置，即两个端头子板100上的焊盘层相对设置。
由上可知，本发明实施例中的端头子板100上的铜箔层数(包括线路层 (L1-L18)和焊盘层)为偶数，从而使得子板100层压结构对称，避免发生翘曲现象。
此外，在另一个实施例中，当所有的子板100总数为超过两个时，则步骤S100不仅包括步骤S110，还包括制作中间子板100的步骤S120。其中，如图5和图8所示，步骤S120具体包括以下步骤：
S121，准备两片铜箔、若干个覆铜板110和若干个第三半固化片120，每个所述覆铜板110上下相对的两面均设有线路层，如附图8所示的(L10、L11)和(L12、L13)等。
S122，按照铜箔、若干个覆铜板110、铜箔的顺序由上往下依次层叠形成预压板，其中，相邻的两个所述覆铜板110之间设置至少一个所述第三半固化片120，且两片所述铜箔与所述覆铜板110之间也均设置至少一个所述第三半固化片120。
S123，将所述预压板压合，形成压合板。
S124，在所述压合板上制作导电通孔130，包括钻孔和电镀两个工艺步骤。
S125，在两片所述铜箔上均蚀刻出焊盘形成所述焊盘层(如图8所示的padslayer2、padslayer3或padslayer4、padslayer5)，完成所述中间子板100的制作。
同理，本发明实施例中的中间子板100上的铜箔层数(包括线路层和焊盘层)也为偶数，从而使得子板100层压结构对称，避免发生翘曲现象。同时，中间子板100的双面均设置焊盘层，从而实现与上下两侧的子板100的对接。
需要说明的是，本发明对步骤S110和步骤S120之间的先后排序不做限定，本领域技术人员可根据实际需要进行任意排序或同时进行。
此外，在步骤S100之前还可包括步骤：根据目标订单的钻带和层数将目标线路板对称拆分，从而确定子板100数量。可通过此步骤来确定待压合的子板100总数，使得子板100的设计更加简便，仅需要根据客户的原始设计进行对称拆分制作即可。
如图7所示，本发明还提供了一种采用上述制作方法制作而成的线路板， 包括孔连接层和至少两个子板100，至少两个所述子板100由上往下依次层叠设置，相邻的两个所述子板100之间设有所述孔连接层。所述孔连接层包括预先压合固化于其中一个子板100上的第一绝缘介质层200和设于所述第一绝缘介质层200上的第二绝缘介质层300。所述第二绝缘介质层300用于在压合成型的过程中与相邻的另一个所述子板100粘接。所述第一绝缘介质层200开设有第一承接孔，所述第二绝缘介质层300上开设有第二承接孔，所述第一承接孔和所述第二承接孔内均设有导电介质400。在相邻的两个子板100中，其中一个子板100通过所述导电介质400与另一个子板100电连接。
本发明实施例所述线路板包括新型的孔连接层，使得其既可满足双面填胶的需求，提高相邻的两个子板100的粘合强度，又可控制孔连接层的流动度，防止流胶过大，破坏承接孔的孔型，保证导电介质不被挤压和冲散。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。

Claims (10)

  1. 一种孔连接层的制作方法，在上下依次层叠的至少两个子板中，相邻的两个子板之间设有所述孔连接层，其特征在于，包括以下步骤：
    在其中一个子板面向相邻的另一个子板的一面贴附用于压合填胶的第一绝缘介质层；
    压合固化位于所述子板上的所述第一绝缘介质层；
    在压合固化后的所述第一绝缘介质层上贴附用于压合填胶的第二绝缘介质层，所述第二绝缘介质层背向所述第一绝缘介质层的一面用于与相邻的另一个子板粘接；
    在所述第一绝缘介质层制作第一承接孔、并在所述第二绝缘介质层制作第二承接孔，所述第一承接孔和所述第二承接孔上下相对设置；
    在所述第一承接孔和所述第二承接孔内均填塞导电介质，完成所述孔连接层的制作，其中，每个子板通过所述导电介质与相邻的另一个子板电连接。
  2. 根据权利要求1所述的孔连接层的制作方法，其特征在于，所述第一承接孔的孔径小于或等于相邻的两个子板的导电通孔的孔径；所述第二承接孔的孔径小于或等于相邻的两个子板的导电通孔的孔径。
  3. 根据权利要求1所述的孔连接层的制作方法，其特征在于，所述导电介质为导电树脂。
  4. 根据权利要求1所述的孔连接层的制作方法，其特征在于，所述第一绝缘介质层为热固性的第一半固化片。
  5. 根据权利要求1所述的孔连接层的制作方法，其特征在于，所述在第一绝缘介质层上贴附第二绝缘介质层的步骤中，所述第二绝缘介质层包括第二半固化片和位于所述第二半固化片上的保护层，且所述在第一绝缘介质层制作第一承接孔、并在第二绝缘介质层制作第二承接孔的步骤之后，还包括步骤：去除所述保护膜。
  6. 根据权利要求1至5中任一项所述的孔连接层的制作方法，其特征在于，所述孔连接层的流动距离为25mil～200mil。
  7. 一种线路板的制作方法，其特征在于，包括以下步骤：
    制作子板，所述子板的数量为至少两个，至少两个所述子板由上往下依次设置，其中，所制作的每个所述子板面向相邻的另一个所述子板的一面均设有焊盘层，所述焊盘层设有与所在的子板上的导电通孔一一对应且导通的焊盘；
    在相邻的两个所述子板中，采用如权利要求1至6中任一项所述的孔连接层的制作方法来制作孔连接层；
    将所有的所述子板层压，形成母板。
  8. 根据权利要求7所述的线路板的制作方法，至少两个所述子板由上往下依次设置形成子板组，所述子板组包括位于两端的两个端头子板，所述制作子板的步骤包括制作端头子板的步骤，所述制作端头子板的步骤包括以下步骤：
    准备两片铜箔、若干个覆铜板和若干个第三半固化片，每个所述覆铜板上下相对的两面均设有线路层；
    按照铜箔、若干个覆铜板、铜箔的顺序依次层叠形成预压板，其中，相邻的两个所述覆铜板之间设置至少一个所述第三半固化片，且两片所述铜箔与所述覆铜板之间也均设置至少一个所述第三半固化片；
    将所述预压板压合，形成压合板；
    在所述压合板上制作导电通孔；
    在其中一片所述铜箔上蚀刻出线路、形成表面线路层，在另一片所述铜箔上蚀刻出焊盘、形成所述焊盘层，完成所述端头子板的制作。
  9. 根据权利要求8所述的线路板的制作方法，其特征在于，所述子板的数量为至少三个，所述子板组还包括位于两个端头子板之间的中间子板，所述制作子板的步骤还包括制作中间子板的步骤，所述制作中间子板的步骤包括以下步骤：
    准备两片铜箔、若干个覆铜板和若干个第三半固化片，每个所述覆铜板上下相对的两面均设有线路层；
    按照铜箔、若干个覆铜板、铜箔的顺序依次层叠形成预压板，其中，相邻的两个所述覆铜板之间设置至少一个所述第三半固化片，且两片所述铜箔与所 述覆铜板之间也均设置至少一个所述第三半固化片；
    将所述预压板压合，形成压合板；
    在所述压合板上制作导电通孔；
    在两片所述铜箔上均蚀刻出焊盘、形成所述焊盘层，完成所述中间子板的制作。
  10. 一种线路板，其特征在于，包括孔连接层和至少两个子板，至少两个所述子板由上往下依次层叠设置，相邻的两个所述子板之间设有所述孔连接层，所述孔连接层包括预先压合固化于其中一个子板上的第一绝缘介质层和设于所述第一绝缘介质层上的第二绝缘介质层，所述第二绝缘介质层用于在压合成型的过程中与相邻的另一个所述子板粘接，所述第一绝缘介质层开设有第一承接孔，所述第二绝缘介质层上开设有第二承接孔，所述第一承接孔和所述第二承接孔内均设有导电介质，在相邻的两个子板中，其中一个子板通过所述导电介质与另一个子板电连接。
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