WO2018233271A1 - 印制电路板及其制作方法 - Google Patents

印制电路板及其制作方法 Download PDF

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Publication number
WO2018233271A1
WO2018233271A1 PCT/CN2017/120093 CN2017120093W WO2018233271A1 WO 2018233271 A1 WO2018233271 A1 WO 2018233271A1 CN 2017120093 W CN2017120093 W CN 2017120093W WO 2018233271 A1 WO2018233271 A1 WO 2018233271A1
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WIPO (PCT)
Prior art keywords
impedance
printed circuit
circuit board
layer
design
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PCT/CN2017/120093
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English (en)
French (fr)
Inventor
程柳军
陈蓓
李艳国
王红飞
Original Assignee
广州兴森快捷电路科技有限公司
深圳市兴森快捷电路科技股份有限公司
宜兴硅谷电子科技有限公司
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Publication of WO2018233271A1 publication Critical patent/WO2018233271A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0776—Resistance and impedance
    • H05K2201/0784—Uniform resistance, i.e. equalizing the resistance of a number of conductors

Definitions

  • the present invention relates to the field of printed circuit boards, and in particular, to a printed circuit board and a method of fabricating the same.
  • PCB printed circuit board
  • impedance control accuracy of the PCB is getting higher and higher.
  • the impedance control accuracy of PCB products is generally ⁇ 10%.
  • Some high-end products require impedance control to achieve higher precision, such as impedance control accuracy of ⁇ 7% or ⁇ 5%, and the number of such products is increasing.
  • a method of manufacturing a printed circuit board comprising the steps of:
  • laminated structure design According to the design requirements of the printed circuit board, the laminated structure design is obtained, and the initial dielectric layer thickness and the initial dielectric constant of each dielectric layer of the printed circuit board are obtained, and the initial layers of the printed circuit board are obtained.
  • the copper thickness value wherein the initial dielectric layer thickness of the layer where the impedance line of the printed circuit board is H 0 , the initial dielectric constant is Er 0 , and the initial copper thickness value is T 0 , as the initial medium of the shielding layer of the impedance line
  • the layer thickness is H 0 ', and the initial dielectric constant is Er 0 ';
  • Impedance design According to the impedance control requirements of the printed circuit board, the impedance design software is used for impedance design, and the initial impedance design parameters of the impedance line of the printed circuit board are obtained;
  • the core board and the prepreg are opened according to the PCB imposition size, and the core board and the prepreg of the same batch after the cutting are selected for testing, and the actual core thickness H 1 of the layer where the impedance line is obtained is obtained.
  • the actual core dielectric constant Er 1 , the actual prepreg thickness H 2 as the shielding layer of the impedance line and the actual prepreg dielectric constant Er 2 respectively H 1 , H 2 , Er 1 , Er 2 and the corresponding H 0 , H 0 ', Er 0 , Er 0 ' for comparison, if the difference between H 1 , H 2 and H 0 , H 0 ' is within the preset thickness control tolerance, Er 1 , Er 2 and Er 0 , Er 0 ' The difference is within the preset dielectric constant control tolerance, then the initial impedance design parameter obtained in step S2 is still selected as the new impedance design parameter; if the difference between H 1 , H 2 and H 0 , H 0 ' is at the preset thickness In addition to the control tolerance, the difference between Er 1 , Er 2 and Er 0 , Er 0 ' is outside the preset dielectric constant control tolerance, then H 1 , H 2 , Er 1 , Er 2 are brought
  • the FA board is fabricated for etching, and the actual impedance design parameters of the FA board are tested after etching, and the actual impedance design parameters are compared with the latest impedance design parameters. If the difference between the two is within the preset impedance parameter control tolerance, the subsequent Mass production; if the difference between the two is outside the preset impedance parameter control tolerance, adjust the etching production parameters, re-create the FA plate and test the etched impedance design parameters until the difference is within the preset impedance parameter control tolerance, then adjust Post-etching production parameters for mass production;
  • the manufacturing method of the printed circuit board further comprises the steps of:
  • the initial dielectric layer thickness of the core layer of the layer where the impedance line of the printed circuit board is located is >100 ⁇ m, and/or the initial medium of the prepreg as the shielding layer of the impedance line Layer thickness > 100 ⁇ m.
  • the initial copper thickness of the layer where the impedance line of the printed circuit board is located is 8 ⁇ m, 12 ⁇ m or 18 ⁇ m, and the initial copper thickness of the shielding layer of the impedance line is 8 ⁇ m. 12 ⁇ m or 18 ⁇ m.
  • each dielectric layer of the printed circuit board is a low dielectric constant characteristic material.
  • step S5 specifically includes the following steps:
  • step S51 when performing the hot pressing process, adjusting the pressing procedure of the material, adjusting the amount of the buffer material when the stacking is performed, so that the heating rate of the material is lowered by 0.2 ° C / min to 0.5 ° C / Min.
  • the method further comprises the steps of: performing a sampling test in the mass production process to test the impedance line of the etched product. Whether the impedance design parameter is within the preset impedance parameter control tolerance, if it is, continue mass production; if not, adjust the etching production parameters according to the test result.
  • the manufacturing method of the printed circuit board further comprises the following steps:
  • the TDR device is used to test the impedance value of the printed circuit board after mass production, and the inner layer impedance of the printed circuit board is judged according to the impedance control tolerance.
  • a printed circuit board produced by the method of manufacturing a printed circuit board as described above.
  • the manufacturing method of the printed circuit board firstly performs the laminated structure design and the impedance design according to the customer's requirements, obtains the initial parameters of the dielectric layers of the printed circuit board, and obtains the impedance in the printed circuit board through the impedance design software.
  • the initial impedance design parameters of the line are then adjusted and corrected according to the actual parameters of the actual material after the material is opened, and then the new impedance design is influenced according to the actual production factors in the process of making the inner layer.
  • the parameters are adjusted and corrected, and the production parameters of the etching are adjusted to obtain a printed circuit board having a multilayer board structure.
  • the manufacturing method of the printed circuit board can monitor and adjust the factors affecting the impedance value during the production process of the material opening and the inner layer circuit, thereby solving the problem that the inner layer impedance of the printed circuit board is difficult to control due to various factors in the production process.
  • the problem is that the inner layer impedance of the printed circuit board is stably controlled to meet the requirements of high precision, and the high-speed signal transmission performance of the printed circuit board is improved, thereby improving the impedance yield of the printed circuit board, reducing the impedance rejection rate, and reducing the production. Cost, reducing the delay of delivery due to poor impedance problems.
  • the printed circuit board is produced by the above-mentioned manufacturing method of the printed circuit board, and the product has high impedance qualification rate, low production cost, and is less prone to impedance defects.
  • FIG. 1 is a schematic structural diagram 1 of a method for fabricating a printed circuit board according to an embodiment of the present invention
  • FIG. 2 is a second schematic structural diagram of a method for fabricating a printed circuit board according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an example of a printed circuit board according to an embodiment of the present invention.
  • a method for manufacturing a printed circuit board includes the following steps:
  • laminated structure design According to the design requirements of the printed circuit board, the laminated structure design is obtained, and the initial dielectric layer thickness and the initial dielectric constant of each dielectric layer of the printed circuit board are obtained, and the initial layers of the printed circuit board are obtained.
  • the copper thickness value wherein the initial dielectric layer thickness of the layer where the impedance line of the printed circuit board is H 0 , the initial dielectric constant is Er 0 , and the initial copper thickness value is T 0 , as the initial medium of the shielding layer of the impedance line
  • the layer thickness is H 0 ' and the initial dielectric constant is Er 0 '.
  • the PCB thickness, power layer, ground layer design requirements, as well as the signal frequency, signal rate on the PCB, etc. select the appropriate material for the laminated structure design, and get the initial of each dielectric layer.
  • the dielectric layer thickness and the initial dielectric constant give the initial copper thickness values of the various layers of the printed circuit board.
  • the initial dielectric layer thickness of the core layer of the layer where the impedance line of the printed circuit board is located is >100 ⁇ m, and/or the initial dielectric layer thickness of the prepreg as the shielding layer of the impedance line is >100 ⁇ m. Furthermore, the initial dielectric layer thickness of the core layer of the layer where the impedance line is located, the initial dielectric layer thickness of the prepreg as the shielding layer of the impedance line are thicker, and the uniformity is better, and the impedance design parameters can be better controlled when the impedance design is performed. .
  • the initial copper thickness of the layer of the impedance line of the printed circuit board is 8 ⁇ m, 12 ⁇ m or 18 ⁇ m
  • the initial copper thickness of the shielding layer of the impedance line is 8 ⁇ m, 12 ⁇ m or 18 ⁇ m.
  • the copper thickness is thicker and the copper thickness uniformity is better.
  • the impedance design is performed, the impedance design parameters can be better controlled, and the impedance control is less difficult.
  • each dielectric layer of the printed circuit board is a low dielectric constant material, which further reduces the difficulty of impedance control.
  • the low dielectric constant property material means a material having a dielectric constant Er of less than 4.0.
  • impedance design According to the impedance control requirements of the printed circuit board, and according to the data obtained in step S1, the impedance design software is used for impedance design, and the initial impedance design parameters of the impedance line of the printed circuit board are obtained. Specifically, when the impedance line is a single-ended impedance line, the initial impedance design parameter is an initial upper line width value W 10 and an initial lower line width value W 20 ; when the impedance line is a differential impedance line, the The initial impedance design parameters are an initial upper line width value W 10 , an initial lower line width value W 20 , and an initial lower line width value W 20 /initial line spacing value S 0 .
  • the core board and the prepreg are opened according to the PCB imposition size, and the core board and the prepreg of the same batch after the cutting are selected for testing, and the actual core thickness H 1 of the layer where the impedance line is obtained is obtained.
  • the actual core dielectric constant Er 1 , the actual prepreg thickness H 2 as the shielding layer of the impedance line and the actual prepreg dielectric constant Er 2 respectively H 1 , H 2 , Er 1 , Er 2 and the corresponding H 0 , H 0 ', Er 0 , Er 0 ' for comparison, if the difference between H 1 , H 2 and H 0 , H 0 ' is within the preset thickness control tolerance, Er 1 , Er 2 and Er 0 , Er 0 ' The difference is within the preset dielectric constant control tolerance, then the initial impedance design parameter obtained in step S2 is still selected as the new impedance design parameter; if the difference between H 1 , H 2 and H 0 , H 0 ' is at the preset thickness In addition to the control tolerance, the difference between Er 1 , Er 2 and Er 0 , Er 0 ' is outside the preset dielectric constant control tolerance, then H 1 , H 2 , Er 1 , Er 2 are brought
  • the dielectric layer thickness, dielectric constant, etc. of different batches of PCB materials may fluctuate somewhat, this fluctuation has a certain influence on the impedance control of the conventional impedance product (impedance control precision tolerance ⁇ 10%) but not too large, but The influence of high-precision impedance products (impedance control accuracy tolerance ⁇ 10% such as ⁇ 7% or ⁇ 5%) cannot be ignored, and it is easy to cause the ultimate high-precision product to have excessive impedance control.
  • the core plates and prepregs of the same batch are selected, and the H 1 , H 2 , Er 1 , and Er 2 values after the opening are retested, and then H 1 and H 0 , H are obtained.
  • the nine-point method can be used to test and calculate the thickness values of the core plate and the prepreg, and the dielectric constant value of the core plate and the prepreg can be obtained by the cavity method test.
  • the preset thickness control tolerance may be ⁇ 1%, within the preset thickness control tolerance, ⁇ 1%, and outside the preset thickness control tolerance, >1%.
  • the preset dielectric constant control tolerance can be ⁇ 0.1, ⁇ 0.1 within the preset dielectric constant control tolerance, and > ⁇ 0.1 outside the preset dielectric constant control tolerance.
  • the control of the inner layer impedance is high and can meet the actual demand.
  • the new impedance design parameter obtained in step S3 is selected as the latest impedance design parameter;
  • T is brought into the impedance design software to optimize the impedance design, and the adjusted second impedance design parameter is output as the latest impedance design parameter, where T' Indicates the browning effect value;
  • fabricate the FA plate for etching test the actual impedance design parameters of the FA plate after etching, and compare the actual impedance design parameters with the latest impedance design parameters, if the difference between the two is in the preset impedance parameter control tolerance Afterwards, subsequent mass production can be performed; if the difference between the two is outside the preset impedance parameter control tolerance, the etching production parameters are adjusted, the FA plate is re-formed, and the etched impedance design parameters are tested until Different parameters within a predetermined impedance control tolerance, places etched
  • step S4 by testing the actual copper thickness value T of the core layer of the layer after the development and before the etching, the (TT') is compared with T 0 according to the preset.
  • the copper thickness control tolerance further adjusts and corrects the impedance design parameters to obtain the latest impedance design parameters, and then adjusts and modifies the etching production parameters according to the influence of the actual etching on the impedance, which can effectively solve the production of printed circuit boards.
  • the factors cause the inner layer impedance to be difficult to control, and improve the impedance yield of the product.
  • the subsequent browning effect is fully considered, and the impedance control is more accurate, which can effectively improve the impedance qualification rate of the product.
  • the specific steps for fabricating the inner layer circuit of the core layer of the layer after the impedance line after step S3 are: roughening and cleaning the core sheet copper by chemical micro-etching method, and then laminating the film, and adopting LDI
  • the exposure machine performs graphics transfer.
  • the actual copper thickness value T can be tested using a copper thickness gauge.
  • the core plate and the prepreg are both 1 to 3 pieces, they can be tested separately, and then averaged to obtain the corresponding copper thickness value, and the test is more accurate.
  • the preset copper thickness control tolerance may be ⁇ 1 ⁇ m, ⁇ 1 ⁇ m within the preset thickness control tolerance, and > ⁇ 1 ⁇ m outside the preset thickness control tolerance, and the impedance control precision is high.
  • the T' is 0.5 ⁇ m, in accordance with the actual browning effect.
  • the method further comprises the steps of: performing the sampling test in the mass production process, and testing whether the impedance design parameter of the impedance line of the etched product is The resistance is within the control tolerance of the preset impedance parameter. If it is, the mass production is continued; if not, the production parameters of the etching are adjusted according to the test result.
  • the sampling test the etching parameters can be fine-tuned in real time according to the test results, and the inner layer impedance of the inner layer line is further controlled, so that the inner layer impedance of the multilayer printed circuit board satisfies the high precision requirement, and the impedance pass rate is effectively improved.
  • the manufacturing method of the printed circuit board firstly performs the laminated structure design and the impedance design according to the customer's requirements, obtains the initial parameters of the dielectric layers of the printed circuit board, and obtains the impedance in the printed circuit board through the impedance design software.
  • the initial impedance design parameters of the line are then adjusted and corrected according to the actual parameters of the actual material after the material is opened, and then the new impedance design is influenced according to the actual production factors in the process of making the inner layer.
  • the parameters are adjusted and corrected, and the production parameters of the etching are adjusted to obtain a printed circuit board having a multilayer board structure.
  • factors affecting PCB impedance are mainly wire width, dielectric layer thickness, copper thickness, dielectric constant, solder mask thickness, and the like.
  • the impedance control of the outer impedance line is more difficult than the inner layer, and the line loss of the outer microstrip line is also larger than that of the inner strip line. Therefore, the high-speed impedance line of the high-speed PCB product is generally disposed in the inner layer of the PCB.
  • the manufacturing method of the printed circuit board can provide a method for manufacturing a multilayer printed circuit board with high precision inner layer impedance, and correct the factors affecting the impedance value during the manufacturing process of the material opening and the inner layer line.
  • the inner layer impedance of the printed circuit board is difficult to control due to various factors in the production process, stably control the inner layer impedance of the printed circuit board to meet the high precision requirement, and improve the high-speed signal transmission performance of the printed circuit board, and further It can improve the impedance qualification rate of printed circuit boards, reduce the impedance rejection rate, reduce the production cost, and reduce the delay of delivery due to poor impedance problems, especially for high-precision impedance products (inner layer impedance control accuracy is less than ⁇ 10%) For the production of ⁇ 7% and ⁇ 5% tolerance, the problem of low impedance yield of high-precision impedance products can be effectively improved.
  • the manufacturing method of the printed circuit board further includes the following steps:
  • balance copper spots are laid in the open area and/or isolated line area of the graphic design of the printed circuit board.
  • the uniformity of the residual copper distribution of the pattern can be improved, thereby achieving the requirement of high-precision impedance control.
  • the balance copper point can be laid according to the actual situation, and the PCB file is properly optimized, and the high-precision impedance control requirement is achieved without affecting the electrical performance of the PCB.
  • the balanced copper dots may be laid in a square or a circle with a certain size and a spacing, and the size and spacing may be determined according to the residual copper ratio of the graphic region, thereby ensuring the residual copper ratio and the pattern of the balanced copper spot region.
  • the area is quite.
  • step S5 specifically includes the following steps:
  • step S52 drilling, electroplating, outer layer etching, solder masking: drilling, electroplating, outer layer etching and solder masking of multilayer boards to form a complete printed circuit board of multi-layer board structure.
  • step S52 a printed circuit board manufacturing process with conventional impedance control accuracy can be used for fabrication.
  • the mass-produced product controlled by the S4 step can be subjected to subsequent processing, thereby obtaining a printed circuit board having a multilayer board structure.
  • step S51 when the hot pressing process is performed, the pressing procedure of the material is adjusted, and the amount of the buffering material when the laminated plate is adjusted, so that the heating rate of the material is lowered by 0.2 ° C / min to 0.5 ° C / min. Specifically, the rate of temperature rise of the material is lowered by 0.2 ° C / min to 0.5 ° C / min relative to conventional manufacturing parameters. Furthermore, the thickness uniformity of the dielectric layer can be improved while ensuring good filling, the impedance control difficulty is further reduced, and the impedance yield of the product is improved. Further, between steps S51 and S52, the core board cannot be reworked to avoid affecting the impedance control.
  • the manufacturing method of the printed circuit board further includes the following steps:
  • the TDR device is used to test the impedance value of the printed circuit board after mass production, and the inner layer impedance of the printed circuit board is judged according to the impedance control tolerance. Further, it is possible to detect the manufactured product and determine whether the inner layer impedance of the product is acceptable or not, and the operation is convenient. In this embodiment, a device with a TDR with a rise time of less than 35 ps can be used for testing, and the impedance value of the printed circuit board with high precision inner layer impedance can be tested.
  • the manufacturing method of the printed circuit board according to the embodiment by performing file optimization design, laminated structure design, impedance design, etc. on the printed circuit board, monitors and real-time adjusts various factors affecting the impedance value in the production process. It can solve the problem that the inner layer impedance of the printed circuit board is difficult to control due to factors such as design and production, and can stably control the inner layer impedance of the multilayer printed circuit board to meet the high precision requirement, and can significantly improve the same large board.
  • the uniformity of the impedance of the signal lines in different regions avoids signal integrity problems such as signal reflection and distortion caused by impedance mismatch in the high-speed signal lines in the PCB, thereby improving the high-speed signal transmission performance of the printed circuit board and significantly improving the high-precision impedance.
  • the impedance yield of the PCB, the reduction of the impedance rejection rate and the delay of the delivery period, etc., have the advantages of strong operability, good effect, and effective improvement of the impedance pass rate.
  • the printed circuit board of the embodiment is a multi-layer board structure, which includes a plurality of core boards and prepregs, the core board is formed into a circuit pattern, and a plurality of core boards are combined with the prepreg, and are pressed and obtained.
  • the transmission line of the printed circuit board has an inner layer impedance control requirement, and the inner layer impedance control precision is a high precision control requirement of less than ⁇ 10% such as ⁇ 7%, ⁇ 5% tolerance.
  • the printed circuit board is produced by the above-mentioned manufacturing method of the printed circuit board, and the product has high impedance qualification rate, low production cost, and is less prone to impedance defects.
  • the printed circuit board to be fabricated has an 8-layer structure.
  • the layout of each layer is as follows: ART01 layer is SIG01 layer, ART02 layer is GND01 layer, ART03 layer is SIG02 layer, ART04 layer is GND02 layer, ART05
  • the layer is the POWER layer
  • the ART06 layer is the SIG03 layer
  • the ART07 layer is the GND03 layer
  • the ART08 layer is the SIG04 layer.
  • the SIG02 layer and the SIG03 layer are wiring layers of impedance lines of high-speed signals, wherein each layer is provided with a single-ended impedance line 300 and a differential impedance line 400.
  • the impedance precision of the impedance line is strict, and the impedance control tolerance is ⁇ 5%.
  • the method for manufacturing the printed circuit board with high precision inner layer impedance includes the following steps:
  • S0, file optimization design Appropriate optimization of PCB files, laying balanced copper spots in the inner layer of the PCB pattern, such as open space, isolated lines, etc., to improve the uniform distribution of residual copper in the pattern, wherein the balance copper points can be laid as a circle
  • the diameter of the circle may be 1.25 mm, and the center distance of the upper and lower sides of the adjacent circle may be 2 mm.
  • the modified FR4 material of Low Dk/Low Loss is selected for the laminated structure design.
  • the dielectric layer (prepreg 100) of SIG01 layer to GND01 layer, the dielectric layer of GND01 layer to SIG02 layer (core board 200), the dielectric layer of SIG02 layer to GND02 layer (prepreg 100), and GND02 layer can be designed according to experience.
  • the dielectric layer of the POWER layer (core board 200), the dielectric layer of the POWER layer to the SIG03 layer (prepreg 100), the dielectric layer of the SIG03 layer to the GND03 layer (core board 200), the GND03 layer to the dielectric layer of the SIG04 layer (prepreg 100) Initial dielectric layer thickness and initial dielectric constant.
  • the initial copper thickness values of the SIG01 layer, the GND01 layer, the GND03 layer, and the SIG04 layer were both 18 ⁇ m, and the initial copper thickness values of the SIG02 layer, the SIG03 layer, the GND02 layer, and the POWER layer were both 12 ⁇ m.
  • the VLP type can be selected for the copper foil type.
  • impedance design After the laminated structure design is completed, according to the impedance control requirements and the data obtained in S1, the impedance design software is used to perform the corresponding impedance design, and the initial impedance design parameters of the impedance lines of the printed circuit board are obtained.
  • the impedance lines of the SIG02 layer and the SIG03 layer have impedance control requirements, and the impedance lines of the SIG02 layer and the SIG03 layer are high-speed signal transmission lines, the impedance control tolerance is required to be ⁇ 5%, and the single-ended impedance requirements of each impedance layer are required.
  • the differential impedance is required to be 100 ohms.
  • the reference shield of the SIG02 layer is the GND01 layer and the GND02 layer
  • the reference shield of the SIG03 layer is the POWER layer and the GND03 layer.
  • the initial impedance design parameters of the single-ended impedance line satisfying the above process conditions that is, the initial upper line width value W 10 and the initial lower line width value W 20 can be calculated by the impedance design software, and the initial impedance design parameter of the differential impedance line is the initial upper line width value.
  • W 10 , initial lower line width value W 20 and initial lower line width value W 20 / initial line spacing value S 0 initial upper line width value.
  • the core board and prepreg of the specified material are cut into a certain size according to the PCB imposition size.
  • the single-ended impedance line 300 of the SIG02 layer as an example, three core sheets which can be used for the ART02 layer and the ART03 layer are selected, and the thickness of each core board is tested by a nine-point method and the mean value is calculated to obtain H 1 , which can be selected for the ART03 layer and Three sheets of prepreg of ART04 layer were pressed into composite plates, and the thickness was tested by nine-point method and the average value was calculated to obtain H 2 .
  • the dielectric constants of core plate and prepreg were measured by resonant cavity method, Er 1 and Er 2 respectively, respectively, H 1 , H 2 , Er 1 , and Er 2 are compared with the corresponding H 0 , H 0 ', Er 0 , and Er 0 ' to obtain a new impedance design parameter of the single-ended impedance line of the SIG02 layer.
  • H 1 , H 2 , Er 1 , and Er 2 are compared with the corresponding H 0 , H 0 ', Er 0 , and Er 0 ' to obtain a new impedance design parameter of the single-ended impedance line of the SIG02 layer.
  • the above steps can be used to obtain the corresponding new impedance design parameters.
  • the copper of the core sheet is roughened and cleaned by a chemical micro-etching method, and then a LDI dry film of 25 ⁇ m thickness is attached, and the image transfer is performed by using an LDI exposure machine.
  • the etching before the test meter thick copper layer ART03 copper thickness and the actual value of the core plate ART06 layer are T 1 and T 2
  • the (T 1 -0.5) compared with the initial value of the thick copper layer ART03 (T 2 -0.5) is compared with the initial copper thickness value of the ART06 layer to obtain the latest impedance design parameters of the impedance lines of the respective layers.
  • the core plates of the ART02 and ART03 layers, the ART06 and ART07 layers were selected as the FA plates, and the first plate was fabricated at an etching rate of 4.2 m/min.
  • the impedance of the ART03 layer and the ART06 layer was tested by the line width measuring instrument.
  • the actual impedance design parameters of the line are then compared with the latest impedance design parameters in the previous step to determine whether the production parameters are used for the production of the etching or the production parameters are adjusted until the conditions are met to adjust the production of the etching.
  • the parameters are mass produced. In the mass production process, every 10 core plates are sampled and tested for actual impedance design parameters, and the etching production parameters are fine-tuned in real time according to the test results.
  • Impedance test The impedance value of the printed circuit board of the 8-layer board structure is tested by a vector network analyzer with a rise time of 22.3 ps, and it is judged whether each impedance value satisfies the requirement of ⁇ 5% tolerance, and the product is judged to be qualified.

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  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

提供了一种印制电路板及其制作方法，所述印制电路板的制作方法包括以下步骤：层叠结构设计（S1），阻抗设计（S2），开料及优化阻抗设计（S3），制作内层线路（S4）以及后处理形成多层板结构的印制电路板（S5）。所述印制电路板及其制作方法，通过开料及制作内层线路的生产过程中对影响阻抗值的因素进行监控和调整，可解决印制电路板因生产过程中各因素导致内层阻抗难以控制的问题，稳定地控制印制电路板的内层阻抗满足高精度的要求，提高印制电路板的高速信号传输性能，进而能够提高印制电路板的阻抗合格率，降低阻抗报废率，降低生产成本，减少因阻抗不良问题而导致的交期延误问题。

Description

印制电路板及其制作方法 技术领域
本发明涉及印制电路板技术领域，尤其涉及一种印制电路板及其制作方法。
背景技术
随着PCB(Printed Circuit Board，印制电路板)趋于高速化和高频化方向发展，对于PCB的阻抗控制精度越来越高。PCB产品的阻抗控制精度一般为±10％，也有部分高端产品要求阻抗控制能达到更高精度，如阻抗控制精度达到±7％或±5％，且此类产品数量越来越多。
传统的，在对PCB进行阻抗设计时，通常会采用一些阻抗计算软件对阻抗进行模拟预测，然后依据客户的要求如叠层结构、线宽、介质层厚度等选择一套合适的控制方案，产品制作时就依据设计时的控制方案进行制作让产品的阻抗符合客户要求的阻抗。但是，由于影响PCB阻抗的因素较多，且PCB制作流程较为繁琐，采用传统方法得到的产品尤其是具有高精度阻抗控制需求的产品，其阻抗合格率较差，进而导致产品报废率高、制作成本高，产品出现交期延误问题。
发明内容
基于此，有必要提供一种印制电路板及其制作方法，该印制电路板及其制作方法能够提高产品的阻抗合格率，降低生产成本，减少因阻抗不良问题而导致的交期延误问题。
其技术方案如下：
一种印制电路板的制作方法，包括以下步骤：
S1、层叠结构设计：根据印制电路板的设计要求进行叠层结构设计，得到印制电路板的各介质层的初始介质层厚度和初始介电常数，得到印制电路板的各层的初始铜厚值，其中，印制电路板的阻抗线所在层的初始介质层厚度为H 0、 初始介电常数为Er 0、初始铜厚值为T 0，作为该阻抗线的屏蔽层的初始介质层厚度为H 0′、初始介电常数为Er 0′；
S2、阻抗设计：根据印制电路板的阻抗控制要求，采用阻抗设计软件进行阻抗设计，获得印制电路板的阻抗线的初始阻抗设计参数；
S3、开料及优化阻抗设计：根据PCB拼版尺寸将芯板和半固化片进行开料，选取该开料后的同批次的芯板及半固化片进行测试，获得阻抗线所在层的实际芯板厚度H 1和实际芯板介电常数Er 1，获得作为该阻抗线的屏蔽层的实际半固化片厚度H 2和实际半固化片介电常数Er 2，分别将H 1、H 2、Er 1、Er 2与对应的H 0、H 0′、Er 0、Er 0′进行对比，若H 1、H 2与H 0、H 0′的差异在预设厚度控制公差内，Er 1、Er 2与Er 0、Er 0′的差异在预设介电常数控制公差内，则仍选用步骤S2中获得的初始阻抗设计参数作为新的阻抗设计参数；若H 1、H 2与H 0、H 0′的差异在预设厚度控制公差以外，Er 1、Er 2与Er 0、Er 0′的差异在预设介电常数控制公差以外，则将H 1、H 2、Er 1、Er 2带入阻抗设计软件进行优化阻抗设计，并输出调整后的第一阻抗设计参数作为新的阻抗设计参数；
S4、制作内层线路：对经过步骤S3后的阻抗线所在层的芯板进行内层线路制作，在显影后、蚀刻前测试获得阻抗线所在层的芯板的实际铜厚值T，将(T-T′)与T 0进行对比，若(T-T′)与T 0的差异在预设铜厚控制公差内，则选用步骤S3中获得的新的阻抗设计参数作为最新的阻抗设计参数；若(T-T′)与T 0的差异在预设铜厚控制公差以外，则将T带入阻抗设计软件进行优化阻抗设计，并输出调整后的第二阻抗设计参数作为最新的阻抗设计参数，其中，T′表示棕化影响值；
制作FA板进行蚀刻，蚀刻后测试该FA板的实际阻抗设计参数，并将实际阻抗设计参数与最新的阻抗设计参数进行对比，若两者差异在预设阻抗参数控制公差内，则可进行后续批量生产；若两者差异在预设阻抗参数控制公差以外，则调整蚀刻的生产参数，重新制作FA板并测试蚀刻后的阻抗设计参数，直至差异在预设阻抗参数控制公差内，则以调整后的蚀刻的生产参数进行批量生产；
S5、后处理形成多层板结构的印制电路板。
在其中一个实施例中，在步骤S1之前，所述印制电路板的制作方法还包括步骤：
S0、文件优化设计：印制电路板布线完成后，在印制电路板的图形设计的空旷区及/或孤立线区域铺设平衡铜点。
在其中一个实施例中，在所述步骤S1中：印制电路板的阻抗线所在层的芯板的初始介质层厚度＞100μm，及/或，作为该阻抗线的屏蔽层的半固化片的初始介质层厚度＞100μm。
在其中一个实施例中，在所述步骤S1中：印制电路板的阻抗线所在层的初始铜厚值为8μm、12μm或18μm，作为该阻抗线的屏蔽层的初始铜厚值为8μm、12μm或18μm。
在其中一个实施例中，在所述步骤S1中：印制电路板的各介质层均为低介电常数特性材料。
在其中一个实施例中，所述步骤S5具体包括以下步骤：
S51、棕化、压合：将阻抗线所在层的芯板进行棕化处理获得棕化层，并采用开料后的同批次的半固化片进行叠合，使得半固化片位于芯板之间，形成叠层板，通过热压工艺对叠合板进行压合形成多层板；
S52、钻孔、电镀、外层线路蚀刻、阻焊：对多层板进行钻孔、电镀、外层线路蚀刻以及阻焊制作，形成完整的多层板结构的印制电路板。
在其中一个实施例中，在所述步骤S51中：进行热压工艺时，调整材料的压合程序，调整叠板时缓冲材料的用量，使得材料的升温速率下调0.2℃/min～0.5℃/min。
在其中一个实施例中，在所述步骤S4中，在以调整后的蚀刻的生产参数进行批量生产步骤之后，还包括步骤：在批量生产过程中进行抽测检验，测试蚀刻后产品的阻抗线的阻抗设计参数是否阻在预设阻抗参数控制公差内，若在，继续进行批量生产；若不在，则根据测试结果对蚀刻的生产参数进行调整。
在其中一个实施例中，在步骤S5之后，所述印制电路板的制作方法还包括以下步骤：
S6、阻抗测试：采用TDR设备测试批量生产后的印制电路板的阻抗值，并根据阻抗控制公差判定印制电路板的内层阻抗是否合格。
一种印制电路板，采用如上所述的印制电路板的制作方法制作得到。
本发明的有益效果在于：
所述印制电路板的制作方法，首先根据客户需求依次进行层叠结构设计及阻抗设计，得到印制电路板的各介质层的各初始参数，进而通过阻抗设计软件得到印制电路板中的阻抗线的初始阻抗设计参数，然后在开料后根据实际开料后的材料实际参数对初始阻抗设计参数进行调整修正，接着又在制作内层线路的过程中根据实际生产因素影响对新的阻抗设计参数进行调整修正，对蚀刻的生产参数进行调整，得到多层板结构的印制电路板。所述印制电路板的制作方法，通过开料及制作内层线路的生产过程中对影响阻抗值的因素进行监控和调整，可解决印制电路板因生产过程中各因素导致内层阻抗难以控制的问题，稳定地控制印制电路板的内层阻抗满足高精度的要求，提高印制电路板的高速信号传输性能，进而能够提高印制电路板的阻抗合格率，降低阻抗报废率，降低生产成本，减少因阻抗不良问题而导致的交期延误问题。
所述印制电路板，采用上述的印制电路板的制作方法制作得到，产品的阻抗合格率高、生产成本低，不易出现阻抗不良问题。
附图说明
图1为本发明实施例所述的印制电路板的制作方法的流程结构示意图一；
图2为本发明实施例所述的印制电路板的制作方法的流程结构示意图二；
图3为本发明实施例所述的印制电路板的实例结构示意图。
附图标记说明：
100、半固化片，200、芯板，300、单端阻抗线，400、差分阻抗线。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。 附图中给出了本发明的较佳实施方式。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本发明的公开内容理解的更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。相反，当元件被称作“直接在”另一元件“上”时，不存在中间元件。本文所使用的术语“垂直的”、“水平的”、“左”、“右”以及类似的表述只是为了说明的目的，并不表示是唯一的实施方式。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。本文所使用的术语“第一”、“第二”等在本文中用于区分对象，但这些对象不受这些术语限制。
如图1所示，一种印制电路板的制作方法，包括以下步骤：
S1、层叠结构设计：根据印制电路板的设计要求进行叠层结构设计，得到印制电路板的各介质层的初始介质层厚度和初始介电常数，得到印制电路板的各层的初始铜厚值，其中，印制电路板的阻抗线所在层的初始介质层厚度为H 0、初始介电常数为Er 0、初始铜厚值为T 0，作为该阻抗线的屏蔽层的初始介质层厚度为H 0′、初始介电常数为Er 0′。具体地，可根据客户需求，根据PCB的板厚、电源层、地层等的设计要求，以及PCB上的信号频率、信号速率等选择合适的材料进行叠层结构设计，并得到各介质层的初始介质层厚度和初始介电常数，得到印制电路板的各层的初始铜厚值。
可选地，在步骤S1中，印制电路板的阻抗线所在层的芯板的初始介质层厚度＞100μm，及/或，作为该阻抗线的屏蔽层的半固化片的初始介质层厚度＞100μm。进而，阻抗线所在层的芯板的初始介质层厚度、作为该阻抗线的屏蔽层的 半固化片的初始介质层厚度均较厚，均匀性更好，进行阻抗设计时阻抗设计参数能够更好的控制。可选地，印制电路板的阻抗线所在层的初始铜厚值为8μm、12μm或18μm，作为该阻抗线的屏蔽层的初始铜厚值为8μm、12μm或18μm。进而，铜厚值较厚，铜厚均匀性更好，进行阻抗设计时阻抗设计参数能够更好的控制，阻抗控制难度降低。可选地，印制电路板的各介质层均为低介电常数特性材料，可进一步降低阻抗控制难度。具体地，低介电常数特性材料是指介电常数Er小于4.0的材料。
S2、阻抗设计：根据印制电路板的阻抗控制要求，并根据步骤S1中获得的各数据，采用阻抗设计软件进行阻抗设计，获得印制电路板的阻抗线的初始阻抗设计参数。具体地，当所述阻抗线为单端阻抗线时，所述初始阻抗设计参数为初始上线宽值W 10和初始下线宽值W 20；当所述阻抗线为差分阻抗线时，所述初始阻抗设计参数为初始上线宽值W 10、初始下线宽值W 20和初始下线宽值W 20/初始线距值S 0。
S3、开料及优化阻抗设计：根据PCB拼版尺寸将芯板和半固化片进行开料，选取该开料后的同批次的芯板及半固化片进行测试，获得阻抗线所在层的实际芯板厚度H 1和实际芯板介电常数Er 1，获得作为该阻抗线的屏蔽层的实际半固化片厚度H 2和实际半固化片介电常数Er 2，分别将H 1、H 2、Er 1、Er 2与对应的H 0、H 0′、Er 0、Er 0′进行对比，若H 1、H 2与H 0、H 0′的差异在预设厚度控制公差内，Er 1、Er 2与Er 0、Er 0′的差异在预设介电常数控制公差内，则仍选用步骤S2中获得的初始阻抗设计参数作为新的阻抗设计参数；若H 1、H 2与H 0、H 0′的差异在预设厚度控制公差以外，Er 1、Er 2与Er 0、Er 0′的差异在预设介电常数控制公差以外，则将H 1、H 2、Er 1、Er 2带入阻抗设计软件进行优化阻抗设计，并输出调整后的第一阻抗设计参数作为新的阻抗设计参数。
由于不同批次PCB材料的介质层厚度、介电常数等会有一定的波动，此波动对于常规阻抗产品(阻抗控制精度公差≥±10％)的阻抗控制有一定影响但不太大，而对于高精度阻抗产品(阻抗控制精度公差＜±10％如±7％或±5％等)的影响不容忽视，容易导致该最终的高精度产品的阻抗控制超标。所述步骤S3， 通过在开料后，选取同批次的芯板及半固化片，重新测试得到开料后的H 1、H 2、Er 1、Er 2值，然后将H 1与H 0、H 2与H 0′、Er 1与Er 0、Er 2与Er 0′分别进行对比，根据预设厚度控制公差及预设介电常数控制公差进行相应调整修正，得到新的阻抗设计参数，进而对根据实际生产因素对阻抗控制进行调整，可解决印制电路板因生产因素导致内层阻抗难以控制的问题，提高产品的阻抗合格率。
可选地，可采用九点法测试、计算获得芯板及半固化片的厚度值，可采用谐振腔法测试获得芯板及半固化片的介电常数值。选取该开料后的同批次的芯板及半固化片时，可选取1～3片芯板及1～3片半固化片分别进行测试，然后取平均值获得相应的厚度值及介电常数值，测试更加精确，对阻抗控制也更加精确。可选地，预设厚度控制公差可以为±1％，在预设厚度控制公差内是指≤±1％，在预设厚度控制公差以外是指＞±1％。预设介电常数控制公差可以为±0.1，在预设介电常数控制公差内是指≤±0.1，在预设介电常数控制公差以外是指＞±0.1。进而，对内层阻抗的控制精度高，可满足实际需求。
S4、制作内层线路：对经过步骤S3后的阻抗线所在层的芯板进行内层线路制作，在显影后、蚀刻前测试获得阻抗线所在层的芯板的实际铜厚值T，将(T-T′)与T 0进行对比，若(T-T′)与T 0的差异在预设铜厚控制公差内，则选用步骤S3中获得的新的阻抗设计参数作为最新的阻抗设计参数；若(T-T′)与T 0的差异在预设铜厚控制公差以外，则将T带入阻抗设计软件进行优化阻抗设计，并输出调整后的第二阻抗设计参数作为最新的阻抗设计参数，其中，T′表示棕化影响值；制作FA板进行蚀刻，蚀刻后测试该FA板的实际阻抗设计参数，并将实际阻抗设计参数与最新的阻抗设计参数进行对比，若两者差异在预设阻抗参数控制公差内，则可进行后续批量生产；若两者差异在预设阻抗参数控制公差以外，则调整蚀刻的生产参数，重新制作FA板并测试蚀刻后的阻抗设计参数，直至差异在预设阻抗参数控制公差内，则以调整后的蚀刻的生产参数进行批量生产。
所述步骤S4，通过在制作内层线路时，测试显影后、蚀刻前的阻抗线所在层的芯板的实际铜厚值T，并将(T-T′)与T 0进行对比，进而根据预设铜厚控 制公差对阻抗设计参数进行进一步的调整修正，得到最新的阻抗设计参数，然后再根据实际蚀刻生产时对阻抗的影响对蚀刻的生产参数进行调整修正，可有效解决印制电路板因生产因素导致内层阻抗难以控制的问题，提高产品的阻抗合格率。此外，在对比过程中，还充分考虑后续的棕化影响，对阻抗控制更加精确，能够有效提高产品的阻抗合格率。
本实施例中，对经过步骤S3后的阻抗线所在层的芯板进行内层线路制作的具体步骤为：采用化学微蚀方法对芯板表铜进行粗化、清洁，而后贴膜，并采用LDI曝光机进行图形转移。可采用铜厚测量仪测试实际铜厚值T。同样的，当上述芯板及半固化片均为1～3片时，可分别进行测试，然后取平均值获得相应的铜厚值，测试更加精确。可选地，预设铜厚控制公差可以为±1μm，在预设厚度控制公差内是指≤±1μm，在预设厚度控制公差以外是指＞±1μm，对阻抗控制精度高。可选地，所述T′为0.5μm，符合实际棕化影响。
进一步地，在所述步骤S4中，在以调整后的蚀刻的生产参数进行批量生产步骤之后，还包括步骤：在批量生产过程中进行抽测检验，测试蚀刻后产品的阻抗线的阻抗设计参数是否阻在预设阻抗参数控制公差内，若在，继续进行批量生产；若不在，则根据测试结果对蚀刻的生产参数进行调整。通过进行抽测检验，能够根据测试结果实时微调蚀刻参数，进一步控制内层线路的内层阻抗，使得多层印制电路板的内层阻抗满足高精度要求，有效提高阻抗合格率。
S5、后处理形成多层板结构的印制电路板。
所述印制电路板的制作方法，首先根据客户需求依次进行层叠结构设计及阻抗设计，得到印制电路板的各介质层的各初始参数，进而通过阻抗设计软件得到印制电路板中的阻抗线的初始阻抗设计参数，然后在开料后根据实际开料后的材料实际参数对初始阻抗设计参数进行调整修正，接着又在制作内层线路的过程中根据实际生产因素影响对新的阻抗设计参数进行调整修正，对蚀刻的生产参数进行调整，得到多层板结构的印制电路板。
一般地，影响PCB阻抗的因素主要有线宽、介质层厚度、铜厚、介电常数、阻焊层厚度等。外层阻抗线的阻抗控制比内层更加困难，且外层微带线的线路 损耗等也比内层带状线更大，因而高速PCB产品的高速阻抗线一般布置在PCB的内层。所述印制电路板的制作方法，可提供一种高精度内层阻抗的多层印制电路板的制作方法，通过开料及制作内层线路的制作过程中对影响阻抗值的因素进行纠正，可解决印制电路板因生产过程中各因素导致内层阻抗难以控制的问题，稳定地控制印制电路板的内层阻抗满足高精度的要求，提高印制电路板的高速信号传输性能，进而能够提高印制电路板的阻抗合格率，降低阻抗报废率，降低生产成本，减少因阻抗不良问题而导致的交期延误问题，尤其适用于高精度阻抗产品(内层阻抗控制精度小于±10％,如为±7％、±5％公差)的制作，能够有效改善高精度阻抗产品的阻抗合格率低的问题。
进一步地，如图1、图2所示，在步骤S1之前，所述印制电路板的制作方法还包括步骤：
S0、文件优化设计：印制电路板布线完成后，在印制电路板的图形设计的空旷区及/或孤立线区域铺设平衡铜点。通过在PCB的图形设计的空旷区、孤立线等区域铺设平衡铜点，能够提升图形的残铜分布均匀性，进而达到高精度阻抗控制的要求。本实施例中，平衡铜点可根据实际情况进行铺设，对PCB文件进行适当优化，在不影响PCB电气性能的基础上，达到高精度阻抗控制要求。可选地，所述平衡铜点可铺设为一定尺寸、间距的正方形或圆形，其大小、间距可依据图形区域的残铜率进行确定，保证铺设的平衡铜点区域的残铜率与图形区域相当。
进一步地，所述步骤S5具体包括以下步骤：
S51、棕化、压合：将阻抗线所在层的芯板进行棕化处理获得棕化层，并采用开料后的同批次的半固化片进行叠合，使得半固化片位于芯板之间，形成叠层板，通过热压工艺对叠合板进行压合形成多层板；
S52、钻孔、电镀、外层线路蚀刻、阻焊：对多层板进行钻孔、电镀、外层线路蚀刻以及阻焊制作，形成完整的多层板结构的印制电路板。具体地，步骤S52中可采用常规阻抗控制精度的印制电路板制作工艺进行制作。
通过采用上述步骤，可对经过S4步骤控制后的批量生产的产品进行后续处 理，进而得到多层板结构的印制电路板。
进一步地，在步骤S51中：进行热压工艺时，调整材料的压合程序，调整叠板时缓冲材料的用量，使得材料的升温速率下调0.2℃/min～0.5℃/min。具体地，材料的升温速率相对于常规制作参数下调0.2℃/min～0.5℃/min。进而，在保证填胶良好的情况下可改善介质层的厚度均匀性，进一步降低阻抗控制难度，提高产品的阻抗合格率。进一步地，在步骤S51与S52之间，芯板不能进行返工处理，以免影响阻抗控制。
本实施例中，在步骤S5之后，所述印制电路板的制作方法还包括以下步骤：
S6、阻抗测试：采用TDR设备测试批量生产后的印制电路板的阻抗值，并根据阻抗控制公差判定印制电路板的内层阻抗是否合格。进而，能够对制作后的产品进行检测，判断产品的内层阻抗是否合格，操作方便。本实施例中，可采用上升时间小于35ps的TDR的设备进行测试，可测试高精度内层阻抗的印制电路板的阻抗值。
本实施例所述的印制电路板的制作方法，通过对印制电路板进行文件优化设计、叠层结构设计、阻抗设计等，在生产过程中对影响阻抗值的各因素进行监控和实时调整，能够解决印制电路板因设计和生产等因素导致内层阻抗难以控制的问题，可稳定地控制多层印制电路板的内层阻抗满足高精度的要求，并可显著提高同一块大板中不同区域信号线的阻抗均匀性，避免PCB中高速信号线因阻抗不匹配问题而引起信号反射和失真等信号完整性问题，从而提高印制电路板的高速信号传输性能，显著提升高精度阻抗PCB的阻抗合格率，降低阻抗报废率及其带来的交期延误问题等，其具有可操作性强、效果良好、有效提升阻抗合格率等优点。
一种印制电路板，采用如上所述的印制电路板的制作方法制作得到。具体地，本实施例的印制电路板为多层板结构，其包括多张芯板和半固化片，所述芯板经制作形成线路图形，多张芯板与半固化片组合，并经压合获得多层印制电路板。并且，该印制电路板的传输线有内层阻抗控制要求，其内层阻抗控制精度为小于±10％如±7％、±5％公差的高精度控制要求。所述印制电路板，采用 上述的印制电路板的制作方法制作得到，产品的阻抗合格率高、生产成本低，不易出现阻抗不良问题。
为了更充分理解本实施例的印制电路板的制作方法，下面结合一具体实例对该制作方法进行详细介绍和说明：
如图3所示，需制作的印制电路板为8层结构，各层的排列分别如下：ART01层为SIG01层，ART02层为GND01层，ART03层为SIG02层，ART04层为GND02层，ART05层为POWER层，ART06层为SIG03层，ART07层为GND03层，ART08层为SIG04层。其中，SIG02层、SIG03层为高速信号的阻抗线的布线层，其中，每层均布置有单端阻抗线300和差分阻抗线400，阻抗线的阻抗精度要求严格，阻抗控制公差在±5％以内。对于此高精度内层阻抗的印制电路板的制作方法对应包括以下步骤：
S0、文件优化设计：对PCB文件进行适当优化，在PCB拼版的内层图形空旷区、孤立线等区域铺设平衡铜点，提升图形的残铜分布均匀性，其中，平衡铜点可铺设为圆形，圆的直径可为1.25mm，相邻圆上下左右的中心距可为2mm。
S1、叠层结构设计：根据PCB的板厚、电源层、地层等的设计要求以及PCB上信号的频率、速率等要求，选择Low Dk/Low Loss的改性FR4材料进行叠层结构设计。其中，可根据经验设计得到SIG01层到GND01层的介质层(半固化片100)、GND01层到SIG02层的介质层(芯板200)、SIG02层到GND02层的介质层(半固化片100)、GND02层到POWER层的介质层(芯板200)、POWER层到SIG03层的介质层(半固化片100)、SIG03层到GND03层的介质层(芯板200)、GND03层到SIG04层的介质层(半固化片100)的初始介质层厚度和初始介电常数。并设计得到SIG01层、GND01层、GND03层和SIG04层的初始铜厚值均为18μm，SIG02层、SIG03层、GND02层和POWER层的初始铜厚值均为12μm。铜箔类型均可选择VLP类型。
S2、阻抗设计：叠层结构设计完成后，根据阻抗控制要求及S1中得到的数据，采用阻抗设计软件进行相应的阻抗设计，获得印制电路板的各阻抗线的初始阻抗设计参数。在该实例中，SIG02层和SIG03层的阻抗线有阻抗控制要求， 且SIG02层和SIG03层的阻抗线为高速信号传输线，阻抗控制公差要求为±5％，各阻抗层的单端阻抗要求值为50ohm，差分阻抗的要求值为100ohm。SIG02层的参考屏蔽层为GND01层和GND02层，SIG03层的参考屏蔽层为POWER层和GND03层。可通过阻抗设计软件计算出满足上述工艺条件的单端阻抗线的初始阻抗设计参数即初始上线宽值W 10和初始下线宽值W 20，差分阻抗线的初始阻抗设计参数即初始上线宽值W 10、初始下线宽值W 20和初始下线宽值W 20/初始线距值S 0。
S3、开料及优化阻抗设计：按照PCB拼版尺寸将指定材料的芯板和半固化片裁减成一定尺寸。以SIG02层的单端阻抗线300为例，选取可用于ART02层和ART03层的芯板3张，用九点法测试每块芯板的厚度并计算均值得到H 1，选取可用于ART03层和ART04层的半固化片3张分别压合成板，用九点法测试其厚度并计算均值得到H 2，采用谐振腔法实测芯板和半固化片的介电常数分别Er 1和Er 2，分别将H 1、H 2、Er 1、Er 2与对应的H 0、H 0′、Er 0、Er 0′进行对比，得到SIG02层的单端阻抗线的新的阻抗设计参数。同样的，对于SIG02层的差分阻抗线、SIG03层的单端阻抗线以及SIG03层的差分阻抗线均可采用上面步骤得到对应的新的阻抗设计参数。
S4、制作内层线路：采用化学微蚀方法对芯板表铜进行粗化、清洁，而后贴覆25μm厚度的LDI干膜，并采用LDI曝光机进行图形转移。在显影后、蚀刻前采用铜厚测量仪测试ART03层和ART06层的芯板的实际铜厚值分别为T 1和T 2，将(T 1-0.5)与ART03层的初始铜厚值进行对比，将(T 2-0.5)与ART06层的初始铜厚值进行对比，获得各层的阻抗线的最新的阻抗设计参数。进一步地，选择ART02与ART03层、ART06与ART07层的芯板各一块作为FA板，采用4.2m/min的蚀刻速度制作首板，蚀刻完成后采用线宽测量仪测试ART03层和ART06层的阻抗线的实际阻抗设计参数，然后分别与上一步中最新的阻抗设计参数进行对比，确定是以该蚀刻时的生产参数进行生产还是对生产参数进行调整，直至满足条件后以调整后的蚀刻的生产参数进行批量生产。在批量生产过程中每10块芯板抽测一块进行实际阻抗设计参数检测，根据测试结果实时微调蚀刻生产参数。
S51、棕化、压合：将上述线宽控制合格的芯板进行棕化处理线获得棕化层，并采用前述测试过厚度、介电常数的同批次半固化片经邦定、打铆钉形成叠合板，半固化片位于芯板之间，并通过热压工艺对叠合板进行压合形成多层板。进一步地，压合时优化调整将压合程序升温段时间延长3min，叠板时牛皮纸的用量与常规上板相一致，使得实测材料的升温速率相比于正常参数3.2℃/min下降至2.8℃/min。
S52、钻孔、电镀、外层线路蚀刻、阻焊等：按常规阻抗控制精度的印制电路板制作工艺进行钻孔、电镀、外层线路蚀刻、阻焊等制作，形成结构完整的8层板结构的印制电路板；
S6、阻抗测试：采用上升时间为22.3ps的矢量网络分析仪测试该8层板结构的印制电路板的阻抗值，判断各阻抗值是否均满足±5％公差的要求，判断产品是否合格。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种印制电路板的制作方法，其特征在于，包括以下步骤：
    S1、层叠结构设计：根据印制电路板的设计要求进行叠层结构设计，得到印制电路板的各介质层的初始介质层厚度和初始介电常数，得到印制电路板的各层的初始铜厚值，其中，印制电路板的阻抗线所在层的初始介质层厚度为H 0、初始介电常数为Er 0、初始铜厚值为T 0，作为该阻抗线的屏蔽层的初始介质层厚度为H 0′、初始介电常数为Er 0′；
    S2、阻抗设计：根据印制电路板的阻抗控制要求，采用阻抗设计软件进行阻抗设计，获得印制电路板的阻抗线的初始阻抗设计参数；
    S3、开料及优化阻抗设计：根据PCB拼版尺寸将芯板和半固化片进行开料，选取该开料后的同批次的芯板及半固化片进行测试，获得阻抗线所在层的实际芯板厚度H 1和实际芯板介电常数Er 1，获得作为该阻抗线的屏蔽层的实际半固化片厚度H 2和实际半固化片介电常数Er 2，分别将H 1、H 2、Er 1、Er 2与对应的H 0、H 0′、Er 0、Er 0′进行对比，若H 1、H 2与H 0、H 0′的差异在预设厚度控制公差内，Er 1、Er 2与Er 0、Er 0′的差异在预设介电常数控制公差内，则仍选用步骤S2中获得的初始阻抗设计参数作为新的阻抗设计参数；若H 1、H 2与H 0、H 0′的差异在预设厚度控制公差以外，Er 1、Er 2与Er 0、Er 0′的差异在预设介电常数控制公差以外，则将H 1、H 2、Er 1、Er 2带入阻抗设计软件进行优化阻抗设计，并输出调整后的第一阻抗设计参数作为新的阻抗设计参数；
    S4、制作内层线路：对经过步骤S3后的阻抗线所在层的芯板进行内层线路制作，在显影后、蚀刻前测试获得阻抗线所在层的芯板的实际铜厚值T，将(T-T′)与T 0进行对比，若(T-T′)与T 0的差异在预设铜厚控制公差内，则选用步骤S3中获得的新的阻抗设计参数作为最新的阻抗设计参数；若(T-T′)与T 0的差异在预设铜厚控制公差以外，则将T带入阻抗设计软件进行优化阻抗设计，并输出调整后的第二阻抗设计参数作为最新的阻抗设计参数，其中，T′表示棕化影响值；
    制作FA板进行蚀刻，蚀刻后测试该FA板的实际阻抗设计参数，并将实际 阻抗设计参数与最新的阻抗设计参数进行对比，若两者差异在预设阻抗参数控制公差内，则可进行后续批量生产；若两者差异在预设阻抗参数控制公差以外，则调整蚀刻的生产参数，重新制作FA板并测试蚀刻后的阻抗设计参数，直至差异在预设阻抗参数控制公差内，则以调整后的蚀刻的生产参数进行批量生产；
    S5、后处理形成多层板结构的印制电路板。
  2. 根据权利要求1所述的印制电路板的制作方法，其特征在于，在步骤S1之前，还包括步骤：
    S0、文件优化设计：印制电路板布线完成后，在印制电路板的图形设计的空旷区及/或孤立线区域铺设平衡铜点。
  3. 根据权利要求1所述的印制电路板的制作方法，其特征在于，在所述步骤S1中：印制电路板的阻抗线所在层的芯板的初始介质层厚度＞100μm，及/或，作为该阻抗线的屏蔽层的半固化片的初始介质层厚度＞100μm。
  4. 根据权利要求1所述的印制电路板的制作方法，其特征在于，在所述步骤S1中：印制电路板的阻抗线所在层的初始铜厚值为8μm、12μm或18μm，作为该阻抗线的屏蔽层的初始铜厚值为8μm、12μm或18μm。
  5. 根据权利要求1所述的印制电路板的制作方法，其特征在于，在所述步骤S1中：印制电路板的各介质层均为低介电常数特性材料。
  6. 根据权利要求1所述的印制电路板的制作方法，其特征在于，所述步骤S5具体包括以下步骤：
    S51、棕化、压合：将阻抗线所在层的芯板进行棕化处理获得棕化层，并采用开料后的同批次的半固化片进行叠合，使得半固化片位于芯板之间，形成叠层板，通过热压工艺对叠合板进行压合形成多层板；
    S52、钻孔、电镀、外层线路蚀刻、阻焊：对多层板进行钻孔、电镀、外层线路蚀刻以及阻焊制作，形成完整的多层板结构的印制电路板。
  7. 根据权利要求6所述的印制电路板的制作方法，其特征在于，在所述步骤S51中：进行热压工艺时，调整材料的压合程序，调整叠板时缓冲材料的用量，使得材料的升温速率下调0.2℃/min～0.5℃/min。
  8. 根据权利要求1所述的印制电路板的制作方法，其特征在于，在所述步骤S4中，在以调整后的蚀刻的生产参数进行批量生产步骤之后，还包括步骤：在批量生产过程中进行抽测检验，测试蚀刻后产品的阻抗线的阻抗设计参数是否阻在预设阻抗参数控制公差内，若在，继续进行批量生产；若不在，则根据测试结果对蚀刻的生产参数进行调整。
  9. 根据权利要求1-8任一项所述的印制电路板的制作方法，其特征在于，在步骤S5之后，还包括以下步骤：
    S6、阻抗测试：采用TDR设备测试批量生产后的印制电路板的阻抗值，并根据阻抗控制公差判定印制电路板的内层阻抗是否合格。
  10. 一种印制电路板，其特征在于，采用如权利要求1-9任一项所述的印制电路板的制作方法制作得到。
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