WO2018223865A1 - 一种电路的工作状态的检测方法及检测装置 - Google Patents

一种电路的工作状态的检测方法及检测装置 Download PDF

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Publication number
WO2018223865A1
WO2018223865A1 PCT/CN2018/088745 CN2018088745W WO2018223865A1 WO 2018223865 A1 WO2018223865 A1 WO 2018223865A1 CN 2018088745 W CN2018088745 W CN 2018088745W WO 2018223865 A1 WO2018223865 A1 WO 2018223865A1
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neural network
circuit
fault
state
sample set
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PCT/CN2018/088745
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English (en)
French (fr)
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毕海峰
唐乌力吉白尔
连龙
王晓杰
郝瑞军
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/329,902 priority Critical patent/US11017700B2/en
Priority to EP18814279.8A priority patent/EP3637117A4/en
Publication of WO2018223865A1 publication Critical patent/WO2018223865A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2846—Fault-finding or characterising using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/047—Probabilistic or stochastic networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N7/00—Computing arrangements based on specific mathematical models
    • G06N7/01—Probabilistic graphical models, e.g. probabilistic networks
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of detection technologies, and in particular, to a method and a detection device for detecting an operating state of a circuit.
  • TFT-LCD thin film transistor-liquid crystal display
  • GOA Gate Driver on Array
  • Hard faults refer to open or short circuits of components, in the GOA circuit.
  • a soft fault is when the component's parameters exceed its predetermined tolerance range. When there is a soft fault in the GOA circuit, it will not directly lead to complete failure of the product, but it will still affect the display performance of the product.
  • a first aspect of the present disclosure provides a method for detecting an operating state of a circuit, including: forming a neural network that acquires a state category of a circuit to be tested; and measuring an electrical characteristic parameter of at least one node in the circuit to be tested, and measuring the measured An electrical characteristic parameter of at least one node is input to the neural network, and a state category of the circuit under test is obtained through the neural network.
  • forming a neural network that acquires a state class of the circuit under test includes: constructing a neural network model; constructing a fault training sample set, wherein the fault training sample set includes a plurality of state categories and among the plurality of state categories An electrical characteristic parameter of at least one node of the circuit under test corresponding to each state category, the plurality of state categories including a normal state of the circuit to be tested and at least one fault state; according to the fault training sample set, The neural network model is trained to obtain a neural network after training, and the neural network is used to acquire a state category of the circuit to be tested.
  • constructing the fault training sample set includes: setting the circuit to be tested according to each of the plurality of state categories, and measuring an electrical characteristic parameter of at least one node in the set circuit to be tested; Constructing a fault training sample set by the plurality of state categories and electrical characteristic parameters of at least one node corresponding to each of the plurality of state categories.
  • setting the circuit under test according to each of the plurality of status categories includes at least one of: in the case where the plurality of status categories includes at least one hard fault status category, Setting, in the circuit under test, an element corresponding to each of the at least one hard fault state category as a short circuit state or an open circuit state; and, in the plurality of state categories, including at least one soft fault state
  • a parameter of an element corresponding to each of the at least one soft fault state category in the circuit to be tested is set to exceed a tolerance range thereof, and the set circuit to be tested is set Perform Monte Carlo transient analysis.
  • the neural network model is trained according to the fault training sample set, and the neural network after the training is completed includes: constructing a fault sample target set, wherein the fault sample target set is Corresponding relationship between the binary code output by the neural network and the plurality of state categories; inputting the fault training sample set into the neural network model to train the neural network model to obtain the trained nerve The internet.
  • the method before the constructing the fault sample target set, the method further includes: performing electrical characteristic parameter data of the at least one node corresponding to each of the plurality of state categories in the fault training sample set Dimensional processing.
  • forming a neural network that acquires a state class of the circuit under test includes: constructing a set of corrected samples, wherein the set of corrected samples includes a plurality of state categories and corresponding to each of the plurality of state categories The electrical characteristic parameter of the at least one node of the circuit to be tested; after the training the neural network model according to the fault training sample set, and obtaining the trained neural network, the method further includes: according to the Correct the sample set and correct the neural network after the training is completed.
  • constructing the calibration sample set includes: setting the circuit to be tested according to each of the plurality of state categories, and measuring an electrical characteristic parameter of at least one node in the set circuit to be tested; A plurality of state categories and electrical characteristic parameters of at least one node corresponding to each of the plurality of state categories are constructed to construct a corrected sample set.
  • setting the circuit under test according to each of the plurality of status categories includes at least one of: in the case where the plurality of status categories includes at least one hard fault status category, Setting, in the circuit under test, an element corresponding to each of the at least one hard fault state category as a short circuit state or an open circuit state; and, in the plurality of state categories, including at least one soft fault state
  • a parameter of an element corresponding to each of the at least one soft fault state category in the circuit to be tested is set to exceed a tolerance range thereof, and the set circuit to be tested is set Perform Monte Carlo transient analysis.
  • correcting the trained neural network according to the corrected sample set includes: concentrating the corrected sample set with electrical characteristics of at least one node corresponding to each of the plurality of state categories
  • the neural network after the training is completed outputs a binary code
  • the output binary code and the correction sample set are between the state categories corresponding to the electrical characteristic parameters of the at least one node.
  • Corresponding relationship is compared with the target set of the fault samples, and determining whether the output result of the neural network is accurate. If the judgment is accurate, the neural network after the training is used to perform fault detection on the circuit to be tested, if Inaccurate, the neural network after training is retrained.
  • a second aspect of the present disclosure provides a device for detecting an operating state of a circuit, comprising: a neural network forming module for forming a neural network for acquiring a state category of a circuit to be tested; and a measuring module for measuring the circuit to be tested The electrical characteristic parameter of the at least one node; the detecting module is respectively connected to the neural network forming module and the measuring module, and the detecting module is configured to acquire the electrical power of the neural network and at least one node of the circuit to be tested And a characteristic parameter, the acquired electrical characteristic parameter of the at least one node is input to the neural network, and the state category of the circuit to be tested is obtained through the neural network.
  • the neural network forming module includes: a model building sub-module for constructing a neural network model; a training sample set building sub-module for constructing a fault training sample set; a training sub-module, and the model constructor
  • the module, the training sample set construction sub-module and the detection module are respectively connected, the training sub-module is configured to acquire the fault training sample set and the neural network model, and the neural network model is set according to the fault training sample set
  • the network model is trained to obtain the neural network after the training is completed.
  • the training sample set construction sub-module includes at least one of a hard fault training sample set construction unit and a soft fault training sample set construction unit coupled to the training sub-module, wherein the hard fault training sample The set building unit is configured to construct a hard fault training sample set; the soft fault training sample set building unit is configured to construct a soft fault training sample set.
  • the training sub-module includes: a target set construction unit, configured to construct a fault sample target set, where the fault sample target set is a correspondence between a binary code output by the neural network and the plurality of status categories a training execution unit, which is respectively connected to the detection module, the target set construction unit, the model construction sub-module, and the training sample set construction sub-module, wherein the training execution unit is configured to acquire the fault sample target Collecting, the fault training sample set and the neural network model, inputting the fault training sample set into the neural network model, training the neural network according to the fault sample target set, and obtaining training after completion Neural Networks.
  • the training sub-module further includes: a dimension reduction unit respectively connected to the training sample set construction sub-module and the training execution unit, wherein the dimension reduction unit is configured to focus on the fault training sample
  • the electrical characteristic parameter data of at least one node corresponding to each of the different state categories is subjected to dimensionality reduction processing.
  • the neural network forming module includes a corrected sample set construction sub-module for constructing a corrected sample set; the training sub-module includes a separate connection with the corrected sample set construction sub-module and the training execution unit a correction unit, configured to correct the neural network after the training is completed according to the corrected sample set.
  • the corrected sample set construction sub-module includes at least one of a hard fault correction sample set construction unit and a soft fault correction sample set construction unit coupled to the correction unit; wherein the hard fault correction sample set The building block is used to construct a hard fault correction sample set; the soft fault correction sample set building unit is used to construct a soft fault correction sample set.
  • a third aspect of the present disclosure provides a computer readable storage medium configured to store computer instructions that, when executed by a processor, perform a method of detecting an operational state of a circuit as described in the first aspect of the present disclosure One or more steps in .
  • a fourth aspect of the present disclosure provides a computer product comprising one or more processors configured to execute computer instructions to perform detection of an operational state of a circuit as in the first aspect of the present disclosure One or more steps in the method.
  • FIG. 1 is a first flowchart of a method for detecting an operating state of a circuit according to Embodiment 1 of the present invention
  • FIG. 2 is a second flowchart of a method for detecting an operating state of a circuit according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic diagram of a topology structure of a probabilistic neural network model according to Embodiment 1 of the present invention.
  • FIG. 4 is a third flowchart of a method for detecting an operating state of a circuit according to Embodiment 1 of the present invention.
  • FIG. 5 is a flowchart 4 of a method for detecting an operating state of a circuit according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural diagram of a resistor circuit according to Embodiment 1 of the present invention.
  • FIG. 7 is a schematic structural diagram of a GOA circuit according to Embodiment 1 of the present invention.
  • FIG. 8 is a schematic structural diagram 1 of a device for detecting an operating state of a circuit according to a second embodiment of the present invention.
  • FIG. 9 is a second schematic structural diagram of a device for detecting an operating state of a circuit according to Embodiment 2 of the present invention.
  • the failure of the GOA circuit is generally detected by microscopically examining the GOA region under a microscope, but this method can only detect hard faults and cannot identify soft faults of the GOA circuit. Therefore, it is necessary to additionally determine whether the GOA film layer is abnormal by TFT characteristic test or scanning electron microscope (SEM) slicing, and then detect the soft fault of the GOA circuit.
  • SEM scanning electron microscope
  • the present embodiment provides a method for detecting an operating state of a circuit.
  • the method for detecting an operating state of the circuit may include: step S1, forming a neural network for acquiring a state category of the circuit to be tested; and step S2; Measuring electrical characteristic parameters of at least one node in the circuit to be tested; and step S3, inputting the measured electrical characteristic parameters of at least one node into the neural network, and obtaining a state category in the circuit to be tested through the neural network.
  • the state class of the circuit to be tested can be obtained through the neural network.
  • the detection method of the working state of the circuit provided by this embodiment is based on a neural network. Since the neural network has the advantages of self-learning, massive parallelism, distributed storage, and processing data, the neural network can continuously optimize itself during the detection process. To improve the accuracy and efficiency of the computational analysis. Therefore, using the neural network to detect the state categories in the circuit to be tested can improve the accuracy of the detection.
  • the state category in the circuit to be tested is obtained, that is, the circuit to be tested is obtained.
  • the working state eliminates the need for microscopy, TFT characterization, or SEM slicing of the circuit to be tested, which saves time and reduces the complexity of manual analysis. Therefore, by using the detection method of the operating state of the circuit provided in the embodiment, the operating state of the circuit can be detected accurately and quickly.
  • the “forming a neural network that acquires the state category of the circuit under test” mentioned in step S1 may obtain a neural network based on the structure of the circuit, and may also use an off-the-shelf neural network. Moreover, when the neural network is obtained based on the circuit structure, it can be obtained according to the structure of the circuit to be tested itself, or can be obtained according to the structure of other circuits having the same structure as the circuit to be tested.
  • the electrical characteristic parameter of the node may be a node voltage parameter, a node current parameter, or a node power parameter of the node.
  • the disclosure does not limit the disclosure. .
  • the normal state included in the status category refers to the state in which the circuit under test is fault-free and in normal operation.
  • step S1 may specifically include: step S11, constructing a neural network model; step S12: constructing a fault training sample set, wherein the fault training sample set may include multiple status categories and each of the plurality of status categories The electrical characteristic parameter of at least one node of the circuit to be tested corresponding to the status category, and the plurality of status categories may include a normal state of the circuit to be tested and at least one fault state; and step S13, according to the fault training sample set, the neural network model The training is performed to obtain the neural network after the training is completed, and the neural network after the training is completed is used to acquire the state category of the circuit to be tested.
  • the training of the neural network model according to the fault training sample set refers to electrical characteristics of at least one of the plurality of state categories in the fault training sample set and the at least one node of the circuit to be tested corresponding to each of the plurality of state categories.
  • the parameter is input into the neural network, so that the neural network correctly grasps the correspondence between the electrical characteristic parameter of the at least one node and the state category, so that after the training of the neural network is completed, at least one node in the circuit to be tested is After the electrical characteristic parameter is input to the neural network, the trained neural network can accurately output the status category corresponding to the input electrical characteristic parameter of at least one node.
  • the process of training a neural network model can also be referred to as a learning process of a neural network model.
  • the neural network after the training is completed has a strong generalization ability, and the correct mapping relationship between input and output is obtained, thereby further improving the accuracy of the neural network operation analysis.
  • the step S11 may specifically include: constructing a probabilistic neural network model according to a newpnn() function used in the Matlab neural network toolbox for designing a neural network model.
  • the constructed probabilistic neural network model is used to obtain the state category of the circuit to be tested.
  • Probabilistic neural network models include input nodes, output nodes, and input/output control algorithms.
  • the circuit to be tested includes N nodes
  • the probabilistic neural network model when the probabilistic neural network model is subsequently trained, for example, the electrical characteristic parameters of the corresponding N nodes in each of the plurality of state categories may be combined into an N-dimensional vector. Input into the probabilistic neural network model. Therefore, the number of input nodes of the constructed probabilistic neural network model needs to be equal to the dimension N of the input vector, that is, the number of input nodes of the probabilistic neural network model is equal to the number of nodes in the circuit to be tested.
  • the electrical characteristic parameters of N nodes By using the electrical characteristic parameters of N nodes to train the probabilistic neural network model, it can further ensure that the probabilistic neural network after training has the correct mapping relationship between input and output. Of course, it is also possible to input only the electrical characteristic parameters of some of the N nodes into the probabilistic neural network model. At this time, the number of input nodes of the probabilistic neural network model is smaller than the number of nodes in the circuit to be tested.
  • the number of output nodes of the constructed probabilistic neural network model should be equal to The number M of state categories in the circuit is measured, that is, the number of output nodes of the probabilistic neural network model is equal to the number of state categories in the circuit to be tested.
  • the probabilistic neural network model has N input nodes: x 1 ⁇ x N , and M output nodes: y 1 ⁇ y M .
  • the constructed neural network model is a probabilistic neural network model, and the probabilistic neural network model is based on the development of Bayes minimum risk compared with the traditional BP neural network model.
  • the step S12 may specifically include: setting a circuit to be tested according to each of the plurality of state categories, and measuring an electrical characteristic parameter of the at least one node in the set circuit to be tested; and, according to the multiple states
  • a fault training sample set is constructed by class and electrical characteristic parameters of at least one node corresponding to each of the plurality of state categories.
  • the state class of the circuit can include a normal state of the circuit under test and at least one fault state, wherein the fault state typically includes a hard fault state and a soft fault state. Therefore, the fault training sample set constructed in step S12 may specifically include at least one of a hard fault training sample set and a soft fault training sample set. Based on this, the step of “setting the circuit to be tested according to each of the plurality of state categories” may specifically include at least one of the following operations:
  • the plurality of status categories includes at least one hard fault status category
  • an element in the circuit under test corresponding to each of the at least one hard fault status category is set to a short circuit state or an open circuit state.
  • electrical characteristic parameters of at least one of the nodes to be tested corresponding to each of the at least one hard fault state category are acquired.
  • a hard fault training sample set is constructed based on at least one hard fault state category and electrical characteristic parameters of at least one node corresponding to each of the at least one hard fault state category.
  • a parameter of an element corresponding to each of the at least one soft fault status category in the circuit to be tested is set to exceed a tolerance range thereof, Monte Carlo transient analysis of the set circuit to be tested is performed, for example, by PSPICE software.
  • electrical characteristic parameters of at least one of the nodes to be tested corresponding to each of the at least one soft fault state category are acquired.
  • a soft fault training sample set is constructed based on at least one soft fault state category and electrical characteristic parameters of at least one node corresponding to each of the at least one soft fault state category.
  • the short circuit or open circuit of the component can be artificially set by using equipment such as laser cutting, and when the node voltage is obtained, the PSPICE software can be used to set the circuit to be tested.
  • the Monte Carlo transient analysis is performed to obtain electrical characteristic parameters of at least one node of the circuit to be tested corresponding to each of the plurality of state categories, and may also be acquired by means of actual measurement.
  • the PSPICE software is a simulation software with powerful circuit diagram drawing function, circuit simulation function, graphic post-processing function and component symbol creation function.
  • the PSPICE software is used to perform Monte Carlo on the set circuit to be tested. State analysis can achieve good simulation analysis results.
  • step S13 may specifically include: in step S131, constructing a fault sample target set.
  • the fault sample target set is a correspondence between a binary code output by the neural network and a plurality of status categories.
  • the circuit under test may include three state categories, such as state class A, state class B, and state class C, and the neural network includes three output nodes, each output node outputting a string of binary codes.
  • the fault sample target set includes: the binary code corresponding to the neural network output 100 corresponds to the status category A, the binary code of the neural network output 010 corresponds to the status category B, and the binary code of the neural network output 001 corresponds to the status category C.
  • step S132 the fault training sample set is input into the neural network model to train the neural network model, and the trained neural network is obtained.
  • the neural network after the completion of the training needs to satisfy: when the electrical characteristic parameter of the at least one node currently measured is input to the neural network after the completion of the training, the state of the binary code outputted by the neural network after the training is completed in the target set of the fault sample.
  • the category is consistent with the status category in which the current circuit under test is actually located.
  • the electrical characteristic parameters of the nodes corresponding to the state category A are input to the neural network after the training is completed, and the binary code of the neural network output after the training is completed should be 100; the electrical characteristics of the nodes corresponding to the state category B are The parameter is input to the neural network after the training is completed.
  • the binary code of the neural network output after the training is completed should be 010; the electrical characteristic parameters of each node corresponding to the state category C are input to the neural network after the training is completed, and the trained nerve is completed.
  • the binary code for the network output should be 001.
  • the method for detecting the working state of the circuit may further include: step S130:
  • the electrical characteristic parameter data of the at least one node corresponding to each of the plurality of state categories in the training sample set is subjected to dimensionality reduction processing.
  • the Principal Component Analysis (PCA) algorithm may be used to perform dimensionality reduction on the electrical characteristic parameter data in the fault training sample set.
  • step S1 may further include: in step S14, constructing a corrected sample set.
  • the correction sample set includes a plurality of state categories and electrical characteristic parameters of at least one of the nodes to be tested corresponding to each of the plurality of state categories; and, in step S15, the training is performed according to the corrected sample set The completed neural network is corrected.
  • construction correction sample set is executed after step S13 for illustrative purposes only. In practical applications, constructing the calibration sample set may also be performed simultaneously with constructing the fault training sample set.
  • the corrected sample set may include at least one of a hard fault correction sample set and a soft fault correction sample set.
  • the neural network model is trained using only the hard fault training sample set
  • the neural network after the training is completed can be corrected by the hard fault correction sample set.
  • the neural network model is trained using only the soft fault training sample set
  • the neural network after the training is completed can be corrected by the soft fault correction sample set.
  • the neural network model is trained with both the hard fault training sample set and the soft fault training sample set, correspondingly, the neural network after training can be corrected by at least one of the hard fault correction sample set and the soft fault correction sample set.
  • the step S14 may specifically include: setting a circuit to be tested according to each of the plurality of state categories, and measuring an electrical characteristic parameter of the at least one node in the set circuit to be tested; and, according to the plurality of state categories and A set of calibration samples is constructed from electrical characteristic parameters of at least one node corresponding to each of the plurality of state categories.
  • the step of “setting the circuit to be tested according to each of the plurality of state categories” may include at least one of the following operations: in the case where the plurality of state categories includes at least one hard fault state category, the circuit to be tested An element corresponding to each hard fault state category in at least one hard fault state category is set to a short circuit state or an open circuit state; and, in a case where the plurality of state categories includes at least one soft fault state category, in the circuit to be tested The parameters of the components corresponding to each soft fault state category in at least one soft fault state category are set to exceed their tolerance ranges, and Monte Carlo transient analysis is performed on the set circuit to be tested, for example, by PSPICE software.
  • the short circuit or open circuit of the component can be artificially set by using equipment such as laser cutting, and when the node voltage is obtained, the PSPICE software can be used to set the circuit to be tested.
  • the Monte Carlo transient analysis is performed to obtain electrical characteristic parameters of at least one node of the circuit to be tested corresponding to each of the plurality of state categories, and may also be acquired by means of actual measurement.
  • the step S15 may specifically include: inputting, in the neural network after the training is completed, the electrical characteristic parameter of the at least one node corresponding to each of the plurality of state categories in the corrected sample set, and outputting the binary code to the neural network after the training is completed.
  • the correspondence between the output binary code and the correction sample set and the state category corresponding to the input electrical characteristic parameter of at least one node is compared with the fault sample target set to determine whether the output result of the neural network is accurate.
  • the accuracy of the output of the neural network may be compared with a preset threshold. If the accuracy is higher than or equal to the threshold, the output of the neural network is determined to be accurate, and the neural network after the training is completed may be used for the circuit to be tested. Fault detection; if the accuracy is lower than the threshold, it is determined that the output of the neural network is inaccurate, and then the neural network after the training is completed needs to be retrained.
  • the accuracy of the neural network in detecting the working state of the circuit to be tested can be judged. If the judgment is inaccurate, the neural network after the training is completed needs to be re-established. The training is performed until the neural network after the completion of the re-training accurately detects the failure of the circuit to be tested.
  • the detection method is applicable to various circuits, such as a resistor circuit, a single-stage GOA circuit of an LTPS product, etc., and the circuit structure shown in FIG. 6 and FIG. 7 is taken as an example, and the detection method of the working state of the above circuit is described in detail.
  • the circuit shown in Fig. 6 includes 20 resistors (R1 to R20) and 12 nodes (P1 to P12). Assume that the circuit includes eight status categories: one normal state and seven fault states, seven of which include R1+40%, R1-50%, R6 open, R9 short, R18 open, R20+50%, R19+ 50% and R20 is open. Taking R1+40% and R1-50% as examples, R1+40% means that the parameter value of R1 is higher than 40% of the tolerance range, and R1-50% means that the parameter value of R1 is lower than 40% of the tolerance range. All are soft faults.
  • Step H1 Construct a probabilistic neural network model, wherein the probabilistic neural network model includes 6 input nodes, 8 output nodes, and an input/output control algorithm.
  • Step H2 Performing a Monte Carlo transient analysis for each of the eight state categories to obtain nodes P2, P5, P6, P8, P9, and P11 in the circuit under test in each state category.
  • Voltage Among them, the node voltage of 6 nodes in the circuit to be tested obtained by 20 Monte Carlo transient analysis is used to construct the fault training sample set, and the 6 nodes in the circuit to be tested obtained by 10 Monte Carlo transient analysis are The node voltage is used to build a calibration sample set. It should be understood that for each circuit under test in the state category, the voltages of the nodes obtained by the multiple Monte Carlo analysis are different or not identical, so the results of multiple Monte Carlo analysis can be formed. Samples.
  • the fault training sample set contains 160 fault training samples. .
  • the calibration sample set contains 80 calibration samples.
  • Step H3 Performing a dimensionality reduction on the node voltage data of each of the six corresponding eight state categories included in the fault training sample set by using the PCA algorithm.
  • part of the code of the PCA algorithm in the Matlab environment is as follows:
  • Step H4 construct a fault sample target set, wherein the correspondence between the binary code outputted by the probabilistic neural network and the status category is as shown in Table 1:
  • Step H5 Input the fault training sample set after the dimension reduction processing into the probabilistic neural network model, and train the probabilistic neural network model to obtain a probabilistic neural network after the training is completed.
  • the part of the code to train the probabilistic neural network model in the Matlab environment is as follows:
  • Step H6 Extract the node voltage data of the six nodes corresponding to the four state categories R1-50%, R9 short circuit, R18 open circuit and R20+50% from the corrected sample set, and correct the trained neural network.
  • the node voltage data of the six nodes corresponding to the four state categories R1-50%, R9 short circuit, R18 open circuit and R20+50% respectively are as shown in Table 2:
  • the node voltages of the six nodes corresponding to the R1-50% state category are respectively input into the trained probabilistic neural network, and the binary code of the probabilistic neural network output is 00100000; the node voltages of the six nodes corresponding to the R9 short-circuit state category are respectively input.
  • the binary code of the probabilistic neural network output is 00001000; the node voltages of the six nodes corresponding to the R18 open state category are respectively input into the trained probabilistic neural network, and the binary code of the probabilistic neural network output is 00000100.
  • the node voltages of the six nodes corresponding to the R20+50% state category are respectively input into the trained probabilistic neural network, and the binary code of the probabilistic neural network output is 00000010.
  • the code for calling the neural network for correction in the Matlab environment is as follows:
  • Step H7 Measure the node voltages of the nodes P2, P5, P6, P8, P9, and P11 in the circuit.
  • Step H8 Input the measured node voltage into the trained probabilistic neural network, and obtain the state category of the circuit through the probabilistic neural network.
  • the detecting method of the operating state of the circuit according to the embodiment of the present invention can also be applied to the GOA circuit.
  • the GOA circuit is damaged and has many types of display defects on the display panel (LCD), such as displaying a black screen, displaying a split screen, displaying a flower screen, and a bottom bright line.
  • LCD display panel
  • each display defect corresponds to an abnormal operating state of the device inside the circuit.
  • the single-stage GOA circuit includes 8 transistors and 2 capacitors. It is assumed that the circuit includes a normal state and four fault states, and the four fault states are T1 open circuit, T3 open circuit, and C1+50, respectively. The current Ioff at which % and T4 are in the off state is increased.
  • T1 open circuit and T3 open circuit are hard faults, and C1+50% and T4Ioff increase are soft faults.
  • the external appearance of the T1 open circuit is a black screen display, and the external appearance of the T3 open circuit is a display split screen, and the external appearance of C1+50% is a display screen.
  • the external performance of T4Ioff is the bottom bright line.
  • the actual TFT-LCD product can be tested by using Laser cutting to break down the corresponding components in the GOA circuit on the TFT-LCD product. , you can simulate the corresponding fault. Then, the voltage values of the nodes P1 - P9 in the GOA circuit shown in Fig. 7 are obtained by using a laser probe device and an oscilloscope.
  • the Monte Carlo analysis can be used to obtain the training sample set and the calibration sample set according to the above simulation method of the resistance circuit, and details are not described herein again.
  • the above simulation data is input into a neural network model (for example, a probabilistic neural network model PNN) to train and test the neural network model to obtain a trained neural network.
  • a neural network model for example, a probabilistic neural network model PNN
  • the PCA algorithm can be used to perform dimensionality reduction on the above simulation data.
  • the voltage value data of the corresponding node in the GOA circuit can be obtained by using the laser probe device and the oscilloscope as described above, and the obtained voltage value data of the node is input and trained. Neural network for fault diagnosis.
  • the embodiment provides a detecting device for the working state of the circuit, and the device corresponds to the detecting method of the working state of the circuit provided in the first embodiment.
  • the detecting device for the working state of the circuit includes a neural network forming module 1, a measuring module 2, and a detecting module 3.
  • the neural network forming module 1 is configured to form a neural network that acquires a state category of the circuit to be tested.
  • the measuring module 2 is configured to measure electrical characteristic parameters of at least one node in the circuit to be tested.
  • the detecting module 3 is connected to the neural network forming module 1 and the measuring module 2, respectively.
  • the detecting module 3 is configured to acquire the electrical characteristic parameters of the neural network and at least one node of the circuit to be tested, and input the measured electrical characteristic parameters of the at least one node into the nerve.
  • the network obtains the status category of the circuit under test through the neural network.
  • the detecting device for the operating state of the circuit provided by this embodiment includes a neural network forming module 1. Therefore, using the neural network to detect the state category of the circuit to be tested can improve the accuracy of the detection. Moreover, by using the detecting device of the working state of the circuit provided in this embodiment, only the electrical characteristic parameters of some nodes in the circuit to be tested are input into the neural network, and the state category of the circuit to be tested is obtained, that is, the test is to be tested. The working state of the circuit eliminates the need for microscopy, TFT characterization, or SEM slicing of the circuit to be tested, which saves time. Therefore, by using the detecting device of the operating state of the circuit provided in the embodiment, it is possible to accurately and quickly detect the operating state in the circuit.
  • the electrical characteristic parameter of the node may specifically be a node voltage parameter, a node current parameter or a node power parameter of the node, and may of course be other electrical characteristic parameters that can be received by the neural network.
  • the neural network forming module 1 includes a model building sub-module 4, a training sample set building sub-module 5, and a model building sub-module 4, a training sample set building sub-module 5, and a detecting module 3, respectively.
  • the model building sub-module 4 is used to construct a neural network model.
  • the training sample set construction sub-module 5 is used to construct a fault training sample set.
  • the training sub-module 6 is configured to acquire a fault training sample set and a neural network model, and train the neural network model according to the fault training sample set to obtain a neural network after the training is completed.
  • the neural network after the training is completed has a strong generalization ability, and the correct mapping relationship between input and output is obtained, thereby further improving the accuracy of the neural network operation analysis.
  • the model building sub-module 4 is used to construct a probabilistic neural network model.
  • the constructed probabilistic neural network model includes an input node, an output node, and an input/output control algorithm.
  • the probabilistic neural network model has the advantages of short training time, difficulty in converging to local optimum, and suitable for pattern classification.
  • the detection of the state category of the circuit to be tested by the probabilistic neural network model can further reduce the detection time and improve the accuracy of the detection.
  • the state categories of the circuit include a normal state and a fault state, wherein the fault state typically includes two states, a hard fault and a soft fault. Therefore, the training sample set construction sub-module 5 may include at least one of the hard failure training sample set construction unit 7 connected to the training sub-module 6 and the soft failure training sample set construction unit 8 connected to the training sub-module 6.
  • the hard fault training sample set construction unit 7 is used to construct a hard fault training sample set.
  • the constructed hard fault training sample set includes at least one hard fault status category and electrical characteristic parameters of at least one of the nodes to be tested corresponding to each of the at least one hard fault status category.
  • the soft fault training sample set construction unit 8 is used to construct a soft fault training sample set.
  • the constructed soft fault training sample set includes at least one soft fault state category and electrical characteristic parameters of at least one of the nodes to be tested corresponding to each of the at least one soft fault state category.
  • the training sub-module 6 includes a target set construction unit 9 and a training execution unit 10.
  • the target set construction unit 9 is used to construct a fault sample target set.
  • the training execution unit 10 and the detection module 3, the target set construction unit 9, the model construction sub-module 4, and the training sample set construction sub-module 5 (at least one of the hard failure training sample set construction unit 7 and the soft failure training sample set construction unit 8) One) is separately connected, and the training execution unit 10 is configured to acquire a fault sample target set, a neural network model, and at least one of a hard fault training sample set and a soft fault training sample set, and the training execution unit 10 sets the hard fault training sample set and the soft fault.
  • At least one input neural network model in the training sample set, the neural network is trained according to the target set of the fault sample, and the neural network after the training is completed.
  • the training sub-module 6 may further include dimensionality reduction respectively associated with the training execution unit 10 and the training sample set construction sub-module 5 (at least one of the hard failure training sample set construction unit 7 and the soft failure training sample set construction unit 8)
  • the unit 11, the dimension reduction unit 11 is configured to perform dimension reduction processing on the electrical characteristic parameter data of the at least one node corresponding to each of the plurality of state categories in the fault training sample set, to eliminate the numerous included in the fault training sample set. Information that overlaps each other in the message.
  • the neural network forming module 1 may also include a corrected sample set construction sub-module 12 for constructing a set of corrected samples.
  • the corrected sample set includes a plurality of state categories and electrical characteristic parameters of at least one of the nodes to be tested corresponding to each of the plurality of state categories.
  • the training sub-module 6 further includes a correction unit 13 connected to the corrected sample set construction sub-module 12 and the training execution unit 10, respectively.
  • the correcting unit 13 is configured to correct the neural network after the training is completed according to the corrected sample set.
  • the neural network after completion of the training can be tested according to the corrected sample set, and the accuracy of the neural network in detecting the working state of the circuit to be tested can be determined. If the determination is inaccurate, the nerve after the training is completed The network retrains until the neural network after the completion of the re-training accurately detects the fault of the circuit under test.
  • the corrected sample set construction sub-module 12 specifically includes at least one of the hard fault correction sample set construction unit 14 and the soft fault correction sample set construction unit 15 connected to the correction unit 13.
  • the hard fault correction sample set construction unit 14 is used to construct a hard fault correction sample set.
  • the constructed hard fault training sample set includes at least one hard fault status category and electrical characteristic parameters of at least one of the nodes to be tested corresponding to each of the at least one hard fault status category.
  • the soft fault correction sample set construction unit 15 is used to construct a soft fault correction sample set.
  • the constructed soft fault training sample set includes at least one soft fault state category and electrical characteristic parameters of at least one of the nodes to be tested corresponding to each of the at least one soft fault state category.
  • Each of the modules, sub-modules, and units included in the detection device for the operational state of the circuits described above may be implemented using one or more processors, and they may also include one or more memories for storing computer instructions .
  • the processor performs one or more of the steps or functions of the above-described embodiments when the computer instructions are executed.
  • the memory can be implemented in any type of volatile or non-volatile memory device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable In addition to Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Magnetic Memory, Flash Memory, Disk or Optical Disk.
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read only memory
  • EPROM Programmable Read Only Memory
  • PROM Programmable Read Only Memory
  • ROM Read Only Memory
  • Magnetic Memory Flash Memory
  • Disk Disk
  • Optical Disk Optical Disk
  • the processor can be a central processing unit (CPU) or a field programmable logic array (FPGA) or a microcontroller (MCU) or a digital signal processor (DSP) or an application specific integrated circuit (ASIC) or a graphics processing unit (GPU) with data processing
  • CPU central processing unit
  • FPGA field programmable logic array
  • MCU microcontroller
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • GPU graphics processing unit
  • Computer instructions include one or more processor operations defined by an instruction set architecture corresponding to a processor, which may be logically included and represented by one or more computer programs.

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Abstract

一种电路的工作状态的检测方法及检测装置，所述方法包括：形成获取待测电路的状态类别的神经网络(S1)；测量待测电路中至少一个节点的电学特性参数(S2)；将所测量的至少一个节点的电学特性参数输入神经网络，通过神经网络得到待测电路的状态类别(S3)。

Description

一种电路的工作状态的检测方法及检测装置
相关申请的交叉引用
本申请要求2017年6月8日提交的申请号为201710429375.3且发明名称为“一种电路的工作状态的检测方法及检测系统”的中国申请的优先权，通过引用将其全部内容并入于此。
技术领域
本公开涉及检测技术领域，尤其涉及一种电路的工作状态的检测方法及检测装置。
背景技术
在薄膜晶体管液晶显示器(thin film transistor-liquid crystal display，简称TFT-LCD)产品中，由于阵列制程缺陷或设计缺陷，产品经常会出现显示异常等不良问题，而这些问题多是由产品的电路中存在的故障引起的。以阵列基板行驱动(Gate Driver on Array，以下简称GOA)电路为例，GOA电路中存在的故障通常分为硬故障和软故障两类，硬故障是指元件出现开路或短路，当GOA电路中存在硬故障时，电路的拓扑结构会发生改变，进而导致产品完全失效。软故障是指元件的参数超出其预定的容差范围，当GOA电路中存在软故障时，虽不会直接导致产品完全失效，但仍会影响产品的显示性能。
为了准确找出导致产品出现不良问题的原因，对GOA电路进行故障检测就成为了至关重要的一步。
发明内容
本公开的第一方面提供了一种电路的工作状态的检测方法，包括：形成获取待测电路的状态类别的神经网络；测量所述待测电路中至少一个节点的电学特性参数，将所测量的至少一个节点的电学特性参数输入所述神经网络，通过所述神经网络得到所述待测电路的状态类别。
在一个示例中，形成获取待测电路的状态类别的神经网络包括：构建神经网络模型；构建故障训练样本集，其中，所述故障训练样本集包括多个状 态类别以及与多个状态类别中的每个状态类别对应的所述待测电路中至少一个节点的电学特性参数，所述多个状态类别包括所述待测电路的正常状态和至少一个故障状态；根据所述故障训练样本集，对所述神经网络模型进行训练，得到训练完成后的神经网络，所述神经网络用于获取所述待测电路的状态类别。
在一个示例中，构建故障训练样本集包括：按照所述多个状态类别中的每个状态类别设置所述待测电路，并测量设置后的待测电路中至少一个节点的电学特性参数；根据所述多个状态类别以及与所述多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数，构建故障训练样本集。
在一个示例中，按照所述多个状态类别中的每个状态类别设置所述待测电路包括以下操作中的至少一个：在所述多个状态类别包括至少一个硬故障状态类别的情况下，将所述待测电路中与所述至少一个硬故障状态类别中的每个硬故障状态类别对应的元件设置为短路状态或断路状态；以及，在所述多个状态类别包括至少一个软故障状态类别的情况下，对所述待测电路中与所述至少一个软故障状态类别中的每个软故障状态类别对应的元件的参数设置为超出其容差范围，并对设置后的待测电路进行蒙特卡罗暂态分析。
在一个示例中，所述根据所述故障训练样本集，对所述神经网络模型进行训练，得到训练完成后的神经网络包括：构建故障样本目标集，其中，所述故障样本目标集为所述神经网络所输出的二进制代码与所述多个状态类别之间的对应关系；将所述故障训练样本集输入所述神经网络模型，以对所述神经网络模型进行训练，得到训练完成后的神经网络。
在一个示例中，在所述构建故障样本目标集之前，所述方法还包括：对所述故障训练样本集中与多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数数据进行降维处理。
在一个示例中，形成获取待测电路的状态类别的神经网络包括：构建校正样本集，其中，所述校正样本集包括多个状态类别以及与所述多个状态类别中的每个状态类别对应的所述待测电路中至少一个节点的电学特性参数；在所述根据所述故障训练样本集，对所述神经网络模型进行训练，得到训练完成后的神经网络之后，还包括：根据所述校正样本集，对训练完成后的神经网络进行校正。
在一个示例中，构建校正样本集包括：按照所述多个状态类别中的每个状态类别设置所述待测电路，并测量设置后的待测电路中至少一个节点的电学特性参数；根据所述多个状态类别以及与所述多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数，构建校正样本集。
在一个示例中，按照所述多个状态类别中的每个状态类别设置所述待测电路包括以下操作中的至少一个：在所述多个状态类别包括至少一个硬故障状态类别的情况下，将所述待测电路中与所述至少一个硬故障状态类别中的每个硬故障状态类别对应的元件设置为短路状态或断路状态；以及，在所述多个状态类别包括至少一个软故障状态类别的情况下，对所述待测电路中与所述至少一个软故障状态类别中的每个软故障状态类别对应的元件的参数设置为超出其容差范围，并对设置后的待测电路进行蒙特卡罗暂态分析。
在一个示例中，根据所述校正样本集，对训练完成后的神经网络进行校正包括：将所述校正样本集中与所述多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数输入训练完成后的神经网络中，使训练完成后的神经网络输出二进制代码，将所输出的二进制代码和所述校正样本集中与所述至少一个节点的电学特性参数对应的状态类别之间的对应关系与所述故障样本目标集进行比对，判断所述神经网络的输出结果是否准确，若判断为准确，则训练完成后的神经网络用于对所述待测电路进行故障检测，若判断为不准确，则对训练完成后的神经网络重新进行训练。本公开的第二方面提供了一种电路的工作状态的检测装置，包括：神经网络形成模块，用于形成获取待测电路的状态类别的神经网络；测量模块，用于测量所述待测电路中至少一个节点的电学特性参数；检测模块，与所述神经网络形成模块和所述测量模块分别相连，所述检测模块用于获取所述神经网络以及所述待测电路中至少一个节点的电学特性参数，将所获取的至少一个节点的电学特性参数输入所述神经网络，通过所述神经网络得到所述待测电路的状态类别。
在一个示例中，所述神经网络形成模块包括：模型构建子模块，用于构建神经网络模型；训练样本集构建子模块，用于构建故障训练样本集；训练子模块，与所述模型构建子模块、所述训练样本集构建子模块和所述检测模块分别相连，所述训练子模块用于获取所述故障训练样本集和所述神经网络模型，根据所述故障训练样本集对所述神经网络模型进行训练，得到训练完 成后的神经网络。
在一个示例中，所述训练样本集构建子模块包括与所述训练子模块相连的硬故障训练样本集构建单元和软故障训练样本集构建单元中的至少一个，其中，所述硬故障训练样本集构建单元用于构建硬故障训练样本集；所述软故障训练样本集构建单元用于构建软故障训练样本集。
在一个示例中，所述训练子模块包括：目标集构建单元，用于构建故障样本目标集，故障样本目标集为所述神经网络所输出的二进制代码与所述多个状态类别之间的对应关系；训练执行单元，与所述检测模块、所述目标集构建单元、所述模型构建子模块以及所述训练样本集构建子模块分别相连，所述训练执行单元用于获取所述故障样本目标集、所述故障训练样本集和所述神经网络模型，将所述故障训练样本集输入所述神经网络模型，根据所述故障样本目标集，对所述神经网络进行训练，得到训练完成后的神经网络。
在一个示例中，所述训练子模块还包括：与所述训练样本集构建子模块和所述训练执行单元分别相连的降维单元，所述降维单元用于对所述故障训练样本集中与不同状态类别中的每个状态类别对应的至少一个节点的电学特性参数数据进行降维处理。
在一个示例中，所述神经网络形成模块包括校正样本集构建子模块，用于构建校正样本集；所述训练子模块包括与所述校正样本集构建子模块、所述训练执行单元分别相连的校正单元，所述校正单元用于根据所述校正样本集，对训练完成后的神经网络进行校正。
在一个示例中，所述校正样本集构建子模块包括与所述校正单元相连的硬故障校正样本集构建单元和软故障校正样本集构建单元中的至少一个；其中，所述硬故障校正样本集构建单元用于构建硬故障校正样本集；所述软故障校正样本集构建单元用于构建软故障校正样本集。
本公开的第三方面提供了一种计算机可读存储介质，被配置为存储计算机指令，所述计算机指令被处理器运行时执行如本公开的第一方面所述的电路的工作状态的检测方法中的一个或多个步骤。
本公开的第四方面提供了一种计算机产品，包括一个或多个处理器，所述处理器被配置为运行计算机指令，以执行如本公开的第一方面所述的电路的工作状态的检测方法中的一个或多个步骤。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明实施例一所提供的电路的工作状态的检测方法的流程图一；
图2为本发明实施例一所提供的电路的工作状态的检测方法的流程图二；
图3为本发明实施例一所提供的概率神经网络模型的拓扑结构示意图；
图4为本发明实施例一所提供的电路的工作状态的检测方法的流程图三；
图5为本发明实施例一所提供的电路的工作状态的检测方法的流程图四；
图6为本发明实施例一所提供的电阻电路的结构示意图；
图7为本发明实施例一所提供的GOA电路的结构示意图；
图8为本发明实施例二所提供的电路的工作状态的检测装置的结构示意图一；
图9为本发明实施例二所提供的电路的工作状态的检测装置的结构示意图二。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本发明保护的范围。
在相关技术中，通常采用在显微镜下对GOA区域进行镜检的方式对GOA电路的故障进行检测，但该种方式仅能对硬故障进行检测，无法识别 GOA电路的软故障。因此，还需额外的通过TFT特性测试或扫描电子显微镜(scanning electron microscope，简称SEM)切片的方式判断GOA膜层是否异常，进而对GOA电路的软故障进行检测。但上述两种检测方式均非常耗费时间，且检测效率低下，不利于对GOA电路的不良进行分析和改善。
实施例一
如图1所示，本实施例提供了一种电路的工作状态的检测方法，该电路的工作状态的检测方法可以包括：步骤S1，形成获取待测电路的状态类别的神经网络；步骤S2，测量待测电路中至少一个节点的电学特性参数；以及步骤S3，将所测量的至少一个节点的电学特性参数输入神经网络，通过神经网络得到待测电路中的状态类别。
在本实施例所提供的电路的工作状态的检测方法中，通过将所测量的待测电路中至少一个节点的电学特性参数输入神经网络，即可通过神经网络得到待测电路的状态类别。本实施例所提供的电路的工作状态的检测方法基于神经网络，由于神经网络具有自学习、大规模并行、分布式存储和处理数据的优势，在检测过程中，神经网络可对自身不断进行优化，提高运算分析的准确度和效率，因此，利用神经网络对待测电路中的状态类别进行检测，能够提高检测的准确性。并且，在对待测电路的状态类别进行检测的过程中，只需将待测电路中部分节点的电学特性参数输入至神经网络中，就可得到待测电路中的状态类别，即获取待测电路的工作状态，无需再对待测电路进行显微镜镜检、TFT特性测试或是SEM切片等操作，很大程度上节省了时间，降低人工分析工作的复杂度。因此，采用本实施例所提供的电路的工作状态的检测方法，能够准确且快速地对电路的工作状态进行检测。
需要说明的是，步骤S1中所提及的“形成获取待测电路的状态类别的神经网络”可以基于电路的结构获得神经网络，也可以使用现成的神经网络。并且，在基于电路结构获得神经网络时，既可以根据待测电路本身的结构来获得，也可以根据与待测电路结构相同的其他电路的结构来获得。
需要说明的是，上述节点的电学特性参数可以为节点的节点电压参数、节点电流参数或节点功率参数，当然，也可以为能够被神经网络接收的其他电学特性参数，本公开不对此做出限制。
可以理解的是，状态类别所包括的正常状态是指待测电路无故障且正常 运行时的状态。
如图2所示，步骤S1具体可包括：步骤S11，构建神经网络模型；步骤S12：构建故障训练样本集，其中，故障训练样本集可以包括多个状态类别以及与多个状态类别中的每个状态类别对应的待测电路中至少一个节点的电学特性参数，并且多个状态类别可以包括待测电路的正常状态和至少一个故障状态；以及步骤S13，根据故障训练样本集，对神经网络模型进行训练，得到训练完成后的神经网络，训练完成后的神经网络用于获取待测电路的状态类别。
其中，根据故障训练样本集，对神经网络模型进行训练是指，将故障训练样本集中的多个状态类别以及与多个状态类别中的每个状态对应的待测电路中至少一个节点的电学特性参数输入至神经网络中，使得神经网络正确地掌握该至少一个节点的电学特性参数与状态类别之间的对应关系，从而使得在对神经网络训练完成后，将待测电路中的至少一个节点的电学特性参数输入神经网络后，训练好的神经网络可以准确输出与所输入的至少一个节点的电学特性参数相对应的状态类别。
对神经网络模型进行训练的过程也可称为神经网络模型的学习过程。通过对神经网络模型进行训练，可以使得训练完成后的神经网络具有较强的泛化能力，得到正确的输入输出的映射关系，从而能够进一步提高神经网络运算分析的准确度。
其中，步骤S11具体可以包括：根据Matlab神经网络工具箱中的用于设计神经网络模型的newpnn()函数构建概率神经网络模型。其中，所构建的概率神经网络模型用于获取待测电路的状态类别。概率神经网络模型包括输入节点、输出节点以及输入/输出控制算法。
假定待测电路中包含N个节点，在后续对概率神经网络模型进行训练时，例如，可以将多个状态类别中的每个状态类别下对应的N个节点的电学特性参数组合成N维向量输入至概率神经网络模型中。因此，所构建的概率神经网络模型的输入节点的个数需等于输入向量的维数N，即概率神经网络模型的输入节点的个数等于待测电路中节点的个数。
利用N个节点的电学特性参数对概率神经网络模型进行训练，可以进一步保证训练完成后的概率神经网络具有正确的输入输出的映射关系。当然， 也可以仅将N个节点中的部分节点的电学特性参数输入至概率神经网络模型中。此时，概率神经网络模型的输入节点的个数小于待测电路中节点的个数。
假定待测电路共有M个状态类别，为了保证利用概率神经网络能够输出全部的状态类别中的任一个状态类别，在一个示例中，所构建的概率神经网络模型的输出节点的个数应等于待测电路中的状态类别的个数M，即概率神经网络模型的输出节点的个数等于待测电路中状态类别的个数。具体的，如图3所示，概率神经网络模型具有N个输入节点：x 1～x N，以及M个输出节点：y 1～y M。
在本实施例所提供的电路的工作状态的检测方法中，所构建的神经网络模型为概率神经网络模型，与传统的BP神经网络模型相比，概率神经网络模型是基于Bayes最小风险发展而来的一种并行算法，具有训练时间短、不易收敛到局部最优且适用于模式分类的优点。因此，基于概率神经网络模型对待测电路的状态类别进行检测，能够进一步降低检测时间，且提高检测的准确性。
在一个示例中，步骤S12具体可以包括：按照多个状态类别中的每个状态类别设置待测电路，并测量设置后的待测电路中至少一个节点的电学特性参数；以及，根据多个状态类别以及与多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数，构建故障训练样本集。
电路的状态类别可以包括待测电路的正常状态和至少一个故障状态，其中，故障状态通常包括硬故障状态和软故障状态。因此，步骤S12中所构建的故障训练样本集具体可以包括硬故障训练样本集和软故障训练样本集中的至少一个。基于此，步骤“按照多个状态类别中的每个状态类别设置待测电路”具体可以包括以下操作中的至少一个：
在多个状态类别包括至少一个硬故障状态类别的情况下，将待测电路中与至少一个硬故障状态类别中的每个硬故障状态类别对应的元件设置为短路状态或断路状态。在该情况下，然后，获取与至少一个硬故障状态类别中的每个硬故障状态类别对应的待测电路中的至少一个节点的电学特性参数。根据至少一个硬故障状态类别以及与至少一个硬故障状态类别中的每个硬故障状态类别对应的至少一个节点的电学特性参数，构建硬故障训练样本集。
以及，在多个状态类别包括至少一个软故障状态类别的情况下，对待测 电路中与至少一个软故障状态类别中的每个软故障状态类别对应的元件的参数设置为超出其容差范围，并例如通过PSPICE软件对设置后的待测电路进行蒙特卡罗暂态分析。在该情况下，然后，获取与至少一个软故障状态类别中的每个软故障状态类别对应的待测电路中的至少一个节点的电学特性参数。根据至少一个软故障状态类别以及与至少一个软故障状态类别中的每个软故障状态类别对应的至少一个节点的电学特性参数，构建软故障训练样本集。
需要说明的是，除了通过软件方式模拟电路的硬故障，还可利用激光切割等设备人为地设置元件的短路或断路，并且，在获取节点电压时，可采用PSPICE软件对设置后的待测电路进行蒙特卡罗暂态分析，以获取与多个状态类别中的每个状态类别对应的待测电路中的至少一个节点的电学特性参数，也可通过实际测量的方式进行获取。
需要说明的是，PSPICE软件是一个具有强大的电路图绘制功能、电路模拟仿真功能、图形后处理功能和元器件符号制作功能的仿真软件，利用PSPICE软件对设置后的待测电路进行蒙特卡罗暂态分析可达到良好的仿真分析效果。
如图4所示，步骤S13具体可包括：在步骤S131中，构建故障样本目标集。其中，故障样本目标集为神经网络所输出的二进制代码与多个状态类别之间的对应关系。
示例性地，待测电路可以包括三个状态类别，诸如状态类别A、状态类别B和状态类别C，且神经网络包括三个输出节点，每一个输出节点输出一串二进制代码。故障样本目标集包括：神经网络输出100的二进制代码对应状态类别A，神经网络输出010的二进制代码对应状态类别B，神经网络输出001的二进制代码对应状态类别C。
接着，在步骤S132中：将故障训练样本集输入神经网络模型以对神经网络模型进行训练，得到训练完成后的神经网络。训练完成后的神经网络需满足：当向训练完成后的神经网络输入当前所测量的至少一个节点的电学特性参数时，训练完成后的神经网络输出的二进制代码在故障样本目标集中所对应的状态类别与当前待测电路实际所处的状态类别相一致。
示例性地，将状态类别A对应的各节点的电学特性参数输入至训练完成 后的神经网络，训练完成后的神经网络输出的二进制代码应为100；将状态类别B对应的各节点的电学特性参数输入至训练完成后的神经网络，训练完成后的神经网络输出的二进制代码应为010；将状态类别C对应的各节点的电学特性参数输入至训练完成后的神经网络，训练完成后的神经网络输出的二进制代码应为001。
为排除故障训练样本集所包括的众多信息中相互重叠的信息，请再次参见图4，在步骤S131之前，本实施例所提供的电路的工作状态的检测方法还可包括：步骤S130：对故障训练样本集中与多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数数据进行降维处理。具体地，可利用主成分分析(Principal Component Analysis，以下简称PCA)算法对故障训练样本集中的电学特性参数数据进行降维处理。
此外，如图5所示，步骤S1还可包括：在步骤S14中，构建校正样本集。其中，校正样本集包括多个状态类别以及与多个状态类别中的每个状态类别对应的待测电路中至少一个节点的电学特性参数；以及，在步骤S15中，根据校正样本集，对训练完成后的神经网络进行校正。
需要说明的是，上述构建校正样本集在步骤S13后执行仅仅为了示例说明，在实际应用中，构建校正样本集还可与构建故障训练样本集同时进行。
具体地，校正样本集可以包括硬故障校正样本集和软故障校正样本集中的至少一个。当仅用硬故障训练样本集对神经网络模型进行训练时，对应地，可通过硬故障校正样本集对训练完成后的神经网络进行校正。当仅用软故障训练样本集对神经网络模型进行训练时，对应地，可通过软故障校正样本集对训练完成后的神经网络进行校正。当同时用硬故障训练样本集和软故障训练样本集对神经网络模型进行训练时，对应地，可通过硬故障校正样本集和软故障校正样本集中的至少一个对训练完成后的神经网络进行校正。
基于此，步骤S14具体可包括：按照多个状态类别中的每个状态类别设置待测电路，并测量设置后的待测电路中至少一个节点的电学特性参数；以及，根据多个状态类别和与多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数，构建校正样本集。
具体地，步骤“按照多个状态类别中的每个状态类别设置待测电路”可以包括以下操作中的至少一个：在多个状态类别包括至少一个硬故障状态类 别的情况下，将待测电路中与至少一个硬故障状态类别中的每个硬故障状态类别对应的元件设置为短路状态或断路状态；以及，在多个状态类别包括至少一个软故障状态类别的情况下，对待测电路中与至少一个软故障状态类别中的每个软故障状态类别对应的元件的参数设置为超出其容差范围，并例如通过PSPICE软件对设置后的待测电路进行蒙特卡罗暂态分析。
需要说明的是，除了通过软件方式模拟电路的硬故障，还可利用激光切割等设备人为地设置元件的短路或断路，并且，在获取节点电压时，可采用PSPICE软件对设置后的待测电路进行蒙特卡罗暂态分析，以获取与多个状态类别中的每个状态类别对应的待测电路中的至少一个节点的电学特性参数，也可通过实际测量的方式进行获取。
步骤S15具体可包括：将校正样本集中与多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数输入训练完成后的神经网络中，使训练完成后的神经网络输出二进制代码，将所输出的二进制代码和校正样本集中与所输入的至少一个节点的电学特性参数对应的状态类别之间的对应关系与故障样本目标集进行比对，判断神经网络的输出结果是否准确。例如，可以将神经网络的输出结果的准确率与预设阈值进行比较，若准确率高于或等于阈值，则判定神经网络的输出结果准确，训练完成后的神经网络可以用于对待测电路进行故障检测；若准确率低于阈值，则判定神经网络的输出结果不准确，这时就需要对训练完成后的神经网络重新进行训练。
基于上述表述，通过校正样本集对完成训练后的神经网络进行测试，可以判断神经网络在对待测电路进行工作状态检测时的准确性，若判断为不准确，需对训练完成后的神经网络重新进行训练，直至使再次训练完成后的神经网络准确检测待测电路的故障。
检测方法适用于各种电路，例如电阻电路、LTPS产品的单级GOA电路等，下面分别以图6、图7所示的电路结构为例，对上述电路的工作状态的检测方法进行详细说明。
图6所示的电路中包括20个电阻(R1～R20)、以及12个节点(P1～P12)。假定该电路包括8个状态类别：一个正常状态和七个故障状态，其中七个故障状态包括R1+40％、R1-50％、R6开路、R9短路、R18开路、R20+50％、R19+50％且R20开路。以R1+40％和R1-50％为例，R1+40％表示R1的参数 值高于容差范围的40％，R1-50％表示R1的参数值低于容差范围的40％，二者均属于软故障。
步骤H1：构建概率神经网络模型，其中，概率神经网络模型包括6个输入节点、8个输出节点以及输入/输出控制算法。
步骤H2：对于8个状态类别中的每个状态类别，进行30次蒙特卡罗暂态分析，获取每个状态类别下的待测电路中的节点P2、P5、P6、P8、P9、P11的电压。其中，20次蒙特卡罗暂态分析获取的待测电路中的6个节点的节点电压用于构建故障训练样本集，10次蒙特卡罗暂态分析获取的待测电路中的6个节点的节点电压用于构建校正样本集。应当了解，对于每一个状态类别下的待测电路来说，多次蒙特卡洛分析所分别获取的节点的电压是不一样或不完全一样的，因而多次蒙特卡洛分析的结果可以形成多个样本。
需要说明的是，在构建故障训练样本集时，由于对8个状态类别中的每个状态类别都进行了20次蒙特卡罗暂态分析，因而该故障训练样本集中包含了160个故障训练样本。同理，在构建校正样本集时，由于对8个状态类别中的每个状态类别都进行了10次蒙特卡罗暂态分析，因而该校正样本集中包含了80个校正样本。
步骤H3：利用PCA算法，对故障训练样本集所包括的8个状态类别中的每个对应的6个节点的节点电压数据进行降维处理。其中，PCA算法在Matlab环境下的部分代码如下所示：
Figure PCTCN2018088745-appb-000001
Figure PCTCN2018088745-appb-000002
步骤H4：构建故障样本目标集，其中，概率神经网络所输出的二进制代码与状态类别之间的对应关系如表1所示：
表1
Figure PCTCN2018088745-appb-000003
步骤H5：将降维处理后的故障训练样本集输入概率神经网络模型，对概率神经网络模型进行训练，得到训练完成后的概率神经网络。其中，Matlab环境下实现对概率神经网络模型进行训练的部分代码如下所示：
Figure PCTCN2018088745-appb-000004
步骤H6：从校正样本集中抽取R1-50％、R9短路、R18开路和R20+50％四个状态类别对应的6个节点的节点电压数据，对训练好的神经网络进行校正。
其中，与R1-50％、R9短路、R18开路和R20+50％这四个状态类别分别对应的6个节点的节点电压数据如表2所示：
表2
P2 P5 P6 P8 P9 P11 状态类别
4.3491 3.1776 2.7966 3.2949 2.5171 2.9567 R1-50％
4.1771 3.3255 2.8933 3.9142 2.8470 3.7100 R9短路
4.0867 3.2338 2.8309 3.3183 2.8341 2.7899 R18开路
4.0937 3.1390 2.7445 3.3669 2.6096 3.1128 R20+50％
将R1-50％状态类别对应的6个节点的节点电压分别输入训练好的概率神经网络中，概率神经网络输出的二进制代码为00100000；将R9短路状态类别对应的6个节点的节点电压分别输入训练好的概率神经网络中，概率神经网络输出的二进制代码为00001000；将R18开路状态类别对应的6个节点的节点电压分别输入训练好的概率神经网络中，概率神经网络输出的二进制代码为00000100；将R20+50％状态类别对应的6个节点的节点电压分别输入训练好的概率神经网络中，概率神经网络输出的二进制代码为00000010。
通过将训练好的概率神经网络输出的二进制代码与表1中的对应关系相比对可以发现，训练好的概率神经网络所输出的二进制代码在表1中对应的状态类别与表2中6个节点的节点电压实际所对应的状态类别是一致的。可见，训练好的概率神经网络的输出结果是准确的，后续可直接用来对待测电路的工作状态进行检测。
具体的，在Matlab环境下调用神经网络进行校正的部分代码如下：
          load net2net；％加载训练好的神经网络
y＝sim(net,p_test)；％对待测试样本p_test进行分类
yc＝vec2ind(y)；％结果转换成行向量
步骤H7：测量电路中节点P2、P5、P6、P8、P9、P11的节点电压。
步骤H8：将所测量的节点电压输入训练好的概率神经网络，通过概率神经网络得到电路的状态类别。
如上所述，根据本发明实施例的电路的工作状态的检测方法还可以应用于GOA电路。GOA电路受损反应在显示器面板(LCD)上的显示缺陷的类型很多，例如显示黑屏、显示分屏、显示花屏和底部亮线等。显然地，每一种显示缺陷都对应于电路内部器件的非正常操作状态。以图7为例，该单级GOA电路包括8个晶体管和2个电容器，假设该电路包含一种正常状态和四 种故障状态，该四种故障状态分别为T1开路、T3开路、C1+50％、T4处于截止状态下的电流Ioff增大。其中，T1开路、T3开路是硬故障，C1+50％、T4Ioff增大是软故障。根据GOA电路的操作机理，在图7所示的GOA电路中，T1开路的外在表现是显示黑屏，T3开路的外在表现是显示分屏，C1+50％的外在表现是显示花屏，T4Ioff的外在表现是底部亮线。
在构建故障训练样本集和校正样本集时，需要收集每个状态类别下的电路中至少一个节点的电学特性参数。对于上述四种故障状态中的两种硬故障、以及正常状态，可以使用实际TFT-LCD产品进行测试，具体方法为：使用Laser cutting将TFT-LCD产品上的GOA电路中相应的元器件击穿，即可模拟对应故障。然后，利用激光探针设备及示波器获取图7所示GOA电路中的节点P1-P9的电压值。对于上述故障状态类别中的两种软故障，可以使用蒙特卡洛分析按照上述电阻电路的模拟方法获得训练样本集和校正样本集，此处不再赘述。
然后，将上述模拟数据输入神经网络模型(例如，概率神经网络模型PNN)以对神经网络模型进行训练及测试，得到训练好的神经网络。当然，如前所述，在输入神经网络模型前，可以先对上述模拟数据使用PCA算法进行降维处理。
之后，当遇到类似不良显示状况时，即可如上所述，使用激光探针设备及示波器获取GOA电路中对应节点的电压值数据，并将所获取的节点的电压值数据输入已训练好的神经网络进行故障诊断。
实施例二
本实施例提供了一种电路的工作状态的检测装置，该装置与实施例一所提供的电路的工作状态的检测方法相对应。
如图8所示，本实施例所提供的电路的工作状态的检测装置包括神经网络形成模块1、测量模块2和检测模块3。其中，神经网络形成模块1用于形成获取待测电路的状态类别的神经网络。测量模块2用于测量待测电路中至少一个节点的电学特性参数。检测模块3分别与神经网络形成模块1和测量模块2相连，检测模块3用于获取神经网络以及待测电路中至少一个节点的电学特性参数，将所测量的至少一个节点的电学特性参数输入神经网络，通过神经网络得到待测电路的状态类别。
本实施例所提供的电路的工作状态的检测装置包括神经网络形成模块1。因此，利用神经网络对待测电路的状态类别进行检测，能够提高检测的准确性。并且，采用本实施例所提供的电路的工作状态的检测装置，只需将待测电路中部分节点的电学特性参数输入至神经网络中，就可得到待测电路的状态类别，即获取待测电路的工作状态，无需再对待测电路进行显微镜镜检、TFT特性测试或是SEM切片等操作，很大程度上节省了时间。因此，采用本实施例所提供的电路的工作状态的检测装置，能够准确快速地对电路中的工作状态进行检测。
需要说明的是，上述节点的电学特性参数具体可以为节点的节点电压参数、节点电流参数或节点功率参数，当然，也可以为能够被神经网络接收的其他电学特性参数。
具体地，如图9所示，神经网络形成模块1包括模型构建子模块4、训练样本集构建子模块5、与模型构建子模块4、训练样本集构建子模块5和检测模块3分别相连的训练子模块6。模型构建子模块4用于构建神经网络模型。训练样本集构建子模块5用于构建故障训练样本集。训练子模块6用于获取故障训练样本集和神经网络模型，根据故障训练样本集对神经网络模型进行训练，得到训练完成后的神经网络。
通过对神经网络模型进行训练，可以使得训练完成后的神经网络具有较强的泛化能力，得到正确的输入输出的映射关系，从而能够进一步提高神经网络运算分析的准确度。
在一个示例中，模型构建子模块4用于构建概率神经网络模型。其中，所构建的概率神经网络模型包括输入节点、输出节点以及输入/输出控制算法。与传统的BP神经网络模型相比，概率神经网络模型具有训练时间短、不易收敛到局部最优以及适用于模式分类的优点。采用概率神经网络模型对待测电路的状态类别进行检测，能够进一步的降低检测时间，且提高检测的准确性。
电路的状态类别包括正常状态和故障状态，其中，故障状态通常包括硬故障和软故障两种状态。因此，训练样本集构建子模块5可包括与训练子模块6相连的硬故障训练样本集构建单元7和与训练子模块6相连的软故障训练样本集构建单元8中的至少一个。
其中，硬故障训练样本集构建单元7用于构建硬故障训练样本集。所构建的硬故障训练样本集包括至少一个硬故障状态类别，以及与至少一个硬故障状态类别中的每个硬故障状态类别对应的待测电路中的至少一个节点的电学特性参数。软故障训练样本集构建单元8用于构建软故障训练样本集。所构建的软故障训练样本集包括至少一个软故障状态类别，以及与至少一个软故障状态类别中的每个软故障状态类别对应的待测电路中的至少一个节点的电学特性参数。
训练子模块6包括目标集构建单元9和训练执行单元10。其中，目标集构建单元9用于构建故障样本目标集。训练执行单元10与检测模块3、目标集构建单元9、模型构建子模块4、和训练样本集构建子模块5(硬故障训练样本集构建单元7和软故障训练样本集构建单元8中的至少一个)分别相连，训练执行单元10用于获取故障样本目标集、神经网络模型，以及硬故障训练样本集和软故障训练样本集中的至少一个，训练执行单元10将硬故障训练样本集和软故障训练样本集中的至少一个输入神经网络模型，根据故障样本目标集，对神经网络进行训练，得到训练完成后的神经网络。
此外，训练子模块6还可包括与训练执行单元10以及训练样本集构建子模块5(硬故障训练样本集构建单元7和软故障训练样本集构建单元8中的至少一个)分别相连的降维单元11，降维单元11用于对故障训练样本集中与多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数数据进行降维处理，以排除故障训练样本集所包括的众多信息中相互重叠的信息。
神经网络形成模块1还可包括校正样本集构建子模块12，校正样本集构建子模块12用于构建校正样本集。校正样本集包括多个状态类别以及与多个状态类别中的每个状态对应的待测电路中的至少一个节点的电学特性参数。
训练子模块6还包括与校正样本集构建子模块12、训练执行单元10分别相连的校正单元13。校正单元13用于根据校正样本集，对训练完成后的神经网络进行校正。
通过设置校正单元13，可根据校正样本集对完成训练后的神经网络进行测试，判断神经网络在对待测电路进行工作状态检测时的准确性，若判断出不准确，需对训练完成后的神经网络重新进行训练，直至使再次训练完成后的神经网络准确检测待测电路的故障。
校正样本集构建子模块12具体包括与校正单元13相连的硬故障校正样本集构建单元14和软故障校正样本集构建单元15中的至少一个。
其中，硬故障校正样本集构建单元14用于构建硬故障校正样本集。所构建的硬故障训练样本集包括至少一个硬故障状态类别，以及与至少一个硬故障状态类别中的每个硬故障状态类别对应的待测电路中的至少一个节点的电学特性参数。软故障校正样本集构建单元15用于构建软故障校正样本集。所构建的软故障训练样本集包括至少一个软故障状态类别，以及与至少一个软故障状态类别中的每个软故障状态类别对应的待测电路中的至少一个节点的电学特性参数。
以上所描述的电路的工作状态的检测装置中所包括的各模块、子模块和单元都可以使用一个或多个处理器来实现，并且它们还可以包括一个或多个存储器，用于存储计算机指令。当运行计算机指令时，处理器执行上述实施例中的一个或多个步骤或功能。
存储器可以是各种由任何类型的易失性或非易失性存储设备或者它们的组合实现，如静态随机存取存储器(SRAM)，电可擦除可编程只读存储器(EEPROM)，可擦除可编程只读存储器(EPROM)，可编程只读存储器(PROM)，只读存储器(ROM)，磁存储器，快闪存储器，磁盘或光盘。
处理器可以是中央处理单元(CPU)或者现场可编程逻辑阵列(FPGA)或者单片机(MCU)或者数字信号处理器(DSP)或者专用集成电路(ASIC)或者图形处理器(GPU)等具有数据处理能力和/或程序执行能力的逻辑运算器件。
计算机指令包括了一个或多个由对应于处理器的指令集架构定义的处理器操作，这些计算机指令可以被一个或多个计算机程序在逻辑上包含和表示。
以上所述仅为本发明的实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种电路的工作状态的检测方法，包括：
    形成获取待测电路的状态类别的神经网络；
    测量所述待测电路中至少一个节点的电学特性参数；
    将所测量的至少一个节点的电学特性参数输入所述神经网络，通过所述神经网络得到所述待测电路的状态类别。
  2. 根据权利要求1所述的电路的工作状态的检测方法，其中，形成获取待测电路的状态类别的神经网络包括：
    构建神经网络模型；
    构建故障训练样本集，其中，所述故障训练样本集包括多个状态类别以及与多个状态类别中的每个状态类别对应的所述待测电路中至少一个节点的电学特性参数，所述多个状态类别包括所述待测电路的正常状态和至少一个故障状态；
    根据所述故障训练样本集，对所述神经网络模型进行训练，得到训练完成后的神经网络，所述神经网络用于获取所述待测电路的状态类别。
  3. 根据权利要求2所述的电路的工作状态的检测方法，其中，构建故障训练样本集包括：
    按照所述多个状态类别中的每个状态类别设置所述待测电路，并测量设置后的待测电路中的至少一个节点的电学特性参数；
    根据所述多个状态类别以及与所述多个状态类别中的每个状态类别对应的所述至少一个节点的电学特性参数，构建故障训练样本集。
  4. 根据权利要求3所述的电路的工作状态的检测方法，其中，按照所述多个状态类别中的每个状态类别设置所述待测电路包括以下操作中的至少一个：
    在所述多个状态类别包括至少一个硬故障状态类别的情况下，将所述待测电路中与所述至少一个硬故障状态类别中的每个硬故障状态类别对应的元件设置为短路状态或断路状态；以及
    在所述多个状态类别包括至少一个软故障状态类别的情况下，对所述待测电路中与所述至少一个软故障状态类别中的每个软故障状态类别对应的元 件的参数设置为超出其容差范围，对设置后的待测电路进行蒙特卡罗暂态分析。
  5. 根据权利要求2所述的电路的工作状态的检测方法，其中，
    所述根据所述故障训练样本集，对所述神经网络模型进行训练，得到训练完成后的神经网络包括：
    构建故障样本目标集，其中，所述故障样本目标集为所述神经网络所输出的二进制代码与所述多个状态类别之间的对应关系；
    将所述故障训练样本集输入所述神经网络模型以对所述神经网络模型进行训练，得到训练完成后的神经网络。
  6. 根据权利要求5所述的电路的工作状态的检测方法，其中，在所述构建故障样本目标集之前，所述方法还包括：对所述故障训练样本集中与多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数数据进行降维处理。
  7. 根据权利要求1-6任一所述的电路的工作状态的检测方法，其中，所述形成获取所述待测电路的状态类别的神经网络包括：构建校正样本集，其中，所述校正样本集包括多个状态类别以及与所述多个状态类别中的每个状态类别对应的所述待测电路中至少一个节点的电学特性参数；
    在所述根据所述故障训练样本集，对所述神经网络模型进行训练，得到训练完成后的神经网络之后，还包括：根据所述校正样本集，对训练完成后的神经网络进行校正。
  8. 根据权利要求7所述的电路的工作状态的检测方法，其中，所述构建校正样本集包括：
    按照所述多个状态类别中的每个状态类别设置所述待测电路，并测量设置后的待测电路中至少一个节点的电学特性参数；
    根据所述多个状态类别以及与所述多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数，构建校正样本集。
  9. 根据权利要求8所述的方法，其中，按照所述多个状态类别中的每个状态类别设置所述待测电路包括以下操作中的至少一个：
    在所述多个状态类别包括至少一个硬故障状态类别的情况下，将所述待测电路中与所述至少一个硬故障状态类别中的每个硬故障状态类别对应的元 件设置为短路状态或断路状态；以及
    在所述多个状态类别包括至少一个软故障状态类别的情况下，对所述待测电路中与所述至少一个软故障状态类别中的每个软故障状态类别对应的元件的参数设置为超出其容差范围，对设置后的待测电路进行蒙特卡罗暂态分析。
  10. 根据权利要求7-9任一所述的电路的工作状态的检测方法，其中，所述根据所述校正样本集，对训练完成后的神经网络进行校正包括：
    将所述校正样本集中与所述多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数输入训练完成后的神经网络中，使训练完成后的神经网络输出二进制代码，将所输出的二进制代码和所述校正样本集中与所述至少一个节点的电学特性参数对应的状态类别之间的对应关系与所述故障样本目标集进行比对，判断所述神经网络的输出结果是否准确，若判断为准确，则训练完成后的神经网络用于对所述待测电路进行故障检测，若判断为不准确，则对训练完成后的神经网络重新进行训练。
  11. 一种电路的工作状态的检测装置，包括：
    神经网络形成模块，用于形成获取待测电路的状态类别的神经网络；
    测量模块，用于测量所述待测电路中至少一个节点的电学特性参数，
    检测模块，与所述神经网络形成模块和所述测量模块分别相连，所述检测模块用于获取所述神经网络以及所述待测电路中至少一个节点的电学特性参数，将所获取的至少一个节点的电学特性参数输入所述神经网络，通过所述神经网络得到所述待测电路的状态类别。
  12. 根据权利要求11所述的电路的工作状态的检测装置，其中，所述神经网络形成模块包括：
    模型构建子模块，用于构建神经网络模型；
    训练样本集构建子模块，用于构建故障训练样本集；
    训练子模块，与所述模型构建子模块、所述训练样本集构建子模块和所述检测模块分别相连，所述训练子模块用于获取所述故障训练样本集和所述神经网络模型，根据所述故障训练样本集对所述神经网络模型进行训练，得到训练完成后的神经网络。
  13. 根据权利要求12所述的电路的工作状态的检测装置，其中，
    所述训练样本集构建子模块包括与所述训练子模块相连的硬故障训练样本集构建单元和软故障训练样本集构建单元中的至少一个，
    其中，所述硬故障训练样本集构建单元用于构建硬故障训练样本集；所述软故障训练样本集构建单元用于构建软故障训练样本集。
  14. 根据权利要求12所述的电路的工作状态的检测装置，其中，
    所述训练子模块包括：
    目标集构建单元，用于构建故障样本目标集，所述故障样本目标集为所述神经网络所输出的二进制代码与所述多个状态类别之间的对应关系；
    训练执行单元，与所述检测模块、所述目标集构建单元、所述模型构建子模块以及所述训练样本集构建子模块分别相连，所述训练执行单元用于获取所述故障样本目标集、所述故障训练样本集和所述神经网络模型，将所述故障训练样本集输入所述神经网络模型，根据所述故障样本目标集，对所述神经网络进行训练，得到训练完成后的神经网络。
  15. 根据权利要求14所述的电路的工作状态的检测装置，其中，所述训练子模块还包括：与所述训练样本集构建子模块和所述训练执行单元分别相连的降维单元，所述降维单元用于对所述故障训练样本集中与多个状态类别中的每个状态类别对应的至少一个节点的电学特性参数数据进行降维处理。
  16. 根据权利要求11-15任一所述的电路的工作状态的检测装置，其中，所述神经网络形成模块包括校正样本集构建子模块，所述校正样本集构建子模块用于构建校正样本集；
    所述训练子模块包括与所述校正样本集构建子模块、所述训练执行单元分别相连的校正单元，所述校正单元用于根据所述校正样本集，对训练完成后的神经网络进行校正。
  17. 根据权利要求16所述的电路的工作状态的检测装置，其中，所述校正样本集构建子模块包括与所述校正单元相连的硬故障校正样本集构建单元和软故障校正样本集构建单元中的至少一个；其中，所述硬故障校正样本集构建单元用于构建硬故障校正样本集；所述软故障校正样本集构建单元用于构建软故障校正样本集。
  18. 一种计算机可读存储介质，被配置为存储计算机指令，所述计算机指令被处理器运行时执行如权利要求1-10任一项所述的电路的工作状态的检 测方法中的一个或多个步骤。
  19. 一种计算机产品，包括一个或多个处理器，所述处理器被配置为运行计算机指令，以执行如权利要求1-10任一项所述的电路的工作状态的检测方法中的一个或多个步骤。
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