WO2024000731A1 - 晶圆缺陷评估方法、装置、存储器芯片和可读存储介质 - Google Patents

晶圆缺陷评估方法、装置、存储器芯片和可读存储介质 Download PDF

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WO2024000731A1
WO2024000731A1 PCT/CN2022/110342 CN2022110342W WO2024000731A1 WO 2024000731 A1 WO2024000731 A1 WO 2024000731A1 CN 2022110342 W CN2022110342 W CN 2022110342W WO 2024000731 A1 WO2024000731 A1 WO 2024000731A1
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wafer
defect
test
data
failure
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PCT/CN2022/110342
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French (fr)
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郑宇廷
熊世英
丁赛赛
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/70—Arrangements for image or video recognition or understanding using pattern recognition or machine learning
    • G06V10/77—Processing image or video features in feature spaces; using data integration or data reduction, e.g. principal component analysis [PCA] or independent component analysis [ICA] or self-organising maps [SOM]; Blind source separation
    • G06V10/774—Generating sets of training patterns; Bootstrap methods, e.g. bagging or boosting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/70—Arrangements for image or video recognition or understanding using pattern recognition or machine learning
    • G06V10/82—Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30—Computing systems specially adapted for manufacturing

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a wafer defect evaluation method, a wafer defect evaluation device, a memory and a computer-readable storage medium.
  • KR Kill Ratio
  • DGD defect good die
  • DBD defect bad die
  • CP Chip Probing
  • CGD clean good die
  • CBD clean bad die
  • the purpose of this disclosure is to provide a wafer defect assessment method, device, memory chip and readable storage medium, which can reduce the workload of CP testing, shorten the CP testing cycle, and thereby improve the production efficiency of memory chips. .
  • a wafer defect assessment method including: obtaining defect detection data from random inspections of wafers during the manufacturing process stage;
  • the defect detection data is input into the test stage failure prediction model to predict the test failure prediction data of all bare dies on the wafer after the end of the process based on the test stage failure prediction model, wherein the test stage failure prediction model uses
  • the real failure big data in the test phase is used as training samples for model training and generation.
  • the real failure big data includes defect data in the wafer process stage and test failure data after the end of the process with corresponding relationships;
  • Defect evaluation indicators of the wafer are calculated based on the defect detection data and the test failure prediction data.
  • inputting the defect detection data into a test stage failure prediction model to predict test failure prediction data in the test stage based on the test stage failure prediction model includes:
  • the defect detection data includes a first detection value and a second detection value.
  • the first detection value is the number of detected defective dies that passed the test.
  • the second detection value is the number of detected defective dies that passed the test.
  • the number of failed die, the first detection value and the second detection value are input into the test stage failure prediction model to output the test failure prediction data, the test failure prediction data includes the first prediction value and A second prediction value, the first prediction value is the predicted number of defective die that pass the wafer test, and the second prediction value is the number of defective die that fail in the wafer test.
  • the defect evaluation index includes at least one of a relevance index, an importance index, and a sensitivity index
  • the correlation index is used to characterize the correlation between the defect detection data and the test failure prediction data
  • the importance index is used to characterize the impact of defects on test failure
  • the sensitivity index is used It is used to characterize the change rate of the defect detection data with the test failure prediction data.
  • calculating the defect evaluation index based on the defect detection data and the test failure prediction data includes:
  • the first formula is R is the correlation index
  • DGD is the first detection value
  • DBD is the second detection value
  • CBD′ is the second prediction value
  • Total′ is the first prediction value and the second prediction value. The sum of predicted values.
  • calculating the defect evaluation index based on the defect detection data and the test failure prediction data includes:
  • the importance indicator is calculated based on the second formula
  • the second formula is I is the importance index
  • DGD is the first detection value
  • DBD is the second detection value
  • CBD′ is the second predicted value
  • Total′ is the first predicted value and the second The sum of predicted values.
  • calculating the defect evaluation index based on the defect detection data and the test failure prediction data includes:
  • the sensitivity index is calculated based on the third formula
  • the third formula is S is the sensitivity index
  • DGD is the first detection value
  • DBD is the second detection value
  • CBD′ is the second prediction value.
  • Key process wafer layers are screened out based on the defect evaluation indicators, and the key process wafer layers are used to predict the deletion of failed die in later testing.
  • screening out key process wafer layers based on the defect evaluation index includes:
  • the defect evaluation indicators are screened based on the screening priority to obtain the key process wafer layer based on the screening results.
  • the method before screening the defect evaluation indicators based on the screening priority to obtain the key process wafer layer based on the screening results, the method further includes:
  • the first threshold is used to screen the importance indicators
  • the second threshold is used to screen the sensitivity indicators
  • the third threshold is used to screen the correlation indicators.
  • screening the defect evaluation indicators based on the screening priority to obtain the key process wafer layer based on the screening results includes:
  • the sensitivity index greater than the second threshold is used as a second screening priority, and a second group of key wafer layers is screened out from the remaining wafer layers based on the first group of key wafer layers and all The second group of key wafer layers is used to obtain the key process wafer layer.
  • screening the defect evaluation indicators based on the screening priority to obtain the key process wafer layer based on the screening results also includes:
  • the defect detection data of the key process wafer layer is input into the test stage failure prediction model to output the location information of the failed die in the key process wafer layer based on the corresponding relationship.
  • the method before obtaining the defect detection data for spot inspection of the wafer during the manufacturing stage, the method further includes:
  • the training model is configured based on the assumption that defects are assigned a specified probability distribution on each wafer layer
  • the failure training features in the training samples are extracted, and the training model is iteratively trained based on the failure training features to obtain the failure prediction model in the test phase.
  • failure training features in the training samples are extracted, and the training model is iteratively trained based on the failure training features to obtain the failure prediction model in the test phase, which includes:
  • the failure training features include the number of defects on each wafer layer and the location of the die where the defects are located.
  • the iterative training is performed based on the number of defects and the location of the die to obtain the failure in the test phase. Predictive model.
  • performing the iterative training based on the defect number and the die position to obtain the test phase failure prediction model further includes:
  • the failure training features include shape features of the defect, and the iterative training is performed based on the shape until the training model converges to satisfy the corresponding relationship,
  • the shape characteristics include the perimeter and/or area of the defect.
  • a wafer defect evaluation device including: an acquisition module for acquiring defect detection data for random inspection of wafers during the manufacturing process; and a prediction module for converting the defect detection data into Input the test stage failure prediction model to predict the test failure prediction data of all the dies on the wafer after the end of the process based on the test stage failure prediction model, wherein the test stage failure prediction model uses the real failure big data of the test stage As training samples, model training is generated.
  • the real failure big data includes defect data at the wafer process stage and test failure data after the process with corresponding relationships; a calculation module for based on the defect detection data and the test failure.
  • the prediction data calculates defect assessment metrics for the wafer.
  • a memory chip is provided.
  • the memory chip adopts the wafer defect evaluation method described in the above embodiment for defect evaluation and detection.
  • a computer-readable medium on which a computer program is stored.
  • the program is executed by a processor, the defect assessment method as described in the above embodiments is implemented.
  • the wafer defect assessment solution collects defect data at the wafer process stage and test failure data after the process, and generates training samples based on the correspondence between the two, so as to perform model based on the training samples.
  • the failure prediction model in the test stage is trained.
  • the defect detection data is obtained through defect detection in the wafer process stage, the defect detection data is input into the failure prediction model in the test stage to output the predicted test failure prediction data to further use the defect detection data and test
  • the failure prediction data calculates the defect evaluation index of the wafer, and obtains the test failure prediction data by presetting the failure prediction model in the test stage. Based on the test failure prediction data, it is possible to determine which bare wafers to focus on for CP testing in the actual CP test. CP testing needs to be performed on all bare chips, which can reduce the workload of CP testing, shorten the CP testing cycle, and thus improve the production efficiency of memory chips.
  • the defect evaluation index of the wafer is obtained, and the process defects can be evaluated based on the defect evaluation index.
  • Figure 1 shows a flow chart of a wafer defect assessment method provided by one embodiment of the present disclosure
  • Figure 2 shows a flow chart of a wafer defect assessment method provided by another embodiment of the present disclosure
  • Figure 3 shows a flow chart of a wafer defect assessment method provided by yet another embodiment of the present disclosure
  • Figure 4 shows a flow chart of a wafer defect assessment method provided by yet another embodiment of the present disclosure
  • Figure 5 shows a flow chart of a wafer defect assessment method provided by yet another embodiment of the present disclosure
  • Figure 6 shows a schematic diagram of wafer defects provided by an embodiment of the present disclosure
  • FIG. 7 shows a schematic diagram of shape characteristics of defects on a wafer layer provided by an embodiment of the present disclosure
  • FIG. 8 shows a schematic diagram of shape characteristics of defects on a wafer layer in a die area provided by another embodiment of the present disclosure
  • Figure 9 shows a flow chart of a wafer defect assessment method provided by yet another embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a computer system suitable for implementing an electronic device according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • defect detection inline defect scan
  • DGD means that the detection result is Pass
  • DBD is the number of defective die with a test result of Fail.
  • CP Chip Probing
  • CGD is the CP test result. is the number of die with Pass and no defects
  • CBD is the number of die with CP test result of Fail and without defects.
  • the failure rate Kill Ratio, KR is calculated based on DGD, DBD, CGD and CBD. In order to obtain CGD and CBD, All bare chips need to be tested in the CP test, which results in a long test cycle and high test cost for the CP test.
  • an embodiment of the present disclosure first provides a wafer defect assessment method, including:
  • Step S102 Obtain defect detection data from random inspections of wafers during the manufacturing process.
  • the process stage refers to multiple film deposition processes and photolithography processes. Through different process processes, corresponding structures are formed on the current wafer layer. After the corresponding process process is completed, the current wafer will be Conduct random inspections on the layer surface to obtain defect detection data of the current wafer layer.
  • Step S104 input the defect detection data into the test stage failure prediction model to predict the test failure prediction data of all the bare dies on the wafer after the end of the process based on the test stage failure prediction model, where the test stage failure prediction model uses the test stage real Failure big data is used as training samples for model training and generation.
  • Real failure big data includes corresponding defect data at the wafer process stage and test failure data after the process is completed.
  • the corresponding relationship includes the test results of the process defect detection on the same die (1) and the CP test.
  • the test results (2), the test results (1) also include which wafer layer, which area was sampled, etc.
  • test failure data after the end of the process is obtained through CP testing.
  • CP testing is between wafer manufacturing and packaging in the entire chip production process. After the wafer Wafer production is completed, thousands of bare wafers (that is, unpackaged chips) are regularly distributed throughout the entire Wafer. Since they have not yet been diced and packaged, the pins of the chip are all exposed. These extremely tiny pins need to be connected to the testing machine Tester through a thinner probe Probe for testing.
  • CP test the above test failure data is the failure data obtained through CP test.
  • the predicted test failure prediction data can be output. Based on the test failure prediction data, it can be further determined which die should be focused on CP in the subsequent actual CP test. testing to reduce the workload of CP testing.
  • Step S106 Calculate the defect evaluation index of the wafer based on the defect detection data and the test failure prediction data.
  • the defect evaluation index of the wafer includes but is not limited to at least one of a correlation index, an importance index and a sensitivity index.
  • model training is performed based on the training samples to obtain a test stage failure prediction model.
  • defect detection data is obtained through defect detection at the wafer process stage
  • the defect detection data is input into the test stage failure prediction model to output the predicted test failure prediction data to further calculate the wafer based on the defect detection data and test failure prediction data.
  • Defect evaluation indicators by presetting the failure prediction model in the test stage, obtain the test failure prediction data. Based on the test failure prediction data, it can determine which dies to focus on CP testing in the actual CP test, and there is no need to perform CP testing on all dies. , can reduce the workload of CP testing, shorten the CP testing cycle, and thus improve the production efficiency of memory chips.
  • the defect evaluation index of the wafer is obtained, and the process defects can be evaluated based on the defect evaluation index.
  • inputting the defect detection data into the test stage failure prediction model to predict the test failure prediction data in the test stage based on the test stage failure prediction model includes: the defect detection data includes a first detection value and the second detection value.
  • the first detection value is the number of defective dies detected on the wafer layer and passed the test, that is, the number of areas that passed the defect detection DGD.
  • the second detection value is the number of defective dies detected and passed the test.
  • the number of failed dies that is, the number of areas that failed defect detection DBD, inputs the first detection value and the second detection value into the test stage failure prediction model to output test failure prediction data
  • the test failure prediction data includes the first prediction value and a second prediction value
  • the first prediction value is the predicted number of defective die CGD′ that pass the wafer test
  • the second prediction value is the number CBD′ of the defective die that fail during the wafer test.
  • the defect data of the wafer process stage includes the number of first die that passed the defect detection and the number of the second die that failed the defect detection detected in the completed wafer process stage.
  • test failure data includes the number of third die that passed the test and the number of fourth die that failed the test during the completed CP test, based on the number of first die and the number of second die and the number of third die and the corresponding relationship between the number of fourth die, model training is performed, and a failure prediction model in the test stage is obtained.
  • the test stage failure prediction model by inputting the first detection value and the second detection value into the test stage failure prediction model to output the corresponding first prediction value and the second prediction value, it can be based on the failure of the test in the wafer test.
  • the number of failed die and their locations further determine the die that need to be focused on testing in the actual CP test.
  • the correlation index R (Relevance) is used to characterize the correlation between defect detection data and test failure prediction data
  • the importance index I (Importance) is used to characterize The degree of impact of defects on test failure.
  • the sensitivity index S (Sensitivity) is used to characterize the rate of change of defect detection data with test failure prediction data.
  • the above indicators are calculated in units of wafer layers, that is, after each completion of one or more processes, corresponding defect detection is performed on the current wafer layer, based on Based on the detection results, the correlation index R, importance index I and sensitivity index S of this layer can be calculated.
  • the process is completed, multiple repeating units are formed on the wafer surface, each unit is called a die, and each die corresponds to a different area on the wafer.
  • the correlation index R the importance index I and the sensitivity index S as defect evaluation indicators
  • the impact of defects on the actual yield can be quantified from multiple aspects, the impact of quantified defects on the actual yield can be improved.
  • the specific evaluation method is given in the subsequent description.
  • calculating the correlation index based on the defect detection data and the test failure prediction data includes:
  • the correlation index is calculated based on the first formula.
  • the first formula is shown in Equation (2):
  • R is the correlation index
  • DGD is the first detection value
  • DBD is the second detection value
  • CBD′ is the second prediction value
  • Total′ is the sum of the first prediction value and the second prediction value, that is, CGD′ and CBD ''s sum.
  • the larger the value of R the greater the correlation between the actually detected first detection value DGB and the second detection value DBD and the predicted first prediction value CGD′ and second prediction value CBD′
  • the greater the sensitivity that is to say, the greater the impact of defects detected in the process stage on the results of subsequent CP tests.
  • calculating the importance index based on defect detection data and test failure prediction data includes:
  • Equation (3) The importance index is calculated based on the second formula.
  • Equation (3) The second formula is shown in Equation (3):
  • I is the importance index
  • DGD is the first detection value
  • DBD is the second detection value
  • CBD′ is the second prediction value
  • Total′ is the sum of the first prediction value and the second prediction value.
  • a larger value of I indicates that the detected defect of the wafer layer is more important, that is, the defect of this layer has a greater impact on the wafer yield.
  • calculating the sensitivity index based on the defect detection data and the test failure prediction data includes:
  • the sensitivity index is calculated based on the third formula, which is shown in Equation (4):
  • S is the sensitivity index
  • DGD is the first detection value
  • DBD is the second detection value
  • CBD′ is the second prediction value.
  • the defects on the wafer layer can be evaluated from multiple aspects. In improving the evaluation In addition to accuracy and reliability, it can also further screen out the wafer layers that need to be focused on based on the above index values, so as to simplify the CP test and improve the corresponding wafer layer process based on the screening results.
  • the key process wafer layer is used to predict the deletion of failed dies in post-test based on the failure prediction model in the test stage, that is, these failed dies will no longer be tested in post-test.
  • the wafer layer corresponding to the key process is screened based on the size of at least one of the correlation index R, the importance index I and the sensitivity index S among the defect evaluation indicators. Based on the screening As a result, on the one hand, it is possible to determine which process film layers are easily prepared to cause failure of the die in the CP test, and on the other hand, it is also possible to further determine which die need to be terminal tested in the CP test.
  • a specific implementation method of screening out key process wafer layers based on defect evaluation indicators includes:
  • Step S202 Sort the importance indicators, sensitivity indicators and correlation indicators from high to low according to the screening priority.
  • Step S204 Screen the defect evaluation indicators based on the screening priority to obtain key process wafer layers based on the screening results.
  • filtering based on the importance index I, R filtering based on the sensitivity index S, and filtering based on the correlation index are sorted from high to low according to the filtering priority.
  • Step S302 Perform correlation analysis on the defect shape characteristics and test failure data in the defect data at the wafer process stage.
  • Step S304 Set a first threshold, a second threshold and a third threshold based on the analysis results of the correlation analysis.
  • the first threshold is used to screen the importance indicators
  • the second threshold is used to screen the sensitivity indicators
  • the third threshold is used to screen the sensitivity indicators. Used to filter correlation indicators.
  • the correlation analysis includes but is not limited to how many defective areas on each wafer layer in the real failure big data in the test phase will cause CP test failure, and which shape characteristics of the defective areas are likely to cause Subsequent CP test failures of the die in this area, etc., based on the above correlation analysis results, the corresponding first threshold, second threshold and third threshold can be configured, so that the first threshold, second threshold and third threshold can be configured. At least one of them is used as a screening benchmark to obtain the screened key process wafer layers.
  • Step S306 Sort the importance index, sensitivity index and correlation index from high to low according to the screening priority.
  • defect evaluation indicators are screened based on the screening priority to obtain a specific implementation of the key process wafer layer based on the screening results, including:
  • Step S308 Filter out wafer layers whose importance index is less than or equal to 0 from all wafer layers to obtain wafer layers to be screened.
  • Step S310 Use the importance index greater than the first threshold as the first screening priority, screen out the first group of key wafer layers from the wafer layers to be screened, and obtain the remaining wafer layers.
  • Step S312 Use the sensitivity index greater than the second threshold as the second screening priority, and screen out the second group of key wafer layers from the remaining wafer layers to base on the first group of key wafer layers and the second group of key wafer layers.
  • the key process wafer layer is obtained.
  • Table 1 shows the calculation results of the three indices of each wafer layer from Layer1 to Layer26.
  • the key process wafer layers are obtained.
  • the improvement direction of the process can be further determined.
  • a method for screening key process wafer layers specifically includes:
  • Step S402 Perform a sampling scanning operation on the wafer to obtain defect detection data.
  • Step S404 Input the defect detection data into the test stage failure prediction model and output the test failure prediction data.
  • Step S406 Calculate the correlation index, importance index and sensitivity index based on the defect detection data and test failure prediction data. The calculation results are shown in Table 3.
  • Step S408 Determine defect attributes that can affect the CP test based on the threshold. The determination results are shown in Table 4.
  • Step S410 recalculate the correlation index, importance index and sensitivity index based on the defect attributes.
  • the calculation results are shown in Table 5.
  • step S102 the defect detection data for random inspection of the wafer during the manufacturing stage is also included:
  • Step S502 Configure a training model based on the assumption that defects are distributed on each wafer layer with a specified probability distribution.
  • the training model can be generated based on the neural network. Specifically, according to the task itself, the number of nodes in the input layer and output layer of the neural network can be determined. For example, the input layer and the output layer have two nodes respectively, and then assume that all grains are Defects with constant probability appear randomly, the initial parameters in the model are determined, and the training model is obtained.
  • Step S504 Extract the failure training features in the training samples, perform iterative training on the training model based on the failure training features, and obtain a failure prediction model in the test phase.
  • test stage failure prediction model is obtained.
  • the test stage failure prediction model obtained through machine learning can fully learn the defect data and process of the wafer process stage. Correspondence between the test failure data after completion, so better prediction results can be obtained for the test failure prediction data.
  • the failure training features in the training samples are extracted, the training model is iteratively trained based on the failure training features, and the failure prediction model obtained in the test stage includes: the failure training features include: The number of defects and the location of the die where the defects are located are iteratively trained based on the number of defects and the location of the die to obtain a failure prediction model in the test phase.
  • iterative training is performed based on the number of defects and the location of the die to obtain a failure prediction model in the test phase, which further includes: failure training features include shape features of defects, and iterative training is performed based on the shape. , until the training model converges to satisfy the correspondence relationship, where the shape features include the perimeter and/or area of the defect.
  • the shape features including the perimeter and/or area of the defect as failure training features, combined with the training of the corresponding relationship, it is possible to learn what shape of defects will cause the failure of the CP test.
  • the shape can be focused on.
  • the probability of defects in this shape is reduced by improving the process to improve the wafer preparation yield. .
  • FIG. 6 shows a defective wafer layer 60 and a die area 602 corresponding to the defective area on the wafer layer.
  • FIG. 7 illustrates defect length X and defect width Y for die area 602 .
  • FIG. 8 shows the defect area XY of die area 602.
  • Iterative training of the model based on the above-mentioned defect shape characteristics can determine which shapes of defects have a greater impact on wafer yield.
  • the training method of the failure prediction model in the test phase specifically includes:
  • Step S902 Collect defect data including defect parameters at the wafer process stage and test failure data after the process is completed.
  • Step S904 Perform iterative training based on the number of defects and the location of the defects.
  • Step S906 Iterative training is performed based on the shape until the training model converges to satisfy the corresponding relationship, and a failure prediction model in the test stage is obtained.
  • screening the defect evaluation indicators based on the screening priority to obtain the key process wafer layer based on the screening results also includes: inputting the defect detection data of the key process wafer layer into the test stage
  • the failure prediction model is used to output the location information of the failed die in the key process wafer layer based on the corresponding relationship.
  • FIG. 10 a schematic structural diagram of a computer system 1000 suitable for implementing an electronic device according to an embodiment of the present disclosure is shown.
  • the computer system 1000 of the electronic device shown in FIG. 10 is only an example, and should not bring any limitations to the functions and scope of use of the embodiments of the present disclosure.
  • computer system 1000 includes a central processing unit (CPU) 1001 that can operate according to a program stored in a read-only memory (ROM) 1002 or loaded from a storage portion 1008 into a random access memory (RAM) 1003 And perform various appropriate actions and processing.
  • CPU 1001, ROM 1002 and RAM 1003 are connected to each other through bus 1004.
  • An input/output (I/O) interface 1009 is also connected to bus 1004.
  • the following components are connected to the I/O interface 1005: an input section 1006 including a keyboard, a mouse, etc.; an output section 1007 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., speakers, etc.; and a storage section 1008 including a hard disk, etc. ; and a communication section 1009 including a network interface card such as a LAN card, a modem, etc.
  • the communication section 1009 performs communication processing via a network such as the Internet.
  • Driver 1010 is also connected to I/O interface 1005 as needed.
  • Removable media 1011 such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage portion 1008 as needed.
  • this application also provides a computer-readable medium.
  • the computer-readable medium may be included in the electronic device described in the above embodiments; it may also exist independently without being assembled into the electronic device. middle.
  • the computer-readable medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device implements the defect assessment method as in the above embodiment.
  • the electronic device can implement as shown in Figure 1: Step S102, obtain defect detection data for random inspection of wafers during the manufacturing process; Step S104, input the defect detection data into the test stage failure prediction model to predict the failure based on the test stage failure.
  • the prediction model predicts the test failure prediction data of all the die on the wafer after the end of the process.
  • the failure prediction model in the test phase uses the real failure big data in the test phase as training samples for model training and generation.
  • the real failure big data includes corresponding relationships.
  • embodiments of the present disclosure include a computer program product including a computer program carried on a computer-readable medium, the computer program containing program code for performing the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network via the communications component, and/or installed from removable media.
  • the central processing unit CPU
  • the above-mentioned functions defined in the system of the present application are executed.
  • the computer-readable medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the above two.
  • the computer-readable storage medium may be, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any combination thereof. More specific examples of computer readable storage media may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard drive, random access memory (RAM), read only memory (ROM), removable Programmd read-only memory (EPROM or flash memory), fiber optics, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • a computer-readable storage medium may be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.
  • a computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device .
  • Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the foregoing.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more logic functions that implement the specified executable instructions.
  • the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown one after another may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved.
  • each block in the block diagram or flowchart illustration, and combinations of blocks in the block diagram or flowchart illustration can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or may be implemented by special purpose hardware-based systems that perform the specified functions or operations. Achieved by a combination of specialized hardware and computer instructions.
  • the units involved in the embodiments of the present disclosure can be implemented in software or hardware, and the described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation on the unit itself under certain circumstances.
  • the example embodiments described here can be implemented by software, or can be implemented by software combined with necessary hardware. Therefore, the technical solution according to the embodiment of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to cause a computing device (which may be a personal computer, a server, a mobile terminal, a network device, etc.) to execute a method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a mobile terminal, a network device, etc.

Abstract

本公开提供了一种晶圆缺陷评估方法、装置、存储器芯片和可读存储介质，涉及半导体技术领域。其中，晶圆缺陷评估方法包括：获取在制程阶段对晶圆进行抽检的缺陷检测数据；将缺陷检测数据输入测试阶段失效预测模型，以基于测试阶段失效预测模型预测出在制程结束后晶圆上所有裸片的测试失效预测数据，其中，测试阶段失效预测模型使用测试阶段真实失效大数据作为训练样本进行模型训练生成，真实失效大数据包括具有对应关系的晶圆制程阶段缺陷数据和制程结束后的测试失效数据；基于缺陷检测数据和测试失效预测数据计算晶圆的缺陷评估指标。通过本公开的技术方案，能够减少CP测试的工作量，缩短CP测试周期，进而提升内存芯片的生产效率。

Description

晶圆缺陷评估方法、装置、存储器芯片和可读存储介质
本公开要求于2022年06月27日提交的申请号为202210745208.0、名称为“晶圆缺陷评估方法、装置、存储器芯片和可读存储介质”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种晶圆缺陷评估方法、一种晶圆缺陷评估装置、一种存储器和一种计算机可读存储介质。
背景技术
相关技术中，为了评估芯片的良率，提出了一种指标值KR(Kill Ratio)，KR的计算方式如式(1)所示：
Figure PCTCN2022110342-appb-000001
其中，在晶圆制造过程中，每形成一层膜层，会选择少量的裸片进行缺陷检测，并得到检测结果，DGD(defect good die)是检测结果为Pass且有缺陷的裸片数量，DBD(defect bad die)是测试结果为Fail且有缺陷的裸片数量，在制程结束后，还需要对生成的每个裸片进行CP(Chip Probing)测试，CGD(clean good die)是CP测试结果为Pass且无缺陷的裸片数量，CBD(clean bad die)是CP测试结果为Fail且无缺陷的裸片数量，而为了得到CGD和CBD，需要在CP测试中对所有的裸片进行测试，这就导致了CP测试的测试周期长，测试成本高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种晶圆缺陷评估方法、装置、存储器芯片和可读存储介质，能够减少CP测试的工作量，缩短CP测试周期，进而能够提升内存芯片的生产效率。。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
根据本公开的一个方面，提供一种晶圆缺陷评估方法，包括：获取在制程阶段对晶圆进行抽检的缺陷检测数据；
将所述缺陷检测数据输入测试阶段失效预测模型，以基于所述测试阶段失效预测模型预测出在制程结束后晶圆上所有裸片的测试失效预测数据，其中，所述测试阶段失效预测模型使用测试阶段真实失效大数据作为训练样本进行模型训练生成，所述真实失效大数据包括具有对应关系的晶圆制程阶段缺陷数据和制程结束后的测试失效数据；
基于所述缺陷检测数据和所述测试失效预测数据计算所述晶圆的缺陷评估指标。
在本公开的一种示例性实施例中，所述将所述缺陷检测数据输入测试阶段失效预测 模型，以基于所述测试阶段失效预测模型预测出在测试阶段的测试失效预测数据包括：
所述缺陷检测数据包括第一检测值和第二检测值，所述第一检测值为检测到的有缺陷且测试通过的裸片数量，所述第二检测值为检测到的有缺陷且测试失效的裸片数量，将所述第一检测值和所述第二检测值输入所述测试阶段失效预测模型，以输出所述测试失效预测数据，所述测试失效预测数据包括第一预测值和第二预测值，所述第一预测值为预测出的通过晶圆测试且无缺陷裸片数量，所述第二预测值为在所述晶圆测试中失效且无缺陷裸片数量。
在本公开的一种示例性实施例中，所述缺陷评估指标包括关联性指标、重要性指标和敏感度指标中的至少一种，
其中，所述关联性指标用于表征所述缺陷检测数据和所述测试失效预测数据之间的相关性，所述重要性指标用于表征缺陷对测试失效的影响程度，所述敏感度指标用于表征所述缺陷检测数据随所述测试失效预测数据的变化率。
在本公开的一种示例性实施例中，所述基于所述缺陷检测数据和所述测试失效预测数据计算所述缺陷评估指标包括：
基于第一公式计算所述关联性指标，
其中，所述第一公式为
Figure PCTCN2022110342-appb-000002
R为所述关联性指标，DGD为所述第一检测值，DBD为所述第二检测值，CBD′为所述第二预测值，Total′为所述第一预测值和所述第二预测值之和。
在本公开的一种示例性实施例中，所述基于所述缺陷检测数据和所述测试失效预测数据计算所述缺陷评估指标包括：
基于第二公式计算所述重要性指标，
其中，所述第二公式为
Figure PCTCN2022110342-appb-000003
I为所述重要性指标，DGD为所述第一检测值，DBD为所述第二检测值，CBD′为所述第二预测值，Total′为所述第一预测值和所述第二预测值之和。
在本公开的一种示例性实施例中，所述基于所述缺陷检测数据和所述测试失效预测数据计算所述缺陷评估指标包括：
基于第三公式计算所述敏感度指标，
其中，所述第三公式为
Figure PCTCN2022110342-appb-000004
S为所述敏感度指标，DGD为所述第一检测值，DBD为所述第二检测值，CBD′为所述第二预测值。
在本公开的一种示例性实施例中，还包括：
基于所述缺陷评估指标筛选出关键制程晶圆层，所述关键制程晶圆层用于预测出在后期测试中删除失效裸片。
在本公开的一种示例性实施例中，所述基于所述缺陷评估指标筛选出关键制程晶圆层包括：
将所述重要性指标、所述敏感度指标和所述关联性指标按照筛选优先级从高到低进行排序；
基于所述筛选优先级对所述缺陷评估指标进行筛选，以基于筛选结果得到所述关键制程晶圆层。
在本公开的一种示例性实施例中，在基于所述筛选优先级对所述缺陷评估指标进行筛选，以基于筛选结果得到所述关键制程晶圆层之前，还包括：
对所述晶圆制程阶段缺陷数据中的缺陷形状特征和所述测试失效数据进行相关性分析；
基于所述相关性分析的分析结果设置第一阈值、第二阈值和第三阈值，
其中，所述第一阈值用于对所述重要性指标进行筛选，所述第二阈值用于对所述敏感度指标进行筛选，所述第三阈值用于对所述关联性指标进行筛选。
在本公开的一种示例性实施例中，所述基于所述筛选优先级对所述缺陷评估指标进行筛选，以基于筛选结果得到所述关键制程晶圆层包括：
从全部晶圆层中过滤掉所述重要性指标小于或等于0的晶圆层，得到待筛选晶圆层；
将所述重要性指标大于所述第一阈值作为第一筛选优先级，从所述待筛选晶圆层中筛选出第一组关键晶圆层，并得到剩余晶圆层；
将所述敏感度指标大于所述第二阈值作为第二筛选优先级，从所述剩余晶圆层中筛选出第二组关键晶圆层，以基于所述第一组关键晶圆层和所述第二组关键晶圆层得到所述关键制程晶圆层。
在本公开的一种示例性实施例中，基于所述筛选优先级对所述缺陷评估指标进行筛选，以基于筛选结果得到所述关键制程晶圆层，还包括：
将所述关键制程晶圆层的缺陷检测数据输入所述测试阶段失效预测模型，以基于所述对应关系输出所述失效裸片在所述关键制程晶圆层的位置信息。
在本公开的一种示例性实施例中，所述在获取在制程阶段对晶圆进行抽检的缺陷检测数据之前，还包括：
基于缺陷在每层晶圆上均以指定概率分布的假设条件配置训练模型；
提取所述训练样本中的失效训练特征，基于所述失效训练特征对所述训练模型进行迭代训练，得到所述测试阶段失效预测模型。
在本公开的一种示例性实施例中，提取所述训练样本中的失效训练特征，基于所述失效训练特征对所述训练模型进行迭代训练，得到所述测试阶段失效预测模型包括：
所述失效训练特征包括所述每层晶圆上的缺陷数量和所述缺陷所在的裸片位置，基于所述缺陷数量和所述裸片位置进行所述迭代训练，以得到所述测试阶段失效预测模型。
在本公开的一种示例性实施例中，所述基于所述缺陷数量和所述裸片位置进行所述迭代训练，以得到所述测试阶段失效预测模型，还包括：
所述失效训练特征包括所述缺陷的形状特征，基于所述形状进行所述迭代训练，直至所述训练模型收敛至满足所述对应关系，
其中，所述形状特征包括所述缺陷的周长和/或面积。
根据本公开的另一个方面，提供了一种晶圆缺陷评估装置，包括：获取模块，用于获 取在制程阶段对晶圆进行抽检的缺陷检测数据；预测模块，用于将所述缺陷检测数据输入测试阶段失效预测模型，以基于所述测试阶段失效预测模型预测出在制程结束后晶圆上所有裸片的测试失效预测数据，其中，所述测试阶段失效预测模型使用测试阶段真实失效大数据作为训练样本进行模型训练生成，所述真实失效大数据包括具有对应关系的晶圆制程阶段缺陷数据和制程结束后的测试失效数据；计算模块，用于基于所述缺陷检测数据和所述测试失效预测数据计算所述晶圆的缺陷评估指标。
根据本公开的再一个方面，提供了一种存储器芯片，所述存储器芯片采用采用上述实施例所述的晶圆缺陷评估方法进行缺陷评估和检测。
根据本公开的又一个方面，提供了一种计算机可读介质，其上存储有计算机程序，所述程序被处理器执行时实现如上述实施例中所述的缺陷评估方法。
本公开的实施例所提供的晶圆缺陷评估方案，通过收集晶圆制程阶段缺陷数据和制程结束后的测试失效数据，并基于二者之间的对应关系生成训练样本，以基于训练样本进行模型训练得到测试阶段失效预测模型，在晶圆制程阶段通过缺陷检测得到缺陷检测数据时，将缺陷检测数据输入测试阶段失效预测模型，以输出预测的测试失效预测数据，以进一步基于缺陷检测数据和测试失效预测数据计算出晶圆的缺陷评估指标，通过预设测试阶段失效预测模型，得到测试失效预测数据，能够基于测试失效预测数据确定在实际CP测试中重点对哪些裸片进行CP测试，则不需要对全部裸片进行CP测试，能够减少CP测试的工作量，缩短CP测试周期，进而能够提升内存芯片的生产效率。
进一步地，通过采用缺陷检测数据和测试失效预测数据进行计算，得到晶圆的缺陷评估指标，能够基于缺陷评估指标进行制程缺陷的评估。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开的一个实施例提供的晶圆缺陷评估方法的流程图；
图2示出了本公开的另一个实施例提供的晶圆缺陷评估方法的流程图；
图3示出了本公开的再一个实施例提供的晶圆缺陷评估方法的流程图；
图4示出了本公开的又一个实施例提供的晶圆缺陷评估方法的流程图；
图5示出了本公开的又一个实施例提供的晶圆缺陷评估方法的流程图；
图6示出了本公开的一个实施例提供的晶圆缺陷示意图；
图7示出了本公开的一个实施例提供的晶圆层上缺陷的形状特征的示意图；
图8示出了本公开的另一个实施例提供的裸片区域中晶圆层上的缺陷的形状特征的示意图；
图9示出了本公开的又一个实施例提供的晶圆缺陷评估方法的流程图；
图10为本公开的一种实施例提供的适于用来实现本公开实施例的电子设备的计算机系统的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明，不是必须包括所有的内容和步骤，也不是必须按所描述的顺序执行。例如，有的步骤还可以分解，而有的步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。用语“一个”、“一”和“上述”等用以表示存在一个或多个要素/组成部分/等。术语“包含”、“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
相关技术中，在晶圆制造过程中，在相应的制程阶段，会对晶圆上当前的膜层上的局部区域进行缺陷检测(inline defect scan)，并得到检测结果，DGD是检测结果为Pass且有缺陷的裸片数量，DBD是测试结果为Fail且有缺陷的裸片数量，在制程结束后，还需要对最终获得的每个裸片进行CP(Chip Probing)测试，CGD是CP测试结果为Pass且无缺陷的裸片数量，CBD是CP测试结果为Fail且无缺陷的裸片数量，基于DGD、DBD、CGD和CBD计算失效率(Kill Ratio，KR)，而为了得到CGD和CBD，需要在CP测试中对所有的裸片进行测试，这就导致了CP测试的测试周期长，测试成本高。
参照图1，本公开的实施例首先提供了一种晶圆缺陷评估方法，包括：
步骤S102，获取在制程阶段对晶圆进行抽检的缺陷检测数据。
其中，制程阶段指包括多个膜层沉积工艺和光刻工艺等，通过不同的制程工艺，在当前晶圆层上形成相应的结构，在执行完相应的制程工艺后，会对当前的晶圆层表面进行抽检，获得当前晶圆层的缺陷(defect)检测数据。
步骤S104，将缺陷检测数据输入测试阶段失效预测模型，以基于测试阶段失效预测模型预测出在制程结束后晶圆上所有裸片的测试失效预测数据，其中，测试阶段失效预测模型使用测试阶段真实失效大数据作为训练样本进行模型训练生成，真实失效大数据包括具有对应关系的晶圆制程阶段缺陷数据和制程结束后的测试失效数据。
其中，基于对同一晶圆Wafer分别进行制程中的缺陷检测和制程后的CP测试得到的测试结果，对应关系包括测试结果中的同一裸片进行制程defect检测的检测结果(1)和进行CP测试的测试结果(2)，检测结果(1)还包括在哪一晶圆层对哪个区域进行抽检等。
另外，制程结束后的测试失效数据通过CP测试得到，CP测试在整个芯片的制作流程中处于晶圆制造和封装之间，晶圆Wafer制作完成之后，成千上万的裸片(即未封装的芯片)规则的分布满整个Wafer，由于尚未进行划片封装，芯片的管脚全部裸露在外，这些极微小的管脚需要通过更细的探针Probe来与测试机台Tester连接，以进行CP测试，上述的测试失效数据即通过CP测试得到的失效数据。
通过收集晶圆制程阶段缺陷数据和制程结束后的测试失效数据，得到模型训练的训练样本，通过机器学习进行模型训练，以得到测试阶段失效预测模型。
通过将获取到的缺陷检测数据输入测试阶段失效预测模型，即可输出预测出的测试失效预测数据，基于测试失效预测数据即可进一步确定在后续的实际CP测试中，重点对哪些裸片进行CP测试，以减少CP测试的工作量。
步骤S106，基于缺陷检测数据和测试失效预测数据计算晶圆的缺陷评估指标。
其中，晶圆的缺陷评估指标包括但不限于关联性指标、重要性指标和敏感度指标中的至少一种。
在该实施例中，通过收集晶圆制程阶段缺陷数据和制程结束后的测试失效数据，并基于二者之间的对应关系生成训练样本，以基于训练样本进行模型训练得到测试阶段失效预测模型，在晶圆制程阶段通过缺陷检测得到缺陷检测数据时，将缺陷检测数据输入测试阶段失效预测模型，以输出预测的测试失效预测数据，以进一步基于缺陷检测数据和测试失效预测数据计算出晶圆的缺陷评估指标，通过预设测试阶段失效预测模型，得到测试失效预测数据，能够基于测试失效预测数据确定在实际CP测试中重点对哪些裸片进行CP测试，则不需要对全部裸片进行CP测试，能够减少CP测试的工作量，缩短CP测试周期，进而能够提升内存芯片的生产效率。
进一步地，通过采用缺陷检测数据和测试失效预测数据进行计算，得到晶圆的缺陷评估指标，能够基于缺陷评估指标进行制程缺陷的评估。
在本公开的一种示例性实施例中，将缺陷检测数据输入测试阶段失效预测模型，以基于测试阶段失效预测模型预测出在测试阶段的测试失效预测数据包括：缺陷检测数据包括第一检测值和第二检测值，第一检测值为晶圆层上检测到的有缺陷且测试通过的裸片数量，即通过缺陷检测的区域的数量DGD，第二检测值为检测到的有缺陷且测试失效的 裸片数量，即未通过缺陷检测的区域的数量DBD，将第一检测值和第二检测值输入测试阶段失效预测模型，以输出测试失效预测数据，测试失效预测数据包括第一预测值和第二预测值，第一预测值为预测出的通过晶圆测试且无缺陷裸片数量CGD′，第二预测值为在晶圆测试中失效且无缺陷裸片数量CBD′。
其中，本领域的技术人员能够理解的是，晶圆制程阶段缺陷数据包括在已完成的晶圆制程阶段中检测到的通过缺陷检测的第一裸片数量和未通过缺陷检测的第二裸片数量，测试失效数据包括已完成的CP测试过程中通过测试的第三裸片数量和没有通过测试的第四裸片数量，基于第一裸片数量和第二裸片数量与第三裸片数量和第四裸片数量之间的对应关系，进行模型训练，得到测试阶段失效预测模型。
在该实施例中，通过将第一检测值和第二检测值输入测试阶段失效预测模型，以输出对应的第一预测值和第二预测值，则可基于在晶圆测试中未通过测试的失效裸片数量与其所处的位置，进一步确定在实际CP测试中需要重点测试的裸片。
另外，由于KR不能够准确地量化缺陷对实际良率的影响，例如，如果在晶圆制造过程中的缺陷检测只检测出一个缺陷区域，而CP测试也失效，此时KR＝1，但是实际的良率影响仍未知。
进一步地，由于晶圆制造过程中的缺陷检测与晶圆制程结束后的CP测试存在样本之间的差异，因此在目前的良率评估方案中，也无法确定制造过程中哪一晶圆膜层的制程缺陷对后续的CP测试产生重要影响。
基于上述缺陷，在本公开的一种示例性实施例中，关联性指标R(Relevance)用于表征缺陷检测数据和测试失效预测数据之间的相关性，重要性指标I(Importance)用于表征缺陷对测试失效的影响程度，敏感度指标S(Sensitivity)用于表征缺陷检测数据随测试失效预测数据的变化率。
具体地，本领域的技术人员能够理解的是，上述指标的计算以晶圆层为单位进行计算，即在每完成一道或多道制程工艺后，对当前晶圆层进行对应的缺陷检测，基于检测结果，即可计算出该层的关联性指标R、重要性指标I和敏感度指标S。另外，本领域技术人员能够理解的是，在制程完成后，晶圆表面上形成了多个重复的单元，每个单元即称之为裸片，每个裸片对应晶圆上不同的区域。
在该实施例中，通过采用关联性指标R、重要性指标I和敏感度指标S作为缺陷评估指标，由于能够从多个方面量化缺陷对实际良率的影响，因此能够提升量化缺陷对实际良率的影响的准确性，另外，通过计算出上述三个缺陷评估指标，也能够进一步评估出哪些制程缺陷对CP测试和晶圆良率影响较大，具体评估方式在后续描述中给出。
在本公开的一种示例性实施例中，基于缺陷检测数据和测试失效预测数据计算关联性指标包括：
基于第一公式计算关联性指标，第一公式如式(2)所示：
Figure PCTCN2022110342-appb-000005
其中，R为关联性指标，DGD为第一检测值，DBD为第二检测值，CBD′为第二预测值，Total′为第一预测值和第二预测值之和，即CGD′和CBD′的和。
在该实施例中，R的值越大，表明实际检测到的第一检测值DGB和第二检测值DBD，与预测出的第一预测值CGD′和第二预测值CBD′之间的关联性越大，也就是说，在制程阶段检测到的缺陷defect对后续的CP测试的结果的影响越大。
在本公开的一种示例性实施例中，基于缺陷检测数据和测试失效预测数据计算重要性指标包括：
基于第二公式计算重要性指标，第二公式如式(3)所示：
Figure PCTCN2022110342-appb-000006
其中，I为重要性指标，DGD为第一检测值，DBD为第二检测值，CBD′为第二预测值，Total′为第一预测值和第二预测值之和。
在该实施例中，I的值越大，表明检测到的晶圆层的缺陷defect的重要性越高，即该层缺陷对晶圆良率的影响越大。
在本公开的一种示例性实施例中，基于缺陷检测数据和测试失效预测数据计算敏感度指标包括：
基于第三公式计算敏感度指标，第三公式如式(4)所示：
Figure PCTCN2022110342-appb-000007
其中，S为敏感度指标，DGD为第一检测值，DBD为第二检测值，CBD′为第二预测值。
具体地，如果S＝1，表明检测到的缺陷对CP测试结果的发生不起作用，如果S＞1，表明检测到的缺陷是危险因素，如果S＜1，表明检测到的缺陷是保护因素。
在上述实施例中，通过分别计算出每一晶圆层的关联性指标R、重要性指标I和敏感度指标S，实现了从多个方面对晶圆层上的缺陷进行评估，在提升评估准确性和可靠性的同时，也能够进一步基于上述指标值筛选出需要重点关注的晶圆层，以基于筛选结果进行CP测试的简化和相应晶圆层制程的改进等操作。
进一步地，为了确定制造过程中哪一晶圆膜层的制程缺陷对后续的CP测试产生重要影响，在本公开的一种示例性实施例中，还包括：基于缺陷评估指标筛选出关键制程晶圆层，关键制程晶圆层用于基于测试阶段失效预测模型预测出在后期测试中删除失效裸片，即在后期测试中不再对这些失效的裸片进行测试。
在该实施例中，通过基于缺陷评估指标中的关联性指标R、重要性指标I和敏感度指标S中的至少一种的指标值的大小，进行关键制程对应晶圆层的筛选，基于筛选结果，一方面，能够确定哪些工艺膜层的制备容易导致CP测试中裸片的失效，另一方，也能够进一步确定在CP测试中需要对哪些裸片进行终端测试。
如图2所示，在本公开的一种示例性实施例中，基于缺陷评估指标筛选出关键制程晶圆层的一种具体实现方式，包括：
步骤S202，将重要性指标、敏感度指标和关联性指标按照筛选优先级从高到低进行排序。
步骤S204，基于筛选优先级对缺陷评估指标进行筛选，以基于筛选结果得到关键制程晶圆层。
其中，作为筛选优先级的一种配置方式，将基于重要性指标I筛选、R基于敏感度指标S筛选和基于关联性指标筛选按照筛选优先级，从高到低排序。
在该实施例中，通过基于筛选优先级对缺陷评估指标进行筛选的筛选方式，能够得到需要重点关注的关键制程晶圆层，以保证筛选出的关键制程晶圆层的有效性。
如图3所示，在本公开的一种示例性实施例中，在基于筛选优先级对缺陷评估指标进行筛选，以基于筛选结果得到关键制程晶圆层之前，还包括：
步骤S302，对晶圆制程阶段缺陷数据中的缺陷形状特征和测试失效数据进行相关性分析。
步骤S304，基于相关性分析的分析结果设置第一阈值、第二阈值和第三阈值，第一阈值用于对重要性指标进行筛选，第二阈值用于对敏感度指标进行筛选，第三阈值用于对关联性指标进行筛选。
在该实施例中，相关性分析包括但不限于测试阶段真实失效大数据中的每个晶圆层上的缺陷区域的数量达到多少时会导致CP测试失效，以及缺陷区域的哪些形状特征容易导致该区域的裸片后续的CP测试失效等，基于上述的相关性分析结果，即可配置对应的第一阈值、第二阈值和第三阈值，从而将第一阈值、第二阈值和第三阈值中的至少一个作为筛选基准，得到筛选出的关键制程晶圆层。
步骤S306，将重要性指标、敏感度指标和关联性指标按照筛选优先级从高到低进行排序。
在本公开的一种示例性实施例中，步骤S204，基于筛选优先级对缺陷评估指标进行筛选，以基于筛选结果得到关键制程晶圆层的一种具体实现方式，包括：
步骤S308，从全部晶圆层中过滤掉重要性指标小于或等于0的晶圆层，得到待筛选晶圆层。
步骤S310，将重要性指标大于第一阈值作为第一筛选优先级，从待筛选晶圆层中筛选出第一组关键晶圆层，并得到剩余晶圆层。
步骤S312，将敏感度指标大于第二阈值作为第二筛选优先级，从剩余晶圆层中筛选出第二组关键晶圆层，以基于第一组关键晶圆层和第二组关键晶圆层得到关键制程晶圆层。
具体地，表1示出了Layer1至Layer26中，每个晶圆层的三个指数的计算结果。
表1
STEP_NAME Relevance Importance Sensitivity
Layer1 1.169 0.103 2.660
Layer2 1.610 0.096 3.792
Layer3 1.392 0.095 4.116
Layer4 1.201 0.068 2.125
Layer5 1.594 0.064 2.997
Layer6 2.266 0.053 4.739
Layer7 1.294 0.051 2.005
Layer8 1.258 0.051 1.941
Layer9 1.182 0.045 1.719
Layer10 1.481 0.028 2.033
Layer11 1.177 0.018 1.377
Layer12 1.552 0.016 2.031
Layer13 1.018 0.003 1.045
Layer14 1.427 0.001 1.587
Layer15 0.990 0.000 0.985
Layer16 0.924 -0.003 0.889
Layer17 0.930 -0.005 0.887
Layer18 0.791 -0.008 0.717
Layer19 0.609 -0.014 0.510
Layer20 0.731 -0.015 0.628
Layer21 0.649 -0.015 0.547
Layer22 0.468 -0.017 0.377
Layer23 0.690 -0.020 0.568
Layer24 0.533 -0.023 0.417
Layer25 0.673 -0.032 0.516
Layer26 0.486 -0.139 0.204
基于上述的筛选优先级，首先过滤掉I指小于或等于0的晶圆层，然后对表1中的数据进行统一处理后，得到表2中的数据，然后基于重要性指标I进行筛选，筛选结果如表2中的Layer1至Layer6。
其中，对表1中的数据进行统一处理的处理方式包括：基于给定检查层的扫描裸片的数量Ns和所有裸片的数量Nt计算比值Weight，将Weight作为系数重新计算Nt，得到Nt’，重新计算Cf(Cf＝DBD+CBD′),得到Cf’，重新计算Cp(Cp＝Nt’-Cf’)，得到Cp’，重新计算第二预测值CBD’＝max(Cf’-DBD,0)，重新计算第一预测值CGD’＝Nt’-DBD-CBD’-DGD。
基于上述重新计算的值，重新计算关联性指标、重要性指标和敏感度指标，得到表2中的数据。
进一步基于敏感度指标S进行筛选，筛选出对CP失效检测具有比较高的敏感性的Layer20、Layer15、Layer17、Layer13、Layer19和Layer21，如表2所示。
基于上述的筛选结果得到关键制程晶圆层，一方面，基于每层对应的制程工艺，可以进一步确定该工艺的改进方向，另一方面，基于这些关键制程晶圆层，也可以进一步确定哪些裸片在CP测试中需要重点关注，哪些不需要。
表2
Figure PCTCN2022110342-appb-000008
Figure PCTCN2022110342-appb-000009
如图4所示，根据本公开的一个实施例的关键制程晶圆层的筛选方法，具体包括：
步骤S402，对晶圆进行抽样扫描操作，得到缺陷检测数据。
步骤S404，将缺陷检测数据输入测试阶段失效预测模型，输出测试失效预测数据。
步骤S406，基于缺陷检测数据和测试失效预测数据计算关联性指标、重要性指标和敏感度指标。计算结果如表3所示。
步骤S408，基于阈值确定能够影响CP测试的缺陷属性。确定结果如表4所示。
步骤S410，基于缺陷属性重新计算关联性指标、重要性指标和敏感度指标。计算结果如表5所示。
表3
STEP_NAME Relevance Importance Sensitivity
Layer1 1.169 0.103 2.660
Layer2 1.610 0.096 3.792
Layer3 1.392 0.095 4.116
Layer4 1.201 0.068 2.125
Layer5 1.594 0.064 2.997
Layer6 2.266 0.053 4.739
Layer7 1.294 0.051 2.005
Layer8 1.258 0.051 1.941
Layer9 1.182 0.045 1.719
Layer10 1.481 0.028 2.033
Layer11 1.177 0.018 1.377
Layer12 1.552 0.016 2.031
Layer13 1.018 0.003 1.045
Layer14 1.427 0.001 1.587
表4
STEP_NAME DEF.Attributes DEF.Value DC.Fail Dies DEF.Dies
Layer1 Attri.1 555 1 1
Layer2 Attri.2 535.004 1 1
Layer3 Attri.3 396.635 0 0
Layer4 Attri.4 68.96679 0 0
Layer5 Attri.5 41.203 0 0
Layer6 Attri.6 1.708 223 702
Layer7 Attri.7 0.00139934 568 2258
Layer8 Attri.8 57.731 1 1
Layer9 Attri.9 57.637 0 0
Layer10 Attri.10 5 601 1141
Layer11 Attri.11 0.01153249 106 298
Layer12 Attri.12 0.6439 229 716
…etc … … … …
表5
STEP_NAME Relevance Importance Sensitivity
Layer1 1.300 0.080 2.483
Layer2 1.986 0.074 4.533
Layer3 3.106 0.048 8.519
Layer4 2.053 0.033 3.445
Layer5 3.971 0.032 11.867
Layer6 1.906 0.031 2.992
Layer7 1.844 0.022 2.665
Layer8 1.512 0.018 1.986
如图5所示，在本公开的一种示例性实施例中，在步骤S102，获取在制程阶段对晶圆进行抽检的缺陷检测数据之前，还包括：
步骤S502，基于缺陷在每层晶圆上均以指定概率分布的假设条件配置训练模型。
其中，训练模型可以基于神经网络生成，具体地，根据任务本身，可以确定神经网络输入层与输出层的节点个数，比如，输入层和输出层分别设2个节点，然后假设所有晶粒都随机出现概率恒定的缺陷，确定模型中的初始参数，得到训练模型。
步骤S504，提取训练样本中的失效训练特征，基于失效训练特征对训练模型进行迭代训练，得到测试阶段失效预测模型。
在该实施例中，通过运用统计方法与机器学习进行模型的迭代训练，得到测试阶段失效预测模型，通过机器学习得到的测试阶段失效预测模型，由于能够充分学习到晶圆制程阶段缺陷数据和制程结束后的测试失效数据之间的对应关系，因此对测试失效预测数据能够得到较好的预测效果。
在本公开的一种示例性实施例中，提取训练样本中的失效训练特征，基于失效训练特征对训练模型进行迭代训练，得到测试阶段失效预测模型包括：失效训练特征包括每层晶圆上的缺陷数量和缺陷所在的裸片位置，基于缺陷数量和裸片位置进行迭代训练，以得到测试阶段失效预测模型。
在该实施例中，通过将每层晶圆上的缺陷数量和缺陷所在的裸片位置确定为失效训练特征，结合对对应关系的训练，即可获知每个晶圆上大概有多少个缺陷时会造成CP测试的失效，以及失效裸片的所在位置。
在本公开的一种示例性实施例中，基于缺陷数量和裸片所在的位置进行迭代训练，以得到测试阶段失效预测模型，还包括：失效训练特征包括缺陷的形状特征，基于形状进行迭代训练，直至训练模型收敛至满足对应关系，其中，形状特征包括缺陷的周长和/或面积。
在该实施例中，通过将包括缺陷的周长和/或面积在内的形状特征作为失效训练特征，结合对对应关系的训练，即可获知何种形状的缺陷会造成CP测试的失效，一方面，在CP测试中，对该形状可以进行重点关注，另一方面，在晶圆制程过程中，通过对工艺的改善，减小该形状的缺陷出现的概率，以提升晶圆的制备良率。
图6示出了一个有缺陷的晶圆层60，以及该晶圆层上的缺陷区域对应的裸片区域602。
图7示出了裸片区域602的缺陷长度X和缺陷宽度Y。
图8示出了裸片区域602的缺陷面积XY。
基于上述的缺陷的形状特征进行模型的迭代训练，可以确定哪些形状的缺陷对晶圆良率造成的影响较大。
如图9所示，根据本公开的一个实施例的测试阶段失效预测模型的训练方法，具体包括：
步骤S902，分别收集包括缺陷参数的晶圆制程阶段缺陷数据和制程结束后的测试失效数据。
步骤S904，基于缺陷数量和缺陷所在的位置进行迭代训练。
步骤S906，基于形状进行迭代训练，直至训练模型收敛至满足对应关系，得到测试阶段失效预测模型。
在本公开的一种示例性实施例中，基于筛选优先级对缺陷评估指标进行筛选，以基于筛选结果得到关键制程晶圆层，还包括：将关键制程晶圆层的缺陷检测数据输入测试阶段失效预测模型，以基于对应关系输出失效裸片在关键制程晶圆层的位置信息。
下面参考图10，其示出了适于用来实现本公开实施例的电子设备的计算机系统1000的结构示意图。图10示出的电子设备的计算机系统1000仅是一个示例，不应对本公开实施例的功能和使用范围带来任何限制。
如图10所示，计算机系统1000包括中央处理单元(CPU)1001，其可以根据存储在只读存储器(ROM)1002中的程序或者从存储部分1008加载到随机访问存储器(RAM)1003中的程序而执行各种适当的动作和处理。在RAM 1003中，还存储有系统操作所需的各种程序和数据。CPU 1001、ROM 1002以及RAM 1003通过总线1004彼此相连。输入/输出(I/O)接口1009也连接至总线1004。
以下部件连接至I/O接口1005：包括键盘、鼠标等的输入部分1006；包括诸如阴极射线管(CRT)、液晶显示器(LCD)等以及扬声器等的输出部分1007；包括硬盘等的存储部分1008；以及包括诸如LAN卡、调制解调器等的网络接口卡的通信部分1009。通信部分1009经由诸如因特网的网络执行通信处理。驱动器1010也根据需要连接至I/O接口 1005。可拆卸介质1011，诸如磁盘、光盘、磁光盘、半导体存储器等等，根据需要安装在驱动器1010上，以便于从其上读出的计算机程序根据需要被安装入存储部分1008。
作为另一方面，本申请还提供了一种计算机可读介质，该计算机可读介质可以是上述实施例中描述的电子设备中所包含的；也可以是单独存在，而未装配入该电子设备中。上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被一个该电子设备执行时，使得该电子设备实现如上述实施例中的缺陷评估方法。
例如，电子设备可以实现如图1中所示的：步骤S102，获取在制程阶段对晶圆进行抽检的缺陷检测数据；步骤S104，将缺陷检测数据输入测试阶段失效预测模型，以基于测试阶段失效预测模型预测出在制程结束后晶圆上所有裸片的测试失效预测数据，其中，测试阶段失效预测模型使用测试阶段真实失效大数据作为训练样本进行模型训练生成，真实失效大数据包括具有对应关系的晶圆制程阶段缺陷数据和制程结束后的测试失效数据；步骤S106，基于缺陷检测数据和测试失效预测数据计算晶圆的缺陷评估指标。
特别地，根据本公开的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在计算机可读介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分从网络上被下载和安装，和/或从可拆卸介质被安装。在该计算机程序被中央处理单元(CPU)执行时，执行本申请的系统中限定的上述功能。
需要说明的是，本公开所示的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本公开中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本公开中，计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：无线、电线、光缆、RF等等，或者上述的任意合适的组合。
附图中的流程图和框图，图示了按照本公开各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，上述模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框 实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图或流程图中的每个方框、以及框图或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
描述于本公开实施例中所涉及到的单元可以通过软件的方式实现，也可以通过硬件的方式来实现，所描述的单元也可以设置在处理器中。其中，这些单元的名称在某种情况下并不构成对该单元本身的限定。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、移动终端、或者网络设备等)执行根据本公开实施方式的方法。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (17)

  1. 一种晶圆缺陷评估方法，包括：
    获取在制程阶段对晶圆进行抽检的缺陷检测数据；
    将所述缺陷检测数据输入测试阶段失效预测模型，以基于所述测试阶段失效预测模型预测出在制程结束后晶圆上所有裸片的测试失效预测数据，其中，所述测试阶段失效预测模型使用测试阶段真实失效大数据作为训练样本进行模型训练生成，所述真实失效大数据包括具有对应关系的晶圆制程阶段缺陷数据和制程结束后的测试失效数据；
    基于所述缺陷检测数据和所述测试失效预测数据计算所述晶圆的缺陷评估指标。
  2. 根据权利要求1所述的晶圆缺陷评估方法，其中，所述将所述缺陷检测数据输入测试阶段失效预测模型，以基于所述测试阶段失效预测模型预测出在测试阶段的测试失效预测数据包括：
    所述缺陷检测数据包括第一检测值和第二检测值，所述第一检测值为检测到的有缺陷且测试通过的裸片数量，所述第二检测值为检测到的有缺陷且测试失效的裸片数量，将所述第一检测值和所述第二检测值输入所述测试阶段失效预测模型，以输出所述测试失效预测数据，所述测试失效预测数据包括第一预测值和第二预测值，所述第一预测值为预测出的通过晶圆测试且无缺陷裸片数量，所述第二预测值为在所述晶圆测试中失效且无缺陷裸片数量。
  3. 根据权利要求2所述的晶圆缺陷评估方法，其中，所述缺陷评估指标包括关联性指标、重要性指标和敏感度指标中的至少一种，
    其中，所述关联性指标用于表征所述缺陷检测数据和所述测试失效预测数据之间的相关性，所述重要性指标用于表征缺陷对测试失效的影响程度，所述敏感度指标用于表征所述缺陷检测数据随所述测试失效预测数据的变化率。
  4. 根据权利要求3所述的晶圆缺陷评估方法，其中，所述基于所述缺陷检测数据和所述测试失效预测数据计算所述缺陷评估指标包括：
    基于第一公式计算所述关联性指标，
    其中，所述第一公式为
    Figure PCTCN2022110342-appb-100001
    R为所述关联性指标，DGD为所述第一检测值，DBD为所述第二检测值，CBD′为所述第二预测值，Total′为所述第一预测值和所述第二预测值之和。
  5. 根据权利要求3或4所述的晶圆缺陷评估方法，其中，所述基于所述缺陷检测数据和所述测试失效预测数据计算所述缺陷评估指标包括：
    基于第二公式计算所述重要性指标，
    其中，所述第二公式为
    Figure PCTCN2022110342-appb-100002
    I为所述重要性指标，DGD为所述第一检测值，DBD为所述第二检测值，CBD′为所述第二预测值，Total′为所述第一预测值和所述第二预测值之和。
  6. 根据权利要求3至5中任一项所述的晶圆缺陷评估方法，其中，所述基于所述缺 陷检测数据和所述测试失效预测数据计算所述缺陷评估指标包括：
    基于第三公式计算所述敏感度指标，
    其中，所述第三公式为
    Figure PCTCN2022110342-appb-100003
    S为所述敏感度指标，DGD为所述第一检测值，DBD为所述第二检测值，CBD′为所述第二预测值。
  7. 根据权利要求3至6中任一项所述的晶圆缺陷评估方法，其中，还包括：
    基于所述缺陷评估指标筛选出关键制程晶圆层，所述关键制程晶圆层用于预测出在后期测试中删除失效裸片。
  8. 根据权利要求7所述的晶圆缺陷评估方法，其中，所述基于所述缺陷评估指标筛选出关键制程晶圆层包括：
    将所述重要性指标、所述敏感度指标和所述关联性指标按照筛选优先级从高到低进行排序；
    基于所述筛选优先级对所述缺陷评估指标进行筛选，以基于筛选结果得到所述关键制程晶圆层。
  9. 根据权利要求8所述的晶圆缺陷评估方法，其中，在基于所述筛选优先级对所述缺陷评估指标进行筛选，以基于筛选结果得到所述关键制程晶圆层之前，还包括：
    对所述晶圆制程阶段缺陷数据中的缺陷形状特征和所述测试失效数据进行相关性分析；
    基于所述相关性分析的分析结果设置第一阈值、第二阈值和第三阈值，
    其中，所述第一阈值用于对所述重要性指标进行筛选，所述第二阈值用于对所述敏感度指标进行筛选，所述第三阈值用于对所述关联性指标进行筛选。
  10. 根据权利要求9所述的晶圆缺陷评估方法，其中，所述基于所述筛选优先级对所述缺陷评估指标进行筛选，以基于筛选结果得到所述关键制程晶圆层包括：
    从全部晶圆层中过滤掉所述重要性指标小于或等于0的晶圆层，得到待筛选晶圆层；
    将所述重要性指标大于所述第一阈值作为第一筛选优先级，从所述待筛选晶圆层筛选出第一组关键晶圆层，并得到剩余晶圆层；
    将所述敏感度指标大于所述第二阈值作为第二筛选优先级，从所述剩余晶圆层中筛选出第二组关键晶圆层，以基于所述第一组关键晶圆层和所述第二组关键晶圆层得到所述关键制程晶圆层。
  11. 根据权利要求8至10中任一项所述的晶圆缺陷评估方法，其中，基于所述筛选优先级对所述缺陷评估指标进行筛选，以基于筛选结果得到所述关键制程晶圆层，还包括：
    将所述关键制程晶圆层的缺陷检测数据输入所述测试阶段失效预测模型，以基于所述对应关系输出所述失效裸片在所述关键制程晶圆层的位置信息。
  12. 根据权利要求1至11中任一项所述的晶圆缺陷评估方法，其中，所述在获取在制程阶段对晶圆进行抽检的缺陷检测数据之前，还包括：
    基于缺陷在每层晶圆上均以指定概率分布的假设条件配置训练模型；
    提取所述训练样本中的失效训练特征，基于所述失效训练特征对所述训练模型进行迭代训练，得到所述测试阶段失效预测模型。
  13. 根据权利要求12所述的晶圆缺陷评估方法，其中，提取所述训练样本中的失效训练特征，基于所述失效训练特征对所述训练模型进行迭代训练，得到所述测试阶段失效预测模型包括：
    所述失效训练特征包括所述每层晶圆上的缺陷数量和所述缺陷所在的裸片位置，基于所述缺陷数量和所述裸片位置进行所述迭代训练，以得到所述测试阶段失效预测模型。
  14. 根据权利要求13所述的晶圆缺陷评估方法，其中，所述基于所述缺陷数量和所述裸片位置进行所述迭代训练，以得到所述测试阶段失效预测模型，还包括：
    所述失效训练特征包括所述缺陷的形状特征，基于所述形状进行所述迭代训练，直至训练模型收敛至满足所述对应关系，
    其中，所述形状特征包括所述缺陷的周长和/或面积。
  15. 一种晶圆缺陷评估装置，包括：
    获取模块，用于获取在制程阶段对晶圆进行抽检的缺陷检测数据；
    预测模块，用于将所述缺陷检测数据输入测试阶段失效预测模型，以基于所述测试阶段失效预测模型预测出在制程结束后晶圆上所有裸片的测试失效预测数据，其中，所述测试阶段失效预测模型使用测试阶段真实失效大数据作为训练样本进行模型训练生成，所述真实失效大数据包括具有对应关系的晶圆制程阶段缺陷数据和制程结束后的测试失效数据；
    计算模块，用于基于所述缺陷检测数据和所述测试失效预测数据计算所述晶圆的缺陷评估指标。
  16. 一种存储器芯片，所述存储器芯片采用如权利要求1-14中任一项所述的晶圆缺陷评估方法进行缺陷评估和检测。
  17. 一种计算机可读介质，其上存储有计算机程序，所述程序被处理器执行时实现如权利要求1-14中任一项所述的晶圆缺陷评估方法。
PCT/CN2022/110342 2022-06-27 2022-08-04 晶圆缺陷评估方法、装置、存储器芯片和可读存储介质 WO2024000731A1 (zh)

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