WO2018223712A1 - 像素电路及其驱动方法、显示面板和显示装置 - Google Patents

像素电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2018223712A1
WO2018223712A1 PCT/CN2018/073912 CN2018073912W WO2018223712A1 WO 2018223712 A1 WO2018223712 A1 WO 2018223712A1 CN 2018073912 W CN2018073912 W CN 2018073912W WO 2018223712 A1 WO2018223712 A1 WO 2018223712A1
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Prior art keywords
node
voltage
transistor
control
pixel circuit
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PCT/CN2018/073912
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English (en)
French (fr)
Inventor
徐映嵩
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US16/322,006 priority Critical patent/US10665658B2/en
Publication of WO2018223712A1 publication Critical patent/WO2018223712A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level

Definitions

  • the present disclosure relates to the field of display screens, and in particular, to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • AMOLED displays have been favored at home and abroad because of the excellent display effect of AMOLED (Active-matrix organic light emitting diode) displays.
  • the related industries have developed rapidly, and various pixel circuits have been developed. come out.
  • ELA Excimer Laser Annealing
  • Doping doping
  • TFTs Thin Film Transistors
  • an embodiment of the present disclosure provides a pixel circuit, including: a driver, a data input device, a first controller, a second controller, a first memory, and a second memory;
  • the data input device is connected to the first scan end, the data signal end and the first node, and the data input device is configured to transmit the reference voltage of the data signal end to the first node under the control of the first scan end;
  • the second controller is connected to the power level terminal, the second scan end and the second node, and the second controller is configured to be turned off under the control of the second scanning end to disconnect the power level end and the second node;
  • the driver is connected to the first node, the second node, and the third node, the driver is configured to transmit the signal of the second node to the third node under the signal control of the first node;
  • the first controller is connected to the third node, the first scanning end and the common end, and the first controller is configured to transmit the voltage of the third node to the common end under the control of the first scanning end;
  • the first memory is configured to store a voltage between the power level terminal and the second node;
  • the second memory is connected to the second node and the first node, and the second memory is configured to store the first node And a voltage between the second node; a maximum value of the voltage stored in the first memory is greater than a maximum value of the voltage stored in the second memory;
  • the data input device is further configured to transmit the data voltage of the data signal end to the first node under the control of the first scanning end; the driver is further configured to be turned off under the control of the voltage difference between the first node and the second node;
  • the data input device is further configured to be turned off under the control of the first scanning end; the second controller is further configured to transmit the power supply voltage of the power supply level terminal to the second node under the control of the second scanning end; the driver is further configured to be at the first node And the second node is under the control of the voltage difference and is in an amplified state, and outputs a driving signal to the third node under the voltage control of the second node.
  • the pixel circuit further includes a display connected to the third node and the common end for emitting light under the control of the driving signal.
  • the driver comprises a first transistor; a gate of the first transistor is connected to the first node, a first end of the first transistor is connected to the second node, and a second end of the first transistor is connected to the third node.
  • the data input device comprises a second transistor; the gate of the second transistor is connected to the first scan end, the first end of the second transistor is connected to the data signal end, and the second end of the second transistor is connected to the first node.
  • the first controller comprises a third transistor; the gate of the third transistor is connected to the first scan end, the first end of the third transistor is connected to the third node, and the second end of the third transistor is connected to the common end.
  • the second controller includes a fourth transistor; a gate of the fourth transistor is connected to the second scan end, a first end of the fourth transistor is connected to the power level terminal, and a second end of the fourth transistor is connected to the second node.
  • the first memory includes a first capacitor; the first end of the first capacitor is connected to the power level terminal, and the second end of the first capacitor is connected to the second node.
  • the second memory includes a second capacitor; the first end of the second capacitor is connected to the second node, and the second end of the second capacitor is connected to the first node.
  • the display comprises a light emitting diode; the anode of the light emitting diode is connected to the third node, and the cathode of the light emitting diode is connected to the common end.
  • an embodiment of the present disclosure provides a driving method of a pixel circuit provided by the first aspect, including: a reset phase, a data writing phase, and a driving phase; the reset phase, the data writing phase, and the driving phase are sequentially a continuous period of time;
  • the data input device transmits the reference voltage of the data signal end to the first node under the control of the first scanning end; the second controller is in the off state under the control of the second scanning end; the signal control of the driver at the first node Transmitting the voltage of the second node to the third node, the first controller transmitting the voltage of the third node to the common end under the control of the first scanning end; the first memory stores the voltage between the power level terminal and the second node The second memory stores the voltage between the first node and the second node; the phase resets the voltages of the first node and the second node, thereby avoiding the influence of the last illumination received by the current illumination.
  • the data input device transmits the data voltage of the data signal end to the first node under the control of the first scanning end; the driver is turned off under the voltage difference control between the first node and the second node; the second memory is stored A voltage between the first node and the second node; the phase writes a data voltage to the first node, and the second node voltage also changes due to the action of the first memory and the second memory.
  • the data input device is turned off under the control of the first scanning end; the second controller transmits the power supply voltage at the power supply level end to the second node under the control of the second scanning end; the driver is at the first node and the second node The voltage difference is controlled under the amplification state, and the driving signal is output to the third node under the voltage control of the second node; the phase changes the voltage of the second node, and the voltage of the first node also changes due to the action of the second memory.
  • the voltage difference between the first node and the second node causes the driver to send a driving signal to the third node, and the calculation of the voltage of the first node and the second node caused by the current stage and the previous stage and the calculation formula of the driving current can obtain a Drive current formula with turn-on voltage and supply voltage.
  • an embodiment of the present disclosure provides a display panel including the pixel circuit provided by the first aspect.
  • an embodiment of the present disclosure provides a display device including the display device provided by the third aspect.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a signal timing diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel circuit in a reset phase according to an embodiment of the present disclosure
  • FIG. 5 is a signal timing diagram of a pixel circuit in a reset phase according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a pixel circuit in a data writing phase according to an embodiment of the present disclosure
  • FIG. 7 is a timing diagram of signals of a pixel circuit in a data writing phase according to an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of a pixel circuit in an illuminating phase according to an embodiment of the present disclosure
  • FIG. 9 is a timing diagram of signals of a pixel circuit in an illuminating phase according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics, and the transistors employed in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, the source is referred to as a first end, and the drain is referred to as a second end. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the Vth provided by the TFT is inconsistent, which in turn causes a deviation in the driving current obtained according to Vth.
  • the display panel may be unevenly illuminated, and the power supply voltages obtained by the pixel circuits at different positions may also be inconsistent due to the problem of the voltage drop of the wires, so that the display panel and the driver are driven.
  • the brightness of the pixel circuits with different IC distances is also different.
  • an embodiment of the present disclosure provides a pixel circuit including: a driver 11 , a data input device 12 , a first controller 13 , a second controller 14 , a first memory 15 , and a second Memory 16.
  • the data input device 12 is connected to the first scan terminal Gate, the data signal terminal DL and the first node N1, and the data input device 12 is configured to transmit the reference voltage of the data signal terminal DL to the first node N1 under the control of the first scan terminal Gate. .
  • the second controller 14 is connected to the power level terminal DY, the second scan terminal EM and the second node N2, and the second controller 14 is configured to be turned off under the control of the second scan terminal EM to make the power level terminal DY and the second node N2 disconnect.
  • the driver 11 is connected to the first node N1, the second node N2, and the third node N3, and the driver 11 is configured to transmit the signal of the second node N2 to the third node N3 under the control of the signal of the first node N1.
  • the first controller 13 is connected to the third node N3, the first scanning end Gate and the common terminal Vss, and the first controller 13 is configured to transmit the voltage of the third node N3 to the common terminal Vss under the control of the first scanning end Gate.
  • the first memory 15 is connected to the power level terminal DY and the second node N2, and the first memory 15 is configured to store the voltage between the power level terminal DY and the second node N2.
  • the second memory 16 is connected to the second node N2 and the first node N1, and the second memory 16 is configured to store a voltage between the first node N1 and the second node N2.
  • the maximum value of the voltage stored in the first memory 15 is greater than the maximum value of the voltage stored in the second memory 16.
  • the data inputter 12 is also configured to transmit the data voltage of the data signal terminal DL to the first node N1 under the control of the first scanning terminal Gate.
  • the driver 11 is also configured to be turned off under the control of the voltage difference between the first node N1 and the second node N2.
  • the data inputter 12 is also configured to be turned off under the control of the first scanning end Gate.
  • the second controller 14 is further configured to transmit the power supply voltage of the power supply level terminal DY to the second node N2 under the control of the second scanning terminal EM.
  • the driver 11 is also configured to be in an amplified state under the control of the voltage difference of the first node N1 and the second node N2, and to output a driving signal to the third node N3 under the voltage control of the second node N2.
  • the pixel circuit provided by the embodiment of the present disclosure includes the driver 11, the data input device 12, the first controller 13, the second controller 14, the first memory 15, and the second memory 16.
  • the data input device 12 is connected to the first scan terminal Gate, the data signal terminal DL and the first node N1, and the data input device 12 is configured to transmit the reference voltage of the data signal terminal DL to the first node under the control of the first scan terminal Gate. N1.
  • the second controller 14 is connected to the power level terminal DY, the second scan terminal EM and the second node N2, and the second controller 14 is configured to be turned off under the control of the second scan terminal EM to enable the power level terminal DY and the second node. N2 is disconnected.
  • the driver 11 connects the first node N1, the second node N2, and the third node N3, and the driver 11 transmits the signal of the second node N2 to the third node N3 under the control of the signal of the first node N1.
  • the first controller 13 is connected to the third node N3, the first scanning end Gate and the common terminal Vss, and the first controller 13 is configured to transmit the voltage of the third node N3 to the common terminal Vss under the control of the first scanning end Gate. .
  • the first memory 15 is connected to a power level terminal DY and a second node N2, the first memory 15 being configured to store a voltage between the power level terminal DY and the second node N2.
  • the second memory 16 is connected to the second node N2 and the first node N1, the second memory 16 being configured to store a voltage between the first node N1 and the second node N2.
  • the maximum value of the voltage stored in the first memory 15 is greater than the maximum value of the voltage stored in the second memory 16.
  • the data inputter 12 is also configured to transmit the data voltage of the data signal terminal DL to the first node N1 under the control of the first scanning terminal Gate.
  • the driver 11 is also configured to be turned off under the control of the voltage difference between the first node N1 and the second node N2.
  • the data inputter 12 is also configured to be turned off under the control of the first scanning end Gate.
  • the second controller 14 is further configured to transmit the power supply voltage of the power supply level terminal DY to the second node N2 under the control of the second scanning terminal EM.
  • the driver 11 is also configured to be in an amplified state under the control of the voltage difference of the first node N1 and the second node N2, and to output a driving signal to the third node N3 under the voltage control of the second node N2. Therefore, when driving the pixel circuit, the voltage of the first node N1 is changed to a reference voltage by the voltage control of the first scanning terminal Gate, the data signal terminal DL and the second scanning terminal EM, so that the voltage of the second node N2 passes.
  • the third node N3 directly enters the common terminal Vss, thereby resetting the potential of the second node N2.
  • the voltage of the first node N1 becomes the data voltage by the voltage control of the data signal terminal DL, and at the same time, the voltage of the second node N2 changes accordingly due to the action of the second memory 16 and the first memory 15.
  • the voltage control of the first scanning end Gate and the second scanning end EM the voltage of the second node N2 is changed to the power supply voltage, because the action of the second memory 16 causes the voltage of the first node N1 to change accordingly, thereby The driver 11 is caused to output a drive signal to the third node N3.
  • the first scanning terminal Gate, the second scanning terminal EM, the data signal terminal DL, and the respective devices cooperate to prevent the turn-on voltage and the power supply voltage from appearing in the on-voltage formula of the final driver 11.
  • the drive current obtained according to the turn-on voltage is not affected by the turn-on voltage and the power supply voltage, and the obtained drive current is prevented from being deviated.
  • the above pixel circuit may further include a display 17, which is connected to the third node N3 and the common terminal Vss, and the display 17 is configured to emit light under the control of the driving signal.
  • the turn-on voltage and the power supply voltage do not appear in the on-voltage formula of the final driver 11
  • the turn-on voltage and the power supply voltage do not appear in the current formula of the display 17, and thus the brightness of the display 17 is followed.
  • the turn-on voltage is independent of the power supply voltage, and the brightness of the display panel composed of the pixel circuits is kept consistent. Therefore, the luminance of the pixel circuit provided by the embodiment of the present disclosure remains unchanged, which solves the problem that the display panel composed of a plurality of pixel circuits has uneven brightness due to the inconsistency between the turn-on voltage and the power supply voltage.
  • FIG. 2 For a more detailed description of the pixel circuit provided by the embodiment of the present disclosure, the specific structure of the pixel circuit provided by the embodiment of the present disclosure is described with reference to FIG. 2, wherein:
  • the driver 11 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the first node N1, the first end of the first transistor T1 is connected to the second node N2, and the second end of the first transistor T1 is connected to the third node N3.
  • the data input device 12 includes a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan terminal Gate, the first end of the second transistor T2 is connected to the data signal terminal DL, and the second end of the second transistor T2 is connected to the first node N1.
  • the first controller 13 includes a third transistor T3.
  • the gate of the third transistor T3 is connected to the first scanning end Gate, the first end of the third transistor T3 is connected to the third node N3, and the second end of the third transistor T3 is connected to the common terminal Vss.
  • the second controller 14 includes a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the second scan terminal EM, the first end of the fourth transistor T4 is connected to the power level terminal DY, and the second end of the fourth transistor T4 is connected to the second node N2.
  • the first memory 15 includes a first capacitor 01.
  • the first end of the first capacitor 01 is connected to the power level terminal, and the second end of the first capacitor 01 is connected to the second node N2.
  • the second memory 16 includes a second capacitor 02.
  • the first end of the second capacitor 02 is connected to the second node N2, and the second end of the second capacitor 02 is connected to the first node N1.
  • the capacitance value C1 of the first capacitor 01 is much larger than the capacitance value C2 of the second capacitor 02.
  • the display 17 includes a light emitting diode OLED.
  • the anode of the light emitting diode OLED is connected to the third node N3, and the cathode of the light emitting diode OLED is connected to the common terminal Vss.
  • the switching transistor and the driving transistor used in the embodiments of the present disclosure are both P-type transistors, but an N-type transistor can also be used in this pixel circuit.
  • the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • the P-type driving transistor is in an amplified state or a saturated state when the gate voltage is at a low level (the gate voltage is smaller than the source voltage) and the absolute value of the gate-source voltage difference is greater than the threshold voltage.
  • the gate voltage of the N-type driving transistor is at a high level (the gate voltage is greater than the source voltage), and the absolute value of the voltage difference of the gate source is greater than the threshold voltage, it is in an amplified state or a saturated state.
  • the pixel circuit provided by the embodiment of the present disclosure may also adopt an N-type transistor, and the structure needs to be relatively simplely modified on the driver, and in the operation, only the switch signal needs to be simply replaced (high level to low level, The low level becomes high level, and the change is obvious to those skilled in the art, and is also within the protection scope of the embodiments of the present disclosure.
  • an embodiment of the present disclosure further provides a driving method of a pixel circuit, including a reset phase, a data writing phase, and a lighting phase; a reset phase, a data writing phase, and The illuminating phase is three consecutive periods of sequential cycling.
  • the reset phase (t1) it can be seen from the timing diagram of FIG. 3 that the first scan terminal Gate is set to a low level, the second scan terminal EM is set to a high level, and the data signal terminal DL is a reference voltage Vref.
  • the data input unit 12 transmits the reference voltage Vref of the data signal terminal DL to the first node N1 under the control of the first scanning terminal Gate.
  • the second controller 14 is in an off state under the control of the second scanning terminal EM.
  • the driver 11 transmits the voltage of the second node N2 to the third node N3 under the control of the signal of the first node N1.
  • the first controller 13 transmits the voltage of the third node N3 to the common terminal Vss under the control of the first scanning terminal Gate.
  • the first memory 15 stores the voltage between the power source level terminal DY and the second node N2.
  • the second memory 16 stores the voltage between the first node N1 and the second node N2.
  • the reset phase mainly functions to reset the voltages of the first node N1 and the second node N2 from the voltage of the illumination phase of the previous driving process to perform the current illumination.
  • the data writing phase (t2) it can be seen from the timing diagram of FIG. 3 that the first scanning end Gate is set to a low level, the second scanning end EM is set to a high level, and the data signal end DL is a data voltage Vdata.
  • the reference voltage Vref is at a low level, and the data voltage Vdata is less than the reference voltage Vref.
  • the data input unit 12 transmits the data voltage Vdata of the data signal terminal DL to the first node N1 under the control of the first scanning terminal Gate.
  • the driver 11 is turned off under the control of the voltage difference between the first node N1 and the second node N2.
  • the second memory 16 stores the voltage between the first node N1 and the second node N2.
  • the data writing phase is mainly for causing the second node N2 to generate a required voltage change under the action of the voltage change of the first node N1 and the first memory 15 and the second memory 16.
  • the driving phase (t3) It can be seen from the timing diagram of FIG. 3 that the first scanning end Gate is set to a high level, the second scanning end EM is set to a low level, and the data signal terminal DL is not controlled.
  • the data input unit 12 is turned off under the control of the first scanning end Gate.
  • the second controller 14 transmits the power supply voltage Vdd of the power supply level terminal DY to the second node N2 under the control of the second scanning terminal EM.
  • the driver 11 is in an amplified state under the control of the voltage difference between the first node N1 and the second node N2, and outputs a driving signal to the third node N3 under the voltage control of the second node N2.
  • the driving phase changes the voltage of the second node N2, and at the same time, the voltage of the first node N1 also changes due to the action of the second memory 16.
  • the voltage difference between the first node N1 and the second node N2 causes the driver 11 to issue a drive signal to the third node N3.
  • a driving current formula not containing the turn-on voltage Vth and the power supply voltage Vdd can be obtained, thereby making the pixel circuit according to the pixel circuit
  • the obtained driving current is constant, that is, the driving current provided by the pixel circuit for a structure such as a display is constant, and the display panel composed of the pixel circuit is no longer uneven in brightness due to the difference in the opening voltage of each pixel circuit and the power supply voltage. .
  • the reset phase needs to reset the second node N2 voltage, this phase requires sufficient time because of the action of the first memory 15. Because the data writing phase needs to make the voltage of the second node N2 not decrease too much because the voltage of the first node N1 changes, the time of the data writing phase is shorter, that is, t1>t2; Make specific restrictions.
  • the first scan terminal Gate is set to a low level, so that the second transistor T2 and the third transistor T3 are turned on.
  • the control data signal terminal DL inputs the reference voltage Vref such that the voltage of the first node N1 becomes Vref.
  • the second scanning terminal EM is set to a high level, so that the fourth transistor T4 is turned off. Because of the influence of the last illumination phase of the previous driving process, the voltage of the second node N2 is the power supply voltage Vdd of the power supply level terminal DY.
  • the voltage of the second node N2 is gradually decreased until the first transistor T1 is turned off, that is, the potential of the second node N2 becomes Vref-Vth.
  • the first scanning terminal Gate is set to a low level, so that the second transistor T2 and the third transistor T3 are turned on.
  • the second scanning terminal EM is set to a high level, so that the fourth transistor T4 is turned off.
  • the control data signal terminal DL inputs the data voltage Vdata such that the voltage of the first node N1 becomes Vdata. Because the coupling of the first capacitor 01 and the second capacitor 02 causes the voltage of the second node to become Vref-Vth+(Vdata-Vref)C2/(C1+C2), it is necessary to ensure that the voltage of the second node N2 is not due to the first stage.
  • a transistor T1 and a third transistor T3 are turned on to cause a large change, so that the capacitance value C1 of the first capacitor 01 is required to be sufficiently large, and the time in the data writing phase is relatively small.
  • the first scanning terminal Gate is set to a high level, so that the second transistor T2 and the third transistor T3 are turned off.
  • the second scanning terminal EM is set to a low level, so that the fourth transistor T4 is turned on, so that the voltage of the second node N2 jumps to the power supply voltage Vdd, because the coupling of the first capacitor 01 causes the voltage of the first node N1 to become Vdata+Vdd-Vref+Vth-(Vdata-Vref)C2/(C1+C2).
  • no control is performed on the data signal terminal DL.
  • the driving method of the pixel circuit provided by the above embodiment is because in the pixel circuit provided by the embodiment of the present disclosure, the driver 11 can be the first transistor T1.
  • the gate of the first transistor T1 is connected to the first node N1, the first end of the first transistor T1 is connected to the second node N2, and the second end of the first transistor T1 is connected to the third node N3.
  • the data input device 12 can be a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan terminal Gate, the first end of the second transistor T2 is connected to the data signal terminal DL, and the second end of the second transistor T2 is connected to the first node N1.
  • the first controller 13 can be a third transistor T3, the gate of the third transistor T3 is connected to the first scan end Gate, the first end of the third transistor T3 is connected to the third node N3, and the second end of the third transistor T3 is connected to the common End Vss.
  • the second controller 14 can be a fourth transistor T4, the gate of the fourth transistor T4 is connected to the second scanning end EM, the first end of the fourth transistor T4 is connected to the power level terminal DY, and the second end of the fourth transistor T4 is connected.
  • the first memory 15 can be a first capacitor 01. The first end of the first capacitor 01 is connected to the power level terminal DY, and the second end of the first capacitor 01 is connected to the second node N2.
  • the second memory 16 can be a second capacitor 02.
  • the first end of the second capacitor 02 is connected to the second node N2, and the second end of the second capacitor 02 is connected to the first node N1.
  • the capacitance of the first capacitor 01 is much larger than the capacitance of the second capacitor 02.
  • the second transistor T2 and the third transistor T3 are turned on under the control of the first scanning end Gate, and the fourth transistor T4 is turned off under the control of the second scanning terminal EM, and the data signal terminal DL is input to the data voltage. Therefore, the second node N2 generates a required voltage change under the influence of the voltage change of the first node N1 and the first memory 15 and the second memory 16.
  • the second transistor T2 and the third transistor T3 are turned off under the control of the first scanning end Gate, and the fourth transistor T4 is turned on under the control of the second scanning end EM, so that the voltage of the second node N2 jumps.
  • the power supply voltage thereby changing the voltage of the second node N2 and the voltage of the first node N1 also changes.
  • the voltage difference between the first node N1 and the second node N2 causes the driver 11 to issue a drive signal to the third node N3.
  • the entire driving process is caused by three stages of the change of the voltage of the first node N1 and the second node N2 and the calculation formula of the driving current can obtain a driving current formula that does not contain the turn-on voltage and the power supply voltage, thereby obtaining the obtained according to the pixel circuit.
  • the driving current is constant, that is, the driving current provided by the pixel circuit for a structure such as a display is constant, and the display panel composed of the pixel circuit is no longer uneven in brightness due to the difference in the turn-on voltage of each pixel circuit and the power supply voltage.
  • the embodiment of the present disclosure further provides a display panel including the pixel circuit provided by the foregoing embodiment.
  • the display panel 100 includes a display area 101 and a driving area 102, wherein the display area 101 includes a plurality of pixel circuits 103 provided by the foregoing embodiments.
  • Embodiments of the present disclosure provide a display device including the above display panel.
  • the display device 1001 includes a display panel 100.
  • Display device 100 may also include other structures that are suitable.
  • the display device 100 herein may be any product or component having a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Embodiments of the present disclosure also provide a computer program that can be directly loaded into a memory and contains software code that can be loaded and executed by a computer to implement the above-described process of driving a pixel circuit.

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Abstract

一种像素电路及其驱动方法。电路包括：数据输入器（12）用于将参考电压（Vref）传输至第一节点（N1）；第二控制器（14）配置为使电源电平端（DY）和第二节点（N2）断开；驱动器（11）配置为将第二节点（N2）的信号传输至第三节点（N3）；第一控制器（13）配置为将第三节点（N3）的电压传输至公共端（Vss）；第一存储器（15）配置为存储电源电平端（DY）和第二节点（N2）之间的电压；第二存储器（16）配置为存储第一节点（N1）和第二节点（N2）之间的电压；数据输入器（12）还配置为将数据信号端（DL）的数据电压（Vdata）传输至第一节点（N1）；第二控制器（14）还配置为将电源电平端（DY）的电源电压传输至第二节点（N2）；驱动器（11）还配置为向第三节点（N3）输出驱动信号。

Description

像素电路及其驱动方法、显示面板和显示装置
本申请要求于2017年6月5日提交中国专利局、申请号为201710414846.3、发明名称为“一种像素电路及其驱动方法、显示面板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示屏领域，尤其涉及一种像素电路及其驱动方法、显示面板和显示装置。
背景技术
近年来，因为AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极体)显示器的优异显示效果，国内外AMOLED显示器大受青睐，其相关产业发展迅速，各种像素电路相继被开发出来。但应用在实际生产中所用到的制作AMOLED显示屏中的TFT(Thin Film Transistor，薄膜晶体管)的ELA(Excimer Laser Annealing，准分子激光退火)及掺杂(Doping)工艺并不能够保证TFT良好的均一性，从而存在Vth(开启电压)偏差现象，导致根据Vth获得的驱动电流出现偏差。例如，就AMOLED显示屏中最基本的2T1C(两个晶体管和一个电容的像素电路)电路来说，当相同的数据(Data)信号写入时，会由于电流公式中存在不同的Vth而导致各像素(pixel)亮度不均一。并且由于实际AMOLED显示器中存在导线压降，会导致驱动晶体管(DTFT)栅极电压变化即和电源距离不同的晶体管的栅极电压不同，从而导致AMOLED显示器的亮度有差异。
发明内容
第一方面，本公开的实施例提供一种像素电路，包括：驱动器、数据输入器、第一控制器、第二控制器、第一存储器和第二存储器；
数据输入器连接第一扫描端、数据信号端和第一节点，该数据 输入器配置为在第一扫描端的控制下将数据信号端的参考电压传输至第一节点；
第二控制器连接电源电平端、第二扫描端和第二节点，该第二控制器配置为在第二扫描端的控制下截止以使电源电平端和第二节点断开；
驱动器连接第一节点、第二节点和第三节点，该驱动器配置为在第一节点的信号控制下将第二节点的信号传输至第三节点；
第一控制器连接第三节点、第一扫描端和公共端，该第一控制器配置为在第一扫描端的控制下将第三节点的电压传输至公共端；
连接电源电平端和第二节点，该第一存储器配置为存储电源电平端和第二节点之间的电压；第二存储器连接第二节点和第一节点，该第二存储器配置为存储第一节点和第二节点之间的电压；第一存储器存储的电压的最大值大于第二存储器存储的电压的最大值；
数据输入器还配置为在第一扫描端的控制下将数据信号端的数据电压传输至第一节点；驱动器还配置为在第一节点和第二节点之间的电压差控制下截止；
数据输入器还配置为在第一扫描端的控制下截止；第二控制器还配置为在第二扫描端的控制下将电源电平端的电源电压传输至第二节点；驱动器还配置为在第一节点和第二节点的电压差控制下处于放大状态，并在第二节点的电压控制下向第三节点输出驱动信号。
可选的，像素电路还包括显示器，显示器连接第三节点和公共端，用于在驱动信号的控制下发光。
可选的，驱动器包括第一晶体管；第一晶体管的栅极连接第一节点，第一晶体管的第一端连接第二节点，第一晶体管的第二端连接第三节点。
可选的，数据输入器包括第二晶体管；第二晶体管的栅极连接第一扫描端，第二晶体管的第一端连接数据信号端，第二晶体管的第二端连接第一节点。
可选的，第一控制器包括第三晶体管；第三晶体管的栅极连接 第一扫描端，第三晶体管的第一端连接第三节点，第三晶体管的第二端连接公共端。
可选的，第二控制器包括第四晶体管；第四晶体管的栅极连接第二扫描端，第四晶体管的第一端连接电源电平端，第四晶体管的第二端连接第二节点。
可选的，第一存储器包括第一电容；第一电容的第一端连接电源电平端，第一电容的第二端连接第二节点。
可选的，第二存储器包括第二电容；第二电容的第一端连接第二节点，第二电容的第二端连接第一节点。
可选的，显示器包括发光二极管；发光二极管的阳极连接第三节点，发光二极管的阴极连接公共端。
第二方面，本公开的实施例提供一种第一方面提供的像素电路的驱动方法，包括：重置阶段、数据写入阶段和驱动阶段；重置阶段、数据写入阶段和驱动阶段为依次循环连续的时段；
在重置阶段：数据输入器在第一扫描端的控制下将数据信号端的参考电压传输至第一节点；第二控制器在第二扫描端的控制下处于截止状态；驱动器在第一节点的信号控制下将第二节点的电压传输至第三节点，第一控制器在第一扫描端的控制下将第三节点的电压传输至公共端；第一存储器存储电源电平端和第二节点之间的电压；第二存储器存储第一节点和第二节点之间的电压；该阶段重置了第一节点和第二节点的电压，从而避免本次发光收到上次发光的影响。
在数据写入阶段：数据输入器在第一扫描端的控制下将数据信号端的数据电压传输至第一节点；驱动器在第一节点和第二节点之间的电压差控制下截止；第二存储器存储第一节点和第二节点之间的电压；该阶段对第一节点写入数据电压，同时因为第一存储器和第二存储器的作用使第二节点电压也产生改变。
在驱动阶段：数据输入器在第一扫描端的控制下截止；第二控制器在第二扫描端的控制下将电源电平端的电源电压传输至第二节点；驱动器在第一节点和第二节点的电压差控制下处于放大状态，并 在第二节点的电压控制下向第三节点输出驱动信号；该阶段通过改变第二节点电压，同时因为第二存储器的作用，使得第一节点电压也产生改变，第一节点和第二节点的电压差使得驱动器向第三节点发出驱动信号，由于本阶段和上一阶段造成的第一节点和第二节点电压的变化以及驱动电流的计算公式可以得到一个不含有开启电压和电源电压的驱动电流公式。
第三方面，本公开的实施例提供一种显示面板，包括第一方面提供的像素电路。
第四方面，本公开的实施例提供一种显示装置，包括第三方面提供的显示装置。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本公开实施例提供的一种像素电路结构示意图；
图2为本公开实施例提供的一种像素电路结构示意图；
图3为本公开实施例提供的一种像素电路的信号时序图；
图4为本公开实施例提供的像素电路在重置阶段的结构示意图；
图5为本公开实施例提供的像素电路在重置阶段的信号时序图；
图6为本公开实施例提供的像素电路在数据写入阶段的结构示意图；
图7为本公开实施例提供的像素电路在数据写入阶段的信号时序图；
图8为本公开实施例提供的像素电路在发光阶段的结构示意图；
图9为本公开实施例提供的像素电路在发光阶段的信号时序图；
图10为本公开实施例提供的显示面板的结构示意图；
图11为本公开实施例提供的显示装置的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要说明的是，本公开实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本公开实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
还需要说明的是，本公开实施例中，“的(英文：of)”，“相应的(英文：corresponding，relevant)”和“对应的(英文：corresponding)”有时可以混用，应当指出的是，在不强调其区别时，其所要表达的含义是一致的。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中源极称为第一端，漏极称为第二端。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。
现有技术中因为TFT的制造工艺问题，使得该TFT提供的Vth不一致，进而导致根据Vth获得的驱动电流出现偏差。例如，当TFT给显示面板的像素电路提供的Vth不一致时，会导致显示面板发光不 均，同时因为导线压降的问题，不同位置的像素电路能得到的电源电压也不一致，使得显示面板和驱动IC距离不同的像素电路发光亮度也不同。
为了解决上述问题，参照图1所示，本公开实施例提供一种像素电路，包括：驱动器11、数据输入器12、第一控制器13、第二控制器14、第一存储器15和第二存储器16。
数据输入器12连接第一扫描端Gate、数据信号端DL和第一节点N1，数据输入器12配置为在第一扫描端Gate的控制下将数据信号端DL的参考电压传输至第一节点N1。
第二控制器14连接电源电平端DY、第二扫描端EM和第二节点N2，第二控制器14配置为在第二扫描端EM的控制下截止以使电源电平端DY和第二节点N2断开。
驱动器11连接第一节点N1、第二节点N2和第三节点N3，驱动器11配置为在第一节点N1的信号控制下将第二节点N2的信号传输至第三节点N3。
第一控制器13连接第三节点N3、第一扫描端Gate和公共端Vss，第一控制器13配置为在第一扫描端Gate的控制下将第三节点N3的电压传输至公共端Vss。
第一存储器15连接电源电平端DY和第二节点N2，第一存储器15配置为存储电源电平端DY和第二节点N2之间的电压。第二存储器16连接第二节点N2和第一节点N1，第二存储器16配置为存储第一节点N1和第二节点N2之间的电压。第一存储器15存储的电压的最大值大于第二存储器16存储的电压的最大值。
数据输入器12还配置为在第一扫描端Gate的控制下将数据信号端DL的数据电压传输至第一节点N1。驱动器11还配置为在第一节点N1和第二节点N2之间的电压差控制下截止。
数据输入器12还配置为在第一扫描端Gate的控制下截止。第二控制器14还配置为在第二扫描端EM的控制下将电源电平端DY的电源电压传输至第二节点N2。驱动器11还配置为在第一节点N1 和第二节点N2的电压差控制下处于放大状态，并在第二节点N2的电压控制下向第三节点N3输出驱动信号。
本公开实施例提供的像素电路，因为该像素电路包括：驱动器11、数据输入器12、第一控制器13、第二控制器14、第一存储器15和第二存储器16。数据输入器12连接第一扫描端Gate、数据信号端DL和第一节点N1，该数据输入器12配置为在第一扫描端Gate的控制下将数据信号端DL的参考电压传输至第一节点N1。第二控制器14连接电源电平端DY、第二扫描端EM和第二节点N2，该第二控制器14配置为在第二扫描端EM的控制下截止以使电源电平端DY和第二节点N2断开。驱动器11连接第一节点N1、第二节点N2和第三节点N3，该驱动器11在第一节点N1的信号控制下将第二节点N2的信号传输至第三节点N3。第一控制器13连接第三节点N3、第一扫描端Gate和公共端Vss，该第一控制器13配置为在第一扫描端Gate的控制下将第三节点N3的电压传输至公共端Vss。第一存储器15连接电源电平端DY和第二节点N2，该第一存储器15配置为存储电源电平端DY和第二节点N2之间的电压。第二存储器16连接第二节点N2和第一节点N1，该第二存储器16配置为存储第一节点N1和第二节点N2之间的电压。第一存储器15存储的电压的最大值大于第二存储器16存储的电压的最大值。数据输入器12还配置为在第一扫描端Gate的控制下将数据信号端DL的数据电压传输至第一节点N1。驱动器11还配置为在第一节点N1和第二节点N2之间的电压差控制下截止。数据输入器12还配置为在第一扫描端Gate的控制下截止。第二控制器14还配置为在第二扫描端EM的控制下将电源电平端DY的电源电压传输至第二节点N2。驱动器11还配置为在第一节点N1和第二节点N2的电压差控制下处于放大状态，并在第二节点N2的电压控制下向第三节点N3输出驱动信号。所以在驱动该像素电路时，首先通过第一扫描端Gate、数据信号端DL和第二扫描端EM的电压控制，使第一节点N1的电位变为参考电压，使第二节点N2的电压通过第三节点N3直接进入公共端Vss，从而重置了第二节点 N2的电位。而后通过对数据信号端DL的电压控制使第一节点N1的电压变为数据电压，同时因为第二存储器16和第一存储器15的作用，第二节点N2的电压也相应产生变化。最后通过对第一扫描端Gate和第二扫描端EM的电压控制，使第二节点N2的电压变为电源电压，因为第二存储器16的作用使第一节点N1的电压也相应产生变化，从而使得驱动器11向第三节点N3输出驱动信号。整个像素电路的驱动过程中，通过第一扫描端Gate、第二扫描端EM、数据信号端DL以及各个器的共同作用使得最终驱动器11的导通电压公式中不出现开启电压和电源电压，从而使得根据该导通电压获得的驱动电流不受开启电压和电源电压的影响，避免了获得的驱动电流出现偏差。
例如，如图1所示，上述像素电路还可包括显示器17，显示器17连接第三节点N3和公共端Vss，显示器17配置为在驱动信号的控制下发光。在本发明提供的实施例中，由于最终驱动器11的导通电压公式中不出现开启电压和电源电压，则显示器17的电流公式中也不出现开启电压和电源电压，进而显示器17的发光亮度跟开启电压和电源电压无关，像素电路组成的显示面板发光亮度也就保持了一致。所以本公开实施例提供的像素电路发光亮度会保持不变，也就解决了多个像素电路组成的显示面板因为开启电压和电源电压的不一致导致亮度不均的问题。
为了更详细说明本公开实施例提供的像素电路，参照图2所示，对本公开实施例提供的像素电路具体结构进行说明，其中：
驱动器11包括第一晶体管T1。第一晶体管T1的栅极连接第一节点N1，第一晶体管T1的第一端连接第二节点N2，第一晶体管T1的第二端连接第三节点N3。
数据输入器12包括第二晶体管T2。第二晶体管T2的栅极连接第一扫描端Gate，第二晶体管T2的第一端连接数据信号端DL，第二晶体管T2的第二端连接第一节点N1。
第一控制器13包括第三晶体管T3。第三晶体管T3的栅极连接第一扫描端Gate，第三晶体管T3的第一端连接第三节点N3，第三晶 体管T3的第二端连接公共端Vss。
第二控制器14包括第四晶体管T4。第四晶体管T4的栅极连接第二扫描端EM，第四晶体管T4的第一端连接电源电平端DY，第四晶体管T4的第二端连接第二节点N2。
第一存储器15包括第一电容01。第一电容01的第一端连接电源电平端，第一电容01的第二端连接第二节点N2。第二存储器16包括第二电容02。第二电容02的第一端连接第二节点N2，第二电容02的第二端连接第一节点N1。在本公开的一个实施例中，第一电容01的电容值C1远大于第二电容02的电容值C2。
显示器17包括发光二极管OLED。发光二极管OLED的阳极连接第三节点N3，发光二极管OLED的阴极连接公共端Vss。
本公开实施例中所采用的开关晶体管和驱动晶体管均为P型晶体管，但在此像素电路中也可使用N型晶体管。N型开关晶体管为在栅极为高电平时导通工作，在栅极为低电平时截止。P型驱动晶体管在栅极电压为低电平(栅极电压小于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态。N型驱动晶体管的栅极电压为高电平(栅极电压大于源极电压)，且栅极源极的压差的绝对值大于阈值电压时，处于放大状态或饱和状态。在实际中，本公开实施例提供的像素电路也可以采用N型晶体管，结构上需要对驱动器做相应简单改动，而在操作中只需要对开关信号进行简单替换(高电平变低电平，低电平变高电平)即可，这中改变对于本领域技术人员来讲是很显而易见可以得到的，也在本公开实施例保护范围内。
为了体现本公开实施例提供的像素电路的驱动过程，本公开实施例还提供一种像素电路的驱动方法，包括重置阶段、数据写入阶段和发光阶段；重置阶段、数据写入阶段和发光阶段为依次循环连续的三个时段。
参照图1和图3对本公开实施例提供的像素电路的驱动方法进行具体说明：
在重置阶段(t1)：由图3时序图可知此阶段，第一扫描端Gate置低电平，第二扫描端EM置高电平，数据信号端DL为参考电压Vref。
数据输入器12在第一扫描端Gate的控制下将数据信号端DL的参考电压Vref传输至第一节点N1。第二控制器14在第二扫描端EM的控制下处于截止状态。驱动器11在第一节点N1的信号控制下将第二节点N2的电压传输至第三节点N3。第一控制器13在第一扫描端Gate的控制下将第三节点N3的电压传输至公共端Vss。第一存储器15存储电源电平端DY和第二节点N2之间的电压。第二存储器16存储第一节点N1和第二节点N2之间的电压。
具体的，重置阶段主要作用是将第一节点N1和第二节点N2的电压从上一驱动过程的发光阶段的电压重置回来以便进行本次发光。
在数据写入阶段(t2)：由图3时序图可知此阶段，第一扫描端Gate置低电平，第二扫描端EM置高电平，数据信号端DL为数据电压Vdata。在本公开的实施例中，参考电压Vref为低电平，数据电压Vdata小于参考电压Vref。
数据输入器12在第一扫描端Gate的控制下将数据信号端DL的数据电压Vdata传输至第一节点N1。驱动器11在第一节点N1和第二节点N2之间的电压差控制下截止。第二存储器16存储第一节点N1和第二节点N2之间的电压。
具体的，数据写入阶段主要是为了使第二节点N2在第一节点N1的电压变化和第一存储器15以及第二存储器16的作用下产生需要的电压变化。
在驱动阶段(t3)：由图3时序图可知此阶段，第一扫描端Gate置高电平，第二扫描端EM置低电平，数据信号端DL不做控制。
数据输入器12在第一扫描端Gate的控制下截止。第二控制器14在第二扫描端EM的控制下将电源电平端DY的电源电压Vdd传输至第二节点N2。驱动器11在第一节点N1和第二节点N2的电压差控制下处于放大状态，并在第二节点N2的电压控制下向第三节点N3输出驱动信号。
具体的，驱动阶段通过改变第二节点N2电压，同时因为第二存储器16的作用，使得第一节点N1电压也产生改变。第一节点N1和第二节点N2的电压差使得驱动器11向第三节点N3发出驱动信号。由于本阶段和上一阶段造成的第一节点N1和第二节点N2电压的变化以及驱动电流的计算公式可以得到一个不含有开启电压Vth和电源电压Vdd的驱动电流公式，从而使得根据该像素电路获得的驱动电流恒定，即通过该像素电路为例如显示器等结构提供的驱动电流恒定，该像素电路组成的显示面板也不会再因为各像素电路的开启电压不同和电源电压的不同而亮度不均匀。
需要说明的是，因为重置阶段需要使得第二节点N2电压下降重置，因为第一存储器15的作用，此阶段需要足够时间。因为数据写入阶段需要使得第二节点N2电压在因为第一节点N1的电压变化而变化后不会降低太多，所以数据写入阶段的时间要较短，即t1>t2；发光阶段则不做具体限制。
示例性的，参照图4所示的重置阶段的像素电路结构图(图4中晶体管上有斜线的表示截止)和图5所示的时序状态图(图中阴影部分表示为像素电路所处的时段)对本公开实施提供的像素电路在重置阶端的工作原理进行说明：
在重置阶段即t1阶段：令第一扫描端Gate置低电平，使得第二晶体管T2和第三晶体管T3导通。控制数据信号端DL输入参考电压Vref，使得第一节点N1电压变为Vref。令第二扫描端EM置高电平，使得第四晶体管T4截止。因为上一驱动过程最后的发光阶段的影响，此时第二节点N2电压为电源电平端DY的电源电压Vdd。又因为此阶段第一晶体管T1和第三晶体管T3均导通，所以第二节点N2电压会逐渐降低直至第一晶体管T1处于截止，即第二节点N2电位变为Vref-Vth为止。
示例性的，参照图6所示的数据写入阶段的像素电路结构图(图6中晶体管上有斜线的表示截止)和图7所示的时序状态图(图中阴影部分表示为像素电路所处的时段)对本公开实施提供的像素电路在 数据写入阶段的工作原理进行说明：
在数据写入阶段即t2阶段：令第一扫描端Gate置低电平，使得第二晶体管T2和第三晶体管T3导通。令第二扫描端EM置高电平，使得第四晶体管T4截止。控制数据信号端DL输入数据电压Vdata，使得第一节点N1电压变为Vdata。因为第一电容01和第二电容02的耦合作用，使得第二节点电压变为Vref-Vth+(Vdata-Vref)C2/(C1+C2)，此阶段需要保证第二节点N2电压不会因为第一晶体管T1和第三晶体管T3的导通而产生较大变化，所以需要第一电容01的电容值C1足够大，而且数据写入阶段的时间要比较小才可以。
示例性的，参照图8所示的驱动阶段的像素电路结构图(图8中晶体管上有斜线的表示截止)和图9所示的时序状态图(图中阴影部分表示为像素电路所处的时段)对本公开实施提供的像素电路在发光阶段的工作原理进行说明：
在驱动阶段即t3阶段：令第一扫描端Gate置高电平，使得第二晶体管T2和第三晶体管T3截止。令第二扫描端EM置低电平，使得第四晶体管T4导通，使得第二节点N2电压跳变为电源电压Vdd，因为第一电容01的耦合作用，使第一节点N1的电压变为Vdata+Vdd-Vref+Vth-(Vdata-Vref)C2/(C1+C2)。此时对数据信号端DL不做控制。在第一节点N1和第二节点N2的电压差Vgs的控制下使得第一晶体管T1处于放大状态，从而向第三节点N3发出驱动信号，驱动电流则为Idrive＝K[Vgs-Vth] 2＝K[(Vdata-Vref)C1/(C1+C2)] 2≈K(Vdata-Vref) 2(因为C1足够大，远大于C2)。可以从公式中看出，经过三个阶段以后，驱动电流不受开启电压和电源电压的影响。
上述实施例提供的像素电路的驱动方法，因为在本公开的实施例提供的像素电路中：驱动器11可为第一晶体管T1。第一晶体管T1的栅极连接第一节点N1，第一晶体管T1的第一端连接第二节点N2，第一晶体管T1的第二端连接第三节点N3。数据输入器12可为第二晶体管T2。第二晶体管T2的栅极连接第一扫描端Gate，第二晶体管 T2的第一端连接数据信号端DL，第二晶体管T2的第二端连接第一节点N1。第一控制器13可为第三晶体管T3，第三晶体管T3的栅极连接第一扫描端Gate，第三晶体管T3的第一端连接第三节点N3，第三晶体管T3的第二端连接公共端Vss。第二控制器14可为第四晶体管T4，第四晶体管T4的栅极连接第二扫描端EM，第四晶体管T4的第一端连接电源电平端DY，第四晶体管T4的第二端连接第二节点N2。第一存储器15可为第一电容01，第一电容01的第一端连接电源电平端DY，第一电容01的第二端连接第二节点N2。第二存储器16可为第二电容02，第二电容02的第一端连接第二节点N2，第二电容02的第二端连接第一节点N1。第一电容01的电容值远大于第二电容02的电容值。在对该像素电路进行驱动时，首先重置阶段，在第一扫描端Gate控制下使第二晶体管T2和第三晶体管T3导通，在第二扫描端EM控制下使第四晶体管T4截止，数据信号端DL控制为参考电压从而将第一节点N1和第二节点N2的电压从上一驱动过程的发光阶段的电压重置。然后数据写入阶段，在第一扫描端Gate控制下使得第二晶体管T2和第三晶体管T3导通，在第二扫描端EM控制下使得第四晶体管T4截止，控制数据信号端DL输入数据电压，从而使第二节点N2在第一节点N1的电压变化和第一存储器15以及第二存储器16的作用下产生需要的电压变化。最后驱动阶段，在第一扫描端Gate控制下使得第二晶体管T2和第三晶体管T3截止，在第二扫描端EM控制下使得第四晶体管T4导通，使得第二节点N2的电压跳变为电源电压，从而通过改变第二节点N2的电压同时因为第二存储器的作用，使得第一节点N1的电压也产生改变。第一节点N1和第二节点N2的电压差使得驱动器11向第三节点N3发出驱动信号。整个驱动过程由三个阶段造成的第一节点N1和第二节点N2电压的变化以及驱动电流的计算公式可以得到一个不含有开启电压和电源电压的驱动电流公式，从而使得根据该像素电路获得的驱动电流恒定，即通过该像素电路为例如显示器等结构提供的驱动电流恒定，该像素电路组成的显示面板也不会再因为各像素电路的开启电压 不同和电源电压的不同而亮度不均匀。
本公开实施例还提供一种显示面板，包括前述实施例提供的像素电路。
示例性的，参照图10所示的显示面板，显示面板100包括显示区域101和驱动区域102，其中，显示区域101中包括多个前述实施例提供的像素电路103。
本公开的实施例提供一种显示装置，包括上述的显示面板。示例性的，参照图11所示的显示装置，显示装置1001包括显示面板100。显示装置100还可包括适用的其他结构。这里的显示装置100可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供一种计算机程序，该计算机程序可直接加载到存储器中，并含有软件代码，该计算机程序经由计算机载入并执行后能够实现上述的驱动像素电路的过程。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (12)

  1. 一种像素电路，包括：驱动器、数据输入器、第一控制器、第二控制器、第一存储器和第二存储器；
    所述数据输入器连接第一扫描端、数据信号端和第一节点，所述数据输入器配置为在所述第一扫描端的控制下将所述数据信号端的参考电压传输至所述第一节点；
    所述第二控制器连接电源电平端、第二扫描端和第二节点，所述第二控制器配置为在所述第二扫描端的控制下截止以使所述电源电平端和所述第二节点断开；
    所述驱动器连接所述第一节点、所述第二节点和第三节点，所述驱动器配置为在所述第一节点的信号控制下将所述第二节点的信号传输至所述第三节点；
    所述第一控制器连接所述第三节点、所述第一扫描端和公共端，所述第一控制器配置为在所述第一扫描端的控制下将所述第三节点的电压传输至所述公共端；
    所述第一存储器连接所述电源电平端和所述第二节点，所述第一存储器配置为存储所述电源电平端和所述第二节点之间的电压；所述第二存储器连接所述第二节点和所述第一节点，所述第二存储器配置为存储所述第一节点和所述第二节点之间的电压；所述第一存储器存储的电压的最大值大于所述第二存储器存储的电压的最大值；
    所述数据输入器还配置为在所述第一扫描端的控制下将所述数据信号端的数据电压传输至所述第一节点；所述驱动器还配置为在所述第一节点和所述第二节点之间的电压差控制下截止；
    所述数据输入器还配置为在所述第一扫描端的控制下截止；所述第二控制器还配置为在所述第二扫描端的控制下将所述电源电平端的电源电压传输至所述第二节点；所述驱动器还配置为在所述第一节点和所述第二节点的电压差控制下处于放大状态，并在所述第二节点的电压控制下向所 述第三节点输出驱动信号。
  2. 根据权利要求1所述的像素电路，其中，所述像素电路还包括显示器，所述显示器连接所述第三节点和所述公共端，所述显示器配置为在所述驱动信号的控制下发光。
  3. 根据权利要求1所述的像素电路，其中，所述驱动器包括第一晶体管；
    所述第一晶体管的栅极连接所述第一节点，所述第一晶体管的第一端连接所述第二节点，所述第一晶体管的第二端连接所述第三节点。
  4. 根据权利要求1所述的像素电路，其中，所述数据输入器包括第二晶体管；
    所述第二晶体管的栅极连接所述第一扫描端，所述第二晶体管的第一端连接所述数据信号端，所述第二晶体管的第二端连接所述第一节点。
  5. 根据权利要求1所述的像素电路，其中，所述第一控制器包括第三晶体管；
    所述第三晶体管的栅极连接所述第一扫描端，所述第三晶体管的第一端连接所述第三节点，所述第三晶体管的第二端连接所述公共端。
  6. 根据权利要求1所述的像素电路，其中，所述第二控制器包括第四晶体管；
    所述第四晶体管的栅极连接所述第二扫描端，所述第四晶体管的第一端连接所述电源电平端，所述第四晶体管的第二端连接所述第二节点。
  7. 根据权利要求1所述的像素电路，其中，所述第一存储器包括第一电容；
    所述第一电容的第一端连接所述电源电平端，所述第一电容的第二端连接所述第二节点。
  8. 根据权利要求1所述的像素电路，其中，所述第二存储器包括第二电容；
    所述第二电容的第一端连接所述第二节点，所述第二电容的第二端连 接所述第一节点。
  9. 根据权利要求2所述的像素电路，其中，所述显示器包括发光二极管；
    所述发光二极管的阳极连接所述第三节点，所述发光二极管的阴极连接所述公共端。
  10. 一种如权利要求1-9任一项所述的像素电路的驱动方法，包括重置阶段、数据写入阶段和驱动阶段；所述重置阶段、所述数据写入阶段和所述驱动阶段为依次循环连续的时段；
    在所述重置阶段：
    所述数据输入器在所述第一扫描端的控制下将所述数据信号端的参考电压传输至所述第一节点；所述第二控制器在所述第二扫描端的控制下处于截止状态；所述驱动器在所述第一节点的信号控制下将所述第二节点的电压传输至所述第三节点，所述第一控制器在所述第一扫描端的控制下将所述第三节点的电压传输至所述公共端；所述第一存储器存储所述电源电平端和所述第二节点之间的电压；所述第二存储器存储所述第一节点和所述第二节点之间的电压；
    在所述数据写入阶段：
    所述数据输入器在所述第一扫描端的控制下将所述数据信号端的数据电压传输至所述第一节点；所述驱动器在所述第一节点和所述第二节点之间的电压差控制下截止；所述第二存储器存储所述第一节点和所述第二节点之间的电压；
    在所述驱动阶段：
    所述数据输入器在所述第一扫描端的控制下截止；所述第二控制器在所述第二扫描端的控制下将所述电源电平端的电源电压传输至所述第二节点；所述驱动器在所述第一节点和所述第二节点的电压差控制下处于放大状态，并在所述第二节点的电压控制下向所述第三节点输出驱动信号。
  11. 一种显示面板，包括权利要求1-9任一项所述的像素电路。
  12. 一种显示装置，包括权利要求11所述的显示面板。
PCT/CN2018/073912 2017-06-05 2018-01-24 像素电路及其驱动方法、显示面板和显示装置 WO2018223712A1 (zh)

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