WO2018223427A1 - 一种薄膜晶体管、tft基板以及显示面板 - Google Patents

一种薄膜晶体管、tft基板以及显示面板 Download PDF

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Publication number
WO2018223427A1
WO2018223427A1 PCT/CN2017/089460 CN2017089460W WO2018223427A1 WO 2018223427 A1 WO2018223427 A1 WO 2018223427A1 CN 2017089460 W CN2017089460 W CN 2017089460W WO 2018223427 A1 WO2018223427 A1 WO 2018223427A1
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Prior art keywords
shaped
curved
curved structure
structures
interconnected
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French (fr)
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石龙强
陈书志
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/568,873 priority Critical patent/US10509279B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor, a TFT substrate, and a display panel.
  • GOA gate driver on array
  • TFTs Thin A film shift register consisting of a film transistor. Due to the gate The driver has achieved the above array of glass substrates, eliminating the space for gate driver bonding, which is beneficial to the production of narrow borders on the gate side.
  • FIG. 1 A cross-sectional view of the structure of the Oxide)-TFT is shown in FIG. 1.
  • the gate electrode 11 of the thin film transistor 10 is disposed on the upper surface of the semiconductor layer 12, and the source electrode 13 and the drain electrode 14 are electrically connected to the semiconductor layer 12, respectively.
  • the thin film transistor 10 has the advantages of high mobility and small parasitic capacitance, and can be outputted with RC.
  • a good waveform with a small delay (resistance and capacitance delay) is a hot topic in current research.
  • Existing Top-Gate IGZO A top view of the structure of the TFT is shown in Fig. 2, and an I-type structure is employed.
  • the length W of the thin film transistor 10 of this structure is very long in the X direction, and the space occupying the X axis is large. Such a structure is disadvantageous for the production of a narrow frame on the gate side when performing GOA production.
  • the technical problem to be solved by the present invention is to provide a thin film transistor, a TFT substrate, and a display panel, which are advantageous for the fabrication of a narrow bezel of the display panel.
  • a technical solution adopted by the present invention is to provide a thin film transistor including a gate, a source, and a drain, wherein the source is set to a first curved structure, and the drain is set to a first a second curved structure, the gate is disposed as a third curved structure, wherein the first curved structure of the source is opposite to the second curved structure of the drain, and the third curved structure of the gate is disposed at the first curved structure of the source and Between the second curved structures of the drain.
  • a TFT substrate which includes a display area and a non-display area, wherein the display area is provided with a plurality of pixel units arranged in a matrix, and the display unit is not displayed.
  • the region is provided with a gate driving circuit for driving the pixel unit, and the gate driving circuit includes a plurality of thin film transistors, wherein:
  • the thin film transistor includes a gate, a source, and a drain, wherein the source is disposed as a first curved structure, the drain is disposed as a second curved structure, and the gate is disposed as a third curved structure, wherein the first curved structure of the source Opposite to the second curved structure of the drain, the third curved structure of the gate is disposed between the first curved structure of the source and the second curved structure of the drain;
  • the source and the drain of the thin film transistor of each row or column are respectively connected in series.
  • a display panel including a TFT substrate, a CF substrate, and a liquid crystal layer, wherein the TFT substrate and the CF substrate are oppositely disposed, and the liquid crystal layer is disposed on the TFT.
  • the TFT substrate comprises a display area and a non-display area, wherein the display area is provided with a plurality of pixel units arranged in a matrix, and the non-display area is provided with a gate driving circuit for driving the pixel unit, the gate
  • the driving circuit includes a plurality of thin film transistors, wherein:
  • the thin film transistor includes a gate, a source, and a drain, wherein the source is disposed as a first curved structure, the drain is disposed as a second curved structure, and the gate is disposed as a third curved structure, wherein the first curved structure of the source Opposite to the second curved structure of the drain, the third curved structure of the gate is disposed between the first curved structure of the source and the second curved structure of the drain;
  • the source and the drain of the thin film transistor of each row or column are respectively connected in series.
  • the invention has the beneficial effects that the present invention provides a thin film transistor, a TFT substrate and a display panel.
  • the thin film transistor includes a gate, a source and a drain, wherein the source is set to be the first bend. a structure, the drain is disposed as a second curved structure, and the gate is disposed as a third curved structure, wherein the first curved structure of the source is opposite to the second curved structure of the drain, and the third curved structure of the gate is disposed at the source Between the first curved structure of the pole and the second curved structure of the drain.
  • the gate electrode, the source electrode and the drain electrode of the thin film transistor of the present invention are all provided in a curved structure, which reduces the space occupied by the thin film in the bending direction, thereby facilitating the fabrication of the narrow bezel of the display panel.
  • FIG. 1 is a schematic cross-sectional structural view of a thin film transistor of the prior art
  • FIG. 2 is a schematic top plan view of a prior art thin film transistor
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic circuit diagram of a gate driving circuit in the array substrate shown in FIG. 7;
  • FIG. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • the thin film transistor 30 of the present embodiment includes a gate electrode 31, a source electrode 33, a drain electrode 32, and a semiconductor layer 34.
  • the source 33 is disposed as the first curved structure 331
  • the drain 32 is disposed as the second curved structure 321
  • the gate 31 is disposed as the third curved structure 311 .
  • the first curved structure 331 of the source 33 is disposed opposite to the second curved structure 321 of the drain 32, and the source 33 and the drain 32 are electrically connected to the semiconductor layer 34, respectively.
  • the third curved structure 311 of the gate electrode 31 is disposed between the first curved structure 331 of the source 33 and the second curved structure 321 of the drain 32.
  • the first curved structure 331 is disposed opposite to the second curved structure 321 , that is, the first curved structure 331 and the second curved structure 321 are interpenetrated, and a part of the first curved structure 331 is inserted into the second curved structure 321 .
  • a portion of the second curved structure 321 is also inserted into the first curved structure 331.
  • the first curved structure 331 and the second curved structure 321 are not connected, and a gap is further reserved between the first curved structure 331 and the second curved structure 321 to set the third curved structure 311. Since the gate 31, the source 33, and the drain 32 provided in this embodiment are both curved structures, the present embodiment reduces the space of the thin film transistor 30 in the extending direction of the curved structure.
  • the first curved structure 331 is at least one U-shaped structure or at least one T-shaped structure
  • the second curved structure 321 is at least one U-shaped structure or at least one T-shaped structure
  • the third curved structure 311 is at least one waveform.
  • the first curved structure 331 is one of N interconnected U-shaped structures and N interconnected T-shaped structures
  • the second curved structure 321 is N interconnected U-shaped structures and N mutual mutually
  • the third curved structure 311 is N waveform structures, wherein N is an integer greater than or equal to 1.
  • N of this embodiment is equal to 3.
  • the first curved structure 331 of the embodiment is three interconnected T-shaped structures 332
  • the second curved structure 321 is three interconnected U-shaped structures 322
  • the third curved structure 311 is three square waves. Structure 312.
  • the opening 323 of the U-shaped structure 322 is disposed opposite to the T-shaped structure 332, and the protruding portion 333 of the T-shaped structure 332 is inserted from the opening 323 of the U-shaped structure 322, and the square wave structure 312 is in the U-shaped structure 322 and the T-shaped structure. Bend between 332. Therefore, the present embodiment further reduces the space in the direction perpendicular to the extending direction of the curved structure.
  • the protruding portion 333 of the T-shaped structure 332 may be disposed only at the opening 323 of the U-shaped structure 322 or a predetermined distance from the opening 323 of the U-shaped structure 322.
  • the square wave structure 312 is curved between the opening 323 of the U-shaped structure 322 and the convex portion 333 of the T-shaped structure 332. As shown in Figure 4.
  • first curved structure 331 may also be N interconnected U-shaped structures
  • second curved structure 321 may also be N interconnected T-shaped structures
  • third curved structure 311 is N. Waveform structure.
  • FIG. 5 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • the thin film transistor 40 of the present embodiment still includes a gate electrode 41, a source electrode 43, a drain electrode 42, and a semiconductor layer 44.
  • the gate electrode 41, the source electrode 43 and the drain electrode 42 are still the third curved structure 411, the first curved structure 431, and the second curved structure 421, respectively.
  • the source 43 and the drain 42 are electrically connected to the semiconductor layer 44, respectively.
  • the thin film transistor 40 of the present embodiment is different from the thin film transistor 30 described above in that the first curved structure 431 is N interconnected U-shaped structures 432, and the second curved structure 421 is N interconnected U-shaped structures 422.
  • the third curved structure 411 is N square wave structures 412, where N is an integer greater than or equal to 1. N of this embodiment is 3.
  • the opening 433 of the U-shaped structure 432 of the first curved structure 431 and the opening 423 of the U-shaped structure 422 of the second curved structure 421 are disposed opposite to each other, and the U-shaped structure 432 and the second curved structure 421 of the first curved structure 431
  • the U-shaped structures 422 are offset from each other such that the sidewalls 434 of the U-shaped structure 432 of the first curved structure 431 and the sidewalls 424 of the U-shaped structure 422 of the second curved structure 421 can be inserted into each other's openings, and the square wave structure 412 is
  • the U-shaped structure 432 of the first curved structure 431 and the U-shaped structure 422 of the second curved structure 421 are bent.
  • the structure of the present embodiment can be set to be similar to the structure described above.
  • the sidewall 434 of the U-shaped structure 432 can be disposed only at the opening 423 of the U-shaped structure 422 or a predetermined distance from the opening 423 of the U-shaped structure 422, and the square wave structure 412 is in the U-shaped structure 422.
  • the sidewall 424 and the sidewall 434 of the U-shaped structure 432 are curved.
  • one of the first curved structure 431 and the second curved structure 432 may be N-1 interconnected U-shaped structures, and in this case, N is an integer greater than or equal to 2.
  • FIG. 6 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • the thin film transistor 50 of the present embodiment still includes a gate electrode 51, a source electrode 53, a drain electrode 52, and a semiconductor layer 54.
  • the gate 51, the source 53 and the drain 52 are still the third curved structure 511, the first curved structure 531, and the second curved structure 521, respectively.
  • the source 53 and the drain 52 are electrically connected to the semiconductor layer 54, respectively.
  • the thin film transistor 50 of the present embodiment is different from the thin film transistor 30 described above in that the first curved structure 531 is N interconnected T-shaped structures 532, and the second curved structure 521 is N-1 interconnected T-types.
  • Structure 522, third curved structure 511 is N square wave structures 512, where N is an integer greater than or equal to two. N of this embodiment is 3.
  • the T-shaped structure 532 of the first curved structure 531 and the convex portions 533 and 523 of the T-shaped structure 522 of the second curved structure 521 are disposed opposite to each other, and are disposed offset, and the square wave structure 512 is in the T-shaped structure 532 of the first curved structure 531. It is bent between the T-shaped structure 522 of the second curved structure 521.
  • the convex portion 523 of the T-shaped structure 522 and the convex portion 533 of the T-shaped structure 523 are respectively inserted between the two convex portions of the counterpart. In other embodiments, it is also possible to provide that the convex portion 523 of the T-shaped structure 522 and the convex portion 533 of the T-shaped structure 523 are not inserted into each other.
  • the first curved structure 531 may be N N-connected T-shaped structures 532, and the second curved structure 521 is N interconnected T-shaped structures 522.
  • the embodiment of the present invention further provides a TFT substrate 60.
  • the TFT substrate 60 includes a display area 61 and a non-display area 62.
  • the display area 61 is provided with a plurality of pixel units 611 arranged in a matrix, which are not displayed.
  • the region 62 is provided with a gate driving circuit 621 for driving the pixel unit, the gate driving circuit 621 is disposed on the TFT substrate 60 by the technique of GOA, and the gate driving circuit 621 is a displacement temporarily formed by a plurality of TFT (thin film transistor) structures.
  • the memory is shown in Figure 8.
  • the thin film transistor is a thin film transistor as described above, and details are not described herein again.
  • the source and the drain of the thin film transistor of each row or column are respectively connected in series.
  • the distance between the source and the drain in the bending direction thereof is reduced as compared with the existing structure, which is advantageous for the fabrication of the narrow frame of the display panel.
  • the present invention further provides a display panel 70 including a TFT substrate 71, a CF substrate 72, and a liquid crystal layer 73.
  • the TFT substrate 71 and the CF substrate 72 are oppositely disposed, and the liquid crystal layer 73 is disposed on the TFT. Between the substrate 71 and the CF substrate 72.
  • the TFT substrate 71 is the TFT substrate 60 described above, and details are not described herein again.
  • the gate, the source and the drain of the thin film transistor are both arranged in a curved structure, the distance in the bending direction can be reduced, which is advantageous for the fabrication of the narrow frame of the display panel.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

一种薄膜晶体管、TFT基板以及显示面板。薄膜晶体管（30）包括栅极（31）、源极（33）以及漏极（32），其中，源极设置为第一弯曲结构（331），漏极设置为第二弯曲结构（321），栅极设置为第三弯曲结构（311），其中，源极的第一弯曲结构与漏极的第二弯曲结构相对设置，栅极的第三弯曲结构设置在源极的第一弯曲结构和漏极的第二弯曲结构之间，从而有利于显示面板的窄边框的制作。

Description

一种薄膜晶体管、TFT基板以及显示面板
【技术领域】
本发明涉及显示技术领域，尤其是涉及一种薄膜晶体管、TFT基板以及显示面板。
【背景技术】
GOA(gate driver on array，栅极驱动电路制作在阵列基板上)是由很多TFT（Thin Film Transistor，薄膜晶体管）组成的位移暂存器(shift register)。由于将gate driver做到了array玻璃基板上面，省去了gate driver bonding（栅极驱动电路绑定）的空间，有利于gate侧窄边框的制作。
栅极设置在上部的氧化铟镓锌薄膜晶体管Top gate IGZO（Indium Gallium Zinc Oxide）-TFT的结构的截面图如图1所示，薄膜晶体管10的栅极11设置在半导体层12的上面，源极13和漏极14分别与半导体层12电连接。该薄膜晶体管10具有高迁移率和寄生电容小的优点，可以输出具有RC delay（电阻电容延迟）小的良好波形，是目前研究的热点。现有的Top-Gate IGZO TFT的结构的俯视图如图2所示，采用I-type的结构。该结构的薄膜晶体管10的长度W在X方向的长度非常长，占据X轴的空间大。这样的结构在进行GOA制作时不利于gate侧窄边框的制作。
【发明内容】
本发明主要解决的技术问题是提供一种薄膜晶体管、TFT基板以及显示面板，有利于显示面板的窄边框的制作。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种薄膜晶体管，该薄膜晶体管包括栅极、源极以及漏极，其中，源极设置为第一弯曲结构，漏极设置为第二弯曲结构，栅极设置为第三弯曲结构，其中，源极的第一弯曲结构与漏极的第二弯曲结构相对设置，栅极的第三弯曲结构设置在源极的第一弯曲结构和漏极的第二弯曲结构之间。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT基板，该TFT基板包括显示区和非显示区，其中，显示区设置了多个呈矩阵设置的像素单元，非显示区设置了驱动像素单元的栅极驱动电路，栅极驱动电路包括多个薄膜晶体管，其中：
薄膜晶体管包括栅极、源极以及漏极，其中，源极设置为第一弯曲结构，漏极设置为第二弯曲结构，栅极设置为第三弯曲结构，其中，源极的第一弯曲结构与漏极的第二弯曲结构相对设置，栅极的第三弯曲结构设置在源极的第一弯曲结构和漏极的第二弯曲结构之间；
其中，每行或每列的薄膜晶体管的源极和漏极分别串联连接。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种显示面板，该显示面板包括TFT基板、CF基板以及液晶层，其中，TFT基板和CF基板相对设置，液晶层设置在TFT基板和CF基板之间；其中，TFT基板包括显示区和非显示区，其中，显示区设置了多个呈矩阵设置的像素单元，非显示区设置了驱动像素单元的栅极驱动电路，栅极驱动电路包括多个薄膜晶体管，其中：
薄膜晶体管包括栅极、源极以及漏极，其中，源极设置为第一弯曲结构，漏极设置为第二弯曲结构，栅极设置为第三弯曲结构，其中，源极的第一弯曲结构与漏极的第二弯曲结构相对设置，栅极的第三弯曲结构设置在源极的第一弯曲结构和漏极的第二弯曲结构之间；
其中，每行或每列的薄膜晶体管的源极和漏极分别串联连接。
本发明的有益效果是：区别于现有技术的情况，本发明提供一种薄膜晶体管、TFT基板以及显示面板，薄膜晶体管包括栅极、源极以及漏极，其中，源极设置为第一弯曲结构，漏极设置为第二弯曲结构，栅极设置为第三弯曲结构，其中，源极的第一弯曲结构与漏极的第二弯曲结构相对设置，栅极的第三弯曲结构设置在源极的第一弯曲结构和漏极的第二弯曲结构之间。因此，本发明的薄膜晶体管的栅极、源极和漏极均设置为弯曲的结构，减少了其在弯曲方向上所占用的空间，从而有利于显示面板的窄边框的制作。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图：
图1是现有技术的一种薄膜晶体管的截面结构示意图；
图2是现有技术的薄膜晶体管的俯视结构示意图；
图3是本发明实施例提供的一种薄膜晶体管的结构示意图；
图4是本发明实施例提供的另一种薄膜晶体管的结构示意图；
图5是本发明实施例提供的又一种薄膜晶体管的结构示意图；
图6是本发明实施例提供的又一种薄膜晶体管的结构示意图；
图7是本发明实施例提供的一种阵列基板的结构示意图；
图8是图7所示的阵列基板中的栅极驱动电路的电路结构示意图；
图9是本发明实施例提供的一种显示面板的结构示意图。
【具体实施方式】
下面将结合本发明实施例的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图3，图3是本发明实施例提供的一种薄膜晶体管的结构示意图。如图3所示，本实施例的薄膜晶体管30包括栅极31、源极33、漏极32以及半导体层34。其中，源极33设置为第一弯曲结构331，漏极32设置为第二弯曲结构321，栅极31设置为第三弯曲结构311。源极33的第一弯曲结构331与漏极32的第二弯曲结构321相对设置，且源极33和漏极32分别与半导体层34电连接。栅极31的第三弯曲结构311设置在源极33的第一弯曲结构331和漏极32的第二弯曲结构321之间。本实施例中，第一弯曲结构331与第二弯曲结构321对合设置，即第一弯曲结构331和第二弯曲结构321相互穿插，第一弯曲结构331的一部分插入第二弯曲结构321结构中，第二弯曲结构321的一部分也插入第一弯曲结构331中。并且第一弯曲结构331和第二弯曲结构321不相连接，进一步在第一弯曲结构331和第二弯曲结构321之间预留有空隙来设置第三弯曲结构311。由于本实施例设置的栅极31、源极33以及漏极32均为弯曲结构，因此，本实施例减少了薄膜晶体管30在弯曲结构的延伸方向上的空间。
本实施例中，第一弯曲结构331为至少一个Ｕ型结构或至少一个T型结构，第二弯曲结构321为至少一个Ｕ型结构或至少一个T型结构，第三弯曲结构311为至少一个波形结构，其中，波形为周期波形，且前半周期的波形和后半周期的波形刚好相反，其可为方波波形、正弦波波形以及三角波波形等。本实施例举例以第三弯曲结构311为方波波形进行详述。
更具体的，第一弯曲结构331为N个相互连接的U型结构和N个相互连接的T型结构的其中一种，第二弯曲结构321为N个相互连接的U型结构和N个相互连接的T型结构的另外一种，第三弯曲结构311为N个波形结构，其中，N为大于或等于1的整数。
如图3所示，本实施例的N等于3。具体而言，本实施例的第一弯曲结构331为三个相互连接的T型结构332，第二弯曲结构321为三个相互连接的U型结构322，第三弯曲结构311为三个方波结构312。
其中，U型结构322的开口323对着T型结构332设置，并且T型结构332的凸出部分333从U型结构322的开口323插入，方波结构312在U型结构322和T型结构332之间弯曲。因此本实施例还进一步减少了垂直于弯曲结构的延伸方向的方向上的空间。
在其他实施例中，为了降低制作难度，还可将T型结构332的凸出部分333仅设置在U型结构322的开口323处或距离U型结构322的开口323一预设距离的位置，方波结构312在U型结构322的开口323和T型结构332的凸出部分333之间弯曲。如图4所示。
应理解，在其他实施例中，第一弯曲结构331还可为N个相互连接的U型结构，第二弯曲结构321还可以为N个相互连接的T型结构，第三弯曲结构311为N个波形结构。
请参阅图5，图5是本发明实施例提供的又一种薄膜晶体管的结构示意图。如图5所示，本实施例的薄膜晶体管40依然包括栅极41、源极43、漏极42和半导体层44。并且，栅极41、源极43以及漏极42依然分别为第三弯曲结构411、第一弯曲结构431以及第二弯曲结构421。源极43和漏极42分别和半导体层44电连接。
本实施例的薄膜晶体管40和前文所述的薄膜晶体管30的区别在于：第一弯曲结构431为N个相互连接的U型结构432，第二弯曲结构421为N个相互连接的U型结构422，第三弯曲结构411为N个方波结构412，其中，N为大于或等于1的整数。本实施例的N为3。
其中，第一弯曲结构431的U型结构432的开口433和第二弯曲结构421的U型结构422的开口423相向设置，并且第一弯曲结构431的U型结构432和第二弯曲结构421的Ｕ型结构422错位相对设置，使得第一弯曲结构431的U型结构432的侧壁434和第二弯曲结构421的U型结构422的侧壁424可以彼此插入对方的开口，方波结构412在第一弯曲结构431的U型结构432和第二弯曲结构421的U型结构422之间弯曲。
在其他实施例中，为了降低制作难度，可将本实施例的结构设置为类似于前文所述的结构。具体而言，可将U型结构432的侧壁434仅设置在U型结构422的开口423处或距离U型结构422的开口423一预设距离的位置，方波结构412在U型结构422的侧壁424和U型结构432的侧壁434之间弯曲。
进一步的，为了节省材料，还可以设置第一弯曲结构431和第二弯曲结构432之间的一个为N-1个相互连接的U型结构，此时，N为大于或等于2的整数。
请参阅图6，图6是本发明实施例提供的又一种薄膜晶体管的结构示意图。如图6所示，本实施例的薄膜晶体管50依然包括栅极51、源极53、漏极52和半导体层54。并且，栅极51、源极53以及漏极52依然分别为第三弯曲结构511、第一弯曲结构531以及第二弯曲结构521。源极53和漏极52分别和半导体层54电连接。
本实施例的薄膜晶体管50和前文所述的薄膜晶体管30的区别在于：第一弯曲结构531为N个相互连接的Ｔ型结构532，第二弯曲结构521为N-1个相互连接的Ｔ型结构522，第三弯曲结构511为N个方波结构512，其中，N为大于或等于2的整数。本实施例的N为3。
第一弯曲结构531的Ｔ型结构532和第二弯曲结构521的Ｔ型结构522的凸出部分533和523相向设置，且错位设置，方波结构512在第一弯曲结构531的T型结构532和第二弯曲结构521的T型结构522的之间弯曲。
本实施例中，T型结构522的凸出部分523和T型结构523的凸出部分533分别从对方的两凸出部分之间插入。在其他实施例中，还可以设置T型结构522的凸出部分523和T型结构523的凸出部分533相互不插入。
在其他实施例中，也可以设置为第一弯曲结构531为N个相互连接的Ｔ型结构532，第二弯曲结构521为N个相互连接的T型结构522。
本发明实施例还提供了一种TFT基板60，请参阅图7，该TFT基板60包括显示区61和非显示区62，其中显示区61设置了多个呈矩阵设置的像素单元611，非显示区62设置了驱动像素单元的栅极驱动电路621，栅极驱动电路621通过GOA的技术设置在TFT基板60上，且栅极驱动电路621是由多个TFT（薄膜晶体管）结构形成的位移暂存器，如图8所示。其中，该薄膜晶体管为前文所述的薄膜晶体管，在此不再赘述。
本实施例中，每行或每列的薄膜晶体管的源极和漏极分别串联连接。这样在相同的宽度的情况下，跟现有的结构相比，减少了源极和漏极在其弯曲方向上的距离，有利于显示面板的窄边框的制作。
请参阅图9，本发明还提供了一种显示面板70，显示面板70包括TFT基板71、CF基板72以及液晶层73，其中，TFT基板71和CF基板72相对设置，液晶层73设置在TFT基板71和CF基板72之间。其中，TFT基板71为前文所述的TFT基板60，在此不再赘述。
综上所述，本发明由于将薄膜晶体管的栅极、源极和漏极均设置为弯曲结构，因此可以减少其在弯曲方向上的距离，有利于显示面板的窄边框的制作。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括栅极、源极以及漏极，其中，所述源极设置为第一弯曲结构，所述漏极设置为第二弯曲结构，所述栅极设置为第三弯曲结构，其中，所述源极的第一弯曲结构与所述漏极的第二弯曲结构相对设置，所述栅极的第三弯曲结构设置在所述源极的第一弯曲结构和所述漏极的第二弯曲结构之间。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一弯曲结构为至少一个Ｕ型结构或至少一个T型结构，所述第二弯曲结构为至少一个Ｕ型结构或至少一个T型结构，所述第三弯曲结构为至少一个波形结构，其中，所述波形为周期波形，且前半周期的波形和后半周期的波形刚好相反。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述第一弯曲结构为N个相互连接的U型结构和N个相互连接的T型结构的其中一种，所述第二弯曲结构为N个相互连接的U型结构和N个相互连接的T型结构的另外一种，所述第三弯曲结构为N个波形结构，所述N为大于或等于1的整数；
    其中，所述U型结构的开口对着所述T型结构设置，所述T型结构的凸出部分从所述U型结构的开口插入，所述波形结构在所述U型结构和所述T型结构之间弯曲。
  4. 根据权利要求2所述的薄膜晶体管，其中，所述第一弯曲结构为N个相互连接的U型结构，所述第二弯曲结构为N个相互连接的U型结构，所述第三弯曲结构为N个波形结构，其中，所述N为大于或等于1的整数；
    其中，所述第一弯曲结构的U型结构的开口和所述第二弯曲结构的U型结构的开口相向设置，并且所述第一弯曲结构的U型结构和所述第二弯曲结构的Ｕ型结构错位相对设置，使得第一弯曲结构的U型结构的侧壁和第二弯曲结构的U型结构的侧壁可以彼此插入对方的开口，所述波形结构在第一弯曲结构的U型结构和所述第二弯曲结构的U型结构之间弯曲。
  5. 根据权利要求2所述的薄膜晶体管，其中，所述第一弯曲结构为N个相互连接的Ｔ型结构，所述第二弯曲结构为N-1个相互连接的Ｔ型结构，所述第三弯曲结构为N个波形结构，其中，所述N为大于或等于2的整数；
    所述第一弯曲结构的Ｔ型结构和所述第二弯曲结构的Ｔ型结构的凸出部分相向设置，且错位设置，所述波形结构在第一弯曲结构的T型结构和所述第二弯曲结构的T型结构的之间弯曲。
  6. 一种TFT基板，其中，所述TFT基板包括显示区和非显示区，其中，所述显示区设置了多个呈矩阵设置的像素单元，所述非显示区设置了驱动所述像素单元的栅极驱动电路，所述栅极驱动电路包括多个薄膜晶体管，其中：
    所述薄膜晶体管包括栅极、源极以及漏极，其中，所述源极设置为第一弯曲结构，所述漏极设置为第二弯曲结构，所述栅极设置为第三弯曲结构，其中，所述源极的第一弯曲结构与所述漏极的第二弯曲结构相对设置，所述栅极的第三弯曲结构设置在所述源极的第一弯曲结构和所述漏极的第二弯曲结构之间；
    其中，每行或每列的薄膜晶体管的源极和漏极分别串联连接。
  7. 根据权利要求6所述的TFT基板，其中，所述第一弯曲结构为至少一个Ｕ型结构或至少一个T型结构，所述第二弯曲结构为至少一个Ｕ型结构或至少一个T型结构，所述第三弯曲结构为至少一个波形结构，其中，所述波形为周期波形，且前半周期的波形和后半周期的波形刚好相反。
  8. 根据权利要求7所述的TFT基板，其中，所述第一弯曲结构为N个相互连接的U型结构和N个相互连接的T型结构的其中一种，所述第二弯曲结构为N个相互连接的U型结构和N个相互连接的T型结构的另外一种，所述第三弯曲结构为N个波形结构，所述N为大于或等于1的整数；
    其中，所述U型结构的开口对着所述T型结构设置，所述T型结构的凸出部分从所述U型结构的开口插入，所述波形结构在所述U型结构和所述T型结构之间弯曲。
  9. 根据权利要求7所述的TFT基板，其中，所述第一弯曲结构为N个相互连接的Ｔ型结构，所述第二弯曲结构为N-1个相互连接的Ｔ型结构，所述第三弯曲结构为N个波形结构，其中，所述N为大于或等于2的整数；
    所述第一弯曲结构的Ｔ型结构和所述第二弯曲结构的Ｔ型结构的凸出部分相向设置，且错位设置，所述波形结构在第一弯曲结构的T型结构和所述第二弯曲结构的T型结构的之间弯曲。
  10. 一种显示面板，其中，所述显示面板包括 TFT 基板、 CF 基板以及液晶层，其中，所述 TFT 基板和所述 CF 基板相对设置，所述液晶层设置在所述 TFT 基板和所述 CF 基板之间；
    其中，所述 TFT 基板包括显示区和非显示区，其中，所述显示区设置了多个呈矩阵设置的像素单元，所述非显示区设置了驱动所述像素单元的栅极驱动电路，所述栅极驱动电路包括多个薄膜晶体管，其中：
    所述薄膜晶体管包括栅极、源极以及漏极，其中，所述源极设置为第一弯曲结构，所述漏极设置为第二弯曲结构，所述栅极设置为第三弯曲结构，其中，所述源极的第一弯曲结构与所述漏极的第二弯曲结构相对设置，所述栅极的第三弯曲结构设置在所述源极的第一弯曲结构和所述漏极的第二弯曲结构之间；
    其中，每行或每列的薄膜晶体管的源极和漏极分别串联连接。
  11. 根据权利要求10所述的显示面板，其中，所述第一弯曲结构为至少一个Ｕ型结构或至少一个T型结构，所述第二弯曲结构为至少一个Ｕ型结构或至少一个T型结构，所述第三弯曲结构为至少一个波形结构，其中，所述波形为周期波形，且前半周期的波形和后半周期的波形刚好相反。
  12. 根据权利要求11所述的显示面板，其中，所述第一弯曲结构为N个相互连接的U型结构和N个相互连接的T型结构的其中一种，所述第二弯曲结构为N个相互连接的U型结构和N个相互连接的T型结构的另外一种，所述第三弯曲结构为N个波形结构，所述N为大于或等于1的整数；
    其中，所述U型结构的开口对着所述T型结构设置，所述T型结构的凸出部分从所述U型结构的开口插入，所述波形结构在所述U型结构和所述T型结构之间弯曲。
  13. 根据权利要求11所述的显示面板，其中，所述第一弯曲结构为N个相互连接的Ｔ型结构，所述第二弯曲结构为N-1个相互连接的Ｔ型结构，所述第三弯曲结构为N个波形结构，其中，所述N为大于或等于2的整数；
    所述第一弯曲结构的Ｔ型结构和所述第二弯曲结构的Ｔ型结构的凸出部分相向设置，且错位设置，所述波形结构在第一弯曲结构的T型结构和所述第二弯曲结构的T型结构的之间弯曲。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202142535U (zh) * 2011-07-22 2012-02-08 京东方科技集团股份有限公司 一种薄膜场效应晶体管和液晶显示器
CN104134671A (zh) * 2013-04-30 2014-11-05 乐金显示有限公司 薄膜晶体管阵列基板及其制造方法
CN105118865A (zh) * 2015-09-22 2015-12-02 京东方科技集团股份有限公司 薄膜晶体管、像素结构、显示基板、显示面板及显示装置
CN107204375A (zh) * 2017-05-19 2017-09-26 深圳市华星光电技术有限公司 薄膜晶体管及其制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2953416B2 (ja) * 1996-12-27 1999-09-27 日本電気株式会社 半導体装置
US7166867B2 (en) * 2003-12-05 2007-01-23 International Rectifier Corporation III-nitride device with improved layout geometry
KR101246023B1 (ko) * 2005-01-06 2013-03-26 삼성디스플레이 주식회사 어레이 기판 및 이를 갖는 표시장치
CN104485361B (zh) * 2014-12-25 2018-03-30 上海华虹宏力半导体制造有限公司 绝缘体上硅射频开关器件结构
CN105140297A (zh) * 2015-09-17 2015-12-09 重庆京东方光电科技有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
CN205692837U (zh) * 2016-03-29 2016-11-16 上海天马有机发光显示技术有限公司 一种tft结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202142535U (zh) * 2011-07-22 2012-02-08 京东方科技集团股份有限公司 一种薄膜场效应晶体管和液晶显示器
CN104134671A (zh) * 2013-04-30 2014-11-05 乐金显示有限公司 薄膜晶体管阵列基板及其制造方法
CN105118865A (zh) * 2015-09-22 2015-12-02 京东方科技集团股份有限公司 薄膜晶体管、像素结构、显示基板、显示面板及显示装置
CN107204375A (zh) * 2017-05-19 2017-09-26 深圳市华星光电技术有限公司 薄膜晶体管及其制作方法

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