WO2018219345A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

Info

Publication number
WO2018219345A1
WO2018219345A1 PCT/CN2018/089521 CN2018089521W WO2018219345A1 WO 2018219345 A1 WO2018219345 A1 WO 2018219345A1 CN 2018089521 W CN2018089521 W CN 2018089521W WO 2018219345 A1 WO2018219345 A1 WO 2018219345A1
Authority
WO
WIPO (PCT)
Prior art keywords
touch signal
array substrate
sub
pixel
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/089521
Other languages
English (en)
French (fr)
Inventor
霍培荣
王志强
钟德龙
邱亚栋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2018219345A1 publication Critical patent/WO2018219345A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • the array substrate of the in-cell touch display (English: Full in cell) panel generally includes: a stacked thin film transistor (English: Thin Film Transistor; abbreviated as: TFT), a touch signal line, a flat layer, a common electrode, and a passivation Layer and pixel electrodes.
  • the touch signal lines are respectively connected to the touch electrodes and the touch driving circuit, and are used for transmitting touch signals between the touch electrodes and the touch driving circuits.
  • the common electrode can be used as a touch electrode.
  • the application provides an array substrate, a display panel and a display device.
  • an array substrate comprising:
  • the common electrode, the passivation layer and the touch signal line are sequentially disposed on the base substrate, and the touch signal line is configured to transmit the touch signal loaded on the common electrode to the touch driving circuit;
  • the passivation layer is provided with a first via hole
  • the touch signal line is connected to the common electrode through the first via.
  • the touch signal line and the common electrode are made of the same conductive material.
  • the touch signal line and the common electrode are made of the same transparent conductive material.
  • the touch signal line is an indium tin oxide pattern
  • the common electrode is an indium tin oxide electrode
  • the touch signal line is a graphene pattern
  • the common electrode is a graphene electrode
  • the array substrate further includes: a pixel electrode disposed on a side of the passivation layer away from the substrate substrate, and a thin film transistor disposed between the substrate substrate and the common electrode;
  • the pixel electrode is disposed in the same layer and insulated from the touch signal line, and the pixel electrode is connected to a source or a drain of the thin film transistor through a second via.
  • the pixel electrode is spaced apart from the touch signal line.
  • the pixel electrode is an indium tin oxide electrode or a graphene electrode.
  • an orthographic projection of the first via on the substrate substrate does not overlap with an orthographic projection of the second via on the substrate.
  • the common electrode and the passivation layer are sequentially stacked, and the second via hole sequentially penetrates the passivation layer and the common electrode.
  • the pixel electrode and the touch signal line are made of the same conductive material.
  • the pixel electrode and the touch signal line are formed in a patterning process.
  • the array substrate further includes: a flat layer disposed between the base substrate and the common electrode, the flat layer having a thickness greater than a thickness of the passivation layer.
  • the array substrate further includes: a thin film transistor disposed between the base substrate and the common electrode; the thin film transistor includes an active layer, a gate insulation sequentially disposed on the base substrate a layer, a gate, an interlayer dielectric layer, and a source/drain pattern, the source and drain patterns including a source and a drain;
  • the array substrate further includes: a light shielding layer and a buffer layer sequentially disposed between the base substrate and the active layer.
  • the thin film transistor is a low temperature polysilicon thin film transistor
  • the active layer is a polysilicon active layer
  • a display panel comprising the array substrate of any of the first aspects.
  • the display panel includes: a plurality of pixel groups arranged in an array, each pixel group includes a plurality of sub-pixels having different colors, and a plurality of sub-pixels of different colors in each pixel group are sequentially arranged in the first direction.
  • the arrangement of the sub-pixels in the plurality of pixel groups is the same, the first direction includes: a direction in which the pixel row is located or a direction in which the pixel column is located; and the touch signal line is in the first direction , including a plurality of touch signal wire segments;
  • the color of two sub-pixels directly adjacent to each other on the orthographic projection of the touch signal wire segment on the array substrate is directly adjacent to the two sides of the orthographic projection of the other touch signal wire segment on the array substrate At least one of the two sub-pixels has a different color.
  • the display panel includes: a plurality of pixel groups arranged in an array, each pixel group includes a plurality of sub-pixels having different colors, and a plurality of sub-pixels of different colors in each pixel group are sequentially arranged in the first direction.
  • the arrangement of the sub-pixels in the plurality of pixel groups is the same, the first direction includes: a direction in which the pixel row is located or a direction in which the pixel column is located; and the touch signal line is in the first direction
  • the plurality of touch signal wire segments are included; the number of the pixel groups is greater than or equal to 3;
  • the first touch signal wire segments are directly adjacent to the two sub-pixels on both sides of the front projection on the array substrate, and the second touch signal wire segments are directly on both sides of the orthographic projection on the array substrate.
  • the color of the two sub-pixels adjacent to each other, and the color of the two sub-pixels directly adjacent to each other on both sides of the orthographic projection of the third touch signal wire segment on the array substrate are different.
  • the orthographic projection of the touch signal wire segments on the array substrate does not overlap with the orthographic projection of the sub-pixels on the array substrate.
  • the plurality of sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • a display device comprising the display panel of the second aspect.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of still another array substrate provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application.
  • FIG. 5 is a schematic structural view of a TFT after forming a TFT on a substrate
  • FIG. 6 is a schematic structural diagram of a flat layer pattern formed on a substrate on which a TFT is formed according to an embodiment of the present application
  • FIG. 7 is a schematic structural view of a common electrode pattern formed on a base substrate on which a flat layer pattern is formed according to an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram of a passivation layer pattern formed on a base substrate on which a common electrode pattern is formed according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a display panel including a plurality of pixel groups arranged in an array according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a display panel including an array substrate and a color filter substrate according to an embodiment of the present application
  • FIG. 11 is a schematic diagram of a position between a sub-pixel, a touch signal line, and a black matrix in a display panel according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram showing the position between a sub-pixel, a touch signal line, and a black matrix in the related art.
  • the array substrate generally includes: a stacked TFT, a touch signal line, a flat layer, a common electrode, a passivation layer, and a pixel electrode.
  • the touch signal line is disposed in the same layer as the source and drain patterns in the TFT, and both are made of metal.
  • the common electrode is connected to the touch signal line through a via hole disposed in the flat layer, and the common electrode located in the via hole can be regarded as a connection wire between the common electrode and the touch signal line, and the common in the via hole
  • the thickness of the electrode can be regarded as the length of the connecting wire.
  • the thickness of the touch signal line (also referred to as the length of the touch signal line in this application) is due to the large thickness of the source and drain electrodes. Also larger. Since the resistance is positively correlated with the length of the wire, and the thickness of the touch signal line is large, the resistance of the touch signal line is large. And because the flat layer is thicker, the via hole disposed in the flat layer has a larger hole depth, so that the touch signal line in the via hole has a larger thickness, resulting in a connection in the via hole by the touch signal line. The resistance of the wire is large.
  • the array substrate is affected by the resistance of the touch signal line and the resistance of the connecting wire in the via hole.
  • the driving resistance is large, which leads to a large attenuation of the driving signal.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate 00 may include:
  • the common electrode 004, the passivation layer (PVX) 005, and the touch signal line 006 are sequentially disposed on the base substrate 001.
  • the touch signal line 006 is used to transmit the touch signal loaded on the common electrode 004 to the touch driving circuit.
  • the first via is disposed on the passivation layer 005, and the touch signal line 006 is connected to the common electrode 004 through the first via.
  • the touch signal line and the source and drain patterns in the TFT are formed by the same patterning process, and the source and drain images have a large thickness, so that the touch signal line also has a large thickness, due to the resistance and the wire.
  • the length is positively correlated, thus causing a large resistance of the touch signal line.
  • the touch signal line 006 on the array substrate provided by the embodiment of the present application is no longer formed by the same patterning process as the source drain pattern in the TFT. Therefore, the touch signal line 006 can be set smaller.
  • the thickness (for example, the thickness of the touch signal line 006 is reduced by 1/6 relative to the original thickness) to reduce the resistance thereof, thereby reducing the driving resistance of the array substrate.
  • the common electrode, the passivation layer, and the touch signal line are sequentially disposed on the base substrate, and the first via hole is disposed on the passivation layer to make the touch signal
  • the line is connected to the common electrode through the first via hole.
  • the thickness of the touch signal line is not affected by the thickness of the source/drain pattern, so that the touch signal line has a small thickness.
  • the touch signal line has a small resistance, and accordingly, the driving resistance of the array substrate is reduced, thereby reducing the attenuation degree of the driving signal in the array substrate, and then effectively improving the driving capability of the array substrate.
  • the array substrate 00 may further include: a flat layer 003 disposed between the base substrate 001 and the common electrode 004.
  • the thickness of the flat layer 003 may be greater than the thickness of the passivation layer 004.
  • the hole depth of the first via disposed on the passivation layer 005 is reduced compared to the related art, so that the touch disposed in the first via hole
  • the signal line 006 has a small thickness (for example, the thickness is reduced by about 1/20 with respect to the related art), that is, the connecting wire served by the touch signal line 006 in the first via hole has a small thickness.
  • the length, and since the resistance is positively correlated with the length of the wire, the touch signal line 006 in the first via has a smaller resistance, further reducing the driving resistance of the array substrate.
  • a TFT 002 may be disposed between the base substrate 001 and the flat layer 003.
  • the TFT 002 may be a low temperature polysilicon TFT, and the low temperature polysilicon TFT may be sequentially disposed on the substrate 001, on the array substrate to which the Low Temperature Poly-silicon (LTPS) technology is applied.
  • LTPS Low Temperature Poly-silicon
  • Polysilicon (English: Poly-silicon; abbreviation: P-SI) active layer 0021, gate insulating layer (English: Gate Insulator; GI) 0022, gate 0023, interlayer dielectric layer (English: inter-layer Dielectric) Abbreviation: ILD) 0024 and source drain pattern 0025, source drain pattern 0025 can include source 0025a and drain 0025b, and a schematic diagram of the structure thereof will continue to refer to FIG.
  • P-SI gate insulating layer
  • GI Gate Insulator
  • ILD interlayer dielectric layer
  • source drain pattern 0025 can include source 0025a and drain 0025b, and a schematic diagram of the structure thereof will continue to refer to FIG.
  • the array substrate may further include: a light shielding (English: Light Shield; LS) layer 0026 and a buffer layer disposed between the base substrate 001 and the active layer 0021.
  • a light shielding (English: Light Shield; LS) layer 0026 and a buffer layer disposed between the base substrate 001 and the active layer 0021.
  • the touch signal line may be an Indium tin oxide (ITO) pattern or a graphene pattern
  • the common electrode may be an ITO electrode or a graphene electrode.
  • the material of the touch signal line and the common electrode may be the same, that is, the touch signal line and the common electrode may be made of the same conductive material or the same transparent conductive material.
  • the touch signal line may be The ITO pattern, and the common electrode may be an ITO electrode; or the touch signal line may be a graphene pattern, and the common electrode may be a graphene electrode.
  • the materials from which the touch signal lines and the common electrodes are made may be different.
  • the touch signal line is made of ITO or graphene
  • the structure of the touch signal line is relative to the touch signal of the related art.
  • the three-layer structure in which the wire is made of titanium, aluminum, and titanium that is, the touch signal line in the related art is composed of three film layers, which are respectively made of titanium metal, aluminum metal, and titanium metal).
  • the transmittance of the array substrate is improved.
  • graphene has good electrical conductivity, when the touch signal line is a graphene pattern and the common electrode is a graphene electrode, it can not only improve the transmittance of the array substrate, but also reduce the driving of the array substrate. resistance.
  • the touch signal line can also be a pattern made of other transparent materials with better conductivity
  • the common electrode can also be an electrode made of other transparent materials with better conductivity. Specifically limited.
  • the touch signal line and the common electrode are made of the same material.
  • the implementation of the touch signal line and the common electrode made of different materials can further reduce the driving resistance of the array substrate.
  • the array substrate may further include: a pixel electrode 007 disposed on a side of the passivation layer 005 away from the substrate 001, wherein the pixel electrode 007 may be an ITO electrode or a graphene electrode.
  • the pixel electrode 007 is an ITO electrode
  • the transmittance of the array substrate can be improved.
  • the pixel electrode 007 is a graphene electrode
  • the transmittance of the array substrate can be increased correspondingly and the driving resistance of the array substrate can be reduced.
  • the pixel electrode 007 is disposed in the same layer and insulated from the touch signal line 006.
  • the pixel electrode 007 is connected to the source 0025a or the drain 0025b of the TFT through the second via 008.
  • the pixel electrode 007 is insulated from the touch signal line 006.
  • the pixel electrode 007 is spaced apart from the touch signal line 006. For example, a gap may be disposed between the pixel electrode 007 and the touch signal line 006.
  • 007 and the touch signal line 006 are insulated by a gap; or an insulating medium is disposed between the pixel electrode 007 and the touch signal line 006, and the pixel electrode 007 and the touch signal line 006 are insulated by an insulating medium.
  • the orthographic projection of the second via 008 on the substrate substrate does not overlap with the orthographic projection of the first via on the substrate 001.
  • the orthographic projection of the first via on the base substrate does not overlap with the orthographic projection of the second via on the substrate, and the pixel electrode and the touch signal line can be insulated, thereby ensuring insulation between the pixel electrode and the common electrode.
  • the flat layer 003, the common electrode 004, and the passivation layer 005 may be sequentially stacked on the base substrate 001, and the second via 008 may sequentially pass through the passivation layer 005 and the common electrode 004. And the flat layer 003, the bottom of the second via 008 is located above the source 0025a or the drain 0025b of the TFT 002.
  • the pixel electrode 007 and the touch signal line 006 can be made of the same conductive material.
  • the pixel electrode 007 and the touch signal line 006 can be in one patterning process. Formed in order to simplify the manufacturing process of the array substrate. For example, when the materials are the same, both can be formed using the same mask.
  • the forming the pixel electrode 007 and the touch signal line 006 by the same patterning process means: depositing a conductive material having a certain thickness on the entire surface of the passivation layer away from the substrate substrate, and obtaining a conductive material layer.
  • a layer of photoresist having a certain thickness is coated on the conductive material layer to obtain a photoresist layer, and the photoresist layer is exposed by a mask to form a fully exposed region and at least two non-exposed regions. Then, the development process is used to completely remove the photoresist in the completely exposed region, and the photoresist in the non-exposed region is completely retained, and the region corresponding to the completely exposed region on the conductive material layer is etched by an etching process, and then stripped. The photoresist in the non-exposed area is used to obtain the pixel electrode 007 and the touch signal line 006.
  • the array substrate provided by the embodiment of the present invention has a flat layer, a common electrode, a passivation layer, and a touch signal line disposed on the substrate, and a first via hole is disposed on the passivation layer.
  • the touch signal line is connected to the common electrode through the first via hole.
  • the thickness of the touch signal line is not affected by the thickness of the source/drain pattern, and the thickness of the passivation layer is smaller than that of the flat layer.
  • the thickness of the touch signal line has a small thickness, so that the touch signal line has a small resistance, correspondingly, the driving resistance of the array substrate is reduced, thereby reducing the attenuation degree of the driving signal in the array substrate. , in turn, effectively improves the driving capability of the array substrate.
  • the embodiment of the present application further provides a method for manufacturing an array substrate. As shown in FIG. 4, the method may include:
  • Step 301 forming a TFT on the base substrate.
  • the active layer in the TFF may be made of a polysilicon material, and the structure of the TFT 002 is shown in FIG.
  • Step 302 forming a flat layer pattern on the base substrate on which the TFT is formed.
  • the flat layer pattern may include a flat layer via hole and a flat layer via hole located above a source or a drain of the TFT, the flat layer via hole may expose a source or a drain in the TFT of the lower layer of the flat layer pattern .
  • the structure of the base substrate can be as shown in FIG. 6, wherein a flat layer pattern is formed over the source drain pattern 0025, and the flat layer pattern includes a flat layer 003 and a flat layer via 0031, and the source 0025a is The flat layer is exposed in the via hole 0031.
  • Step 303 forming a common electrode pattern on the base substrate on which the flat layer pattern is formed.
  • the common electrode pattern may include a common electrode and a common electrode via, and the common electrode may be an ITO electrode or a graphene electrode, and the common electrode via is in communication with the flat layer via.
  • the structure of the base substrate can be as shown in FIG. 7, wherein the common electrode pattern can include a common electrode 004 and a common electrode via 0041, the common electrode 004 is formed on the flat layer 003, and the common electrode via 0041 is The flat layer vias 0031 are in communication.
  • Step 304 forming a passivation layer pattern on the base substrate on which the common electrode pattern is formed.
  • the passivation layer pattern may include a passivation layer, a first passivation layer via (ie, a first via) and a second passivation via, the second passivation via passing through the common electrode via
  • the planarization layer is connected to the via hole, and the second passivation layer via hole, the common electrode via hole and the flat layer via hole together form a second via hole on the array substrate, and the orthographic projection of the first via hole on the substrate substrate.
  • the orthographic projection of the second via holes on the base substrate does not overlap, and the thickness of the flat layer is greater than the thickness of the passivation layer.
  • the structure of the base substrate can be as shown in FIG. 8, wherein the passivation layer pattern can include a passivation layer 005, a first passivation layer via (ie, a first via) 0051, and a second passivation.
  • the via layer is formed on the common electrode 004.
  • the second passivation layer via 0052 and the common electrode via 0041 and the flat layer via 0031 together form a second via 008 on the array substrate.
  • the orthographic projection of the first via 0051 on the substrate 001 (the dotted line corresponding to the first via 0051) and the orthographic projection of the second via 008 on the substrate 008 (the dotted line corresponding to the second via 008) Do not overlap, and the thickness of the flat layer 003 is greater than the thickness of the passivation layer 005.
  • Step 305 forming a pixel electrode and a touch signal line on the base substrate on which the passivation layer pattern is formed.
  • the pixel electrode is disposed in the same layer and insulated from the touch signal line, and the pixel electrode is connected to the source or the drain of the TFT through the second via hole, and the touch signal line is connected to the common electrode through the first via hole, and is formed in a blunt manner.
  • FIG. 3 for a schematic diagram of the structure of the array substrate on which the pixel electrode and the touch signal line are formed on the substrate of the layered pattern. Wherein, the pixel electrode and the touch signal line can be arranged at intervals to insulate the two.
  • the pixel electrode and the touch signal line may be made of the same material or different materials.
  • the pixel electrode may be made of ITO or graphene, and the touch signal line may also be made of ITO. Or made of graphene.
  • the pixel electrode and the touch signal line are made of different materials, both may be sequentially formed on the base substrate on which the passivation layer pattern is formed.
  • the material of the pixel electrode and the touch signal line are made of the same material, the pixel electrode and the touch signal line can be formed by the same mask, and the manufacturing process of the array substrate can be simplified accordingly.
  • the method for fabricating an array substrate sequentially forms a TFT, a flat layer, a common electrode, a passivation layer, and a touch signal line on the substrate, and the first layer is disposed on the passivation layer.
  • a via hole connects the touch signal line to the common electrode through the first via hole, and the thickness of the touch signal line is not affected by the thickness of the source/drain pattern, and the thickness of the passivation layer is compared with the related art.
  • the thickness of the flat layer is smaller than that of the flat layer, so that the touch signal line has a small resistance, and accordingly, the driving resistance of the array substrate is reduced, thereby reducing the driving in the array substrate.
  • the degree of attenuation of the signal effectively increases the drive capability of the array substrate.
  • the present application also provides a display panel, which may include the array substrate shown in any of FIGS. 1 to 3.
  • the display panel may further include: a plurality of pixel groups M1 arranged in an array, and each of the pixel groups M1 includes a plurality of sub-pixels M2 (in FIG. 9 , the plurality of sub-pixels include red sub-pixels R, the green sub-pixel G and the blue sub-pixel B are exemplified, and a plurality of sub-pixels of the plurality of pixel groups are cyclically arranged in the display panel.
  • the display panel includes: a plurality of pixel groups M1 arranged in an array, each pixel group M1 includes a plurality of sub-pixels M2 having different colors, and a plurality of sub-pixels M2 having different colors in each pixel group M1 are along the first
  • the directions are arranged in sequence, and the arrangement order of the sub-pixels in the plurality of pixel groups is the same.
  • the first direction may include: a direction in which the pixel row is located or a direction in which the pixel column is located, where the pixel row is located and the pixel column is located
  • the direction is vertical.
  • a plurality of sub-pixels M2 having different colors in each pixel group M1 are sequentially arranged in a direction S1 in which the pixel columns are located.
  • the display panel may include an array substrate 00 and a color filter substrate 10.
  • a liquid crystal (not shown in FIG. 10) or a light-emitting layer (not shown in FIG. 10) may be disposed between the array substrate 00 and the color filter substrate 10.
  • the array substrate 00 may include: a TFT, a flat layer, a common electrode, a passivation layer, a pixel electrode, and a touch signal line 006, etc. (only for the purpose of viewing, only the touch signal line 006 in the array substrate 00 is shown in FIG. Set the location).
  • the color filter substrate 10 may include a color resist layer 101 and a black matrix 102.
  • the color resist layer 101 includes a plurality of color filters, for example, may include a red filter, a green filter, and a blue filter.
  • the sub-pixels in the display panel are generally divided according to the position of the filter in the color resist layer.
  • the sub-pixel region where the red filter is located ie, the area indicated by the dotted line
  • the sub-pixel region where the sub-pixel region is located is the green sub-pixel G
  • the sub-pixel region where the blue filter is located is the blue sub-pixel B.
  • Each of the sub-pixels may include a TFT located in the sub-pixel region, a flat layer, a common electrode, a passivation layer, a pixel electrode, a liquid crystal, a color filter, and the like.
  • a touch signal line is disposed in each pixel group, and the position of the touch signal line in each of the three pixel groups sequentially disposed in the first direction is different. That is, referring to FIG. 9, the touch signal line 006 includes a plurality of touch signal wire segments in the first direction. In the first direction, in each adjacent two pixel groups M1, for each adjacent two touch signal wire segments: one touch signal wire segment is directly adjacent to both sides of the orthographic projection 0061 on the array substrate. The color of the two sub-pixels is different from the color of at least one of the two sub-pixels directly adjacent to the two sides of the positive projection 0061 of the other touch signal conductor segment on the array substrate. As shown in FIG.
  • two sub-pixels directly adjacent to each other on the two sides of the positive projection 0061 of the touch signal wire segment are green sub-pixels and blue sub-pixels, and the other touch signal wire segments are on the array substrate.
  • the two sub-pixels directly adjacent to each other on the two sides of the orthographic projection 0061 are a red sub-pixel and a green sub-pixel.
  • the extending direction of the touch signal wire segments may be parallel to the extending direction of the gate lines.
  • the extending direction of the gate line is parallel to the direction S2 in which the pixel row is located
  • the extending direction of the touch signal wire segment is also parallel to the direction S2 in which the pixel row is located.
  • FIG. 9 is only one schematic diagram of each pixel group including a plurality of sub-pixels having different colors, and is not used to limit the present application.
  • a sub-pixel of two colors, a sub-pixel of four colors, or a sub-pixel of more colors may be included in each pixel group, which is not specifically limited in the embodiment of the present application.
  • the color of two sub-pixels directly adjacent to each other on the positive projection side of the touch signal wire segment on the array substrate, and the other two sides of the touch signal wire segment on the front projection on the array substrate are directly The color of two adjacent sub-pixels is also not specifically limited.
  • each pixel group includes three sub-pixels of different colors
  • the sub-pixels of the three colors are sub-pixels of the first color, sub-pixels of the second color, and sub-pixels of the third color, respectively, in the first party.
  • the two touch pixels of the touch signal wire segments directly adjacent to each other on the orthographic projection on the array substrate may respectively
  • the two sub-pixels directly adjacent to the two sides of the orthogonal projection on the array substrate of the touch signal wire segment may be the sub-pixel of the second color and the third The sub-pixel of the color.
  • two sub-pixels directly adjacent to each side of the positive projection of the touch signal wire segment on the array substrate may be a sub-pixel of a first color and a sub-pixel of a third color, and another touch signal wire segment is in the array.
  • the two sub-pixels directly adjacent to both sides of the orthographic projection on the substrate may be sub-pixels of the second color and sub-pixels of the third color, respectively.
  • two sub-pixels directly adjacent to each side of the positive projection of the touch signal wire segment on the array substrate may be a sub-pixel of a first color and a sub-pixel of a third color, and another touch signal wire segment is in the array.
  • the two sub-pixels directly adjacent to both sides of the orthographic projection on the substrate may be sub-pixels of the second color and sub-pixels of the first color, respectively.
  • each of the pixel groups M1 includes N sub-pixels M2 having different colors
  • N touches are sequentially arranged in the first direction.
  • Signal wire segment the color of two sub-pixels directly adjacent to each other on the front projection of the first touch signal wire segment on the array substrate, and the second touch signal wire segment directly on both sides of the orthographic projection on the array substrate
  • the colors of the two sub-pixels adjacent to each other, and, respectively, the color of the two sub-pixels directly adjacent to each other on both sides of the orthographic projection of the Nth touch signal wire segment on the array substrate are different.
  • each pixel group M1 includes three sub-pixels of different colors, which are sub-pixels of the first color, sub-pixels of the second color, and sub-pixels of the third color, respectively.
  • the three touch signal wire segments sequentially arranged along the first direction the first touch signal wire segments are directly on both sides of the orthographic projection on the array substrate
  • the two adjacent sub-pixels may be a sub-pixel of a first color and a sub-pixel of a second color, respectively, and the two sub-pixels of the second touch signal wire segment directly adjacent to each other on the orthographic projection on the array substrate may be respectively
  • the sub-pixels of the second color and the sub-pixels of the third color, and the two sub-pixels directly adjacent to the two sides of the positive projection on the array substrate of the third touch signal wire segment may respectively be sub-pixels of the third color and
  • the sub-pixels of the first color that is, the color of the two sub-pixels directly adjacent to each
  • a black matrix is disposed between every two sub-pixels, and the lateral dimension of the black matrix is the width of the spacing between the two sub-pixels (or the lateral dimension of the black matrix is positively correlated with the width of the spacing between the two sub-pixels).
  • the relative position of the sub-pixel and the touch signal line on the array substrate is shown in the dotted line frame A1 of FIG. 11, and the relative position between the sub-pixel and the black matrix BM is as shown in the dotted line frame A2 of FIG.
  • the pattern size of the black matrix between the two sub-pixels provided with the touch signal lines is larger than the pattern size of the black matrix between the two sub-pixels not provided with the touch signal lines.
  • the black matrix disposed between the two sub-pixels has a larger size, and when no touch signal line is disposed between the two sub-pixels, The black matrix disposed between the two sub-pixels has a smaller size.
  • each pixel group is correspondingly provided with one touch signal line, which can avoid the contact resistance is large due to too few touch signal lines, and then the contact of the touch electrode is poor, or the touch signal line can be avoided too much.
  • the problem that the touch signal line is poorly matched with the first via hole is that the contact between the touch signal line and the common electrode is avoided.
  • the display panel includes a plurality of pixel groups, and each of the pixel groups also includes a plurality of sub-pixels, and the plurality of sub-pixels may be a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, in the plurality of pixel groups.
  • a plurality of sub-pixels are cyclically arranged in the display panel.
  • a touch signal line is disposed in each pixel group, and the touch signal lines are in the same position in each pixel group, and a black matrix is also disposed between each two sub-pixels.
  • the two sub-pixels directly adjacent to each other on the positive projection side of the plurality of conductive line segments of the touch signal line have the same color, for example, in each sub-pixel group, the conductive line segments are on the array substrate.
  • the two sub-pixels directly adjacent to each side of the Orthographic are respectively a blue sub-pixel and a red sub-pixel.
  • the position of the sub-pixel and the touch signal line TPM on the array substrate is as shown in the broken line frame C of FIG. 12, and the position between the sub-pixel and the black matrix BM is as shown in the broken line frame D of FIG.
  • the plurality of conductive line segments of the touch signal line are directly adjacent to each other on both sides of the orthographic projection on the array substrate.
  • the sub-pixels are all the same color.
  • the two sub-pixels directly adjacent to each other on both sides of the black matrix having the larger graphic size have the same color.
  • the color displayed on the entire display panel will appear as directly adjacent to both sides of the larger-sized black matrix.
  • the color of the two sub-pixels is superimposed, for example, assuming that the touch signal line is between the blue sub-pixel and the red sub-pixel of each pixel group (refer to the position shown in FIG. 12 for the position of the touch signal line). That is, in each pixel group, the two sub-pixels directly adjacent to the two sides of the positive projection on the array substrate are respectively a blue sub-pixel and a red sub-pixel, and the entire display panel is displayed.
  • the color of the color is affected by the purple color of the blue and red superimposed, that is, the color displayed on the display panel is purple, which causes the display panel to display an abnormal color, and then the display panel cannot pass the electrostatic discharge (English: Electro-Static) Discharge; abbreviation: ESD) test.
  • ESD Electro-Static Discharge
  • the position of the touch signal line in each of the three adjacent pixel groups is different, that is, in every three pixel groups arranged in the first direction, Three touch signal wire segments arranged in one direction in sequence: the two touch signal wire segments have different colors of two sub-pixels directly adjacent to each other on both sides of the orthographic projection on the array substrate.
  • the influence of the black matrix at the corresponding position in each of the three pixel groups on the display panel display color is three
  • the superposition of the colors of two sub-pixels directly adjacent to each other on both sides of the black matrix having a larger image size in the pixel group is the position shown in FIG. 11 , and the position of the touch signal line in the adjacent three pixel groups is different.
  • the color displayed by the panel at the corresponding position is the superposition of the colors of the two sub-pixels directly adjacent to each other on both sides of the black matrix having the larger size of the three pixel groups. That is, please continue to refer to FIG. 11 , the display panel includes a plurality of pixel groups arranged in an array, the number of the plurality of pixel groups is greater than or equal to 3, and for the plurality of pixel groups, sequentially arranged in the first direction In each of the three pixel groups of the cloth, the first touch of the first touch signal wire segment on the two sides of the positive projection on the array substrate are respectively a green sub-pixel and a blue sub-pixel, and the first touch The color of the pixel group where the control signal wire segment is displayed is a superposition of green and blue; the second sub-pixels of the second touch signal wire segment directly adjacent to the orthographic projection on the array substrate are respectively red sub-pixels and The green sub-pixel, the color of the pixel group in which the second touch signal wire segment is located is a superposition of
  • the two sub-pixels are respectively a blue sub-pixel and a red sub-pixel, and the color displayed by the pixel group in which the third touch signal wire segment is displayed is a superposition of blue and red. Moreover, since the superimposed colors of the three colors of red, green and blue are white, when the liquid crystal in the vicinity of the smaller size black matrix is no longer deflected, and the liquid crystal in the vicinity of the larger size black matrix is continuously deflected, the color of the entire display panel will be displayed.
  • the white color is superimposed on the red, green and blue, so that the color displayed by the display panel is not affected by the color of the sub-pixels on both sides of the black matrix having a larger size, that is, relative to the related art, the embodiment of the present application
  • the provided display panel can avoid the display color abnormality of the display panel.
  • the display panel provided by the embodiment of the present invention provides a flat layer, a common electrode, a passivation layer, and a touch signal line on the substrate, and a first via is disposed on the passivation layer.
  • the control signal line is connected to the common electrode through the first via hole. Since the thickness of the flat layer is greater than the thickness of the passivation layer, the touch signal line has a small thickness, so that the touch signal line has a small resistance, correspondingly
  • the driving resistance of the array substrate in the display panel is reduced, thereby reducing the attenuation degree of the driving signal in the array substrate, and then the driving capability of the array substrate is effectively improved.
  • the display panel is prevented from being abnormal in display color.
  • the present application further provides a display device, which includes the above display panel, and the display device may be: a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Any product or part that has a display function.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

本申请公开了一种阵列基板、显示面板及显示装置，属于显示技术领域。所述阵列基板包括：依次设置在衬底基板上的公共电极、钝化层和触控信号线，所述触控信号线用于将公共电极上加载的触控信号传输至触控驱动电路；所述钝化层上设置有第一过孔；所述触控信号线通过所述第一过孔与所述公共电极连接。本申请减小了阵列基板的驱动电阻，进而减小了阵列基板中驱动信号的衰减程度，继而有效地提高了阵列基板的驱动能力。本申请用于显示图像。

Description

阵列基板、显示面板及显示装置
本申请要求于2017年06月01日提交中国国家知识产权局、申请号为201720629918.1、实用新型名称为“阵列基板、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板、显示面板及显示装置。
背景技术
内嵌式触控显示(英文：Full in cell)面板的阵列基板通常包括：叠加设置的薄膜晶体管(英文：Thin Film Transistor；简称：TFT)、触控信号线、平坦层、公共电极、钝化层和像素电极。其中，该触控信号线分别与触控电极和触控驱动电路连接，用于在触控电极和触控驱动电路之间传输触控信号。在Full in Cell面板中，公共电极可以作为触控电极。
申请内容
本申请提供了一种阵列基板、显示面板及显示装置。
第一方面，提供了一种阵列基板，所述阵列基板包括：
依次设置在衬底基板上的公共电极、钝化层和触控信号线，所述触控信号线用于将公共电极上加载的触控信号传输至触控驱动电路；
所述钝化层上设置有第一过孔；
所述触控信号线通过所述第一过孔与所述公共电极连接。
可选地，所述触控信号线与所述公共电极由同一种导电材料制成。或者，所述触控信号线与所述公共电极由同一种透明导电材料制成。
可选地，所述触控信号线为氧化铟锡图案，所述公共电极为氧化铟锡电极。
可选地，所述触控信号线为石墨烯图案，所述公共电极为石墨烯电极。
可选地，所述阵列基板还包括：设置在所述钝化层远离所述衬底基板一侧的像素电极，以及，设置在所述衬底基板与所述公共电极之间的薄膜晶体管；
所述像素电极与所述触控信号线同层设置且绝缘，且所述像素电极通过第 二过孔与所述薄膜晶体管的源极或漏极连接。
可选地，所述像素电极与所述触控信号线间隔设置。
可选地，所述像素电极为氧化铟锡电极或石墨烯电极。
可选地，所述第一过孔在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影不重叠。
可选地，所述所述公共电极和所述钝化层依次叠加设置，所述第二过孔依次贯穿所述钝化层和公共电极。
可选地，所述像素电极与所述触控信号线由同一种导电材料制成。
可选地，所述像素电极与所述触控信号线在一次构图工艺中形成。
可选地，所述阵列基板还包括：设置在所述衬底基板与所述公共电极之间的平坦层，所述平坦层的厚度大于所述钝化层的厚度。
可选地，所述阵列基板还包括：设置在所述衬底基板与所述公共电极之间的薄膜晶体管；所述薄膜晶体管包括依次设置在所述衬底基板上的有源层、栅绝缘层、栅极、层间介电层和源漏极图形，所述源漏极图形包括源极和漏极；
所述阵列基板还包括：依次设置在所述衬底基板和所述有源层之间的遮光层和缓冲层。
可选地，所述薄膜晶体管为低温多晶硅薄膜晶体管，所述有源层为多晶硅有源层。
第二方面，提供了一种显示面板，所述显示面板包括第一方面任一所述的阵列基板。
可选地，所述显示面板包括：阵列排布的多个像素组，每个像素组包括多个颜色不同的子像素，每个像素组中多个颜色不同的子像素沿第一方向依次排布，且所述多个像素组中子像素的排布顺序相同，所述第一方向包括：像素行所在的方向或像素列所在的方向；所述触控信号线在所述第一方向上，包括多个触控信号导线段；
在所述第一方向上，每相邻的两个像素组中，对于每相邻的两条触控信号导线段：
一条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素的颜色，与另一条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素中至少一个子像素的颜色不同。
可选地，所述显示面板包括：阵列排布的多个像素组，每个像素组包括多 个颜色不同的子像素，每个像素组中多个颜色不同的子像素沿第一方向依次排布，且所述多个像素组中子像素的排布顺序相同，所述第一方向包括：像素行所在的方向或像素列所在的方向；所述触控信号线在所述第一方向上包括多个触控信号导线段；所述像素组的个数大于或等于3；
在沿所述第一方向依次排布的每三个像素组中，对于沿所述第一方向依次排布的三条触控信号导线段：
第一条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素的颜色，第二条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素的颜色，以及，第三条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素的颜色均不同。
可选地，所述触控信号导线段在所述阵列基板上的正投影与所述子像素在所述阵列基板上的正投影不重叠。
可选地，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素。
第三方面，提供了一种显示装置，所述显示装置包括第二方面所述的显示面板。
附图说明
图1是本申请实施例提供的一种阵列基板的结构示意图；
图2是本申请实施例提供的另一种阵列基板的结构示意图；
图3是本申请实施例提供的又一种阵列基板的结构示意图；
图4是本申请实施例提供的一种阵列基板的制造方法的流程图；
图5是本申请实施例提供的一种在衬底基板上形成TFT后的结构示意图；
图6是本申请实施例提供的一种在在形成有TFT的衬底基板上形成平坦层图案后的结构示意图；
图7是本申请实施例提供的一种在形成有平坦层图案的衬底基板上形成公共电极图案后的结构示意图；
图8是本申请实施例提供的一种在形成有公共电极图案的衬底基板上形成钝化层图案后的结构示意图；
图9是本申请实施例提供的一种显示面板包括阵列排布的多个像素组的示意图；
图10是本申请实施例提供的一种显示面板包括阵列基板和彩膜基板的示意图；
图11是本申请实施例提供的一种显示面板中子像素、触控信号线和黑矩阵之间的位置示意图；
图12是相关技术中子像素、触控信号线和黑矩阵之间的位置示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，阵列基板通常包括：叠加设置的TFT、触控信号线、平坦层、公共电极、钝化层和像素电极。该触控信号线与该TFT中的源漏极图形同层设置，两者均由金属制成。且公共电极通过设置在平坦层中的过孔与该触控信号线连接，位于该过孔中的公共电极可视为公共电极和触控信号线之间的连接导线，该过孔中的公共电极的厚度可视为该连接导线的长度。
通过同一次构图工艺形成触控信号线与源漏极图形时，由于源漏极具有较大的厚度，使得触控信号线的厚度(在本次申请中也称为触控信号线的长度)也较大。由于电阻与导线的长度正相关，而触控信号线的厚度较大，因此，触控信号线电阻较大。且由于平坦层较厚，设置在平坦层中的过孔具有较大的孔深，使得过孔中的触控信号线具有较大的厚度，导致该过孔中由触控信号线充当的连接导线的电阻较大。并且，由于触控信号线的电阻和该连接导线的电阻是影响阵列基板的驱动电阻的主要因素，在该触控信号线的电阻和该过孔中的连接导线的电阻共同影响下，阵列基板的驱动电阻较大，进而导致驱动信号的衰减较大。
针对上述问题，本申请实施例提供了一种阵列基板，图1是本申请实施例提供的一种阵列基板的结构示意图，如图1所示，该阵列基板00可以包括：
依次设置在衬底基板001上的公共电极004、钝化层(英文：passivation layer；简称：PVX)005和触控信号线006。该触控信号线006用于将公共电极004上加载的触控信号传输至触控驱动电路。
其中，钝化层005上设置有第一过孔，触控信号线006通过该第一过孔与公共电极004连接。
相关技术中，触控信号线与TFT中的源漏极图形通过同一次构图工艺形成， 且源漏极图像具有较大的厚度，使得触控信号线也具有较大的厚度，由于电阻与导线的长度正相关，因此，导致触控信号线电阻较大。相对于相关技术，本申请实施例提供的阵列基板上的触控信号线006不再与TFT中的源漏极图形通过同一次构图工艺形成，因此，可以为该触控信号线006设置较小的厚度(例如：设置该触控信号线006的厚度相对于原有厚度减小了1/6)，以减小其电阻，进而减小阵列基板的驱动电阻。
综上所述，本申请实施例提供的阵列基板，通过在衬底基板上依次设置公共电极、钝化层和触控信号线，且钝化层上设置有第一过孔，使触控信号线通过该第一过孔与公共电极连接，相较于相关技术，由于该触控信号线的厚度不受源漏极图形的厚度的影响，使得该触控信号线具有较小的厚度，进而使得触控信号线具有较小的电阻，相应地，减小了阵列基板的驱动电阻，进而减小了阵列基板中驱动信号的衰减程度，继而有效地提高了阵列基板的驱动能力。
进一步地，请参考图2，该阵列基板00还可以包括：设置在衬底基板001与公共电极004之间的平坦层003。该平坦层003的厚度可以大于钝化层004的厚度。
由于平坦层003的厚度大于钝化层005的厚度，相较于相关技术，该设置在钝化层005上的第一过孔的孔深减小，使得设置在第一过孔中的触控信号线006具有较小的厚度(例如：该厚度相对相关技术减小了约1/20)，也即是，由该第一过孔中的触控信号线006所充当的连接导线具有较小的长度，且由于电阻与导线的长度正相关，使得该第一过孔中的触控信号线006具有较小的电阻，进一步减小了阵列基板的驱动电阻。
需要说明的是，请继续参考图2，该衬底基板001和平坦层003之间可以设置有TFT 002。其中，在应用了低温多晶硅(英文：Low Temperature Poly-silicon；简称：LTPS)技术的阵列基板上，该TFT 002可以为低温多晶硅TFT，该低温多晶硅TFT可以包括依次设置在衬底基板001上的多晶硅(英文：Poly-silicon；简称：P-SI)有源层0021、栅绝缘层(英文：Gate Insulator；简称：GI)0022、栅极0023、层间介电层(英文：inter-layer Dielectric；简称：ILD)0024和源漏极图形0025，源漏极图形0025可以包括源极0025a和漏极0025b，其结构示意图请继续参考图2。
可选地，请继续参考图2，阵列基板还可以包括：依次设置在衬底基板001和有源层0021之间的遮光(英文：Light Shield；简称：LS)层0026和缓冲层 (英文：buffer)0027等膜层，具体可以参考相关技术，在此不再赘述。
可选地，触控信号线可以为氧化铟锡(英文：Indium tin oxide；简称：ITO)图案或石墨烯图案，公共电极可以为ITO电极或石墨烯电极。其中，制成触控信号线和公共电极的材料可以相同，也即是，触控信号线与公共电极可以由同一种导电材料或同一种透明导电材料制成，例如：触控信号线可以为ITO图案，且公共电极可以为ITO电极；或者，触控信号线可以为石墨烯图案，且公共电极可以为石墨烯电极。或者，制成触控信号线和公共电极的材料也可以不同。
由于ITO和石墨烯均为透明材料，且金属钛和金属铝均为不透明材料，当触控信号线由ITO或石墨烯制成时，该触控信号线的结构相对于相关技术中触控信号线由钛、铝和钛制成的三层结构(即相关技术中的触控信号线由三个膜层叠加组成，该三个膜层分别由金属钛、金属铝和金属钛制成)，提高了阵列基板的透过率。并且，由于石墨烯具有较好的导电性能，当触控信号线为石墨烯图案，且公共电极为石墨烯电极时，其不仅能够提高阵列基板的透过率，还能减小阵列基板的驱动电阻。可选地，触控信号线也可以为其他导电性能更好的透明材料制成的图案，公共电极也可以为其他导电性能更好的透明材料制成的电极，本申请实施例对其不做具体限定。
需要说明的是，由于电流在同种材料中传输时受到的阻碍作用小于在不同种材料中传输时受到的阻碍作用，因此，当触控信号线和公共电极由同一种材料制成时，相对于触控信号线和公共电极由不同材料制成的实现方式，可以进一步减小阵列基板的驱动电阻。
可选地，请参考图3，阵列基板还可以包括：设置在钝化层005远离衬底基板001一侧的像素电极007，其中，像素电极007可以为ITO电极或石墨烯电极。当该像素电极007为ITO电极时，能够提高阵列基板的透过率。当像素电极007为石墨烯电极时，也能够相应地提高阵列基板的透过率且减小阵列基板的驱动电阻。
像素电极007与触控信号线006同层设置且绝缘，该像素电极007通过第二过孔008与TFT的源极0025a或漏极0025b连接。该像素电极007与触控信号线006绝缘的实现方式可以包括：像素电极007与触控信号线006间隔设置，例如：像素电极007与触控信号线006之间可以设置有间隙，该像素电极007与触控信号线006通过间隙实现绝缘；或者，像素电极007与触控信号线006之间设置有绝缘介质，像素电极007与触控信号线006通过绝缘介质实现绝缘。
并且，该第二过孔008在衬底基板上的正投影与第一过孔在衬底基板001上的正投影不重叠。第一过孔在衬底基板上的正投影与第二过孔在衬底基板上的正投影不重叠，能够保证像素电极和触控信号线绝缘，进而保证像素电极和公共电极绝缘。
进一步地，在本申请实施例中，平坦层003、公共电极004和钝化层005可依次叠加设置在衬底基板001上，该第二过孔008可以依次贯穿钝化层005、公共电极004和平坦层003，该第二过孔008的底部位于TFT 002的源极0025a或漏极0025b上方。
同时，当像素电极和触控信号线同层设置时，像素电极007与触控信号线006可以由同一种导电材料制成，此时，像素电极007与触控信号线006可以在一次构图工艺中形成，以简化阵列基板的制造工艺。例如：当两者材料相同时，两者能够采用同一张掩膜板形成。其中，通过同一次构图工艺形成像素电极007与触控信号线006是指：在钝化层远离衬底基板的整个表面上沉积一层具有一定厚度的导电材料，得到导电材料层后，在该导电材料层上涂覆一层具有一定厚度的光刻胶得到光刻胶层，采用一个掩膜版对光刻胶层进行曝光，使光刻胶层形成完全曝光区和至少两个非曝光区，之后采用显影工艺处理，使完全曝光区的光刻胶被完全去除，非曝光区的光刻胶全部保留，采用刻蚀工艺对导电材料层上完全曝光区对应的区域进行刻蚀，之后剥离非曝光区的光刻胶，以得到像素电极007与触控信号线006。
综上所述，本申请实施例提供的阵列基板，通过在衬底基板上依次设置平坦层、公共电极、钝化层和触控信号线，且钝化层上设置有第一过孔，使触控信号线通过该第一过孔与公共电极连接，相较于相关技术，由于该触控信号线的厚度不受源漏极图形的厚度的影响，且钝化层的厚度小于平坦层的厚度，使得该触控信号线具有较小的厚度，进而使得触控信号线具有较小的电阻，相应地，减小了阵列基板的驱动电阻，进而减小了阵列基板中驱动信号的衰减程度，继而有效地提高了阵列基板的驱动能力。
本申请实施例还提供了一种阵列基板的制造方法，如图4所示，该方法可以包括：
步骤301、在衬底基板上形成TFT。
其中，该TFF中的有源层可以由多晶硅材料制成，该TFT 002的结构示意 图请参考图5。
步骤302、在形成有TFT的衬底基板上形成平坦层图案。
该平坦层图案可以包括平坦层和平坦层过孔，该平坦层过孔位于TFT的源极或漏极上方，该平坦层过孔可以使平坦层图案下层的TFT中的源极或漏极露出。
本步骤结束时，衬底基板的结构可以如图6所示，其中，平坦层图案形成于源漏极图形0025的上方，平坦层图案包括平坦层003和平坦层过孔0031，源极0025a从平坦层过孔0031中露出。
步骤303、在形成有平坦层图案的衬底基板上形成公共电极图案。
该公共电极图案可以包括公共电极和公共电极过孔，该公共电极可以为ITO电极或石墨烯电极，该公共电极过孔与平坦层过孔连通。
本步骤结束时，衬底基板的结构可以如图7所示，其中，公共电极图案可以包括公共电极004和公共电极过孔0041，公共电极004形成于平坦层003上，公共电极过孔0041与平坦层过孔0031连通。
步骤304、在形成有公共电极图案的衬底基板上形成钝化层图案。
其中，该钝化层图案可以包括钝化层、第一钝化层过孔(即第一过孔)和第二钝化层过孔，该第二钝化层过孔通过公共电极过孔与平坦层过孔连通，该第二钝化层过孔、公共电极过孔与平坦层过孔共同组成了阵列基板上的第二过孔，且第一过孔在衬底基板上的正投影与第二过孔在衬底基板上的正投影不重叠，平坦层的厚度大于钝化层的厚度。
本步骤结束时，衬底基板的结构可以如图8所示，其中，钝化层图案可以包括钝化层005、第一钝化层过孔(即第一过孔)0051和第二钝化层过孔0052，钝化层005形成于公共电极004上，该第二钝化层过孔0052与公共电极过孔0041、平坦层过孔0031共同组成了阵列基板上的第二过孔008，且第一过孔0051在衬底基板001上的正投影(第一过孔0051对应的虚线)与第二过孔008在衬底基板008上的正投影(第二过孔008对应的虚线)不重叠，且平坦层003的厚度大于钝化层005的厚度。
步骤305、在形成有钝化层图案的衬底基板上形成像素电极和触控信号线。
其中，像素电极与触控信号线同层设置且绝缘，像素电极通过第二过孔与TFT的源极或漏极连接，触控信号线通过第一过孔与公共电极连接，在形成有钝化层图案的衬底基板上形成像素电极和触控信号线后的阵列基板的结构示意 图请参考图3。其中，可以通过间隔设置像素电极与触控信号线，使得两者绝缘。
可选地，像素电极和触控信号线可以由相同的材料制成，也可以由不同的材料制成，示例地，像素电极可以由ITO或石墨烯制成，触控信号线也可以由ITO或石墨烯制成。当像素电极和触控信号线由不同的材料制成时，两者可以依次形成在形成有钝化层图案的衬底基板上。当像素电极和触控信号线的材料由相同的材料制成时，像素电极和触控信号线可以采用同一张掩膜板形成，可以相应地简化阵列基板的制造工艺。
综上所述，本申请实施例提供的阵列基板的制造方法，通过在衬底基板上依次形成TFT、平坦层、公共电极、钝化层和触控信号线，且在钝化层上设置第一过孔，使触控信号线通过第一过孔与公共电极连接，相较于相关技术，由于该触控信号线的厚度不受源漏极图形的厚度的影响，且钝化层的厚度小于平坦层的厚度，使得该触控信号线具有较小的厚度，进而使得触控信号线具有较小的电阻，相应地，减小了阵列基板的驱动电阻，进而减小了阵列基板中驱动信号的衰减程度，继而有效地提高了阵列基板的驱动能力。
本申请还提供了一种显示面板，该显示面板可以包括图1至图3任一所示的阵列基板。
可选地，请参考图9，显示面板还可以包括：阵列排布的多个像素组M1，每个像素组M1中包括多个子像素M2(该图9中以该多个子像素包括红色子像素R，绿色子像素G和蓝色子像素B为例进行示意)，多个像素组中的多个子像素循环排列在显示面板中。也即是，显示面板包括：阵列排布的多个像素组M1，每个像素组M1包括多个颜色不同的子像素M2，每个像素组M1中多个颜色不同的子像素M2沿第一方向依次排布，且多个像素组中子像素的排布顺序相同，该第一方向可以包括：像素行所在的方向或像素列所在的方向，该像素行所在的方向与该像素列所在的方向垂直。如图9所示，每个像素组M1中多个颜色不同的子像素M2沿像素列所在的方向S1依次排布。
一般地，请参考图10，显示面板可以包括阵列基板00和彩膜基板10。该阵列基板00和该彩膜基板10之间可以设置有液晶(图10未示出)或发光层(图10未示出)。阵列基板00可以包括：TFT、平坦层、公共电极、钝化层、像素电极和触控信号线006等(为了便于观看，该图10中仅示出了阵列基板00中触控信号线006的设置位置)。彩膜基板10可以包括色阻层101和黑矩阵102， 色阻层101中包括多个彩色滤光片，例如：可以包括红色滤光片、绿色滤光片和蓝色滤光片。且显示面板中的子像素通常根据色阻层中滤光片的设置位置进行划分，例如：红色滤光片所在的子像素区域(即虚线所示区域)为红色子像素R，绿色滤光片所在的子像素区域为绿色子像素G，蓝色滤光片所在的子像素区域为蓝色子像素B。其中，每个子像素可以包括位于子像素区域内的TFT、平坦层、公共电极、钝化层、像素电极、液晶和彩色滤光片等。
每个像素组中设置一个触控信号线，且触控信号线在沿第一方向依次设置的每三个像素组中的位置不同。也即是，请参考图9，触控信号线006在第一方向上包括多个触控信号导线段。在第一方向上，每相邻的两个像素组M1中，对于每相邻的两条触控信号导线段：一条触控信号导线段在阵列基板上的正投影0061两侧直接相邻的两个子像素的颜色，与另一条触控信号导线段在阵列基板上的正投影0061两侧直接相邻的两个子像素中至少一个子像素的颜色不同。如图9所示，一条触控信号导线段在阵列基板上的正投影0061两侧直接相邻的两个子像素为绿色子像素和蓝色子像素，另一条触控信号导线段在阵列基板上的正投影0061两侧直接相邻的两个子像素为红色子像素和绿色子像素。
可选地，该触控信号导线段的延伸方向可以平行于栅线(gate线)的延伸方向。例如：请继续参考图9，假设栅线的延伸方向平行于像素行所在的方向S2，则该触控信号导线段的延伸方向也平行于像素行所在的方向S2。
需要说明的是，图9仅为每个像素组包括多个颜色不同的子像素的一种示意，不用于限制本申请。例如：每个像素组中还可以包括两个颜色的子像素、四个颜色的子像素或更多颜色的子像素，本申请施例对其不做具体限定。且本申请实施例对一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素的颜色，以及，另一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素的颜色也不做具体限定。例如：每个像素组包括三个颜色不同的子像素时，该三个颜色的子像素分别为第一颜色的子像素、第二颜色的子像素和第三颜色的子像素，在第一方向上，每相邻的两个像素组中，对于每相邻的两条触控信号导线段：该一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素可以分别为第一颜色的子像素和第二颜色的子像素，另一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素可以分别为第二颜色的子像素和第三颜色的子像素。或者，一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素可以分别为第一颜色的子像素和 第三颜色的子像素，另一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素可以分别为第二颜色的子像素和第三颜色的子像素。或者，一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素可以分别为第一颜色的子像素和第三颜色的子像素，另一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素可以分别为第二颜色的子像素和第一颜色的子像素。
进一步地，当每个像素组M1中包括N个颜色不同的子像素M2时，在沿第一方向依次排布的N个像素组M2中，对于沿第一方向依次排布的N条触控信号导线段：第一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素的颜色，第二条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素的颜色，……，以及，第N条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素的颜色均不同。
示例地，假设每个像素组M1中包括三个颜色不同的子像素，该三个颜色的子像素分别为第一颜色的子像素、第二颜色的子像素和第三颜色的子像素，在沿第一方向依次排布的每三个像素组中，对于沿该第一方向依次排布的三条触控信号导线段：第一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素可以分别为第一颜色的子像素和第二颜色的子像素，第二条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素可以分别为第二颜色的子像素和第三颜色的子像素，以及，第三条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素可以分别为第三颜色的子像素和第一颜色的子像素，也即是，该三条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素的颜色均不同。
每两个子像素之间设置有黑矩阵，该黑矩阵的横向尺寸为两个子像素之间的间距的宽度(或者，黑矩阵的横向尺寸与两个子像素之间的间距的宽度正相关)。子像素和触控信号线在阵列基板上的正投影0061的相对位置如图11虚线框A1中所示，子像素和黑矩阵BM之间的相对位置如图11虚线框A2中所示，从该图11可以看出，相对于未设置有触控信号线的两个子像素之间的黑矩阵的图形尺寸，设置有触控信号线的两个子像素之间的黑矩阵的图形尺寸较大。也即是，当两个子像素之间设置有触控信号线时，设置在该两个子像素之间的黑矩阵具有较大的尺寸，当两个子像素之间未设置有触控信号线时，设置在该两个子像素之间的黑矩阵具有较小的尺寸。
并且，每个像素组对应设置一个触控信号线，能避免因触控信号线太少而导致接触电阻大，继而出现触控电极接触不良的问题，或者，能避免因触控信号线太多而出现触控信号线与第一过孔匹配不良的问题，也即是，避免触控信号线与公共电极接触不良的问题。
相关技术中，显示面板包括多个像素组，每个像素组中也包括多个子像素，多个子像素可以为红色子像素R，绿色子像素G和蓝色子像素B，多个像素组中的多个子像素循环排列在显示面板中。每个像素组中设置一个触控信号线，且触控信号线在每个像素组中的位置相同，且每两个子像素之间也设置有黑矩阵。也即是，触控信号线的多个导电线段在阵列基板上的正投影两侧直接相邻的两个子像素的颜色均相同，例如：在每个子像素组中，导电线段在阵列基板上的正投影两侧直接相邻的两个子像素均分别为蓝色子像素和红色子像素。子像素和阵列基板上的触控信号线TPM的位置如图12虚线框C中所示，子像素和黑矩阵BM之间的位置如图12虚线框D中所示。
当显示面板中存在静电时，黑矩阵中会累积静电，该累积的静电会驱动其对应的液晶分子进行偏转。其中，当黑矩阵的图形尺寸越大时，该黑矩阵上会累积越多的静电，且黑矩阵上累积的静电越多，该静电能够控制液晶分子越长时间地偏转。因此，图形尺寸较大的黑矩阵相对于图形尺寸较小的黑矩阵，能够使其对应的液晶分子更长时间地偏转。相应的，当较小尺寸的黑矩阵中未累积静电，且较大尺寸的黑矩阵中仍累积有静电时，该较小尺寸的黑矩阵附近的液晶不再偏转，该较大尺寸的黑矩阵附近的液晶持续偏转，使得该黑矩阵两侧直接相邻的两个子像素持续发光，进而使显示面板相应位置处显示的颜色受到该尺寸较大的黑矩阵两侧直接相邻的两个子像素的颜色影响。
相关技术中，由于触控信号线在每个像素组中的位置相同，即在多个像素组中，触控信号线的多个导电线段在阵列基板上的正投影两侧直接相邻的两个子像素的颜色均相同。相应的，在显示面板在多个像素组中，图形尺寸较大的黑矩阵两侧直接相邻的两个子像素的颜色相同。所以当较小尺寸的黑矩阵附近的液晶不再偏转，较大尺寸的黑矩阵附近的液晶持续偏转时，整个显示面板显示的颜色会呈现为该尺寸较大的黑矩阵两侧直接相邻的两个子像素的颜色叠加而成的颜色，例如：假设触控信号线在每个像素组的蓝色子像素和红色子像素之间(该触控信号线的位置请参考图12所示的位置)，也即是，在每个像素组中，触控信号线在阵列基板上的正投影两侧直接相邻的两个子像素均分别为蓝 色子像素和红色子像素，则整个显示面板显示的颜色会受到蓝色和红色叠加而成的紫色的影响，即显示面板显示的颜色呈现为紫色，导致显示面板出现显示颜色异常的情况，继而使显示面板无法通过静电放电(英文：Electro-Static discharge；缩写：ESD)测试。
而本申请实施例提供的显示面板，由于触控信号线在相邻设置的每三个像素组中的位置不同，即在沿第一方向依次排布的每三个像素组中，对于沿第一方向依次排布的三条触控信号导线段：该三条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素的颜色均不同。当较小尺寸的黑矩阵附近的液晶不再偏转，较大尺寸的黑矩阵附近的液晶持续偏转时，该每三个像素组中对应位置处黑矩阵对显示面板显示颜色的影响为每三个像素组中图像尺寸较大的黑矩阵两侧直接相邻的两个子像素的颜色的叠加。例如：假设触控信号线在相邻设置的每三个像素组中的位置为图11所示的位置，由于触控信号线在该相邻设置的三个像素组中的位置不同，则显示面板在相应位置处显示的颜色即为该三个像素组尺寸较大的黑矩阵两侧直接相邻的两个子像素的颜色的叠加。也即是，请继续参考图11，该显示面板包括多个阵列排布的像素组，该多个像素组的个数大于或等于3，对于该多个像素组，在沿第一方向依次排布的每三个像素组中，第一条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素分别为绿色子像素和蓝色子像素，则该第一条触控信号导线段所在的像素组所显示的颜色为绿色和蓝色的叠加；第二条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素分别为红色子像素和绿色子像素，则该第二条触控信号导线段所在的像素组所显示的颜色为红色和绿色的叠加；第三条触控信号导线段在阵列基板上的正投影两侧直接相邻的两个子像素分别为蓝色子像素和红色子像素，则该第三条触控信号导线段所在的像素组所显示的颜色为蓝色和红色的叠加。并且，由于红绿蓝三种颜色的叠加颜色为白色，则当较小尺寸的黑矩阵附近的液晶不再偏转，较大尺寸的黑矩阵附近的液晶持续偏转时，整个显示面板显示的颜色会呈现为该红绿蓝叠加而成的白色，使得显示面板显示的颜色不会受到该尺寸较大的黑矩阵两侧子像素的颜色的影响，也即是，相对于相关技术，本申请实施例提供的显示面板能够避免显示面板出现显示颜色异常的情况。
综上所述，本申请实施例提供的显示面板，通过在衬底基板上依次设置平坦层、公共电极、钝化层和触控信号线，且钝化层上设置第一过孔，使触控信 号线通过第一过孔与公共电极连接，由于平坦层的厚度大于钝化层的厚度，使得该触控信号线具有较小的厚度，使得触控信号线具有较小的电阻，相应地，减小了显示面板中阵列基板的驱动电阻，进而减小了阵列基板中驱动信号的衰减程度，继而有效地提高了阵列基板的驱动能力。并且，通过设置触控信号线在相邻设置的每三个像素组中的位置不同，避免了显示面板出现显示颜色异常的情况。
此外，本申请还提供一种显示装置，该显示装置包括上述显示面板，该显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本申请的较佳实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种阵列基板，所述阵列基板包括：
    依次设置在衬底基板上的公共电极、钝化层和触控信号线，所述触控信号线用于将公共电极上加载的触控信号传输至触控驱动电路；
    所述钝化层上设置有第一过孔；
    所述触控信号线通过所述第一过孔与所述公共电极连接。
  2. 根据权利要求1所述的阵列基板，所述触控信号线与所述公共电极由同一种导电材料制成；
    或者，所述触控信号线与所述公共电极由同一种透明导电材料制成。
  3. 根据权利要求1所述的阵列基板，
    所述触控信号线为氧化铟锡图案，所述公共电极为氧化铟锡电极。
  4. 根据权利要求1所述的阵列基板，
    所述触控信号线为石墨烯图案，所述公共电极为石墨烯电极。
  5. 根据权利要求1至4任一所述的阵列基板，所述阵列基板还包括：设置在所述钝化层远离所述衬底基板一侧的像素电极，以及，设置在所述衬底基板与所述公共电极之间的薄膜晶体管；
    所述像素电极与所述触控信号线同层设置且绝缘，且所述像素电极通过第二过孔与所述薄膜晶体管的源极或漏极连接。
  6. 根据权利要求5所述的阵列基板，所述像素电极与所述触控信号线间隔设置。
  7. 根据权利要求5所述的阵列基板，
    所述像素电极为氧化铟锡电极或石墨烯电极。
  8. 根据权利要求5所述的阵列基板，
    所述第一过孔在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影不重叠。
  9. 根据权利要求8所述的阵列基板，所述公共电极和所述钝化层依次叠加设置，所述第二过孔依次贯穿所述钝化层和公共电极。
  10. 根据权利要求5所述的阵列基板，所述像素电极与所述触控信号线由同一种导电材料制成。
  11. 根据权利要求5所述的阵列基板，所述像素电极与所述触控信号线在一次构图工艺中形成。
  12. 根据权利要求1至4任一所述的阵列基板，所述阵列基板还包括：设置在所述衬底基板与所述公共电极之间的平坦层，所述平坦层的厚度大于所述钝化层的厚度。
  13. 根据权利要求1至4任一所述的阵列基板，所述阵列基板还包括：设置在所述衬底基板与所述公共电极之间的薄膜晶体管；
    所述薄膜晶体管包括依次设置在所述衬底基板上的有源层、栅绝缘层、栅极、层间介电层和源漏极图形，所述源漏极图形包括源极和漏极；
    所述阵列基板还包括：依次设置在所述衬底基板和所述有源层之间的遮光层和缓冲层。
  14. 根据权利要求13所述的阵列基板，所述薄膜晶体管为低温多晶硅薄膜晶体管，所述有源层为多晶硅有源层。
  15. 一种显示面板，所述显示面板包括权利要求1至14任一所述的阵列基板。
  16. 根据权利要求15所述的显示面板，所述显示面板包括：阵列排布的多个像素组，每个像素组包括多个颜色不同的子像素，每个像素组中多个颜色不 同的子像素沿第一方向依次排布，且所述多个像素组中子像素的排布顺序相同，所述第一方向包括：像素行所在的方向或像素列所在的方向；所述触控信号线在所述第一方向上，包括多个触控信号导线段；
    在所述第一方向上，每相邻的两个像素组中，对于每相邻的两条触控信号导线段：
    一条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素的颜色，与另一条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素中至少一个子像素的颜色不同。
  17. 根据权利要求15所述的显示面板，所述显示面板包括：阵列排布的多个像素组，每个像素组包括多个颜色不同的子像素，每个像素组中多个颜色不同的子像素沿第一方向依次排布，且所述多个像素组中子像素的排布顺序相同，所述第一方向包括：像素行所在的方向或像素列所在的方向；所述触控信号线在所述第一方向上包括多个触控信号导线段；所述像素组的个数大于或等于3；
    在沿所述第一方向依次排布的每三个像素组中，对于沿所述第一方向依次排布的三条触控信号导线段：
    第一条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素的颜色，第二条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素的颜色，以及，第三条触控信号导线段在所述阵列基板上的正投影两侧直接相邻的两个子像素的颜色均不同。
  18. 根据权利要求16或17所述的显示面板，所述触控信号导线段在所述阵列基板上的正投影与所述子像素在所述阵列基板上的正投影不重叠。
  19. 根据权利要求16或17所述的显示面板，所述多个颜色不同的子像素包括红色子像素、绿色子像素和蓝色子像素。
  20. 一种显示装置，所述显示装置包括权利要求15至19任一所述的显示面板。
PCT/CN2018/089521 2017-06-01 2018-06-01 阵列基板、显示面板及显示装置 Ceased WO2018219345A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201720629918.1 2017-06-01
CN201720629918.1U CN206741462U (zh) 2017-06-01 2017-06-01 阵列基板、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2018219345A1 true WO2018219345A1 (zh) 2018-12-06

Family

ID=60569003

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/089521 Ceased WO2018219345A1 (zh) 2017-06-01 2018-06-01 阵列基板、显示面板及显示装置

Country Status (2)

Country Link
CN (1) CN206741462U (zh)
WO (1) WO2018219345A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN206741462U (zh) * 2017-06-01 2017-12-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN109671726B (zh) 2019-01-04 2021-01-26 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、显示装置
CN112558800B (zh) * 2019-09-25 2024-01-23 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105573549A (zh) * 2015-12-08 2016-05-11 上海天马微电子有限公司 阵列基板、触控屏和触控显示装置及其制作方法
CN106773221A (zh) * 2017-02-17 2017-05-31 武汉华星光电技术有限公司 阵列基板及其制作方法与In Cell触控显示面板
CN206741462U (zh) * 2017-06-01 2017-12-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105573549A (zh) * 2015-12-08 2016-05-11 上海天马微电子有限公司 阵列基板、触控屏和触控显示装置及其制作方法
CN106773221A (zh) * 2017-02-17 2017-05-31 武汉华星光电技术有限公司 阵列基板及其制作方法与In Cell触控显示面板
CN206741462U (zh) * 2017-06-01 2017-12-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

Also Published As

Publication number Publication date
CN206741462U (zh) 2017-12-12

Similar Documents

Publication Publication Date Title
CN106873212B (zh) 包括盒内式触摸板的背板基板、液晶显示装置及制造方法
US8692756B2 (en) Liquid crystal display device and method for manufacturing same
US9791733B2 (en) Array substrate, manufacture method thereof, and display device
WO2019196632A1 (zh) 阵列基板及其制备方法、显示面板、显示装置
WO2014190727A1 (zh) 阵列基板及其制造方法、显示装置
WO2017004986A1 (zh) 触控显示面板及其制作方法、触控显示装置
US11233106B2 (en) Array substrate, display apparatus, and method of fabricating array substrate
JP2004109248A (ja) 液晶表示装置及びその製造方法
KR101622655B1 (ko) 액정 표시 장치 및 이의 제조 방법
US11758770B2 (en) Display panel and display device with pixel electrode overlapping transparent wires configured to reduce laser-etching damage
CN115206253A (zh) 一种显示基板和显示装置
US10606388B2 (en) Array substrate, manufacturing method thereof and touch display panel
CN108490666B (zh) 显示装置及其阵列基板
US11563068B2 (en) Substantially transparent display substrate, substantially transparent display apparatus, and method of fabricating substantially transparent display substrate
WO2017219702A1 (zh) 一种显示基板、其制作方法及显示装置
CN109270754B (zh) 阵列基板和显示装置
CN104701302A (zh) 阵列基板及其制作方法以及显示装置
US20210303093A1 (en) Array substrate and method for manufacturing same, and display device
CN105448935A (zh) 一种阵列基板及其制作方法、显示装置
JP6881981B2 (ja) アレイ基板、表示装置及びアレイ基板の製造方法
WO2018219345A1 (zh) 阵列基板、显示面板及显示装置
WO2022222404A1 (zh) 阵列基板及其制备方法、显示面板、显示装置
CN202533686U (zh) 一种阵列基板及显示设备
CN106098709A (zh) 阵列基板、显示装置
CN109976047B (zh) 触控电极结构、触控基板及制备方法、显示面板及装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18808835

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 19/05/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18808835

Country of ref document: EP

Kind code of ref document: A1