WO2018219345A1 - Substrat de réseau, panneau d'affichage et dispositif d'affichage - Google Patents

Substrat de réseau, panneau d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2018219345A1
WO2018219345A1 PCT/CN2018/089521 CN2018089521W WO2018219345A1 WO 2018219345 A1 WO2018219345 A1 WO 2018219345A1 CN 2018089521 W CN2018089521 W CN 2018089521W WO 2018219345 A1 WO2018219345 A1 WO 2018219345A1
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WIPO (PCT)
Prior art keywords
touch signal
array substrate
sub
pixel
signal line
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PCT/CN2018/089521
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English (en)
Chinese (zh)
Inventor
霍培荣
王志强
钟德龙
邱亚栋
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2018219345A1 publication Critical patent/WO2018219345A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • the array substrate of the in-cell touch display (English: Full in cell) panel generally includes: a stacked thin film transistor (English: Thin Film Transistor; abbreviated as: TFT), a touch signal line, a flat layer, a common electrode, and a passivation Layer and pixel electrodes.
  • the touch signal lines are respectively connected to the touch electrodes and the touch driving circuit, and are used for transmitting touch signals between the touch electrodes and the touch driving circuits.
  • the common electrode can be used as a touch electrode.
  • the application provides an array substrate, a display panel and a display device.
  • an array substrate comprising:
  • the common electrode, the passivation layer and the touch signal line are sequentially disposed on the base substrate, and the touch signal line is configured to transmit the touch signal loaded on the common electrode to the touch driving circuit;
  • the passivation layer is provided with a first via hole
  • the touch signal line is connected to the common electrode through the first via.
  • the touch signal line and the common electrode are made of the same conductive material.
  • the touch signal line and the common electrode are made of the same transparent conductive material.
  • the touch signal line is an indium tin oxide pattern
  • the common electrode is an indium tin oxide electrode
  • the touch signal line is a graphene pattern
  • the common electrode is a graphene electrode
  • the array substrate further includes: a pixel electrode disposed on a side of the passivation layer away from the substrate substrate, and a thin film transistor disposed between the substrate substrate and the common electrode;
  • the pixel electrode is disposed in the same layer and insulated from the touch signal line, and the pixel electrode is connected to a source or a drain of the thin film transistor through a second via.
  • the pixel electrode is spaced apart from the touch signal line.
  • the pixel electrode is an indium tin oxide electrode or a graphene electrode.
  • an orthographic projection of the first via on the substrate substrate does not overlap with an orthographic projection of the second via on the substrate.
  • the common electrode and the passivation layer are sequentially stacked, and the second via hole sequentially penetrates the passivation layer and the common electrode.
  • the pixel electrode and the touch signal line are made of the same conductive material.
  • the pixel electrode and the touch signal line are formed in a patterning process.
  • the array substrate further includes: a flat layer disposed between the base substrate and the common electrode, the flat layer having a thickness greater than a thickness of the passivation layer.
  • the array substrate further includes: a thin film transistor disposed between the base substrate and the common electrode; the thin film transistor includes an active layer, a gate insulation sequentially disposed on the base substrate a layer, a gate, an interlayer dielectric layer, and a source/drain pattern, the source and drain patterns including a source and a drain;
  • the array substrate further includes: a light shielding layer and a buffer layer sequentially disposed between the base substrate and the active layer.
  • the thin film transistor is a low temperature polysilicon thin film transistor
  • the active layer is a polysilicon active layer
  • a display panel comprising the array substrate of any of the first aspects.
  • the display panel includes: a plurality of pixel groups arranged in an array, each pixel group includes a plurality of sub-pixels having different colors, and a plurality of sub-pixels of different colors in each pixel group are sequentially arranged in the first direction.
  • the arrangement of the sub-pixels in the plurality of pixel groups is the same, the first direction includes: a direction in which the pixel row is located or a direction in which the pixel column is located; and the touch signal line is in the first direction , including a plurality of touch signal wire segments;
  • the color of two sub-pixels directly adjacent to each other on the orthographic projection of the touch signal wire segment on the array substrate is directly adjacent to the two sides of the orthographic projection of the other touch signal wire segment on the array substrate At least one of the two sub-pixels has a different color.
  • the display panel includes: a plurality of pixel groups arranged in an array, each pixel group includes a plurality of sub-pixels having different colors, and a plurality of sub-pixels of different colors in each pixel group are sequentially arranged in the first direction.
  • the arrangement of the sub-pixels in the plurality of pixel groups is the same, the first direction includes: a direction in which the pixel row is located or a direction in which the pixel column is located; and the touch signal line is in the first direction
  • the plurality of touch signal wire segments are included; the number of the pixel groups is greater than or equal to 3;
  • the first touch signal wire segments are directly adjacent to the two sub-pixels on both sides of the front projection on the array substrate, and the second touch signal wire segments are directly on both sides of the orthographic projection on the array substrate.
  • the color of the two sub-pixels adjacent to each other, and the color of the two sub-pixels directly adjacent to each other on both sides of the orthographic projection of the third touch signal wire segment on the array substrate are different.
  • the orthographic projection of the touch signal wire segments on the array substrate does not overlap with the orthographic projection of the sub-pixels on the array substrate.
  • the plurality of sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • a display device comprising the display panel of the second aspect.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of still another array substrate provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application.
  • FIG. 5 is a schematic structural view of a TFT after forming a TFT on a substrate
  • FIG. 6 is a schematic structural diagram of a flat layer pattern formed on a substrate on which a TFT is formed according to an embodiment of the present application
  • FIG. 7 is a schematic structural view of a common electrode pattern formed on a base substrate on which a flat layer pattern is formed according to an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram of a passivation layer pattern formed on a base substrate on which a common electrode pattern is formed according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a display panel including a plurality of pixel groups arranged in an array according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a display panel including an array substrate and a color filter substrate according to an embodiment of the present application
  • FIG. 11 is a schematic diagram of a position between a sub-pixel, a touch signal line, and a black matrix in a display panel according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram showing the position between a sub-pixel, a touch signal line, and a black matrix in the related art.
  • the array substrate generally includes: a stacked TFT, a touch signal line, a flat layer, a common electrode, a passivation layer, and a pixel electrode.
  • the touch signal line is disposed in the same layer as the source and drain patterns in the TFT, and both are made of metal.
  • the common electrode is connected to the touch signal line through a via hole disposed in the flat layer, and the common electrode located in the via hole can be regarded as a connection wire between the common electrode and the touch signal line, and the common in the via hole
  • the thickness of the electrode can be regarded as the length of the connecting wire.
  • the thickness of the touch signal line (also referred to as the length of the touch signal line in this application) is due to the large thickness of the source and drain electrodes. Also larger. Since the resistance is positively correlated with the length of the wire, and the thickness of the touch signal line is large, the resistance of the touch signal line is large. And because the flat layer is thicker, the via hole disposed in the flat layer has a larger hole depth, so that the touch signal line in the via hole has a larger thickness, resulting in a connection in the via hole by the touch signal line. The resistance of the wire is large.
  • the array substrate is affected by the resistance of the touch signal line and the resistance of the connecting wire in the via hole.
  • the driving resistance is large, which leads to a large attenuation of the driving signal.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate 00 may include:
  • the common electrode 004, the passivation layer (PVX) 005, and the touch signal line 006 are sequentially disposed on the base substrate 001.
  • the touch signal line 006 is used to transmit the touch signal loaded on the common electrode 004 to the touch driving circuit.
  • the first via is disposed on the passivation layer 005, and the touch signal line 006 is connected to the common electrode 004 through the first via.
  • the touch signal line and the source and drain patterns in the TFT are formed by the same patterning process, and the source and drain images have a large thickness, so that the touch signal line also has a large thickness, due to the resistance and the wire.
  • the length is positively correlated, thus causing a large resistance of the touch signal line.
  • the touch signal line 006 on the array substrate provided by the embodiment of the present application is no longer formed by the same patterning process as the source drain pattern in the TFT. Therefore, the touch signal line 006 can be set smaller.
  • the thickness (for example, the thickness of the touch signal line 006 is reduced by 1/6 relative to the original thickness) to reduce the resistance thereof, thereby reducing the driving resistance of the array substrate.
  • the common electrode, the passivation layer, and the touch signal line are sequentially disposed on the base substrate, and the first via hole is disposed on the passivation layer to make the touch signal
  • the line is connected to the common electrode through the first via hole.
  • the thickness of the touch signal line is not affected by the thickness of the source/drain pattern, so that the touch signal line has a small thickness.
  • the touch signal line has a small resistance, and accordingly, the driving resistance of the array substrate is reduced, thereby reducing the attenuation degree of the driving signal in the array substrate, and then effectively improving the driving capability of the array substrate.
  • the array substrate 00 may further include: a flat layer 003 disposed between the base substrate 001 and the common electrode 004.
  • the thickness of the flat layer 003 may be greater than the thickness of the passivation layer 004.
  • the hole depth of the first via disposed on the passivation layer 005 is reduced compared to the related art, so that the touch disposed in the first via hole
  • the signal line 006 has a small thickness (for example, the thickness is reduced by about 1/20 with respect to the related art), that is, the connecting wire served by the touch signal line 006 in the first via hole has a small thickness.
  • the length, and since the resistance is positively correlated with the length of the wire, the touch signal line 006 in the first via has a smaller resistance, further reducing the driving resistance of the array substrate.
  • a TFT 002 may be disposed between the base substrate 001 and the flat layer 003.
  • the TFT 002 may be a low temperature polysilicon TFT, and the low temperature polysilicon TFT may be sequentially disposed on the substrate 001, on the array substrate to which the Low Temperature Poly-silicon (LTPS) technology is applied.
  • LTPS Low Temperature Poly-silicon
  • Polysilicon (English: Poly-silicon; abbreviation: P-SI) active layer 0021, gate insulating layer (English: Gate Insulator; GI) 0022, gate 0023, interlayer dielectric layer (English: inter-layer Dielectric) Abbreviation: ILD) 0024 and source drain pattern 0025, source drain pattern 0025 can include source 0025a and drain 0025b, and a schematic diagram of the structure thereof will continue to refer to FIG.
  • P-SI gate insulating layer
  • GI Gate Insulator
  • ILD interlayer dielectric layer
  • source drain pattern 0025 can include source 0025a and drain 0025b, and a schematic diagram of the structure thereof will continue to refer to FIG.
  • the array substrate may further include: a light shielding (English: Light Shield; LS) layer 0026 and a buffer layer disposed between the base substrate 001 and the active layer 0021.
  • a light shielding (English: Light Shield; LS) layer 0026 and a buffer layer disposed between the base substrate 001 and the active layer 0021.
  • the touch signal line may be an Indium tin oxide (ITO) pattern or a graphene pattern
  • the common electrode may be an ITO electrode or a graphene electrode.
  • the material of the touch signal line and the common electrode may be the same, that is, the touch signal line and the common electrode may be made of the same conductive material or the same transparent conductive material.
  • the touch signal line may be The ITO pattern, and the common electrode may be an ITO electrode; or the touch signal line may be a graphene pattern, and the common electrode may be a graphene electrode.
  • the materials from which the touch signal lines and the common electrodes are made may be different.
  • the touch signal line is made of ITO or graphene
  • the structure of the touch signal line is relative to the touch signal of the related art.
  • the three-layer structure in which the wire is made of titanium, aluminum, and titanium that is, the touch signal line in the related art is composed of three film layers, which are respectively made of titanium metal, aluminum metal, and titanium metal).
  • the transmittance of the array substrate is improved.
  • graphene has good electrical conductivity, when the touch signal line is a graphene pattern and the common electrode is a graphene electrode, it can not only improve the transmittance of the array substrate, but also reduce the driving of the array substrate. resistance.
  • the touch signal line can also be a pattern made of other transparent materials with better conductivity
  • the common electrode can also be an electrode made of other transparent materials with better conductivity. Specifically limited.
  • the touch signal line and the common electrode are made of the same material.
  • the implementation of the touch signal line and the common electrode made of different materials can further reduce the driving resistance of the array substrate.
  • the array substrate may further include: a pixel electrode 007 disposed on a side of the passivation layer 005 away from the substrate 001, wherein the pixel electrode 007 may be an ITO electrode or a graphene electrode.
  • the pixel electrode 007 is an ITO electrode
  • the transmittance of the array substrate can be improved.
  • the pixel electrode 007 is a graphene electrode
  • the transmittance of the array substrate can be increased correspondingly and the driving resistance of the array substrate can be reduced.
  • the pixel electrode 007 is disposed in the same layer and insulated from the touch signal line 006.
  • the pixel electrode 007 is connected to the source 0025a or the drain 0025b of the TFT through the second via 008.
  • the pixel electrode 007 is insulated from the touch signal line 006.
  • the pixel electrode 007 is spaced apart from the touch signal line 006. For example, a gap may be disposed between the pixel electrode 007 and the touch signal line 006.
  • 007 and the touch signal line 006 are insulated by a gap; or an insulating medium is disposed between the pixel electrode 007 and the touch signal line 006, and the pixel electrode 007 and the touch signal line 006 are insulated by an insulating medium.
  • the orthographic projection of the second via 008 on the substrate substrate does not overlap with the orthographic projection of the first via on the substrate 001.
  • the orthographic projection of the first via on the base substrate does not overlap with the orthographic projection of the second via on the substrate, and the pixel electrode and the touch signal line can be insulated, thereby ensuring insulation between the pixel electrode and the common electrode.
  • the flat layer 003, the common electrode 004, and the passivation layer 005 may be sequentially stacked on the base substrate 001, and the second via 008 may sequentially pass through the passivation layer 005 and the common electrode 004. And the flat layer 003, the bottom of the second via 008 is located above the source 0025a or the drain 0025b of the TFT 002.
  • the pixel electrode 007 and the touch signal line 006 can be made of the same conductive material.
  • the pixel electrode 007 and the touch signal line 006 can be in one patterning process. Formed in order to simplify the manufacturing process of the array substrate. For example, when the materials are the same, both can be formed using the same mask.
  • the forming the pixel electrode 007 and the touch signal line 006 by the same patterning process means: depositing a conductive material having a certain thickness on the entire surface of the passivation layer away from the substrate substrate, and obtaining a conductive material layer.
  • a layer of photoresist having a certain thickness is coated on the conductive material layer to obtain a photoresist layer, and the photoresist layer is exposed by a mask to form a fully exposed region and at least two non-exposed regions. Then, the development process is used to completely remove the photoresist in the completely exposed region, and the photoresist in the non-exposed region is completely retained, and the region corresponding to the completely exposed region on the conductive material layer is etched by an etching process, and then stripped. The photoresist in the non-exposed area is used to obtain the pixel electrode 007 and the touch signal line 006.
  • the array substrate provided by the embodiment of the present invention has a flat layer, a common electrode, a passivation layer, and a touch signal line disposed on the substrate, and a first via hole is disposed on the passivation layer.
  • the touch signal line is connected to the common electrode through the first via hole.
  • the thickness of the touch signal line is not affected by the thickness of the source/drain pattern, and the thickness of the passivation layer is smaller than that of the flat layer.
  • the thickness of the touch signal line has a small thickness, so that the touch signal line has a small resistance, correspondingly, the driving resistance of the array substrate is reduced, thereby reducing the attenuation degree of the driving signal in the array substrate. , in turn, effectively improves the driving capability of the array substrate.
  • the embodiment of the present application further provides a method for manufacturing an array substrate. As shown in FIG. 4, the method may include:
  • Step 301 forming a TFT on the base substrate.
  • the active layer in the TFF may be made of a polysilicon material, and the structure of the TFT 002 is shown in FIG.
  • Step 302 forming a flat layer pattern on the base substrate on which the TFT is formed.
  • the flat layer pattern may include a flat layer via hole and a flat layer via hole located above a source or a drain of the TFT, the flat layer via hole may expose a source or a drain in the TFT of the lower layer of the flat layer pattern .
  • the structure of the base substrate can be as shown in FIG. 6, wherein a flat layer pattern is formed over the source drain pattern 0025, and the flat layer pattern includes a flat layer 003 and a flat layer via 0031, and the source 0025a is The flat layer is exposed in the via hole 0031.
  • Step 303 forming a common electrode pattern on the base substrate on which the flat layer pattern is formed.
  • the common electrode pattern may include a common electrode and a common electrode via, and the common electrode may be an ITO electrode or a graphene electrode, and the common electrode via is in communication with the flat layer via.
  • the structure of the base substrate can be as shown in FIG. 7, wherein the common electrode pattern can include a common electrode 004 and a common electrode via 0041, the common electrode 004 is formed on the flat layer 003, and the common electrode via 0041 is The flat layer vias 0031 are in communication.
  • Step 304 forming a passivation layer pattern on the base substrate on which the common electrode pattern is formed.
  • the passivation layer pattern may include a passivation layer, a first passivation layer via (ie, a first via) and a second passivation via, the second passivation via passing through the common electrode via
  • the planarization layer is connected to the via hole, and the second passivation layer via hole, the common electrode via hole and the flat layer via hole together form a second via hole on the array substrate, and the orthographic projection of the first via hole on the substrate substrate.
  • the orthographic projection of the second via holes on the base substrate does not overlap, and the thickness of the flat layer is greater than the thickness of the passivation layer.
  • the structure of the base substrate can be as shown in FIG. 8, wherein the passivation layer pattern can include a passivation layer 005, a first passivation layer via (ie, a first via) 0051, and a second passivation.
  • the via layer is formed on the common electrode 004.
  • the second passivation layer via 0052 and the common electrode via 0041 and the flat layer via 0031 together form a second via 008 on the array substrate.
  • the orthographic projection of the first via 0051 on the substrate 001 (the dotted line corresponding to the first via 0051) and the orthographic projection of the second via 008 on the substrate 008 (the dotted line corresponding to the second via 008) Do not overlap, and the thickness of the flat layer 003 is greater than the thickness of the passivation layer 005.
  • Step 305 forming a pixel electrode and a touch signal line on the base substrate on which the passivation layer pattern is formed.
  • the pixel electrode is disposed in the same layer and insulated from the touch signal line, and the pixel electrode is connected to the source or the drain of the TFT through the second via hole, and the touch signal line is connected to the common electrode through the first via hole, and is formed in a blunt manner.
  • FIG. 3 for a schematic diagram of the structure of the array substrate on which the pixel electrode and the touch signal line are formed on the substrate of the layered pattern. Wherein, the pixel electrode and the touch signal line can be arranged at intervals to insulate the two.
  • the pixel electrode and the touch signal line may be made of the same material or different materials.
  • the pixel electrode may be made of ITO or graphene, and the touch signal line may also be made of ITO. Or made of graphene.
  • the pixel electrode and the touch signal line are made of different materials, both may be sequentially formed on the base substrate on which the passivation layer pattern is formed.
  • the material of the pixel electrode and the touch signal line are made of the same material, the pixel electrode and the touch signal line can be formed by the same mask, and the manufacturing process of the array substrate can be simplified accordingly.
  • the method for fabricating an array substrate sequentially forms a TFT, a flat layer, a common electrode, a passivation layer, and a touch signal line on the substrate, and the first layer is disposed on the passivation layer.
  • a via hole connects the touch signal line to the common electrode through the first via hole, and the thickness of the touch signal line is not affected by the thickness of the source/drain pattern, and the thickness of the passivation layer is compared with the related art.
  • the thickness of the flat layer is smaller than that of the flat layer, so that the touch signal line has a small resistance, and accordingly, the driving resistance of the array substrate is reduced, thereby reducing the driving in the array substrate.
  • the degree of attenuation of the signal effectively increases the drive capability of the array substrate.
  • the present application also provides a display panel, which may include the array substrate shown in any of FIGS. 1 to 3.
  • the display panel may further include: a plurality of pixel groups M1 arranged in an array, and each of the pixel groups M1 includes a plurality of sub-pixels M2 (in FIG. 9 , the plurality of sub-pixels include red sub-pixels R, the green sub-pixel G and the blue sub-pixel B are exemplified, and a plurality of sub-pixels of the plurality of pixel groups are cyclically arranged in the display panel.
  • the display panel includes: a plurality of pixel groups M1 arranged in an array, each pixel group M1 includes a plurality of sub-pixels M2 having different colors, and a plurality of sub-pixels M2 having different colors in each pixel group M1 are along the first
  • the directions are arranged in sequence, and the arrangement order of the sub-pixels in the plurality of pixel groups is the same.
  • the first direction may include: a direction in which the pixel row is located or a direction in which the pixel column is located, where the pixel row is located and the pixel column is located
  • the direction is vertical.
  • a plurality of sub-pixels M2 having different colors in each pixel group M1 are sequentially arranged in a direction S1 in which the pixel columns are located.
  • the display panel may include an array substrate 00 and a color filter substrate 10.
  • a liquid crystal (not shown in FIG. 10) or a light-emitting layer (not shown in FIG. 10) may be disposed between the array substrate 00 and the color filter substrate 10.
  • the array substrate 00 may include: a TFT, a flat layer, a common electrode, a passivation layer, a pixel electrode, and a touch signal line 006, etc. (only for the purpose of viewing, only the touch signal line 006 in the array substrate 00 is shown in FIG. Set the location).
  • the color filter substrate 10 may include a color resist layer 101 and a black matrix 102.
  • the color resist layer 101 includes a plurality of color filters, for example, may include a red filter, a green filter, and a blue filter.
  • the sub-pixels in the display panel are generally divided according to the position of the filter in the color resist layer.
  • the sub-pixel region where the red filter is located ie, the area indicated by the dotted line
  • the sub-pixel region where the sub-pixel region is located is the green sub-pixel G
  • the sub-pixel region where the blue filter is located is the blue sub-pixel B.
  • Each of the sub-pixels may include a TFT located in the sub-pixel region, a flat layer, a common electrode, a passivation layer, a pixel electrode, a liquid crystal, a color filter, and the like.
  • a touch signal line is disposed in each pixel group, and the position of the touch signal line in each of the three pixel groups sequentially disposed in the first direction is different. That is, referring to FIG. 9, the touch signal line 006 includes a plurality of touch signal wire segments in the first direction. In the first direction, in each adjacent two pixel groups M1, for each adjacent two touch signal wire segments: one touch signal wire segment is directly adjacent to both sides of the orthographic projection 0061 on the array substrate. The color of the two sub-pixels is different from the color of at least one of the two sub-pixels directly adjacent to the two sides of the positive projection 0061 of the other touch signal conductor segment on the array substrate. As shown in FIG.
  • two sub-pixels directly adjacent to each other on the two sides of the positive projection 0061 of the touch signal wire segment are green sub-pixels and blue sub-pixels, and the other touch signal wire segments are on the array substrate.
  • the two sub-pixels directly adjacent to each other on the two sides of the orthographic projection 0061 are a red sub-pixel and a green sub-pixel.
  • the extending direction of the touch signal wire segments may be parallel to the extending direction of the gate lines.
  • the extending direction of the gate line is parallel to the direction S2 in which the pixel row is located
  • the extending direction of the touch signal wire segment is also parallel to the direction S2 in which the pixel row is located.
  • FIG. 9 is only one schematic diagram of each pixel group including a plurality of sub-pixels having different colors, and is not used to limit the present application.
  • a sub-pixel of two colors, a sub-pixel of four colors, or a sub-pixel of more colors may be included in each pixel group, which is not specifically limited in the embodiment of the present application.
  • the color of two sub-pixels directly adjacent to each other on the positive projection side of the touch signal wire segment on the array substrate, and the other two sides of the touch signal wire segment on the front projection on the array substrate are directly The color of two adjacent sub-pixels is also not specifically limited.
  • each pixel group includes three sub-pixels of different colors
  • the sub-pixels of the three colors are sub-pixels of the first color, sub-pixels of the second color, and sub-pixels of the third color, respectively, in the first party.
  • the two touch pixels of the touch signal wire segments directly adjacent to each other on the orthographic projection on the array substrate may respectively
  • the two sub-pixels directly adjacent to the two sides of the orthogonal projection on the array substrate of the touch signal wire segment may be the sub-pixel of the second color and the third The sub-pixel of the color.
  • two sub-pixels directly adjacent to each side of the positive projection of the touch signal wire segment on the array substrate may be a sub-pixel of a first color and a sub-pixel of a third color, and another touch signal wire segment is in the array.
  • the two sub-pixels directly adjacent to both sides of the orthographic projection on the substrate may be sub-pixels of the second color and sub-pixels of the third color, respectively.
  • two sub-pixels directly adjacent to each side of the positive projection of the touch signal wire segment on the array substrate may be a sub-pixel of a first color and a sub-pixel of a third color, and another touch signal wire segment is in the array.
  • the two sub-pixels directly adjacent to both sides of the orthographic projection on the substrate may be sub-pixels of the second color and sub-pixels of the first color, respectively.
  • each of the pixel groups M1 includes N sub-pixels M2 having different colors
  • N touches are sequentially arranged in the first direction.
  • Signal wire segment the color of two sub-pixels directly adjacent to each other on the front projection of the first touch signal wire segment on the array substrate, and the second touch signal wire segment directly on both sides of the orthographic projection on the array substrate
  • the colors of the two sub-pixels adjacent to each other, and, respectively, the color of the two sub-pixels directly adjacent to each other on both sides of the orthographic projection of the Nth touch signal wire segment on the array substrate are different.
  • each pixel group M1 includes three sub-pixels of different colors, which are sub-pixels of the first color, sub-pixels of the second color, and sub-pixels of the third color, respectively.
  • the three touch signal wire segments sequentially arranged along the first direction the first touch signal wire segments are directly on both sides of the orthographic projection on the array substrate
  • the two adjacent sub-pixels may be a sub-pixel of a first color and a sub-pixel of a second color, respectively, and the two sub-pixels of the second touch signal wire segment directly adjacent to each other on the orthographic projection on the array substrate may be respectively
  • the sub-pixels of the second color and the sub-pixels of the third color, and the two sub-pixels directly adjacent to the two sides of the positive projection on the array substrate of the third touch signal wire segment may respectively be sub-pixels of the third color and
  • the sub-pixels of the first color that is, the color of the two sub-pixels directly adjacent to each
  • a black matrix is disposed between every two sub-pixels, and the lateral dimension of the black matrix is the width of the spacing between the two sub-pixels (or the lateral dimension of the black matrix is positively correlated with the width of the spacing between the two sub-pixels).
  • the relative position of the sub-pixel and the touch signal line on the array substrate is shown in the dotted line frame A1 of FIG. 11, and the relative position between the sub-pixel and the black matrix BM is as shown in the dotted line frame A2 of FIG.
  • the pattern size of the black matrix between the two sub-pixels provided with the touch signal lines is larger than the pattern size of the black matrix between the two sub-pixels not provided with the touch signal lines.
  • the black matrix disposed between the two sub-pixels has a larger size, and when no touch signal line is disposed between the two sub-pixels, The black matrix disposed between the two sub-pixels has a smaller size.
  • each pixel group is correspondingly provided with one touch signal line, which can avoid the contact resistance is large due to too few touch signal lines, and then the contact of the touch electrode is poor, or the touch signal line can be avoided too much.
  • the problem that the touch signal line is poorly matched with the first via hole is that the contact between the touch signal line and the common electrode is avoided.
  • the display panel includes a plurality of pixel groups, and each of the pixel groups also includes a plurality of sub-pixels, and the plurality of sub-pixels may be a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, in the plurality of pixel groups.
  • a plurality of sub-pixels are cyclically arranged in the display panel.
  • a touch signal line is disposed in each pixel group, and the touch signal lines are in the same position in each pixel group, and a black matrix is also disposed between each two sub-pixels.
  • the two sub-pixels directly adjacent to each other on the positive projection side of the plurality of conductive line segments of the touch signal line have the same color, for example, in each sub-pixel group, the conductive line segments are on the array substrate.
  • the two sub-pixels directly adjacent to each side of the Orthographic are respectively a blue sub-pixel and a red sub-pixel.
  • the position of the sub-pixel and the touch signal line TPM on the array substrate is as shown in the broken line frame C of FIG. 12, and the position between the sub-pixel and the black matrix BM is as shown in the broken line frame D of FIG.
  • the plurality of conductive line segments of the touch signal line are directly adjacent to each other on both sides of the orthographic projection on the array substrate.
  • the sub-pixels are all the same color.
  • the two sub-pixels directly adjacent to each other on both sides of the black matrix having the larger graphic size have the same color.
  • the color displayed on the entire display panel will appear as directly adjacent to both sides of the larger-sized black matrix.
  • the color of the two sub-pixels is superimposed, for example, assuming that the touch signal line is between the blue sub-pixel and the red sub-pixel of each pixel group (refer to the position shown in FIG. 12 for the position of the touch signal line). That is, in each pixel group, the two sub-pixels directly adjacent to the two sides of the positive projection on the array substrate are respectively a blue sub-pixel and a red sub-pixel, and the entire display panel is displayed.
  • the color of the color is affected by the purple color of the blue and red superimposed, that is, the color displayed on the display panel is purple, which causes the display panel to display an abnormal color, and then the display panel cannot pass the electrostatic discharge (English: Electro-Static) Discharge; abbreviation: ESD) test.
  • ESD Electro-Static Discharge
  • the position of the touch signal line in each of the three adjacent pixel groups is different, that is, in every three pixel groups arranged in the first direction, Three touch signal wire segments arranged in one direction in sequence: the two touch signal wire segments have different colors of two sub-pixels directly adjacent to each other on both sides of the orthographic projection on the array substrate.
  • the influence of the black matrix at the corresponding position in each of the three pixel groups on the display panel display color is three
  • the superposition of the colors of two sub-pixels directly adjacent to each other on both sides of the black matrix having a larger image size in the pixel group is the position shown in FIG. 11 , and the position of the touch signal line in the adjacent three pixel groups is different.
  • the color displayed by the panel at the corresponding position is the superposition of the colors of the two sub-pixels directly adjacent to each other on both sides of the black matrix having the larger size of the three pixel groups. That is, please continue to refer to FIG. 11 , the display panel includes a plurality of pixel groups arranged in an array, the number of the plurality of pixel groups is greater than or equal to 3, and for the plurality of pixel groups, sequentially arranged in the first direction In each of the three pixel groups of the cloth, the first touch of the first touch signal wire segment on the two sides of the positive projection on the array substrate are respectively a green sub-pixel and a blue sub-pixel, and the first touch The color of the pixel group where the control signal wire segment is displayed is a superposition of green and blue; the second sub-pixels of the second touch signal wire segment directly adjacent to the orthographic projection on the array substrate are respectively red sub-pixels and The green sub-pixel, the color of the pixel group in which the second touch signal wire segment is located is a superposition of
  • the two sub-pixels are respectively a blue sub-pixel and a red sub-pixel, and the color displayed by the pixel group in which the third touch signal wire segment is displayed is a superposition of blue and red. Moreover, since the superimposed colors of the three colors of red, green and blue are white, when the liquid crystal in the vicinity of the smaller size black matrix is no longer deflected, and the liquid crystal in the vicinity of the larger size black matrix is continuously deflected, the color of the entire display panel will be displayed.
  • the white color is superimposed on the red, green and blue, so that the color displayed by the display panel is not affected by the color of the sub-pixels on both sides of the black matrix having a larger size, that is, relative to the related art, the embodiment of the present application
  • the provided display panel can avoid the display color abnormality of the display panel.
  • the display panel provided by the embodiment of the present invention provides a flat layer, a common electrode, a passivation layer, and a touch signal line on the substrate, and a first via is disposed on the passivation layer.
  • the control signal line is connected to the common electrode through the first via hole. Since the thickness of the flat layer is greater than the thickness of the passivation layer, the touch signal line has a small thickness, so that the touch signal line has a small resistance, correspondingly
  • the driving resistance of the array substrate in the display panel is reduced, thereby reducing the attenuation degree of the driving signal in the array substrate, and then the driving capability of the array substrate is effectively improved.
  • the display panel is prevented from being abnormal in display color.
  • the present application further provides a display device, which includes the above display panel, and the display device may be: a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Any product or part that has a display function.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

La présente invention concerne un substrat de réseau, un panneau d'affichage et un dispositif d'affichage, appartenant au domaine des technologies d'affichage. Le substrat de réseau comprend : une électrode commune, une couche de passivation et une ligne de signal tactile qui sont disposées de manière séquentielle sur un substrat. La ligne de signal tactile est utilisée pour transmettre un signal tactile chargé sur l'électrode commune à un circuit de commande tactile. La couche de passivation est pourvue d'un premier trou de liaison. La ligne de signal tactile est connectée à l'électrode commune au moyen du premier trou de liaison. La présente invention réduit la résistance relative à la commande du substrat de réseau, réduisant ainsi le degré d'atténuation d'un signal de commande dans le substrat de réseau, et améliorant ainsi efficacement la capacité de commande du substrat de réseau. La présente invention est utilisée pour afficher une image.
PCT/CN2018/089521 2017-06-01 2018-06-01 Substrat de réseau, panneau d'affichage et dispositif d'affichage WO2018219345A1 (fr)

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CN201720629918.1U CN206741462U (zh) 2017-06-01 2017-06-01 阵列基板、显示面板及显示装置

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CN206741462U (zh) * 2017-06-01 2017-12-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN109671726B (zh) 2019-01-04 2021-01-26 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、显示装置
CN112558800B (zh) * 2019-09-25 2024-01-23 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置

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Publication number Priority date Publication date Assignee Title
CN105573549A (zh) * 2015-12-08 2016-05-11 上海天马微电子有限公司 阵列基板、触控屏和触控显示装置及其制作方法
CN106773221A (zh) * 2017-02-17 2017-05-31 武汉华星光电技术有限公司 阵列基板及其制作方法与In Cell触控显示面板
CN206741462U (zh) * 2017-06-01 2017-12-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105573549A (zh) * 2015-12-08 2016-05-11 上海天马微电子有限公司 阵列基板、触控屏和触控显示装置及其制作方法
CN106773221A (zh) * 2017-02-17 2017-05-31 武汉华星光电技术有限公司 阵列基板及其制作方法与In Cell触控显示面板
CN206741462U (zh) * 2017-06-01 2017-12-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

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