WO2018218954A1 - 一种验证平台和验证方法、计算机存储介质 - Google Patents

一种验证平台和验证方法、计算机存储介质 Download PDF

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Publication number
WO2018218954A1
WO2018218954A1 PCT/CN2017/120088 CN2017120088W WO2018218954A1 WO 2018218954 A1 WO2018218954 A1 WO 2018218954A1 CN 2017120088 W CN2017120088 W CN 2017120088W WO 2018218954 A1 WO2018218954 A1 WO 2018218954A1
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Prior art keywords
module
tested
test
calculation result
data
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PCT/CN2017/120088
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English (en)
French (fr)
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韩彬
徐科
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深圳市中兴微电子技术有限公司
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Publication of WO2018218954A1 publication Critical patent/WO2018218954A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/06—Structured ASICs

Definitions

  • the present invention relates to the field of circuit design verification technologies, and in particular, to a verification platform and a verification method, and a computer storage medium.
  • IP Intellectual property
  • Peripheral Component Interconnect is designed as a module that can modify parameters, allowing other users to directly call these modules, thus greatly reducing the burden on engineers and avoiding duplication of effort.
  • PCI Peripheral Component Interconnect
  • IP multiplexing technology has become an important branch of integrated circuit design. Many design vendors are paying more and more attention to the company's IP core design and accumulation while purchasing IP cores of other companies.
  • the present invention is intended to provide a verification platform and verification method, a computer storage medium, which can improve the efficiency of IP verification testing.
  • the embodiment of the present invention provides a verification platform, which is implemented based on an FPGA, and includes a first interface conversion module, a platform configuration module, a first IP module to be tested, a first memory module, and a comparison module that are interconnected by an on-chip bus. ,among them:
  • the first interface conversion module is configured to receive and convert a first test data of an external computer, where the first test data includes configuration data, a test case, a first calculation result, and a test instruction; Outputting the data to the first IP module to be tested and the platform configuration module, outputting the test case and the first calculation result to the first memory module, and outputting the test command to the first
  • the IP module to be tested is further configured to receive the comparison result of the comparison module, and output the result to an external computer;
  • the platform configuration module is configured to configure the FPGA to which it belongs according to the received configuration data
  • the first IP module to be tested is configured to configure itself according to the received configuration data.
  • the test instruction the test case is obtained from the first memory module and calculated, and a second calculation result is generated, and the second calculation is performed.
  • the result is stored in the first memory module, generating an interrupt signal and outputting to the comparison module;
  • the comparison module is configured to receive an interrupt signal, obtain a first calculation result and a second calculation result from the first memory module, perform comparison, and send the comparison result to the first interface conversion module;
  • the first memory module is configured to store a test case, a first calculation result, and a second calculation result.
  • the on-chip bus is an Advanced EXtensible Interface (AXI) bus.
  • AXI Advanced EXtensible Interface
  • the first IP module to be tested and the platform configuration module are interconnected by an Advanced Peripheral Bus (APB) bridge.
  • API Advanced Peripheral Bus
  • the first interface conversion module and the external computer are connected by a Universal Serial Bus (USB) interface.
  • USB Universal Serial Bus
  • the embodiment of the present invention further provides a verification platform, which is implemented based on an FPGA, and includes a second interface conversion module, a platform configuration module, a second IP module to be tested, and a second memory module, which are interconnected by an on-chip bus, where:
  • the second interface conversion module is configured to receive and perform protocol conversion on the second test data of the external computer, where the second test data includes configuration data, test cases, and test instructions; and output the configuration data to the a second IP module to be tested and the platform configuration module, outputting the test case to the second memory module, outputting the test command to the second IP module to be tested, and configured to receive the first The interrupt signal and the second calculation result of the IP module to be tested, and output the second calculation result to an external computer;
  • the platform configuration module is configured to configure the FPGA to which it belongs according to the received configuration data
  • the second IP module to be tested is configured to configure itself according to the received configuration data.
  • the test case is obtained from the second memory module and calculated, and a second calculation result is generated. Outputting the second calculation result to the second interface conversion module, generating an interrupt signal and outputting to the second interface conversion module;
  • the second memory module is configured to store a test case.
  • the embodiment of the invention further provides a verification method, including:
  • the first test data includes configuration data, a test case, a first calculation result, and a test instruction
  • performing protocol conversion on the first test data includes: converting a protocol used by the first test data into an AXI protocol.
  • the configuring the IP to be tested and the IP to be tested including the APB bridge, configures the IP to be tested and the IP to be tested.
  • the receiving the first test data of the external computer comprises: receiving the first test data of the external computer through a USB interface.
  • the embodiment of the invention further provides a verification method, including:
  • the embodiment of the present invention further provides a computer storage medium, where the computer program is stored, and the computer program is executed by the processor to implement the steps of the verification method according to an embodiment of the present invention; or the computer program is processed by the processor The steps of another verification method of the embodiment of the present invention are implemented when executed.
  • Embodiments of the present invention also provide a verification platform, including: a processor and a memory for storing a computer program capable of running on a processor, wherein the processor is configured to execute the implementation of the present invention when the computer program is executed For example, the steps of one of the methods, or the steps of another of the methods of the embodiments of the present invention.
  • the verification platform and the verification method and the computer storage medium provided by the invention directly place the hardware circuit in the FPGA for calculation, and use the characteristics of the FPGA high-speed parallel array operation to construct a high-speed platform for communication between the PC and the FPGA hardware, and reduce the CPU operation.
  • the pressure has increased the efficiency of ASIC pre-IP verification by thousands of times, solved the problem that IP verification has become the bottleneck of IP R&D efficiency, completely turned random verification into complete verification, and improved the cycle and success rate of IC chip.
  • FIG. 1 is a schematic structural diagram of a verification platform according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a verification platform according to a second embodiment of the present invention.
  • FIG. 3 is a schematic flowchart diagram of a verification method according to a first embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a verification method according to a second embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a verification platform according to a third embodiment of the present invention.
  • a verification platform As shown in FIG. 1 , a verification platform according to an embodiment of the present invention, the verification platform is implemented based on an FPGA, and includes a first interface conversion module, a platform configuration module, a first IP module to be tested, and a first memory that are interconnected by an on-chip bus.
  • Module and comparison module where:
  • the first interface conversion module is configured to receive and convert a first test data of an external computer, where the first test data includes configuration data, a test case, a first calculation result, and a test instruction; Outputting to the first IP module to be tested and the platform configuration module, outputting the test case and the first calculation result to the first memory module, and outputting the test command to the first to-be-waited Measuring the IP module; further configured to receive the comparison result of the comparison module, and output to an external computer;
  • the platform configuration module is configured to configure the FPGA to which it belongs according to the received configuration data
  • the first IP module to be tested is configured to configure the first IP module to be tested according to the received configuration data; obtain a test case from the first memory module according to the test instruction, perform calculation, and generate a second calculation Assending, storing the second calculation result to the first memory module, generating an interrupt signal and outputting to the comparison module;
  • the comparison module is configured to receive an interrupt signal, obtain a first calculation result and a second calculation result from the first memory module, perform comparison, and send the comparison result to the first interface conversion module;
  • the first memory module is configured to store a test case, a first calculation result, and a second calculation result.
  • the comparison module may be implemented in an external computer, or may be implemented in the verification platform of the embodiment of the present invention.
  • the FPGA hardware speeds up the comparison. It can reduce the burden on external computers and improve the efficiency of verification.
  • the on-chip bus is an AXI bus.
  • the AXI protocol is part of the AMBA (Advanced Microcontroller Bus Architecture) protocol proposed by ARM.
  • the AXI bus is a high-performance, high-bandwidth, low-latency on-chip bus with separate address/control and data phases. Unaligned data transmission, in the burst transmission, only the first address, separate read and write data channels, and support for significant transmission access and out-of-order access, and easier parallel timing closure.
  • AXI technology enriches existing AMBA standards to meet the needs of ultra-high performance and complex SoC designs.
  • the first interface conversion module is a master device of the AXI bus.
  • the first IP module to be tested and the platform configuration module are interconnected by an APB bridge, and the AXI interface is between the APB bridge and the AXI bus.
  • the data width between the AXI bus and the first IP module to be tested is 128 bits or 64 bits.
  • the first interface conversion module and the external computer are connected by a USB interface.
  • the first interface conversion module includes a USB interface module and a protocol conversion module
  • the USB interface module is configured to forward configuration data, a test case, a first calculation result, and a test instruction from an external computer to the protocol conversion module through a USB interface; and send a comparison result from the protocol conversion module to the External computer
  • the protocol conversion module is configured to perform protocol conversion on configuration data, test cases, first calculation results, and test instructions; as a master device of the AXI bus, output configuration data to the first IP module to be tested and the platform a configuration module, outputting the test case and the first calculation result to the first memory module, outputting the test instruction to the first IP module to be tested, and further configured to receive the comparison result of the comparison module, and convert After being the USB protocol, it is sent to the USB interface module.
  • the configuration data received by the platform configuration module includes a clock, a reset, a mode, and the like of an FPGA to which it belongs.
  • An embodiment of the present invention further provides a verification platform, including: a processor and a memory for storing a computer program capable of running on a processor, wherein when the processor is configured to execute the computer program, performing: receiving an external The first test data of the computer is subjected to protocol conversion, and the first test data includes configuration data, a test case, a first calculation result, and a test instruction; and the IP to be tested and the IP to be tested included therein are configured according to the configuration data.
  • test instruction Writing the test case and the first calculation result to the memory, sending the test instruction to the IP to be tested, receiving the interrupt signal generated by the IP to be tested, and the IP to be tested according to the test case and The test instruction performs a second calculation result generated by the calculation, compares the second calculation result with the first calculation result, and sends the comparison result to an external computer.
  • the processor is configured to: when the computer program is executed, convert a protocol used by the first test data into an AXI protocol.
  • the processor when the processor is used to run the computer program, the processor performs: configuring the IP to be tested and the IP to be tested included by the APB bridge.
  • the processor is configured to: when the computer program is executed, receive the first test data of the external computer through a USB interface.
  • a verification platform As shown in FIG. 2, a verification platform according to an embodiment of the present invention, the verification platform is implemented based on an FPGA, including a second interface conversion module, a platform configuration module, a second IP module to be tested, and a second memory interconnected by an on-chip bus. Module, where:
  • the second interface conversion module is configured to receive and perform protocol conversion on the second test data of the external computer, where the second test data includes configuration data, test cases, and test instructions; and output the configuration data to the a second IP module to be tested and a platform configuration module, output the test case to the second memory module, output the test command to the second IP module to be tested, and further configured to receive the second to-be-tested Measuring the interrupt signal of the IP module and the second calculation result, and outputting the second calculation result to an external computer;
  • the platform configuration module is configured to configure the FPGA to which it belongs according to the received configuration data
  • the second IP module to be tested is configured to configure itself according to the received configuration data.
  • the test case is obtained from the second memory module and calculated, and a second calculation result is generated. Outputting the second calculation result to the second interface conversion module, generating an interrupt signal and outputting to the second interface conversion module;
  • the second memory module is configured to store a test case.
  • the external computer generates a data source and a first calculation result according to the algorithm C model; and when the external computer receives the second calculation result, compares the first calculation result with the second calculation result, if consistent , the test passes, the next test case is executed; otherwise, the current test case is recorded, and the next test case is started.
  • the on-chip bus is an AXI bus.
  • the second interface conversion module is a master device of the AXI bus.
  • the second IP module to be tested and the platform configuration module are interconnected by an APB bridge, and the AXI interface is between the APB bridge and the AXI bus.
  • the data width between the AXI bus and the second IP module to be tested is 128 bits or 64 bits.
  • the second interface conversion module is connected to an external computer through a USB interface.
  • the configuration data received by the platform configuration module includes a clock, a reset, a mode, and the like of an FPGA to which it belongs.
  • An embodiment of the present invention further provides a verification platform, including: a processor and a memory for storing a computer program capable of running on a processor, wherein when the processor is configured to execute the computer program, performing: receiving an external Second test data of the computer and protocol conversion thereof, the second test data includes configuration data, test cases and test instructions; configuring the test IP to be tested by itself and itself according to the configuration data, and the test is performed
  • the use case is written into the memory, and the test instruction is sent to the IP to be tested; the interrupt signal generated by the IP to be tested is received, and the second calculation result generated by the IP to be tested is calculated according to the test case and the test instruction. And transmitting the second calculation result to an external computer.
  • the verification platform provided by the foregoing embodiment, as shown in FIG. 3, is an authentication method according to an embodiment of the present invention, including:
  • Step 301 The FPGA verification platform receives and converts the first test data of the external computer, where the first test data includes configuration data, a test case, a first calculation result, and a test instruction.
  • the protocol used by the first test data is converted into a protocol supported by the on-chip bus, and the on-chip bus may be an AXI bus.
  • the FPGA verification platform receives the first test data of the external computer through the USB interface.
  • Step 302 The FPGA verification platform configures the IP address to be tested and the IP address to be tested according to the received configuration data, writes the test case and the first calculation result into the memory, and sends the test command to the IP to be tested.
  • the FPGA verification platform configures itself and the IP to be tested contained in the APB bridge through the APB bridge.
  • the FPGA verification platform when the FPGA verification platform configures itself, the FPGA verification platform configures its own clock, reset, mode, and the like.
  • the data width between the AXI bus and the IP to be tested is 128 bits or 64 bits.
  • Step 303 The FPGA verification platform receives the interrupt signal generated by the IP to be tested and the second calculation result generated by the IP address to be tested according to the test case and the test instruction, and the second calculation result and the first calculation result. The results are compared and the comparison results are sent to an external computer.
  • comparison operation described in the embodiment of the present invention may be implemented in an external computer, or may be implemented in the FPGA verification platform of the embodiment of the present invention.
  • the hardware is accelerated by the FPGA. Comparison can reduce the burden on external computers and improve the efficiency of verification.
  • the embodiment of the present invention further provides a computer storage medium, where the computer program is stored, and the computer program is executed by the processor to: receive the first test data of the external computer and perform protocol conversion, the first test The data includes configuration data, a test case, a first calculation result, and a test instruction; configuring, according to the configuration data, the IP to be tested and the IP to be tested, and writing the test case and the first calculation result into the memory, Sending the test command to the IP to be tested; receiving the interrupt signal generated by the IP to be tested and the second calculation result generated by calculating the IP to be tested according to the test case and the test instruction, and the second The calculation result is compared with the first calculation result, and the comparison result is sent to an external computer.
  • the computer program is executed by the processor to: convert the protocol used by the first test data into an AXI protocol.
  • the APB bridge when the computer program is executed by the processor, the APB bridge configures the IP to be tested and the IP to be tested.
  • the computer program is executed by the processor to: receive the first test data of the external computer via a USB interface.
  • another verification method according to an embodiment of the present invention includes:
  • Step 401 The FPGA verification platform receives and converts the second test data of the external computer, where the second test data includes configuration data, test cases, and test instructions.
  • the protocol used by the second test data is converted into a protocol supported by an on-chip bus, and the on-chip bus may be an AXI bus.
  • the FPGA verification platform receives the second test data of the external computer through the USB interface.
  • Step 402 The FPGA verification platform configures the IP address to be tested and the IP address to be tested according to the received configuration data, writes the test case to the memory, and sends the test command to the IP to be tested.
  • the FPGA verification platform configures itself and the IP to be tested contained in the APB bridge through the APB bridge.
  • the FPGA verification platform when the FPGA verification platform configures itself, the FPGA verification platform configures its own clock, reset, mode, and the like.
  • the data width between the AXI bus and the IP to be tested is 128 bits or 64 bits.
  • Step 403 The FPGA verification platform receives the interrupt signal generated by the IP to be tested and the second calculation result generated by the IP to be tested according to the test case and the test instruction, and sends the second calculation result to External computer.
  • the external computer generates a data source and a first calculation result according to the algorithm C model; and when the external computer receives the second calculation result, compare the first calculation result with the second calculation result. Yes, if they are consistent, the test passes and the next test case is executed; otherwise, the current test case is recorded and the next test case is started.
  • the embodiment of the present invention further provides a computer storage medium, where the computer program is stored, and when the computer program is executed by the processor, the second test data of the external computer is received and converted, and the second test is performed.
  • the data includes configuration data, test cases, and test instructions; configuring the IP to be tested and the IP to be tested according to the configuration data, writing the test case to the memory, and transmitting the test command to the IP to be tested;
  • the interrupt signal generated by the IP to be tested and the second calculation result generated by calculating the IP to be tested according to the test case and the test command, and the second calculation result is sent to an external computer.
  • the FPGA verification platform includes the following modules:
  • USB interface protocol conversion module, AXI-AXI bridge, AXI-APB bridge, platform configuration module, comparison module, IP to be tested, DDR memory and status display module, wherein
  • USB interface realizes USB3.0 high-speed communication between FPGA verification platform and external computer (PC);
  • the protocol conversion module converts the data and instructions decoded by the USB interface into the standard AXI protocol of AMBA, and serves as the master device of the AXI128.
  • the AXI-AXI bridge interconnects the IP to be tested, the AXI-APB bridge, the platform configuration module, and the DDR. Memory and comparison module;
  • AXI-APB bridge interconnected IP and platform configuration modules to be tested, configured to configure the IP to be tested and the platform itself;
  • the data width between the IP to be tested and the AXI-AXI bridge may be 128 bits or 64 bits;
  • the DDR memory is mounted with a 4GB DDR memory module through the DDR controller, and is used as a cache for test cases, PC calculation results, and IP calculation results to be tested;
  • the comparison module is configured to obtain the PC calculation result in the DDR and the IP calculation result to be tested, perform comparison, and return the comparison result to the PC;
  • the status display module is configured to display the current working status or working mode.
  • the data source and the PC calculation result are generated on the PC side; at the same time, the generated data source and the PC calculation result are transmitted to the lower computer through USB3.0, and the IP to be tested starts to work and waits for the interrupt signal of the IP transmission to be tested. After the signal to be interrupted is received, the IP test result and the PC calculation result are compared. If the comparison is passed, the next test case is executed; otherwise, the current test case is recorded, and the next test case is started.
  • the performance of the overall system depends on the effective communication bandwidth of USB3.0, the IP to be tested, and the operating frequency of DDR memory.
  • the performance of the PC and the execution efficiency of the algorithm C model largely determine the bottleneck of the overall system. If the PC performance is too low to be full-speed USB3.0 communication, or the execution efficiency of the algorithm C model is low, and the cycle of the FPGA hardware calculation result cannot be kept, it will become a bottleneck of high-speed comparison to some extent.
  • the degree of automation of the PC-end batch program determines the convenience of the overall system high-speed test.
  • the verification platform and the verification method provided by the embodiments of the present invention directly place the hardware circuit in the FPGA for calculation, and use the characteristics of the FPGA high-speed parallel array operation to construct a high-speed platform for communication between the PC and the FPGA hardware, and reduce the CPU operation.
  • the pressure has increased the efficiency of ASIC pre-IP verification by thousands of times, solved the problem that IP verification has become the bottleneck of IP R&D efficiency, completely turned random verification into complete verification, and improved the cycle and success rate of IC chip.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing storage device includes the following steps: the foregoing storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
  • ROM read-only memory
  • RAM random access memory
  • magnetic disk or an optical disk.
  • optical disk A medium that can store program code.
  • the above-described integrated unit of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a standalone product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a RAM, a magnetic disk, or an optical disk.
  • the technical solution of the embodiment of the invention directly places the hardware circuit in the FPGA for calculation, and utilizes the characteristics of the FPGA high-speed parallel array operation to construct a high-speed platform for communication between the PC and the FPGA hardware, thereby reducing the pressure of the CPU operation, and tens of thousands. It has improved the efficiency of IP verification in the early stage of ASIC, solved the problem that IP verification has become the bottleneck of IP R&D efficiency, completely turned random verification into complete verification, and improved the cycle and success rate of IC chip.

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Abstract

本发明实施例公开了一种验证平台和验证方法、计算机存储介质，所述验证平台基于现场可编程门阵列(FPGA)实现，包括通过片上总线互联的：第一接口转换模块，配置为接收外部计算机的测试数据并对其进行协议转换，将测试用例和第一计算结果输出至第一内存模块，将测试指令输出至第一待测IP模块；接收比对结果，并发送至外部计算机；平台配置模块，配置为根据接收的配置数据，对自身所属FPGA进行配置；第一待测IP模块，配置为根据测试指令，获取测试用例并进行计算，生成第二计算结果，产生中断信号；比对模块，配置为获取第一计算结果和第二计算结果进行比对，将比对结果发送至第一接口转换模块。

Description

一种验证平台和验证方法、计算机存储介质
相关申请的交叉引用
本申请基于申请号为201710389863.6、申请日为2017年05月27日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本发明涉及电路设计验证技术领域，尤其涉及一种验证平台和验证方法、计算机存储介质。
背景技术
随着微电子技术的飞速发展，片上系统(System On Chip，SOC)技术已成为国际超大规模集成电路的发展趋势。在SOC系统设计中，为了能够快速、稳定的形成产品，知识产权(Intellectual Property，IP)核积累和复用技术逐渐成为各个芯片厂商的首选。IP核是指用于专用集成电路(Application Specific Integrated Circuit，ASIC)或者现场可编程门阵列(Field Programmable Gate Array，FPGA)的逻辑块或数据块。将一些在数字电路中常用但比较复杂的功能块，如有限长单位冲激响应(Finitary Impulse Response，FIR)滤波器，同步动态随机存储(Synchronous Dynamic Random Access Memory，SDRAM)控制器，外设部件互连标准(Peripheral Component Interconnect，PCI)接口等等设计成可修改参数的模块，让其他用户可以直接调用这些模块，这样就大大减轻了工程师的负担，避免重复劳动。在这样的背景下，IP复用技术成为了集成电路设计的一个重要分支，很多设计厂商在购买其它公司的IP核的同时，也越来越重视本公司的IP核 设计和积累。
在IP累积过程中，设计和验证是最重要的两个部分，而随着IP电路设计功能和结构的日益复杂，验证的工作量和难度更是以几何级数的速度上升。验证就是通过各种仿真，数据比较等手段来证明设计的正确性的过程，由于要在验证过程中需要证明设计在定义的所有的工作条件范围内不能出现错误，所以验证的工作量相对于设计来说更加巨大。对于多媒体IP而言，验证速度已经成为制约多媒体IP开发进度的最大瓶颈。
目前，现有文献的研究方向大都针对集成电路(Integrated Circuit，IC)的自动化验证测试，采用FPGA进行实现验证；也有部分文献采用PCI接口与个人计算机(Personal Computer，PC)进行高速交互，或者基于FPGA，在软件层面进行脚本验证加速。现有文献没有一个针对ASIC IP进行FPGA高速并行自动化验证测试的方案。
发明内容
本发明期望提供一种验证平台和验证方法、计算机存储介质，能够提高IP验证测试的效率。
为了达到本发明目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种验证平台，所述验证平台基于FPGA实现，包括通过片上总线互联的第一接口转换模块、平台配置模块、第一待测IP模块、第一内存模块和比对模块，其中：
所述第一接口转换模块，配置为接收外部计算机的第一测试数据并对其进行协议转换，所述第一测试数据包括配置数据、测试用例、第一计算结果和测试指令；将所述配置数据输出至所述第一待测IP模块和所述平台配置模块，将所述测试用例和所述第一计算结果输出至所述第一内存模块，将所述测试指令输出至所述第一待测IP模块；还配置为接收所述比对模块的比对结果，输出至外部计算机；
所述平台配置模块，配置为根据接收的配置数据，对自身所属FPGA进行配置；
所述第一待测IP模块，配置为根据接收的配置数据，对自身进行配置；根据测试指令，从所述第一内存模块获取测试用例并进行计算，生成第二计算结果，将第二计算结果存储至所述第一内存模块，产生中断信号并输出至所述比对模块；
所述比对模块，配置为接收到中断信号，从所述第一内存模块中获取第一计算结果和第二计算结果并进行比对，将比对结果发送至所述第一接口转换模块；
所述第一内存模块，配置为存储测试用例、第一计算结果和第二计算结果。
在一实施例中，所述片上总线为高级可扩展接口(Advanced eXtensible Interface，AXI)总线。
在一实施例中，所述第一待测IP模块和所述平台配置模块之间通过高级外围总线(Advanced Peripheral Bus，APB)桥互联。
在一实施例中，所述第一接口转换模块和所述外部计算机之间通过通用串行总线(Universal Serial Bus，USB)接口连接。
本发明实施例还提供了一种验证平台，所述验证平台基于FPGA实现，包括通过片上总线互联的第二接口转换模块、平台配置模块、第二待测IP模块和第二内存模块，其中：
所述第二接口转换模块，配置为接收外部计算机的第二测试数据并对其进行协议转换，所述第二测试数据包括配置数据、测试用例和测试指令；将所述配置数据输出至所述第二待测IP模块和所述平台配置模块，将所述测试用例输出至所述第二内存模块，将所述测试指令输出至所述第二待测IP模块；还配置为接收所述第二待测IP模块的中断信号和第二计算结果， 将所述第二计算结果输出至外部计算机；
所述平台配置模块，配置为根据接收的配置数据，对自身所属FPGA进行配置；
所述第二待测IP模块，配置为根据接收的配置数据，对自身进行配置；根据所述测试指令，从所述第二内存模块获取测试用例并进行计算，生成第二计算结果，将所述第二计算结果输出至所述第二接口转换模块，产生中断信号并输出至所述第二接口转换模块；
所述第二内存模块，配置为存储测试用例。
本发明实施例还提供了一种验证方法，包括：
接收外部计算机的第一测试数据并对其进行协议转换，所述第一测试数据包括配置数据、测试用例、第一计算结果和测试指令；
根据所述配置数据对自身和自身包含的待测IP进行配置，将所述测试用例和所述第一计算结果写入内存，将所述测试指令发送至待测IP；
接收所述待测IP生成的中断信号和所述待测IP根据所述测试用例及所述测试指令进行计算生成的第二计算结果，将所述第二计算结果与所述第一计算结果进行比对，将比对结果发送至外部计算机。
在一实施例中，对所述第一测试数据进行协议转换，包括：将所述第一测试数据使用的协议转换成AXI协议。
在一实施例中，所述对自身和自身包含的待测IP进行配置，包括：通过APB桥对自身和自身包含的待测IP进行配置。
在一实施例中，所述接收外部计算机的第一测试数据，包括：通过USB接口接收所述外部计算机的第一测试数据。
本发明实施例还提供了一种验证方法，包括：
接收外部计算机的第二测试数据并对其进行协议转换，所述第二测试数据包括配置数据、测试用例和测试指令；
根据所述配置数据对自身和自身包含的待测IP进行配置，将所述测试用例写入内存，将所述测试指令发送至待测IP；
接收所述待测IP生成的中断信号和所述待测IP根据所述测试用例及测试指令进行计算生成的第二计算结果，将第二计算结果发送至外部计算机。
本发明实施例还提供了一种计算机存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现本发明实施例一种所述验证方法的步骤；或者，该计算机程序被处理器执行时实现本发明实施例另一种所述验证方法的步骤。
本发明实施例还提供了一种验证平台，包括：处理器和用于存储能够在处理器上运行的计算机程序的存储器，其中，所述处理器用于运行所述计算机程序时，执行本发明实施例一种所述方法的步骤，或者，执行本发明实施例另一种所述方法的步骤。
本发明提供的验证平台和验证方法、计算机存储介质，将硬件电路直接置于FPGA进行运算，利用FPGA高速并行阵列运算的特点，构建了高速的PC与FPGA硬件通信的平台，缓减了CPU运算的压力，成千上万倍地提高了ASIC前期IP验证的效率，解决了IP验证成为IP研发效率瓶颈的难题，彻底将随机验证转变为完整验证，提高了IC流片的周期与成功率。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1为本发明第一实施例的一种验证平台的结构示意图；
图2为本发明第二实施例的一种验证平台的结构示意图；
图3为本发明第一实施例的一种验证方法的流程示意图；
图4为本发明第二实施例的一种验证方法的流程示意图；
图5为本发明第三实施例的一种验证平台的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，下文中将结合附图对本发明的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
如图1所示，本发明实施例的一种验证平台，所述验证平台基于FPGA实现，包括通过片上总线互联的第一接口转换模块、平台配置模块、第一待测IP模块、第一内存模块和比对模块，其中：
所述第一接口转换模块，配置为接收外部计算机第一测试数据并对其进行协议转换，所述第一测试数据包括配置数据、测试用例、第一计算结果和测试指令；将所述配置数据输出至所述第一待测IP模块和所述平台配置模块，将所述测试用例和所述第一计算结果输出至所述第一内存模块，将所述测试指令输出至所述第一待测IP模块；还配置为接收所述比对模块的比对结果，输出至外部计算机；
所述平台配置模块，配置为根据接收的配置数据，对自身所属FPGA进行配置；
所述第一待测IP模块，配置为根据接收的配置数据，对第一待测IP模块自身进行配置；根据测试指令，从所述第一内存模块获取测试用例并进行计算，生成第二计算结果，将第二计算结果存储至所述第一内存模块，产生中断信号并输出至所述比对模块；
所述比对模块，配置为接收到中断信号，从所述第一内存模块中获取第一计算结果和第二计算结果并进行比对，将比对结果发送至所述第一接口转换模块；
所述第一内存模块，配置为存储测试用例、第一计算结果和第二计算结果。
需要说明的是，本发明实施例中所述比对模块可以在外部计算机中实现，也可以在本发明实施例的验证平台中实现，当在验证平台中实现时，通过FPGA硬件加速比对，可以减少外部计算机的负担，也可以提高验证的效率。
在一实施例中，所述片上总线为AXI总线。AXI协议是ARM公司提出的AMBA(Advanced Microcontroller Bus Architecture)协议中的一部分，AXI总线是一种高性能、高带宽、低延迟的片内总线，它的地址/控制和数据相位是分离的，支持不对齐的数据传输，同时在突发传输中，只需要首地址，同时分离的读写数据通道、并支持显著传输访问和乱序访问，并更加容易并行时序收敛。AXI技术丰富了现有的AMBA标准内容，满足超高性能和复杂的SoC设计的需求。
在一实施例中，所述第一接口转换模块为AXI总线的主设备。
在一实施例中，所述第一待测IP模块和所述平台配置模块之间通过APB桥互联，所述APB桥与AXI总线之间为AXI接口。
在一实施例中，所述AXI总线和第一待测IP模块之间的数据宽度为128比特或64比特。
在一实施例中，所述第一接口转换模块和所述外部计算机之间通过USB接口连接。
作为一种实施方式，所述第一接口转换模块包括USB接口模块与协议转换模块，
所述USB接口模块，配置为通过USB接口将来自外部计算机的配置数据、测试用例、第一计算结果和测试指令转发至所述协议转换模块；将来自所述协议转换模块的比对结果发送至外部计算机；
所述协议转换模块，配置为对配置数据、测试用例、第一计算结果和测试指令进行协议转换；作为AXI总线的主设备，将配置数据输出至所述 第一待测IP模块和所述平台配置模块，将测试用例和第一计算结果输出至所述第一内存模块，将测试指令输出至所述第一待测IP模块；还配置为接收所述比对模块的比对结果，并转换成USB协议后发送至USB接口模块。
在一实施例中，所述平台配置模块接收的配置数据包括自身所属的FPGA的时钟、复位、模式等。
本发明实施例还提供了一种验证平台，包括：处理器和用于存储能够在处理器上运行的计算机程序的存储器，其中，所述处理器用于运行所述计算机程序时，执行：接收外部计算机的第一测试数据并对其进行协议转换，所述第一测试数据包括配置数据、测试用例、第一计算结果和测试指令；根据所述配置数据对自身和自身包含的待测IP进行配置，将所述测试用例和所述第一计算结果写入内存，将所述测试指令发送至待测IP；接收所述待测IP生成的中断信号和所述待测IP根据所述测试用例及所述测试指令进行计算生成的第二计算结果，将所述第二计算结果与所述第一计算结果进行比对，将比对结果发送至外部计算机。
在一实施例中，所述处理器用于运行所述计算机程序时，执行：将所述第一测试数据使用的协议转换成AXI协议。
在一实施例中，所述处理器用于运行所述计算机程序时，执行：通过APB桥对自身和自身包含的待测IP进行配置。
在一实施例中，所述处理器用于运行所述计算机程序时，执行：通过USB接口接收所述外部计算机的第一测试数据。
如图2所示，本发明实施例的一种验证平台，所述验证平台基于FPGA实现，包括通过片上总线互联的第二接口转换模块、平台配置模块、第二待测IP模块和第二内存模块，其中：
所述第二接口转换模块，配置为接收外部计算机的第二测试数据并对其进行协议转换，所述第二测试数据包括配置数据、测试用例和测试指令； 将所述配置数据输出至所述第二待测IP模块和平台配置模块，将所述测试用例输出至所述第二内存模块，将所述测试指令输出至所述第二待测IP模块；还配置为接收所述第二待测IP模块的中断信号和第二计算结果，将第二计算结果输出至外部计算机；
所述平台配置模块，配置为根据接收的配置数据，对自身所属FPGA进行配置；
所述第二待测IP模块，配置为根据接收的配置数据，对自身进行配置；根据接收的测试指令，从所述第二内存模块获取测试用例并进行计算，生成第二计算结果，将所述第二计算结果输出至所述第二接口转换模块，产生中断信号并输出至第二接口转换模块；
所述第二内存模块，配置为存储测试用例。
需要说明的是，所述外部计算机根据算法C模型，生成数据源以及第一计算结果；当外部计算机接收到第二计算结果后，将第一计算结果和第二计算结果进行比对，如果一致，则测试通过，执行下一个测试用例；反之，则记录当前测试用例，同时开始执行下一个测试用例。
在一实施例中，所述片上总线为AXI总线。
在一实施例中，所述第二接口转换模块为AXI总线的主设备。
在一实施例中，所述第二待测IP模块和平台配置模块之间通过APB桥互联，所述APB桥与AXI总线之间为AXI接口。
在一实施例中，所述AXI总线和第二待测IP模块之间的数据宽度为128比特或64比特。
在一实施例中，所述第二接口转换模块与外部计算机之间通过USB接口连接。
在一实施例中，所述平台配置模块接收的配置数据包括自身所属的FPGA的时钟、复位、模式等。
本发明实施例还提供了一种验证平台，包括：处理器和用于存储能够在处理器上运行的计算机程序的存储器，其中，所述处理器用于运行所述计算机程序时，执行：接收外部计算机的第二测试数据并对其进行协议转换，所述第二测试数据包括配置数据、测试用例和测试指令；根据所述配置数据对自身和自身包含的待测IP进行配置，将所述测试用例写入内存，将所述测试指令发送至待测IP；接收所述待测IP生成的中断信号和所述待测IP根据所述测试用例及所述测试指令进行计算生成的第二计算结果，将所述第二计算结果发送至外部计算机。
基于前述实施例提供的验证平台，如图3所示，为本发明实施例的一种验证方法，包括：
步骤301：FPGA验证平台接收外部计算机的第一测试数据并对其进行协议转换，所述第一测试数据包括配置数据、测试用例、第一计算结果和测试指令。
需要说明的是，所述FPGA验证平台对所述第一测试数据进行协议转换时，将第一测试数据使用的协议转换成片上总线支持的协议，所述片上总线可以为AXI总线。
本实施例中，所述FPGA验证平台通过USB接口接收外部计算机的第一测试数据。
步骤302：FPGA验证平台根据接收的配置数据对自身和自身包含的待测IP进行配置，将所述测试用例和所述第一计算结果写入内存，将所述测试指令发送至待测IP。
在一实施例中，所述FPGA验证平台通过APB桥对自身和自身包含的待测IP进行配置。
在一实施例中，所述FPGA验证平台对自身进行配置时，具体包括：所述FPGA验证平台对自身的时钟、复位、模式等进行配置。
在一实施例中，所述AXI总线和待测IP之间的数据宽度为128比特或64比特。
步骤303：FPGA验证平台接收待测IP生成的中断信号和所述待测IP根据测试用例及所述测试指令进行计算生成的第二计算结果，将所述第二计算结果与所述第一计算结果进行比对，将比对结果发送至外部计算机。
需要说明的是，本发明实施例中所述的比对操作可以在外部计算机中实现，也可以在本发明实施例的FPGA验证平台中实现，当在FPGA验证平台中实现时，通过FPGA硬件加速比对，可以减少外部计算机的负担，也可以提高验证的效率。
本发明实施例还提供了一种计算机存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现：接收外部计算机的第一测试数据并对其进行协议转换，所述第一测试数据包括配置数据、测试用例、第一计算结果和测试指令；根据所述配置数据对自身和自身包含的待测IP进行配置，将所述测试用例和所述第一计算结果写入内存，将所述测试指令发送至待测IP；接收所述待测IP生成的中断信号和所述待测IP根据所述测试用例及所述测试指令进行计算生成的第二计算结果，将所述第二计算结果与所述第一计算结果进行比对，将比对结果发送至外部计算机。
在一实施例中，该计算机程序被处理器执行时实现：将所述第一测试数据使用的协议转换成AXI协议。
在一实施例中，该计算机程序被处理器执行时实现：通过APB桥对自身和自身包含的待测IP进行配置。
在一实施例中，该计算机程序被处理器执行时实现：通过USB接口接收所述外部计算机的第一测试数据。
如图4所示，为本发明实施例的另一种验证方法，包括：
步骤401：FPGA验证平台接收外部计算机的第二测试数据并对其进行 协议转换，所述第二测试数据包括配置数据、测试用例和测试指令。
需要说明的是，所述FPGA验证平台对所述第二测试数据进行协议转换时，将所述第二测试数据使用的协议转换成片上总线支持的协议，所述片上总线可以为AXI总线。
本实施例中，所述FPGA验证平台通过USB接口接收外部计算机的第二测试数据。
步骤402：FPGA验证平台根据接收的配置数据对自身和自身包含的待测IP进行配置，将所述测试用例写入内存，将所述测试指令发送至待测IP。
在一实施例中，所述FPGA验证平台通过APB桥对自身和自身包含的待测IP进行配置。
在一实施例中，所述FPGA验证平台对自身进行配置时，具体包括：所述FPGA验证平台对自身的时钟、复位、模式等进行配置。
在一实施例中，所述AXI总线和待测IP之间的数据宽度为128比特或64比特。
步骤403：FPGA验证平台接收所述待测IP生成的中断信号和所述待测IP根据所述测试用例及所述测试指令进行计算生成的第二计算结果，将所述第二计算结果发送至外部计算机。
需要说明的是，所述外部计算机根据算法C模型，生成数据源以及第一计算结果；当外部计算机接收到第二计算结果后，将所述第一计算结果和所述第二计算结果进行比对，如果一致，则测试通过，执行下一个测试用例；反之，则记录当前测试用例，同时开始执行下一个测试用例。
本发明实施例还提供了一种计算机存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现：接收外部计算机的第二测试数据并对其进行协议转换，所述第二测试数据包括配置数据、测试用例和测试指令；根据所述配置数据对自身和自身包含的待测IP进行配置，将所述测试用例 写入内存，将所述测试指令发送至待测IP；接收所述待测IP生成的中断信号和所述待测IP根据所述测试用例及所述测试指令进行计算生成的第二计算结果，将所述第二计算结果发送至外部计算机。
以下通过一个具体实施例，具体说明本发明实施例的FPGA验证平台。值得注意的是，以下的具体实施例只是为了更好的描述本发明，并不构成对本发明不当的限定。
如图5所示，本发明实施例所述的FPGA验证平台包括以下模块：
USB接口、协议转换模块、AXI-AXI桥、AXI-APB桥、平台配置模块、比对模块、待测IP、DDR内存和状态显示模块，其中，
上述模块之间的关系是：
USB接口实现FPGA验证平台与外部计算机(PC)之间的USB3.0高速通信；
协议转换模块将USB接口解码的数据与指令转换成AMBA的标准AXI协议，并作为AXI128的主设备(Master)，通过AXI-AXI桥互联了待测IP、AXI-APB桥、平台配置模块、DDR内存和比对模块；
AXI-APB桥，互联待测IP和平台配置模块，配置为对待测IP和平台自身进行配置；
待测IP与AXI-AXI桥之间的数据宽度可以为128比特或64比特；
DDR内存通过DDR控制器挂载了4GB的DDR内存条，用作测试用例、PC计算结果及待测IP计算结果的缓存；
比对模块，配置为获取DDR中的PC计算结果及待测IP计算结果，进行比对，并将比对结果返回至PC；
状态显示模块，配置为显示当前的工作状态或工作模式。
根据算法C模型，在PC端生成数据源以及PC计算结果；同时将生成的数据源及PC计算结果通过USB3.0传输到下位机，配置待测IP开始工作 并等待待测IP发送的中断信号；待中断信号收到后，比对待测IP计算结果和PC计算结果，如果比对通过，则执行下一个测试用例；反之，则记录当前测试用例，同时开始执行下一个测试用例。
整体系统的工作性能取决于USB3.0的通信有效带宽、待测IP以及DDR内存的工作频率，同时PC的性能以及算法C模型的执行效率也很大程度上决定了整体系统的瓶颈。如果PC性能太低不足以全速USB3.0通信，或者算法C模型的执行效率低下，跟不上FPGA硬件计算结果的周期，则一定程度上也会成为高速比对的一个瓶颈。同时PC端批处理程序的自动化程度，决定了整体系统高速测试的一个方便程度。
本发明实施例提供的验证平台和验证方法，将硬件电路直接置于FPGA进行运算，利用FPGA高速并行阵列运算的特点，构建了一套高速的PC与FPGA硬件通信的平台，缓减了CPU运算的压力，成千上万倍地提高了ASIC前期IP验证的效率，解决了IP验证成为IP研发效率瓶颈的难题，彻底将随机验证转变为完整验证，提高了IC流片的周期与成功率。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
或者，本发明上述集成的单元如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：移动存储设备、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
工业实用性
本发明实施例的技术方案将硬件电路直接置于FPGA进行运算，利用FPGA高速并行阵列运算的特点，构建了高速的PC与FPGA硬件通信的平 台，缓减了CPU运算的压力，成千上万倍地提高了ASIC前期IP验证的效率，解决了IP验证成为IP研发效率瓶颈的难题，彻底将随机验证转变为完整验证，提高了IC流片的周期与成功率。

Claims (12)

  1. 一种验证平台，所述验证平台基于现场可编程门阵列FPGA实现，包括通过片上总线互联的第一接口转换模块、平台配置模块、第一待测IP模块、第一内存模块和比对模块，其中：
    所述第一接口转换模块，配置为接收外部计算机的第一测试数据并对其进行协议转换，所述第一测试数据包括配置数据、测试用例、第一计算结果和测试指令；将所述配置数据输出至所述第一待测IP模块和所述平台配置模块，将所述测试用例和所述第一计算结果输出至所述第一内存模块，将所述测试指令输出至所述第一待测IP模块；还配置为接收所述比对模块的比对结果，输出至外部计算机；
    所述平台配置模块，配置为根据接收的配置数据，对自身所属FPGA进行配置；
    所述第一待测IP模块，配置为根据接收的配置数据，对自身进行配置；根据测试指令，从所述第一内存模块获取测试用例并进行计算，生成第二计算结果，将第二计算结果存储至所述第一内存模块，产生中断信号并输出至所述比对模块；
    所述比对模块，配置为接收到中断信号，从所述第一内存模块中获取第一计算结果和第二计算结果并进行比对，将比对结果发送至所述第一接口转换模块；
    所述第一内存模块，配置为存储测试用例、第一计算结果和第二计算结果。
  2. 根据权利要求1所述的验证平台，其中，所述片上总线为高级可扩展接口AXI总线。
  3. 根据权利要求1或2所述的验证平台，其中，所述第一待测IP模块和所述平台配置模块之间通过高级外围总线APB桥互联。
  4. 根据权利要求1所述的验证平台，其中，所述第一接口转换模块和所述外部计算机之间通过通用串行总线USB接口连接。
  5. 一种验证平台，所述验证平台基于现场可编程门阵列FPGA实现，包括通过片上总线互联的第二接口转换模块、平台配置模块、第二待测IP模块和第二内存模块，其中：
    所述第二接口转换模块，配置为接收外部计算机的第二测试数据并对其进行协议转换，所述第二测试数据包括配置数据、测试用例和测试指令；将所述配置数据输出至所述第二待测IP模块和所述平台配置模块，将所述测试用例输出至所述第二内存模块，将所述测试指令输出至所述第二待测IP模块；还配置为接收所述第二待测IP模块的中断信号和第二计算结果，将所述第二计算结果输出至外部计算机；
    所述平台配置模块，配置为根据接收的配置数据，对自身所属FPGA进行配置；
    所述第二待测IP模块，配置为根据接收的配置数据，对自身进行配置；根据接收的测试指令，从所述第二内存模块获取测试用例并进行计算，生成第二计算结果，将所述第二计算结果输出至所述第二接口转换模块，产生中断信号并输出至所述第二接口转换模块；
    所述第二内存模块，配置为存储测试用例。
  6. 一种验证方法，包括：
    接收外部计算机的第一测试数据并对其进行协议转换，所述第一测试数据包括配置数据、测试用例、第一计算结果和测试指令；
    根据所述配置数据对自身和自身包含的待测IP进行配置，将所述测试用例和所述第一计算结果写入内存，将所述测试指令发送至待测IP；
    接收所述待测IP生成的中断信号和所述待测IP根据所述测试用例及所述测试指令进行计算生成的第二计算结果，将所述第二计算结果与所述第 一计算结果进行比对，将比对结果发送至外部计算机。
  7. 根据权利要求6所述的验证方法，其中，对所述第一测试数据进行协议转换，包括：将所述第一测试数据使用的协议转换成高级可扩展接口AXI协议。
  8. 根据权利要求6或7所述的验证方法，其中，所述对自身和自身包含的待测IP进行配置，包括：通过高级外围总线APB桥对自身和自身包含的待测IP进行配置。
  9. 根据权利要求6所述的验证方法，其中，所述接收外部计算机的第一测试数据，包括：通过USB接口接收所述外部计算机的第一测试数据。
  10. 一种验证方法，包括：
    接收外部计算机的第二测试数据并对其进行协议转换，所述第二测试数据包括配置数据、测试用例和测试指令；
    根据所述配置数据对自身和自身包含的待测IP进行配置，将所述测试用例写入内存，将所述测试指令发送至待测IP；
    接收所述待测IP生成的中断信号和所述待测IP根据所述测试用例及所述测试指令进行计算生成的第二计算结果，将所述第二计算结果发送至外部计算机。
  11. 一种计算机存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现权利要求6至9任一项所述方法的步骤；
    或者，该计算机程序被处理器执行时实现权利要求10所述方法的步骤。
  12. 一种验证平台，包括：处理器和用于存储能够在处理器上运行的计算机程序的存储器，
    其中，所述处理器用于运行所述计算机程序时，执行权利要求6至9任一项所述方法的步骤，或者，执行权利要求10所述方法的步骤。
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