WO2018218769A1 - 薄膜晶体管制造方法及阵列基板的制作方法 - Google Patents

薄膜晶体管制造方法及阵列基板的制作方法 Download PDF

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WO2018218769A1
WO2018218769A1 PCT/CN2017/094550 CN2017094550W WO2018218769A1 WO 2018218769 A1 WO2018218769 A1 WO 2018218769A1 CN 2017094550 W CN2017094550 W CN 2017094550W WO 2018218769 A1 WO2018218769 A1 WO 2018218769A1
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oxide semiconductor
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李金明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
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    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials

Definitions

  • the present invention claims the priority of the prior art application entitled “Thin-film transistor manufacturing method and method for fabricating an array substrate”, which is incorporated herein by reference. This.
  • the present invention relates to the field of thin film transistor manufacturing technology, and in particular, to a method for fabricating a thin film transistor and a method for fabricating an array substrate.
  • TFT LCD Thin-Film-Transistor Liquid Crystal Display
  • the existence of parasitic capacitance can be reduced, but the metal conductor oxide film is very sensitive to acid, and even a weak acid can quickly etch the oxide semiconductor, and the plasma
  • the doping treatment has poor stability, and the metal doping has the problem of uneven oxide. Therefore, the current conductor treatment process is an urgent problem to be solved.
  • the present invention provides a method of fabricating a thin film transistor which can improve the uniformity of metal doping in an oxide semiconductor.
  • the invention also provides a method for fabricating an array substrate.
  • a method of manufacturing a thin film transistor of the present invention comprising: sequentially forming a buffer layer, an oxide semiconductor layer, a gate insulating layer and a gate electrode sequentially stacked on a first region of the oxide semiconductor layer on a substrate; Two sides of the first region of the oxide semiconductor layer are second regions and expose the gate;
  • Aluminum ions form a conductor region
  • An insulating layer is laminated on the buffer layer, the gate electrode, and the conductor region, and a source and a drain connecting the two conductor regions through the via holes are formed on the insulating layer.
  • the method of forming a buffer layer, a second region of the oxide semiconductor layer, and an aluminum layer of the gate electrode by a physical vapor deposition method, and performing the annealing treatment on the aluminum layer the aluminum layer has a thickness of 20 ⁇ 200A, annealing temperature is 100-400 degrees.
  • the annealing temperature is 100 to 400 degrees in the step of annealing the surface of the buffer layer, the gate and the conductor region to be etched, and oxidizing the conductor region by annealing.
  • the step of sequentially forming a buffer layer, an oxide semiconductor layer, and a gate insulating layer and a gate layer sequentially stacked on the first region of the oxide semiconductor layer on the substrate include:
  • the oxide material layer is patterned to form the oxide semiconductor layer.
  • the step of sequentially forming a buffer layer, an oxide semiconductor layer, and a gate insulating layer and a gate electrode sequentially stacked on the first region of the oxide semiconductor layer on the substrate further includes:
  • a metal layer is deposited on the gate insulating layer by physical vapor deposition and a metal layer is patterned to form the gate.
  • the gate insulating layer is a composite layer of silicon oxide (SiOx) or silicon nitride (SiNx) and silicon oxide (SiOx); and the gate material is one of aluminum, molybdenum, copper, and titanium. Or composite metal.
  • the step of laminating an insulating layer on the buffer layer, the gate and the conductor region, and forming a source and a drain respectively connecting the two conductor regions through the via hole on the insulating layer comprises: using plasma chemistry Depositing the insulating layer by a vapor deposition process, and forming a via hole communicating with the conductor region on the insulating layer by a patterning process;
  • Patterning the metal layer forms the source and drain.
  • the thickness of the oxide material layer is 300 to 1000 angstroms.
  • the insulating layer is a composite layer of silicon oxide (SiOx) or silicon nitride (SiNx) and silicon oxide (SiOx).
  • the buffer layer material is silicon oxide (SIOx), and the deposition thickness is 2,000 to 5,500 angstroms.
  • the method for fabricating the array substrate provided by the method includes:
  • a display element is formed on the thin film transistor.
  • the method for fabricating a thin film transistor according to the present invention uses an annealing process to implant a metal ion covering the oxide semiconductor layer into the oxide semiconductor layer to form a conductor structure, thereby ensuring uniformity of metal doping in the oxide, thereby ensuring performance of the thin film transistor. .
  • FIG. 1 is a flow chart of a method of fabricating a thin film transistor according to the present invention.
  • FIG. 2 to FIG. 5 are schematic diagrams showing respective steps of the method for fabricating the thin film transistor illustrated in FIG. 1.
  • FIG. 6 is a flow chart of a method for manufacturing an array substrate according to the present invention.
  • the present invention provides a method for fabricating a thin film transistor, which is particularly suitable for fabricating a top gate metal oxide thin film crystal.
  • the method includes:
  • step S1 sequentially forming a buffer layer 11, an oxide semiconductor layer 12, a gate insulating layer 13 and a gate electrode 14 sequentially stacked on the first region 121 of the oxide semiconductor layer 12;
  • the two sides of the first region 121 of the oxide semiconductor layer 12 are the second region 122 and expose the gate electrode 14.
  • This step specifically includes:
  • An oxide material layer (not shown) is deposited on the buffer layer 11 by physical vapor deposition; the oxide material layer has a thickness of 300 to 1000 angstroms.
  • the oxide material layer is patterned to form the oxide semiconductor layer 12.
  • a metal layer is deposited on the gate insulating layer 13 by physical vapor deposition and a metal layer is patterned to form the gate electrode 14.
  • the patterning refers to processing a whole layer to form a pattern by a process such as a yellow light process, exposure, etching, or the like.
  • the gate insulating layer 13 is a composite layer of silicon oxide (SiOx) or silicon nitride (SiNx) and silicon oxide (SiOx).
  • the material of the gate electrode 14 is one of aluminum, molybdenum, copper, titanium or a composite metal.
  • the materials of the gate insulating layer 13 and the gate electrode 14 do not limit the types of materials described above.
  • the buffer layer 11 is made of silicon oxide (SIOx) and has a thickness of 2,000 to 5,500 angstroms.
  • step S2 an aluminum layer 15 covering the buffer layer 11, the second region 122 of the oxide semiconductor layer 12, and the gate electrode 14 is formed by a physical vapor deposition method, and the aluminum layer 15 is annealed.
  • the second region 122 of the oxide semiconductor layer 12 is doped with aluminum ions to form the conductor region 16.
  • the aluminum layer has a thickness of 20 to 200 A and an annealing temperature of 100 to 400 degrees.
  • the purpose of this step is to diffuse aluminum into the second region 122 of the oxide semiconductor layer 12 for conductorization.
  • step S3 the remaining aluminum layer remaining in the second region 122 covering the buffer layer 11 and the oxide semiconductor layer 12 after the annealing treatment is etched away.
  • this step mainly after the annealing in the previous step, part of the aluminum ions enter the second region 122 of the oxide semiconductor layer 12, but The buffer layer 11, the second region 122 of the oxide semiconductor layer 12 (that is, the conductor region 16), and the surface of the gate 14 still have an aluminum layer remaining thereon, so that the remaining aluminum layer is removed by etching to avoid affecting the thin film transistor. Subsequent processes and performance.
  • step S4 the buffer layer 11, the gate electrode 14 and the surface of the oxide semiconductor layer 12 on which the conductor region 16 is etched are repaired by annealing and the conductor region 16 is oxidized.
  • the annealing temperature is 100 to 400 degrees.
  • the surface of the annealed conductor region 16 is flat and the conductor region 16 is oxidized to promote the bonding of the aluminum ions to ensure the conductor region.
  • step S5 an insulating layer 17 is laminated on the buffer layer 11, the gate electrode 14 and the conductor region 16, and a source connecting the two conductor regions 16 through the via holes 171 is formed on the insulating layer 17. 18 and drain 19.
  • the insulating layer is a composite layer of silicon oxide (SiOx) or silicon nitride (SiNx) and silicon oxide (SiOx).
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiOx silicon oxide
  • the method includes: depositing the insulating layer 17 by a plasma chemical vapor deposition process, and forming a via hole communicating with the conductor region 16 on the insulating layer 17 by a patterning process;
  • Patterning the metal layer forms the source 18 and the drain 19.
  • the source 18 and the drain 19 are connected to the corresponding conductor region 16 through via holes.
  • the method for fabricating a thin film transistor according to the present invention uses an annealing process to implant a metal ion covering the oxide semiconductor layer into the oxide semiconductor layer to form a conductor structure, thereby ensuring uniformity of metal doping in the oxide, thereby ensuring performance of the thin film transistor. .
  • the present invention also provides a method for fabricating an array substrate, including
  • step S21 a substrate is provided.
  • the substrate is a glass plate.
  • Step S22 forming the thin film transistor on the surface of the substrate.
  • the thin film transistor is formed by the above method.
  • Step S23 forming a display element on the thin film transistor.
  • the display element is an organic light emitting diode or a pixel electrode and a common electrode.

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  • Thin Film Transistor (AREA)

Abstract

本发明提供一种薄膜晶体管制造方法，包括矩阵排列的数个像素电极，每个像素电极包括第一电极区域及与第一电极区域连接的第二电极区域，第一电极区域包括第一外围电极及均设有多个第一分支电极的四个第一子区域，所述第一分支电极倾斜设置且相较于所述第一外围电极呈夹角；所述第二电极区域包括第二外围电极及均设有多个第二分支电极的四个第二子区域，所述四个第二子区域中，两个第二子区域内的第二分支电极横向设置，另外两个第二子区域的第二分支电极纵向设置。

Description

薄膜晶体管制造方法及阵列基板的制作方法
本发明要求2017年6月2日递交的发明名称为“薄膜晶体管制造方法及阵列基板的制作方法”的申请号201710408480.9的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及薄膜晶体管制造技术领域，尤其涉及薄膜晶体管制造方法及阵列基板的制作方法。
背景技术
TFT LCD(Thin-Film-Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)由于其高速度、高亮度、高对比度等优点，目前已经得到普遍的应用。其中，在顶栅金属氧化物薄膜晶体结构中，可以减少寄生电容的存在具有明显优势，但是，其中的金属导体氧化物薄膜对酸非常敏感，即便是弱酸也能快速腐蚀氧化物半导体，而等离子注入掺杂处理稳定性较差，金属掺杂存在氧化物不均匀的问题，所以目前导体化处理工艺是目前急需解决的问题。
发明内容
本发明提供一种薄膜晶体管制造方法，可以提高金属掺杂在氧化物半导体的均匀性。
本发明还提供一种阵列基板的制作方法。
本发明的薄膜晶体管制造方法，所述方法包括，在基板上依次形成缓冲层、氧化物半导体层、依次层叠于所述氧化物半导体层的第一区域上的栅极绝缘层及栅极；其中所述氧化物半导体层的第一区域的两侧为第二区域并露出所述栅极；
采用物理气相沉积方法形成覆盖所述缓冲层、氧化物半导体层的第二区域及栅极的铝层，并且对该铝层进行退火处理，使所述氧化物半导体层的第二区域被掺杂铝离子形成导体区域；
蚀刻掉残留在覆盖所述缓冲层、氧化物半导体层的第二区域的经过所述退火处理后的剩余的铝层；
采用退火对所述缓冲层、栅极及导体区域被蚀刻的表面进行修复以及对导体区域进行氧化处理；
在所述缓冲层、栅极及导体区域上层叠绝缘层并在所述绝缘层上形成通过通孔分别连接两个导体区域的源极和漏极。
其中，所述采用物理气相沉积方法形成覆盖所述缓冲层、氧化物半导体层的第二区域及栅极的铝层，并且对该铝层进行退火处理的步骤中，所述铝层厚度为20～200A，退火温度为100～400度。
所述采用退火对所述缓冲层、栅极及导体区域被蚀刻的表面进行修复以及对导体区域进行氧化处理的步骤中，退火温度为100～400度。
其中，所所述在基板上依次形成缓冲层、氧化物半导体层、依次层叠于所述氧化物半导体层的第一区域上的栅极绝缘层及栅极的步骤包括：
采用等离子化学气沉积方式形成所述缓冲层；
利用物理气相沉积方式在缓冲层上沉积形成氧化物材料层；
以退火温度为150～450℃进行退火处理氧化物材料层；
图案化所述氧化物材料层形成所述氧化物半导体层。
其中，所所述在基板上依次形成缓冲层、氧化物半导体层、依次层叠于所述氧化物半导体层的第一区域上的栅极绝缘层及栅极的步骤还包括：
采用等离子化学气沉积方式形成所述栅极绝缘层；
采用物理气相沉积方式在栅极绝缘层上沉积金属层并图案化金属层形成所述栅极。
其中，所所述栅极绝缘层为氧化硅(SiOx)或者氮化硅(SiNx)和氧化硅(SiOx)的复合层；，所述栅极材料为铝、钼、铜、钛中的一种或复合金属。
其中，所所述在所述缓冲层、栅极及导体区域上层叠绝缘层并在所述绝缘层上形成通过通孔分别连接两个导体区域的源极和漏极的步骤包括：采用等离子化学气相沉积工艺沉积所述绝缘层，并通过图案化工艺在绝缘层上形成与所述导体区域连通的通孔；
采用物理气相沉积方式在绝缘层上沉积金属层；
图案化所述金属层形成所述源极和漏极。
其中，所所述利用物理气相沉积方式在缓冲层上沉积形成氧化物材料层的步骤中，所述氧化物材料层的厚度为300～1000埃。
其中，所所述绝缘层为氧化硅(SiOx)或者氮化硅(SiNx)和氧化硅(SiOx)的复合层。
其中，所所述缓冲层材料为氧化硅(SIOx)，沉积厚度2000～5500埃。
本方法提供的阵列基板的制作方法，包括：
提供一基板，在所述基板表面上形成所述的薄膜晶体管；
在所述的薄膜晶体管上形成显示元件。
本发明所述的薄膜晶体管制造方法采用退火处理将覆盖氧化物半导体层的金属离子注入氧化物半导体层内形成导体结构，保证了金属掺杂在氧化物的均匀性，进而保证了薄膜晶体管的性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明所述的薄膜晶体管制造方法流程图。
图2至图5为图1所述的薄膜晶体管制造方法各个步骤示意图。
图6为本发明所述的阵列基板制造方法流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明提供一种薄膜晶体管制造方法，特别适用于制作顶栅金属氧化物薄膜晶体。所述方法包括：
如图2，步骤S1，在基板10上依次形成缓冲层11、氧化物半导体层12、依次层叠于所述氧化物半导体层12的第一区域121上的栅极绝缘层13及栅极14；其中所述氧化物半导体层12的第一区域121的两侧为第二区域122并露出所述栅极14。
本步骤具体包括：
采用等离子化学气沉积方式形成所述缓冲层11；
利用物理气相沉积方式在缓冲层11上沉积形成氧化物材料层(图未示)；所述氧化物材料层的厚度为300～1000埃。
以退火温度为150～450℃进行退火处理氧化物材料层；
图案化所述氧化物材料层形成所述氧化物半导体层12。
还包括：
采用等离子化学气沉积方式形成所述栅极绝缘层13；
采用物理气相沉积方式在栅极绝缘层13上沉积金属层并图案化金属层形成所述栅极14。其中，所述图案化是指通过黄光工艺、曝光、蚀刻等工艺加工整层形成图案。
本实施例中，所述栅极绝缘层13为氧化硅(SiOx)或者氮化硅(SiNx)和氧化硅(SiOx)的复合层。所述栅极14材料为铝、钼、铜、钛中的一种或复合金属。当然，栅极绝缘层13、栅极14的材料不限定上述所述的材料类型。
所述缓冲层11材料为氧化硅(SIOx)，沉积的厚度为2000～5500埃。
请参阅图3，步骤S2，采用物理气相沉积方法形成覆盖所述缓冲层11、氧化物半导体层12的第二区域122及栅极14的铝层15，并且对该铝层15进行退火处理，使所述氧化物半导体层12的第二区域122被掺杂铝离子形成导体区域16。通过退火处理将铝离子输入到氧化物半导体层中形成导体层，可以保证离子注入的均匀性，进而保证了导体层的稳定性。
本实施例中，所述铝层厚度为20～200A，退火温度为100～400度。本步骤目的是使铝扩散到氧化物半导体层12的第二区域122中进行导体化。
参阅图4，步骤S3，蚀刻掉残留在覆盖所述缓冲层11、氧化物半导体层12的第二区域122的经过所述退火处理后的剩余的铝层。本步骤中，主要是在上一步退火后，部分铝离子进入了氧化物半导体层12的第二区域122，但 是缓冲层11、氧化物半导体层12的第二区域122(也就是导体区域16)及栅极14的表面上还残留有铝层，所以通过蚀刻的方式去除剩余的铝层，避免影响薄膜晶体管后续制程及性能。
步骤S4，采用退火对缓冲层11、栅极14及所述氧化物半导体层12的形成导体区域16被蚀刻的表面进行修复以及对导体区域16进行氧化处理。本步骤中，退火温度为100～400度。经过退火处理的导体区域16的表面平整，同时对导体区域16进行氧化，是促进铝离子充分结合保证导体区域的性能。
请参阅图5，步骤S5，在所述缓冲层11、栅极14及导体区域16上层叠绝缘层17并在所述绝缘层17上形成通过通孔171分别连接两个导体区域16的源极18和漏极19。所述绝缘层为氧化硅(SiOx)或者氮化硅(SiNx)和氧化硅(SiOx)的复合层。当然，不限定上述所述的材料类型。
包括：采用等离子化学气相沉积工艺沉积所述绝缘层17，并通过图案化工艺在绝缘层17上形成与所述导体区域16连通的通孔；
采用物理气相沉积方式在绝缘层17上沉积金属层；
图案化所述金属层形成所述源极18和漏极19。源极18和漏极19通过通孔与对应的导体区域16连接。
本发明所述的薄膜晶体管制造方法采用退火处理将覆盖氧化物半导体层的金属离子注入氧化物半导体层内形成导体结构，保证了金属掺杂在氧化物的均匀性，进而保证了薄膜晶体管的性能。
请参照图6，本发明还提供一阵列基板的制作方法，包括
步骤S21，提供一基板。所述基板为玻璃板。
步骤S22，在所述基板表面上形成所述的薄膜晶体管。其中薄膜晶体管是通过上述方法形成。
步骤S23，在所述的薄膜晶体管上形成显示元件。所述显示元件为有机发光二极管或者像素电极和公共电极。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种薄膜晶体管制造方法，其中所述方法包括，
    在基板上依次形成缓冲层、氧化物半导体层、依次层叠于所述氧化物半导体层的第一区域上的栅极绝缘层及栅极；其中所述氧化物半导体层的第一区域的两侧为第二区域并露出所述栅极；
    采用物理气相沉积方法形成覆盖所述缓冲层、氧化物半导体层的第二区域及栅极的铝层，并且对该铝层进行退火处理，使所述氧化物半导体层的第二区域被掺杂铝离子而形成导体区域；
    蚀刻掉残留在覆盖所述缓冲层、导体区域的经过所述退火处理后的剩余的铝层；
    采用退火对所述缓冲层、栅极及导体区域被蚀刻的表面进行修复以及对导体区域进行氧化处理；
    在所述缓冲层、栅极及导体区域上层叠绝缘层并在所述绝缘层上形成通过通孔分别连接两个导体区域的源极和漏极。
  2. 如权利要求1所述的薄膜晶体管制造方法，其中所述采用物理气相沉积方法形成覆盖所述缓冲层、氧化物半导体层的第二区域及栅极的铝层，并且对该铝层进行退火处理的步骤中，所述铝层厚度为20～200A，退火温度为100～400度。
  3. 如权利要求1所述的薄膜晶体管制造方法，其中所述采用退火对所述缓冲层、栅极及导体区域被蚀刻的表面进行修复以及对导体区域进行氧化处理的步骤中，退火温度为100～400度。
  4. 如权利要求1所述的薄膜晶体管制造方法，其中所述在基板上依次形成缓冲层、氧化物半导体层、依次层叠于所述氧化物半导体层的第一区域上的栅极绝缘层及栅极的步骤包括：
    采用等离子化学气沉积方式形成所述缓冲层；
    利用物理气相沉积方式在缓冲层上沉积形成氧化物材料层；
    以退火温度为150～450℃进行退火处理氧化物材料层；
    图案化所述氧化物材料层形成所述氧化物半导体层。
  5. 如权利要求4所述的薄膜晶体管制造方法，其中所述在基板上依次形成缓冲层、氧化物半导体层、依次层叠于所述氧化物半导体层的第一区域上的栅极绝缘层及栅极的步骤还包括：
    采用等离子化学气沉积方式形成所述栅极绝缘层；
    采用物理气相沉积方式在栅极绝缘层上沉积金属层并图案化金属层形成所述栅极。
  6. 如权利要求5所述的薄膜晶体管制造方法，其中所述栅极绝缘层为氧化硅(SiOx)或者氮化硅(SiNx)和氧化硅(SiOx)的复合层；，所述栅极材料为铝、钼、铜、钛中的一种或复合金属。
  7. 如权利要求1所述的薄膜晶体管制造方法，其中所述在所述缓冲层、栅极及导体区域上层叠绝缘层并在所述绝缘层上形成通过通孔分别连接两个导体区域的源极和漏极的步骤包括：采用等离子化学气相沉积工艺沉积所述绝缘层，并通过图案化工艺在绝缘层上形成与所述导体区域连通的通孔；
    采用物理气相沉积方式在绝缘层上沉积金属层；
    图案化所述金属层形成所述源极和漏极。
  8. 如权利要求4所述的薄膜晶体管制造方法，其中所述利用物理气相沉积方式在缓冲层上沉积形成氧化物材料层的步骤中，所述氧化物材料层的厚度为300～1000埃。
  9. 如权利要求7所述的薄膜晶体管制造方法，其中所述缓冲层材料为氧化硅(SIOx)，沉积厚度2000～5500埃。
  10. 一种阵列基板的制作方法，其中包括：
    提供一基板；
    在所述基板表面上形成的薄膜晶体管；包括，在基板上依次形成缓冲层、氧化物半导体层、依次层叠于所述氧化物半导体层的第一区域上的栅极绝缘层及栅极；其中所述氧化物半导体层的第一区域的两侧为第二区域并露出所述栅极；
    采用物理气相沉积方法形成覆盖所述缓冲层、氧化物半导体层的第二区域及栅极的铝层，并且对该铝层进行退火处理，使所述氧化物半导体层的第二区域被掺杂铝离子而形成导体区域；
    蚀刻掉残留在覆盖所述缓冲层、导体区域的经过所述退火处理后的剩余的铝层；
    采用退火对所述缓冲层、栅极及导体区域被蚀刻的表面进行修复以及对导体区域进行氧化处理；
    在所述缓冲层、栅极及导体区域上层叠绝缘层并在所述绝缘层上形成通过通孔分别连接两个导体区域的源极和漏极；
    在所述的薄膜晶体管上形成显示元件。
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