US20180350843A1 - Manufacturing method for thin film transistor and array substrate - Google Patents

Manufacturing method for thin film transistor and array substrate Download PDF

Info

Publication number
US20180350843A1
US20180350843A1 US15/570,260 US201715570260A US2018350843A1 US 20180350843 A1 US20180350843 A1 US 20180350843A1 US 201715570260 A US201715570260 A US 201715570260A US 2018350843 A1 US2018350843 A1 US 2018350843A1
Authority
US
United States
Prior art keywords
layer
gate electrode
oxide semiconductor
regions
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US15/570,260
Other versions
US10153308B1 (en
Inventor
Jinming LI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Assigned to SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD reassignment SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LI, Jinming
Publication of US20180350843A1 publication Critical patent/US20180350843A1/en
Application granted granted Critical
Publication of US10153308B1 publication Critical patent/US10153308B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/385—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H01L27/3262—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of the manufacturing method for a thin film transistor, in particular to a manufacturing method for a thin film transistor and an array substrate.
  • TFT LCD Thin-Film Transistor Liquid Crystal Display
  • a metal conductor oxide film in the top gate metal oxide thin film crystal structure is very sensitive to acid, since even weak acid can quickly corrode oxide semiconductor.
  • Plasma implantation doping treatment has poor stability, and metal doping treatment exists the problem of uneven oxide. Therefore, conductor processing technology is an urgent problem to be solved currently.
  • the present disclosure provides a method for manufacturing a thin film transistor for improving the uniformity of metal doping in an oxide semiconductor.
  • the present disclosure also provides a method for manufacturing an array substrate.
  • a method for manufacturing a thin film transistor according to the present disclosure comprising: forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer, wherein on both sides of the first region of the oxide semiconductor layer are second regions where the gate electrode is exposed;
  • the thickness of the aluminum layer is in a range of 20 ⁇ to 200 ⁇ and the annealing temperature is in a range of 100 to 400 degrees.
  • the annealing temperature is in a range of 100 to 400 degrees.
  • the step of forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer comprises:
  • annealing the oxide material layer at an annealing temperature of 150 to 450° C.
  • the step of forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer further comprises:
  • the gate insulating layer is made of silicon oxide (SiOx) or a composite layer of silicon oxide (SiOx) and silicon nitride (SiNx), and the material of the gate electrode is one or a composite metal of aluminum, molybdenum, copper, and titanium.
  • the step of stacking an insulating layer on the buffer layer, the gate electrode and the conductor regions, and forming a source electrode and a drain electrode on the insulating layer, the source electrode and the drain electrode respectively being connected to the two conductor regions through via holes comprises:
  • the thickness of the oxide material layer is in a range of 300 ⁇ to 1000 ⁇ .
  • the insulating layer is made of silicon oxide (SiOx) or a composite layer of silicon oxide (SiOx) and silicon nitride (SiNx).
  • the material of the buffer layer is silicon oxide (SiOx), and the deposited thickness of the buffer layer is in a range of 2000 ⁇ to 5500 ⁇ .
  • a method for manufacturing an array substrate provided by the present disclosure comprises:
  • the method for manufacturing a thin film transistor according to the present disclosure uses an annealing treatment to inject metal ions covering the oxide semiconductor layer into an oxide semiconductor layer to form a conductor structure, which ensures the uniformity of the metal doping in the oxide, thereby ensuring the performance of the thin film transistor.
  • FIG. 1 is a flowchart of a method for manufacturing the thin film transistor according to some embodiments of the present disclosure
  • FIG. 2 to FIG. 5 are schematic views showing the respective steps of the thin film transistor manufacturing method described in the FIG. 1 according to some embodiments of the present disclosure
  • FIG. 3 is a flowchart of a method for manufacturing the array substrate according to some embodiments of the present disclosure.
  • the present disclosure provides a method for manufacturing a thin film transistor, which is particularly suitable for the production of a top gate metal oxide thin film crystal, the method comprises:
  • S 1 forming a buffer layer 11 , an oxide semiconductor layer 12 , a gate insulating layer 13 , and a gate electrode 14 sequentially on a substrate 10 , and the gate insulating layer 13 and the gate electrode 14 being sequentially stacked on a first region 121 of the oxide semiconductor layer 12 .
  • the gate insulating layer 13 and the gate electrode 14 being sequentially stacked on a first region 121 of the oxide semiconductor layer 12 .
  • second regions 122 On both sides of the first region 121 of the oxide semiconductor layer 12 are second regions 122 where the gate electrode 14 is exposed.
  • This step specifically comprises:
  • the buffer layer 11 by using a plasma chemical vapor deposition method
  • an oxide material layer (not shown in FIG.) on the buffer layer 11 by a physical vapor deposition method, wherein the thickness of the oxide material layer is in a range of 300 ⁇ to 1000 ⁇ ;
  • This step further comprises:
  • patterning means that the entire layer is processed to form patterns by processes such as yellow light, exposure, etching and the like.
  • the gate insulating layer 13 is made of silicon oxide (SiOx) or a composite layer of silicon oxide (SiOx) and silicon nitride (SiNx).
  • the material of the gate electrode 14 is one or a composite metal of aluminum, molybdenum, copper, and titanium. Certainly, the materials of the gate insulating layer 13 and the gate electrode 14 are not limited to the materials described above.
  • the material of the buffer layer is silicon oxide (SiOx) and the deposited thickness of the buffer layer is in a range of 2000 ⁇ to 5500 ⁇ .
  • an aluminum layer 15 covering the buffer layer 11 , the second regions 122 of the oxide semiconductor layer 12 and the gate electrode 14 is formed by a physical vapor deposition method, and the aluminum layer 15 is annealed, which makes the second regions 122 of the oxide semiconductor layer 12 being doped by aluminum ions to form conductor regions 16 .
  • Aluminum ions are input to the oxide semiconductor layer to form a conductor layer by the annealing treatment, which can ensure the uniformity of ion implantation, thereby ensuring the stability of the conductor layer.
  • the thickness of the aluminum layer is in a range of 20 ⁇ to 200 ⁇ and the annealing temperature is in a range of 100 to 400 degrees.
  • the purpose of this step is to diffuse the aluminum into the second regions 122 of the oxide semiconductor layer 12 for making them conductive.
  • the remaining aluminum layer covering the buffer layer 11 and the second regions 122 of the oxide semiconductor layer 12 is etched after the annealing treatment.
  • a portion of the aluminum ion enters the second regions 122 of the oxide semiconductor layer 12 mainly after the annealing step, but still the aluminum layer is remaining on the surfaces of the buffer layer 11 , the second regions 122 of the oxide semiconductor layer 12 (i.e., the conductor regions 16 ) and the gate electrode 14 , thus the remaining aluminum layer is removed by etching to avoid affecting the subsequent process and performance of the thin film transistor.
  • the etched surfaces of the buffer layer 11 , the gate electrode 14 and the conductor regions 16 formed in the oxide semiconductor layer 12 are renovated by annealing process, and the conductor regions 16 are oxidized by annealing process.
  • the annealing temperature is in a range of 100 to 400 degrees.
  • the surface of the annealed conductor regions 16 is flat, while the conductor regions 16 are oxidized to promote sufficient bonding of the aluminum ions to ensure the performance of the conductor regions.
  • an insulating layer 17 is stacked on the buffer layer 11 , the gate electrode 14 and the conductor regions 16 .
  • a source electrode 18 and a drain electrode 19 are formed on the insulating layer 17 and connected to the two conductor regions 16 through via holes 171 , respectively.
  • the insulating layer is made of silicon oxide (SiOx) or a composite layer of silicon oxide (SiOx) and silicon nitride (SiNx). Certainly, the type of material described above is not limited.
  • This step further comprises:
  • the source electrode 18 and the drain electrode 19 are connected to the corresponding conductor regions 16 through the via holes.
  • the method for manufacturing a thin film transistor according to the present disclosure uses an annealing treatment to inject metal ions covering the oxide semiconductor layer into an oxide semiconductor layer to form a conductor structure, which ensures the uniformity of the metal doping in the oxide, thereby ensuring the performance of the thin film transistor.
  • the present disclosure also provides a method for manufacturing an array substrate comprising:

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present disclosure provides a method for manufacturing a thin film transistor comprising: forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, wherein on both sides of the first region of the oxide semiconductor layer are second regions where the gate electrode is exposed; forming an aluminum layer covering the buffer layer, the second regions of the oxide semiconductor layer and the gate electrode by a physical vapor deposition method, and annealing the aluminum layer, making the second regions of the oxide semiconductor layer being doped by aluminum ions to form conductor regions; etching the remaining aluminum layer after the annealing treatment; renovating the etched surfaces of the buffer layer, the gate electrode and the conductor regions, and oxidizing the conductor regions; stacking an insulating layer, and forming a source electrode and a drain electrode on the insulating layer.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims priority to Chinese Patent Application No. 201710408480.9, entitled “Manufacturing Method for Thin Film Transistor and Array Substrate”, filed on Jun. 2, 2017, the disclosure of which is incorporated herein by reference in its entirety.
    • FIELD OF THE INVENTION
  • The present disclosure relates to the field of the manufacturing method for a thin film transistor, in particular to a manufacturing method for a thin film transistor and an array substrate.
    • BACKGROUND OF THE INVENTION
  • TFT LCD (Thin-Film Transistor Liquid Crystal Display) has been widely used because of its advantages of high speed, high brightness, high contrast and the like. Among them, in a top gate metal oxide thin film crystal structure, the existence of parasitic capacitance can be reduced, thereby having obvious advantages. However, a metal conductor oxide film in the top gate metal oxide thin film crystal structure is very sensitive to acid, since even weak acid can quickly corrode oxide semiconductor. Plasma implantation doping treatment has poor stability, and metal doping treatment exists the problem of uneven oxide. Therefore, conductor processing technology is an urgent problem to be solved currently.
    • SUMMARY OF THE INVENTION
  • The present disclosure provides a method for manufacturing a thin film transistor for improving the uniformity of metal doping in an oxide semiconductor.
  • The present disclosure also provides a method for manufacturing an array substrate.
  • A method for manufacturing a thin film transistor according to the present disclosure, the method comprising: forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer, wherein on both sides of the first region of the oxide semiconductor layer are second regions where the gate electrode is exposed;
  • forming an aluminum layer covering the buffer layer, the second regions of the oxide semiconductor layer and the gate electrode by a physical vapor deposition method, and annealing the aluminum layer, making the second regions of the oxide semiconductor layer being doped by aluminum ions to form conductor regions;
  • etching the remaining aluminum layer covering the buffer layer and the second regions of the oxide semiconductor layer after the annealing treatment;
  • renovating the etched surfaces of the buffer layer, the gate electrode and the conductor regions by annealing, and oxidizing the conductor regions by annealing at the same time;
  • stacking an insulating layer on the buffer layer, the gate electrode and the conductor regions, and forming a source electrode and a drain electrode on the insulating layer, the source electrode and the drain electrode respectively being connected to the two conductor regions through via holes.
  • Hereinto, in the step of forming an aluminum layer covering the buffer layer, the second regions of the oxide semiconductor layer and the gate electrode by a physical vapor deposition method, and annealing the aluminum layer, the thickness of the aluminum layer is in a range of 20 Å to 200 Å and the annealing temperature is in a range of 100 to 400 degrees.
  • In the step of renovating the etched surfaces of the buffer layer, the gate electrode and the conductor regions by annealing, and oxidizing the conductor regions by annealing at the same time, the annealing temperature is in a range of 100 to 400 degrees.
  • Hereinto, the step of forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer comprises:
  • forming the buffer layer by using a plasma chemical vapor deposition method;
  • depositing an oxide material layer on the buffer layer by a physical vapor deposition method;
  • annealing the oxide material layer at an annealing temperature of 150 to 450° C.;
  • patterning the oxide material layer to form the oxide semiconductor layer.
  • Hereinto, the step of forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer further comprises:
  • forming the gate insulating layer by a plasma chemical vapor deposition method;
  • depositing a metal layer on the gate insulating layer by a physical vapor deposition method and patterning the metal layer to form the gate electrode.
  • Hereinto, the gate insulating layer is made of silicon oxide (SiOx) or a composite layer of silicon oxide (SiOx) and silicon nitride (SiNx), and the material of the gate electrode is one or a composite metal of aluminum, molybdenum, copper, and titanium.
  • Hereinto, the step of stacking an insulating layer on the buffer layer, the gate electrode and the conductor regions, and forming a source electrode and a drain electrode on the insulating layer, the source electrode and the drain electrode respectively being connected to the two conductor regions through via holes comprises:
  • depositing the insulating layer by a plasma chemical vapor deposition method and forming the via holes in the insulating layer which are connected to the conductor regions by a patterning method;
  • depositing a metal layer on the insulating layer by a physical vapor deposition method;
  • patterning the metal layer to form the source electrode and the drain electrode.
  • Hereinto, in the step of depositing an oxide material layer on the buffer layer by a physical vapor deposition method, the thickness of the oxide material layer is in a range of 300 Å to 1000 Å.
  • Hereinto, the insulating layer is made of silicon oxide (SiOx) or a composite layer of silicon oxide (SiOx) and silicon nitride (SiNx).
  • Hereinto, the material of the buffer layer is silicon oxide (SiOx), and the deposited thickness of the buffer layer is in a range of 2000 Å to 5500 Å.
  • A method for manufacturing an array substrate provided by the present disclosure comprises:
  • providing a substrate, on the surface of which a thin film transistor is formed;
  • forming a display element on the thin film transistor.
  • The method for manufacturing a thin film transistor according to the present disclosure uses an annealing treatment to inject metal ions covering the oxide semiconductor layer into an oxide semiconductor layer to form a conductor structure, which ensures the uniformity of the metal doping in the oxide, thereby ensuring the performance of the thin film transistor.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • In order to illustrate technical solutions of present disclosure more clearly, the drawings needed in the description of embodiments of present disclosure will be introduced briefly. Apparently, hereinafter described drawings are merely a portion of embodiments of present disclosure. For those skilled in the art, they can obtain other drawings on the base of these drawings without creative work.
  • FIG. 1 is a flowchart of a method for manufacturing the thin film transistor according to some embodiments of the present disclosure;
  • FIG. 2 to FIG. 5 are schematic views showing the respective steps of the thin film transistor manufacturing method described in the FIG. 1 according to some embodiments of the present disclosure;
  • FIG. 3 is a flowchart of a method for manufacturing the array substrate according to some embodiments of the present disclosure.
    •  DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS
  • In order to make those skilled in the art understand the technical solutions of present disclosure better, clear and complete, description of the technical solutions of present disclosure will be illustrated, which combined with the drawings of embodiments in present disclosure. Apparently, described embodiments are merely a portion of embodiments of present disclosure, rather than all of the embodiments. Base on the embodiments of present disclosure, all other embodiments obtained by those skilled in the art without creative work are considered to be encompassed within the scope of the present disclosure.
  • Referring to FIG. 1, the present disclosure provides a method for manufacturing a thin film transistor, which is particularly suitable for the production of a top gate metal oxide thin film crystal, the method comprises:
  • referring to FIG. 2, S1, forming a buffer layer 11, an oxide semiconductor layer 12, a gate insulating layer 13, and a gate electrode 14 sequentially on a substrate 10, and the gate insulating layer 13 and the gate electrode 14 being sequentially stacked on a first region 121 of the oxide semiconductor layer 12. On both sides of the first region 121 of the oxide semiconductor layer 12 are second regions 122 where the gate electrode 14 is exposed.
  • This step specifically comprises:
  • forming the buffer layer 11 by using a plasma chemical vapor deposition method;
  • depositing an oxide material layer (not shown in FIG.) on the buffer layer 11 by a physical vapor deposition method, wherein the thickness of the oxide material layer is in a range of 300 Å to 1000 Å;
  • annealing the oxide material layer at an annealing temperature of 150 to 450 degrees;
  • patterning the oxide material layer to form the oxide semiconductor layer 12.
  • This step further comprises:
  • forming the gate insulating layer 13 by a plasma chemical vapor deposition method;
  • depositing a metal layer on the gate insulating layer 13 by a physical vapor deposition method, and patterning the metal layer to form the gate electrode 14. The term “patterning” means that the entire layer is processed to form patterns by processes such as yellow light, exposure, etching and the like.
  • In this embodiment, the gate insulating layer 13 is made of silicon oxide (SiOx) or a composite layer of silicon oxide (SiOx) and silicon nitride (SiNx). The material of the gate electrode 14 is one or a composite metal of aluminum, molybdenum, copper, and titanium. Certainly, the materials of the gate insulating layer 13 and the gate electrode 14 are not limited to the materials described above.
  • The material of the buffer layer is silicon oxide (SiOx) and the deposited thickness of the buffer layer is in a range of 2000 Å to 5500 Å.
  • Referring to FIG. 3, S2, an aluminum layer 15 covering the buffer layer 11, the second regions 122 of the oxide semiconductor layer 12 and the gate electrode 14 is formed by a physical vapor deposition method, and the aluminum layer 15 is annealed, which makes the second regions 122 of the oxide semiconductor layer 12 being doped by aluminum ions to form conductor regions 16. Aluminum ions are input to the oxide semiconductor layer to form a conductor layer by the annealing treatment, which can ensure the uniformity of ion implantation, thereby ensuring the stability of the conductor layer.
  • In this embodiment, the thickness of the aluminum layer is in a range of 20 Å to 200 Å and the annealing temperature is in a range of 100 to 400 degrees. The purpose of this step is to diffuse the aluminum into the second regions 122 of the oxide semiconductor layer 12 for making them conductive.
  • Referring to FIG. 4, S3, the remaining aluminum layer covering the buffer layer 11 and the second regions 122 of the oxide semiconductor layer 12 is etched after the annealing treatment. In this step, a portion of the aluminum ion enters the second regions 122 of the oxide semiconductor layer 12 mainly after the annealing step, but still the aluminum layer is remaining on the surfaces of the buffer layer 11, the second regions 122 of the oxide semiconductor layer 12 (i.e., the conductor regions 16) and the gate electrode 14, thus the remaining aluminum layer is removed by etching to avoid affecting the subsequent process and performance of the thin film transistor.
  • S4, the etched surfaces of the buffer layer 11, the gate electrode 14 and the conductor regions 16 formed in the oxide semiconductor layer 12 are renovated by annealing process, and the conductor regions 16 are oxidized by annealing process. In this step, the annealing temperature is in a range of 100 to 400 degrees. The surface of the annealed conductor regions 16 is flat, while the conductor regions 16 are oxidized to promote sufficient bonding of the aluminum ions to ensure the performance of the conductor regions.
  • Referring to FIG. 5, S5, an insulating layer 17 is stacked on the buffer layer 11, the gate electrode 14 and the conductor regions 16. A source electrode 18 and a drain electrode 19 are formed on the insulating layer 17 and connected to the two conductor regions 16 through via holes 171, respectively. The insulating layer is made of silicon oxide (SiOx) or a composite layer of silicon oxide (SiOx) and silicon nitride (SiNx). Certainly, the type of material described above is not limited.
  • This step further comprises:
  • depositing the insulating layer 17 by a plasma chemical vapor deposition method and forming the via holes in the insulating layer which are connected to the conductor regions 16 by a patterning method;
  • depositing a metal layer on the insulating layer 17 by a physical vapor deposition method;
  • patterning the metal layer to form the source electrode 18 and drain electrode 19. The source electrode 18 and the drain electrode 19 are connected to the corresponding conductor regions 16 through the via holes.
  • The method for manufacturing a thin film transistor according to the present disclosure uses an annealing treatment to inject metal ions covering the oxide semiconductor layer into an oxide semiconductor layer to form a conductor structure, which ensures the uniformity of the metal doping in the oxide, thereby ensuring the performance of the thin film transistor.
  • Referring to FIG. 6, the present disclosure also provides a method for manufacturing an array substrate comprising:
  • S21, providing a substrate, wherein the substrate is a glass plate;
  • S22, forming a thin film transistor on the surface of the substrate, wherein the thin film transistor is formed by the method described above;
  • S23, forming a display element on the thin film transistor, wherein the display element comprises an organic light emitting diode, or a combination of a pixel electrode and a common electrode.
  • Above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to those skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.

Claims (10)

What is claimed is:
1. A method for manufacturing a thin film transistor, the method comprising:
forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer, wherein on both sides of the first region of the oxide semiconductor layer are second regions where the gate electrode is exposed;
forming an aluminum layer covering the buffer layer, the second regions of the oxide semiconductor layer and the gate electrode by a physical vapor deposition method, and annealing the aluminum layer, making the second regions of the oxide semiconductor layer being doped by aluminum ions to form conductor regions;
etching the remaining aluminum layer covering the buffer layer and the conductor regions after the annealing treatment;
renovating the etched surfaces of the buffer layer, the gate electrode and the conductor regions by annealing, and oxidizing the conductor regions by annealing at the same time;
stacking an insulating layer on the buffer layer, the gate electrode and the conductor regions, and forming a source electrode and a drain electrode on the insulating layer, the source electrode and the drain electrode respectively being connected to the two conductor regions through via holes.
2. The method for manufacturing a thin film transistor as claimed in claim 1, wherein in the step of forming an aluminum layer covering the buffer layer, the second regions of the oxide semiconductor layer and the gate electrode by a physical vapor deposition method, and annealing the aluminum layer, the thickness of the aluminum layer is in a range of 20 Å to 200 Å and the annealing temperature is in a range of 100 to 400 degrees.
3. The method for manufacturing a thin film transistor as claimed in claim 1, wherein in the step of renovating the etched surfaces of the buffer layer, the gate electrode and the conductor regions by annealing, and oxidizing the conductor regions by annealing at the same time, the annealing temperature is in a range of 100 to 400 degrees.
4. The method for manufacturing a thin film transistor as claimed in claim 1, wherein the step of forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer comprises:
forming the buffer layer by using a plasma chemical vapor deposition method;
depositing an oxide material layer on the buffer layer by a physical vapor deposition method;
annealing the oxide material layer at an annealing temperature of 150 to 450 degrees;
patterning the oxide material layer to form the oxide semiconductor layer.
5. The method for manufacturing a thin film transistor as claimed in claim 4, wherein the step of forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer further comprises:
forming the gate insulating layer by a plasma chemical vapor deposition method;
depositing a metal layer on the gate insulating layer by a physical vapor deposition method and patterning the metal layer to form the gate electrode.
6. The method for manufacturing a thin film transistor as claimed in claim 5, wherein the gate insulating layer is made of silicon oxide (SiOx) or a composite layer of silicon oxide (SiOx) and silicon nitride (SiNx), and the material of the gate electrode is one or a composite metal of aluminum, molybdenum, copper, and titanium.
7. The method for manufacturing a thin film transistor as claimed in claim 1, wherein the step of stacking an insulating layer on the buffer layer, the gate electrode and the conductor regions, and forming a source electrode and a drain electrode on the insulating layer, the source electrode and the drain electrode respectively being connected to the two conductor regions through via holes comprises:
depositing the insulating layer by a plasma chemical vapor deposition method and forming the via holes in the insulating layer which are connected to the conductor regions by a patterning method;
depositing a metal layer on the insulating layer by a physical vapor deposition method;
patterning the metal layer to form the source electrode and the drain electrode.
8. The method for manufacturing a thin film transistor as claimed in claim 4, wherein in the step of depositing an oxide material layer on the buffer layer by a physical vapor deposition method, the thickness of the oxide material layer is in a range of 300 Å to 1000 Å.
9. The method for manufacturing a thin film transistor as claimed in claim 7, wherein the material of the buffer layer is silicon oxide (SiOx), and the deposited thickness of the buffer layer is in a range of 2000 Å to 5500 Å.
10. A method for manufacturing an array substrate comprising:
providing a substrate;
forming a thin film transistor on the surface of the substrate, which comprises:
forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on the substrate, and the gate insulating layer and the gate electrode being sequentially stacked on a first region of the oxide semiconductor layer, wherein on both sides of the first region of the oxide semiconductor layer are second regions where the gate electrode is exposed;
forming an aluminum layer covering the buffer layer, the second regions of the oxide semiconductor layer and the gate electrode by a physical vapor deposition method, and annealing the aluminum layer, making the second regions of the oxide semiconductor layer being doped by aluminum ions to form conductor regions;
etching the remaining aluminum layer covering the buffer layer and the conductor regions after the annealing treatment;
renovating the etched surfaces of the buffer layer, the gate electrode and the conductor regions by annealing, and oxidizing the conductor regions by annealing at the same time;
stacking an insulating layer on the buffer layer, the gate electrode and the conductor regions, and forming a source electrode and a drain electrode on the insulating layer, the source electrode and the drain electrode respectively being connected to the two conductor regions through via holes;
forming a display element on the thin film transistor.
US15/570,260 2017-06-02 2017-07-26 Manufacturing method for thin film transistor and array substrate Active US10153308B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201710408480.9 2017-06-02
CN201710408480.9A CN107240550B (en) 2017-06-02 2017-06-02 The production method of method for fabricating thin film transistor and array substrate
PCT/CN2017/094550 WO2018218769A1 (en) 2017-06-02 2017-07-26 Thin film transistor manufacturing method and array substrate manufacturing method

Publications (2)

Publication Number Publication Date
US20180350843A1 true US20180350843A1 (en) 2018-12-06
US10153308B1 US10153308B1 (en) 2018-12-11

Family

ID=59985388

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/570,260 Active US10153308B1 (en) 2017-06-02 2017-07-26 Manufacturing method for thin film transistor and array substrate

Country Status (3)

Country Link
US (1) US10153308B1 (en)
CN (1) CN107240550B (en)
WO (1) WO2018218769A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108389867A (en) * 2018-02-26 2018-08-10 深圳市华星光电半导体显示技术有限公司 The production method of array substrate and array substrate

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100590818C (en) * 2007-09-10 2010-02-17 中华映管股份有限公司 Thin film transistor and fabrication method thereof
KR101930845B1 (en) * 2011-08-09 2018-12-20 삼성디스플레이 주식회사 Thin-film transistor array substrate, organic light emitting display device comprising the same and manufacturing method of the same
CN102683354B (en) * 2012-03-22 2014-12-17 京东方科技集团股份有限公司 Top grid type N-TFT (thin film transistor), array substrate, preparation method of array substrate, and display device
CN105931988B (en) * 2016-05-30 2019-12-24 深圳市华星光电技术有限公司 Manufacturing method of AMOLED pixel driving circuit
CN106098560B (en) * 2016-06-22 2019-03-12 深圳市华星光电技术有限公司 The production method of top gate type thin film transistor
CN106229347B (en) * 2016-08-24 2019-06-07 武汉华星光电技术有限公司 A kind of low-temperature polysilicon film transistor and its manufacturing method
CN106298956A (en) * 2016-09-08 2017-01-04 武汉华星光电技术有限公司 The preparation method of oxide thin film transistor
CN106356306A (en) * 2016-11-14 2017-01-25 深圳市华星光电技术有限公司 Top gate type thin film transistor and production method thereof

Also Published As

Publication number Publication date
WO2018218769A1 (en) 2018-12-06
CN107240550B (en) 2019-09-27
CN107240550A (en) 2017-10-10
US10153308B1 (en) 2018-12-11

Similar Documents

Publication Publication Date Title
KR101522481B1 (en) Method for fabricating array substrate, array substrate and display device
US9768323B2 (en) Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
US9716119B2 (en) Manufacturing method of dual gate TFT substrate and structure thereof
US9761616B2 (en) Manufacturing method of array substrate with reduced number of patterning processes array substrate and display device
US20150171224A1 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
US10290663B2 (en) Manufacturing method of thin film transistor and manufacturing method of array substrate
US20160172389A1 (en) Thin film transistor and manufacturing method thereof
US9704998B2 (en) Thin film transistor and method of manufacturing the same, display substrate, and display apparatus
US10083988B2 (en) Complementary thin film transistor and manufacturing method thereof, array substrate, display apparatus
US20170255044A1 (en) Tft substrates and the manufacturing methods thereof
US20170162708A1 (en) Tft substrates and the manufacturing methods thereof
US20170110587A1 (en) Array substrate and manufacturing method thereof, display panel, display device
US10784287B2 (en) TFT substrate and manufacturing method thereof
WO2017193667A1 (en) Thin film transistor and manufacturing method therefor, array substrate and manufacturing method therefor, and display apparatus
WO2020228499A1 (en) Transistor device and manufacturing method therefor, display substrate and display apparatus
US9685471B2 (en) Manufacturing method of thin film transistor substrate
US10170506B2 (en) LTPS array substrate and method for producing the same
KR20200003143A (en) OLED display panel and its manufacturing method
US20190051713A1 (en) Manufacturing method of tft substrate, tft substrate, and oled display panel
US20170301705A1 (en) Ltps pixel unit and manufacturing method for the same
US9893197B2 (en) Thin film transistor substrate, manufacturing method thereof, and liquid crystal display panel using same
US10153308B1 (en) Manufacturing method for thin film transistor and array substrate
WO2019071824A1 (en) Display panel and fabrication method therefor
US10818704B2 (en) Method for manufacturing thin film transistor, and thin film transistor, including forming an organic light-emitting device
US10170631B2 (en) Manufacturing methods of oxide thin film transistors

Legal Events

Date Code Title Description
AS Assignment

Owner name: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO.

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LI, JINMING;REEL/FRAME:043975/0062

Effective date: 20170907

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4