WO2018216621A1 - Procédé de fabrication de dispositif à semi-conducteurs et bande d'expansion - Google Patents

Procédé de fabrication de dispositif à semi-conducteurs et bande d'expansion Download PDF

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Publication number
WO2018216621A1
WO2018216621A1 PCT/JP2018/019325 JP2018019325W WO2018216621A1 WO 2018216621 A1 WO2018216621 A1 WO 2018216621A1 JP 2018019325 W JP2018019325 W JP 2018019325W WO 2018216621 A1 WO2018216621 A1 WO 2018216621A1
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WIPO (PCT)
Prior art keywords
expanded tape
semiconductor chips
semiconductor
tape
carrier
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PCT/JP2018/019325
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English (en)
Japanese (ja)
Inventor
一尊 本田
鈴木　直也
裕一 乃万
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日立化成株式会社
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Application filed by 日立化成株式会社 filed Critical 日立化成株式会社
Priority to KR1020197031152A priority Critical patent/KR102571926B1/ko
Priority to CN201880033282.1A priority patent/CN110637355B/zh
Priority to JP2019520219A priority patent/JP7173000B2/ja
Publication of WO2018216621A1 publication Critical patent/WO2018216621A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J201/00—Adhesives based on unspecified macromolecular compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and an expanded tape.
  • WLP wafer level package
  • the WLP includes a semiconductor package having the same package area as a semiconductor chip, such as a WLCSP (Wafer Level Chip Scale Package) or FI-WLP (Fan In Wafer Level Package), and a FO-WLP (Fan Out Wafer Level Package).
  • WLCSP Wafer Level Chip Scale Package
  • FI-WLP Fe In Wafer Level Package
  • FO-WLP FO-WLP
  • the present invention provides a manufacturing method of a semiconductor device that can be shortened in time compared with a conventional process having a rearrangement process and that has little damage to a chip, and an expanded tape applicable to the manufacturing method.
  • the purpose is to provide.
  • a method of manufacturing a semiconductor device comprising a tape expanding step of extending an interval between semiconductor chips fixed on the expanded tape by heating while expanding the expanded tape from 100 ⁇ m or less to 300 ⁇ m or more.
  • Expanding tape used for An expanding tape having a tensile stress at a heating temperature of the tape expanding step of 10 MPa or less and a tensile stress at room temperature of 5 MPa or more higher than the tensile stress at the heating temperature.
  • a method for manufacturing a semiconductor device includes a tension holding step for holding the tension of the stretched expanded tape, a transfer step for transferring the semiconductor chip on the expanded tape holding the tension to the carrier, and the transfer to the carrier.
  • the interval between the separated semiconductor chips fixed on the expanded tape is 100 ⁇ m or less to 300 ⁇ m.
  • a method for manufacturing a semiconductor device comprising a tape expanding step that extends as described above.
  • a method of manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface A first A step of preparing an expanded tape, and a plurality of semiconductor chips having a surface opposite to the circuit surface fixed on the expanded tape;
  • a second A step of extending the interval between the plurality of semiconductor chips fixed on the expanded tape by stretching the expanded tape Step 3A for maintaining the tension of the stretched expanded tape, A 4A step of transferring the carrier so that the circuit surfaces of the plurality of semiconductor chips are fixed to the carrier;
  • a method for manufacturing a semiconductor device comprising: [7] A method of manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface, A first B
  • a method of manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface A first D step of preparing an expanded tape and a plurality of semiconductor chips each having a circuit surface fixed on the expanded tape; A second step of extending the interval between the plurality of semiconductor chips fixed on the expanded tape by stretching the expanded tape; A 3D step for maintaining the tension of the stretched expanded tape; A 4D step of transferring the carrier so that the surface opposite to the circuit surface of the plurality of semiconductor chips is fixed; A 5D step of peeling the expanded tape from a plurality of semiconductor chips; A 6D step of sealing a plurality of semiconductor chips on the carrier with a sealing material; A 7D step of polishing the sealing material to expose the pad; An 8D step of peeling the carrier from the plurality of semiconductor chips sealed by the sealing material; A method for manufacturing a semiconductor device comprising a ninth step of forming a plurality of semiconductor packages by dividing a plurality of semiconductor chips sealed with a sealing material into individual semiconductor chips.
  • a method for manufacturing a semiconductor device that can be shortened in time compared with a conventional process having a rearrangement process and that has little damage to a chip, and an expandable tape applicable to the manufacturing method. be able to.
  • FIG. 10 is a schematic cross-sectional view for explaining an embodiment of the first to fourth process steps in the first method for manufacturing a semiconductor device.
  • FIG. 10 is a schematic cross-sectional view for explaining one embodiment of a 5A process to a 7A process in the manufacturing method of the first semiconductor device. It is a schematic cross section for explaining one embodiment of the 8A process and the 9A process in the manufacturing method of the 1st semiconductor device.
  • FIG. 10 is a schematic cross-sectional view for explaining one embodiment of a 1B process to a 4B process in the second semiconductor device manufacturing method.
  • FIG. 10 is a schematic cross-sectional view for explaining an embodiment of a 5B process to an 8B process in the second method for manufacturing a semiconductor device.
  • FIG. 10 is a schematic cross-sectional view for explaining one embodiment of a 1C process to a 4C process in the third method for manufacturing a semiconductor device.
  • FIG. 10 is a schematic cross-sectional view for explaining an embodiment of a 5C process to an 8C process in the third method for manufacturing a semiconductor device.
  • FIG. 10D is a schematic cross-sectional view for explaining another embodiment of the 4C process to the 8C process in the third semiconductor device manufacturing method.
  • 10 is a schematic cross-sectional view for explaining one embodiment of a first D process to a fourth D process in the fourth method for manufacturing a semiconductor device. It is a schematic cross-sectional view for explaining one embodiment of a 5D process to a 9D process in a fourth method for manufacturing a semiconductor device. It is a schematic cross section for explaining other embodiments of the 7D process and the 8D process in the manufacturing method of the 4th semiconductor device. It is a schematic cross section for explaining one embodiment of a manufacturing method of a fifth semiconductor device. It is a schematic cross section for explaining other embodiments of the manufacturing method of the 5th semiconductor device.
  • the manufacturing method of the first semiconductor device of this embodiment is as follows: A method of manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface, A first A step of preparing an expanded tape, and a plurality of semiconductor chips having a surface opposite to the circuit surface fixed on the expanded tape; A second A step of extending the interval between the plurality of semiconductor chips fixed on the expanded tape by stretching the expanded tape; Step 3A for maintaining the tension of the stretched expanded tape, A 4A step of transferring the carrier so that the circuit surfaces of the plurality of semiconductor chips are fixed to the carrier; A 5A step of peeling the expanded tape from a plurality of semiconductor chips; A 6A step of sealing a plurality of semiconductor chips on the carrier with a sealing material; A 7A step of peeling the carrier from the plurality of semiconductor chips sealed by the sealing material; A redistribution layer having a redistribution pattern is formed from pads in a plurality of semiconductor chips sealed with a sealing material, and
  • the first method for manufacturing a semiconductor device of this embodiment it is possible to manufacture a semiconductor package (FO-WLP) in which the package area is larger than the semiconductor chip area and the terminals can be extended to the outside of the chip. Become.
  • FO-WLP is expanding because it can be used in applications where the number of terminals is larger than the chip area. Also, for flip chip BGAs, where the semiconductor chip and package substrate are connected by solder bumps and solder balls are mounted on the package substrate, FO-WLP connects the semiconductor chip to the rewiring layer, and the rewiring layer has a metal pad ( Provide connection terminals) and mount solder balls. For this reason, FO-WLP contributes to reducing the size and thickness of the package, and further shortens the wiring length. Therefore, it is possible to increase the transmission speed (high functionality) and reduce the cost by eliminating the package substrate.
  • a connection terminal pad is formed outside the semiconductor chip via a redistribution layer, so that it is necessary to widen the interval between the semiconductor chips.
  • a method for widening the interval between semiconductor chips includes a rearrangement step in which individual semiconductor chips obtained by dicing a semiconductor wafer are rearranged on a carrier or the like (for example, non-patent). Reference 1).
  • FIG. 1 is a schematic cross-sectional view for explaining one embodiment of Steps 1A to 4A
  • FIG. 2 is a schematic cross-sectional view for explaining one embodiment of Steps 5A to 7A
  • FIG. 3 is a schematic cross-sectional view for explaining one embodiment of the 8A process and the 9A process.
  • step 1A an expanded tape 1 and a plurality of semiconductor chips 2 fixed on the expanded tape 1 are prepared.
  • the expanded tape 1 has an adhesive layer 1 a and a base film 1 b, and the adhesive layer 1 a is in contact with the semiconductor chip 2.
  • the semiconductor chip 2 has a circuit surface provided with pads (circuits) 3 and the surface opposite to the circuit surface is fixed to the expanded tape 1 (FIG. 1A).
  • the plurality of semiconductor chips 2 are arranged at intervals.
  • the expanded tape 1 is stretched to widen the intervals between the plurality of semiconductor chips 2 fixed on the expanded tape 1 (FIG. 1B).
  • the expanded tape 1 is fixed by using the fixing jig 4 to maintain the tension of the expanded tape 1 (FIG.
  • the 4A step transfer is performed on the carrier 5 so that the circuit surfaces of the plurality of semiconductor chips 2 are fixed (FIG. 1D).
  • the pad 3 may be embedded in the carrier 5 (FIG. 1D), and only the pad 3 is in contact with the carrier 5, and a gap is formed between the circuit surface of the semiconductor chip 2 and the carrier 5. May be present (not shown).
  • the expanded tape 1 is peeled from the plurality of semiconductor chips 2 (FIG. 2A).
  • the sixth step A the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6 (FIG. 2B).
  • FIG. 3A is an enlarged view of FIG.
  • the rewiring layer 8 having the rewiring pattern 7 is formed from the pads 3 in the plurality of semiconductor chips 2 sealed with the sealing material 6, and the rewiring pattern is outside the region of the semiconductor chip 2. 7 is provided with a connection terminal pad 9 connected to the semiconductor chip 2 (FIG. 3B).
  • the semiconductor chip 2 and the connection terminal pads 9 connected to the semiconductor chip 2 are separated into a group to form a plurality of semiconductor packages 10 (FIG. 3C).
  • Step 1A> There is no particular limitation on the method for preparing the expanded tape and the plurality of semiconductor chips fixed on the expanded tape.
  • the semiconductor wafer can be transferred to an expanding tape. Dicing may be performed by forming a fragile layer with a laser and expanding. Further, from the viewpoint of improving productivity by omitting the above-described transfer, a semiconductor wafer may be directly laminated on an expanded tape, and the semiconductor wafer may be diced by the above-described method.
  • the initial semiconductor chip interval (semiconductor chip interval before the 2A process) is preferably narrow, preferably 100 ⁇ m or less, more preferably 80 ⁇ m or less, and even more preferably 60 ⁇ m or less. .
  • the semiconductor wafer is wasted as the above-mentioned chip interval is wide. Therefore, the narrower one as described above is preferable from the viewpoint of cost reduction.
  • the initial semiconductor chip interval is preferably 10 ⁇ m or more. If it is smaller than 10 ⁇ m, the expanded tape area between a plurality of semiconductor chips is small, so that it is difficult to spread.
  • the type of pad on the circuit surface of the semiconductor chip is not particularly limited as long as it can be formed on the circuit surface of the semiconductor chip. Even if it is a bump (projection electrode) such as a copper bump or a solder bump, Ni / Au It may be a relatively flat metal pad such as a plating pad.
  • Examples of expanding tape stretching methods include a push-up method and a pulling method.
  • the push-up method after the expanded tape is fixed, the expanded tape is stretched by raising the stage having a predetermined shape.
  • the tension method is a method in which the expanded tape is stretched by fixing the expanded tape and then pulling the expanded tape in a predetermined direction in parallel with the installed expanded tape surface.
  • the push-up method is preferable because the distance between the semiconductor chips can be extended uniformly and the required (occupied) device area is small and compact.
  • the stretching conditions may be appropriately set according to the characteristics of the expanded tape.
  • the push-up amount tensile amount
  • the push-up amount is preferably 10 mm to 500 mm, and more preferably 10 mm to 300 mm.
  • the temperature may be appropriately set according to the properties of the expanded tape, but may be, for example, 10 ° C to 200 ° C, 10 ° C to 150 ° C, or 20 ° C to 100 ° C. When the temperature is 10 ° C.
  • the push-up speed may be set as appropriate according to the properties of the expanded tape. For example, it may be 0.1 mm / second to 500 mm / second, such as 0.1 mm / second to 300 mm / second, 0.1 mm / second to 200 mm / second. It may be seconds. Productivity improves that it is 0.1 mm / second or more. When it is 500 mm / second or less, peeling between the semiconductor chip and the expanded tape is difficult to occur.
  • the interval between the plurality of semiconductor chips after the second step A is preferably 500 ⁇ m or more in order to secure a space necessary for providing the rewiring pattern and the connection terminal pads outside the semiconductor chip region.
  • the semiconductor chip interval is wide.
  • the interval between the plurality of semiconductor chips after the 2A step is more preferably 1 mm or more, and further preferably 2 mm or more.
  • the upper limit is not particularly limited, but can be 5 mm or less.
  • the method of holding the expanded tape tension is not particularly limited as long as the tension is held and the distance between the semiconductor chips is not restored.
  • a method of fixing using a fixing jig such as a grip ring (manufactured by Technovision Co., Ltd.), a method of heating and contracting the outer peripheral portion of the expanded tape (heat shrink), and the like can be mentioned.
  • Step 4A The carrier is transferred (laminated) so that the circuit surfaces of the plurality of semiconductor chips are fixed.
  • the laminating method is not particularly limited, and a roll laminator, a diaphragm laminator, a vacuum roll laminator, a vacuum diaphragm laminator, and the like can be employed.
  • Lamination conditions may be set as appropriate according to the physical properties and characteristics of the expanded tape, semiconductor chip, and carrier.
  • a roll laminator it may be room temperature (25 ° C.) to 200 ° C., preferably room temperature (25 ° C.) to 150 ° C., more preferably room temperature (25 ° C.) to 100 ° C.
  • the semiconductor chip is easily transferred (laminated) to the carrier, and when the temperature is 200 ° C. or lower, the position of the semiconductor chip is shifted due to distortion or sagging due to thermal expansion or low elasticity of the expanded tape (expanded tape and semiconductor chip).
  • the pressing time may be 5 seconds to 300 seconds, preferably 5 seconds to 200 seconds, and more preferably 5 seconds to 100 seconds. If it is 5 seconds or more, the semiconductor chip is easily transferred (laminated) to the carrier, and if it is 300 seconds or less, the productivity is improved.
  • the pressure may be 0.1 MPa to 3 MPa, preferably 0.1 MPa to 2 MPa, more preferably 0.1 MPa to 1 MPa. When it is 0.1 MPa or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when it is 2 MPa or less, damage to the semiconductor chip is reduced.
  • Step 5A The expanded tape is peeled (removed) from the plurality of semiconductor chips.
  • the adhesive force between the expanded tape and the carrier, the expanded tape and the semiconductor chip, and the semiconductor chip and the carrier should be such that the semiconductor chip transferred onto the carrier does not shift or peel off from the carrier. It is necessary to set appropriately.
  • the adhesive force between the expanded tape and the semiconductor chip is preferably the same as or smaller than the adhesive force between the semiconductor chip and the carrier.
  • the adhesive force is increased or decreased by applying a UV curing function to the expanded tape or the carrier surface and irradiating UV.
  • the expanded tape is removed after UV irradiation (adding UV irradiation process).
  • UV is irradiated to lower the adhesive force (adhesive force) of the expanded tape, and then the laminated tape is peeled off from the semiconductor chip by laminating on the carrier. As a result, the stress on the semiconductor chip is reduced, and the transfer can be performed smoothly without misalignment.
  • Step 6A A plurality of semiconductor chips on the carrier are sealed with a sealing material.
  • the sealing method is not particularly limited.
  • compression molding is liquid material, solid material, granule material, film material, etc.
  • transfer mold is liquid material, solid material, granule material
  • laminating film-like sealing materials for example, compression molding (sealing material shape is liquid material, solid material, granule material, film material, etc.), transfer mold (sealing material shape is liquid material, solid material, granule material) , Film material, etc.), and laminating film-like sealing materials.
  • a heat treatment step including post-cure may be added from the viewpoint of adjusting the physical properties of the sealing material. It is necessary to peel off the carrier after Step 6A or after the additional heat treatment step. Also when peeling off, a heat treatment, a UV treatment step or the like may be added. It is necessary to set the adhesion of the carrier (carrier + adhesive layer, carrier + temporary fixing material, etc.) so that the carrier can be peeled off without damaging the semiconductor chip and the sealing material after the above-described steps.
  • Step 7A> A carrier is peeled from a plurality of semiconductor chips sealed with a sealing material. Before the carrier is peeled off, a process of making the carrier easy to peel off by applying a chemical or mechanical change to the carrier surface layer in contact with the sealing material surface by heat treatment or UV irradiation may be introduced.
  • the semiconductor chip is transferred from the expanded tape to the carrier, whereby the risk of heat resistance in the heating process such as the sealing process can be reduced.
  • the semiconductor chip may be displaced or scattered due to distortion of the expandable expandable tape or deformation due to thermal expansion. May occur.
  • misalignment or chip scattering occurs, the productivity is reduced and the cost is increased. Therefore, it is necessary to transfer the semiconductor chip to the carrier.
  • a redistribution layer having a redistribution pattern is formed from pads in a plurality of semiconductor chips sealed with a sealing material, and a connection terminal pad connected to the semiconductor chip by the redistribution pattern outside the region of the semiconductor chip Is provided.
  • a rewiring layer is formed, and connection terminal pads are provided outside the region of the semiconductor chip to increase the bump spacing ( FO-WLP).
  • FO-WLP bump spacing
  • Step 9A The semiconductor chip and the connection terminal pads connected to the semiconductor chip are separated into a group to form a plurality of semiconductor packages.
  • This step can be performed by a conventionally known method.
  • a back grinding process (a process of thinning the sealing material on the back side of the circuit surface of the semiconductor chip) may be introduced.
  • the back grinding process can be introduced, for example, after the 6A process, after the 7A process, or after the 8A process.
  • the expandable tape that can be used in the first method for manufacturing a semiconductor device is not particularly limited as long as it has stretchability that can widen the interval between a plurality of semiconductor chips. It is preferable that the MD and TD chip intervals after the 2A step (after increasing the interval between the semiconductor chips) are uniform, but after the 6A step (after sealing), the semiconductor chip and the connection terminals connected thereto. If the dicing is possible without damaging the semiconductor chip when separating the pads for the group as a group (if the blade does not damage the semiconductor chip), the width of MD and TD is not uniform. Also good. At the time of dicing, the dicing interval width of MD and TD may not be the same. However, MD lines and TD lines are preferably uniform.
  • the expanded tape may have a plurality of layer structures such as a base film (base layer) that greatly contributes to stretchability and an adhesive layer that controls the adhesive strength.
  • base film base layer
  • adhesive layer that controls the adhesive strength
  • the substrate film is not particularly limited as long as it has stretchability and stability for holding the semiconductor chip interval after the tension holding step (step 3A).
  • the base film is a polyester film such as a polyethylene terephthalate film; a polytetrafluoroethylene film, a polyethylene film, a polypropylene film, a polymethylpentene film, a polyvinyl acetate film, and an ⁇ -olefin such as poly-4-methylpentene-1.
  • the base film is not limited to a single layer film, and may be a multilayer film obtained by combining two or more plastic films or two or more plastic films of the same type.
  • the base film is preferably a polyolefin film or a urethane resin film from the viewpoint of stretchability.
  • the base film may contain various additives such as an anti-blocking agent as necessary.
  • the thickness of the base film may be appropriately set as necessary, but is preferably 50 ⁇ m to 500 ⁇ m. If the thickness is less than 50 ⁇ m, the stretchability is deteriorated, and if it is more than 500 ⁇ m, problems such as distortion is likely to occur and handling properties are deteriorated.
  • the thickness of the base film is appropriately selected within a range that does not impair workability.
  • a high energy ray (in particular, ultraviolet ray) curable pressure sensitive adhesive is used as the pressure sensitive adhesive constituting the pressure sensitive adhesive layer, it is necessary to have a thickness that does not inhibit the transmission of the high energy ray.
  • the thickness of the base film may be usually 10 to 500 ⁇ m, preferably 50 to 400 ⁇ m, and more preferably 70 to 300 ⁇ m.
  • the substrate layer is composed of a plurality of substrate films, it is preferable to adjust so that the thickness of the entire substrate layer is within the above range.
  • the base film may be subjected to a chemical or physical surface treatment as necessary in order to improve the adhesion with the adhesive layer. Examples of the surface treatment include corona treatment, chromic acid treatment, ozone exposure, flame exposure, high piezoelectric impact exposure, and ionizing radiation treatment.
  • the adhesive layer is not particularly limited as long as the adhesive force can be controlled (setting so that the semiconductor chip is not displaced or scattered for each process).
  • the pressure-sensitive adhesive layer is preferably composed of a pressure-sensitive adhesive component that has adhesive strength at room temperature and has adhesion to the semiconductor chip.
  • the base resin of the pressure-sensitive adhesive component that constitutes the pressure-sensitive adhesive layer include acrylic resin, synthetic rubber, natural rubber, and polyimide resin.
  • the base resin preferably has a functional group (such as a hydroxyl group or a carboxyl group) that can react with other additives.
  • the adhesive component high energy rays such as ultraviolet rays and radiation, or a resin curable by heat may be used. When such a curable resin is used, the adhesive strength can be reduced by curing the resin.
  • the said adhesive component may contain the crosslinking agent which can carry out a crosslinking reaction with the functional group of the said base resin.
  • the crosslinking agent preferably has at least one functional group selected from the group consisting of an epoxy group, an isocyanate group, an aziridine group, and a melanin group. These crosslinking agents may be used alone or in combination of two or more.
  • catalysts such as an amine and tin, as needed.
  • the adhesive component may appropriately contain rosin-based, tackifiers such as terpene resins, and optional components such as various surfactants.
  • the thickness of the adhesive layer is usually 1 to 100 ⁇ m, preferably 2 to 50 ⁇ m, more preferably 5 to 40 ⁇ m.
  • the thickness of the adhesive layer is usually 1 to 100 ⁇ m, preferably 2 to 50 ⁇ m, more preferably 5 to 40 ⁇ m.
  • the adhesive layer is 10 ⁇ m or more, the substrate film will not be damaged (notched) even if the semiconductor wafer is diced on the expanded tape without using the dicing tape.
  • the step of dicing the semiconductor wafer and transferring (attaching) it to the expanded tape can be omitted.
  • Expandable tapes can be manufactured according to techniques well known in the art. For example, it can be produced according to the following method. By applying a varnish containing an adhesive component and a solvent on the protective film by knife coating, roll coating, spray coating, gravure coating, bar coating, curtain coating, etc., and removing the solvent An adhesive layer is formed. Specifically, it is preferable to perform heating at 50 to 200 ° C. for 0.1 to 90 minutes. If there is no influence on void generation or viscosity adjustment in each step, it is preferable that the conditions are such that the organic solvent volatilizes to 1.5% or less.
  • the produced protective film with an adhesive layer and the substrate film are laminated so that the adhesive layer and the substrate film face each other under a temperature condition of room temperature to 60 ° C.
  • ⁇ Expand tape base film or base film + adhesive layer
  • base film or base film + adhesive layer is used after peeling off the protective film.
  • the thickness of the protective film is appropriately selected within a range that does not impair the workability, and is usually preferably 100 ⁇ m or less from an economical viewpoint.
  • the thickness of the protective film is preferably 10 to 75 ⁇ m, more preferably 25 to 50 ⁇ m. When the thickness of the protective film is 10 ⁇ m or more, problems such as film tearing are difficult to occur during production of an expanded tape. Moreover, if the thickness of the said protective film is 75 micrometers or less, a protective film can be easily peeled at the time of use of an expanded tape.
  • the carrier is particularly limited as long as it can withstand the temperature and pressure at the time of transfer (the chip does not break, the chip interval does not change) and can withstand the temperature and pressure at the time of sealing in the 6A process.
  • the sealing temperature is 100 to 200 ° C.
  • it is preferably heat resistant to withstand that temperature range.
  • the coefficient of thermal expansion is preferably 100 ppm / ° C. or less, more preferably 50 ppm / ° C. or less, and further preferably 20 ppm / ° C. or less. If the coefficient of thermal expansion is large, problems such as misalignment of the semiconductor chip occur.
  • the thermal expansion coefficient is preferably 3 ppm / ° C. or higher because distortion or warpage occurs when the thermal expansion coefficient is smaller than that of the semiconductor chip.
  • the material of the carrier is not particularly limited, and examples thereof include silicon (wafer), glass, SUS, iron, Cu plates, and a glass epoxy substrate.
  • the thickness of the carrier may be 100 ⁇ m to 5000 ⁇ m, preferably 100 ⁇ m to 4000 ⁇ m, and more preferably 100 ⁇ m to 3000 ⁇ m. When it is 100 ⁇ m or more, handleability is improved. Even if it is thick, a remarkable improvement in handling is not expected, and it may be 5000 ⁇ m or less in consideration of economy.
  • the carrier may consist of multiple layers.
  • the adhesion force may be set as appropriate in consideration of the adhesion force of the semiconductor chip or the expanded tape.
  • the thickness is not particularly limited, but may be, for example, 1 ⁇ m to 300 ⁇ m, and preferably 1 ⁇ m to 200 ⁇ m. By setting the thickness to 1 ⁇ m or more, sufficient adhesive strength with the semiconductor chip can be ensured. On the other hand, even if the thickness exceeds 300 ⁇ m, there is no advantage in characteristics and it becomes uneconomical.
  • the sealing method is not particularly limited.
  • compression molding is liquid material, solid material, granule material, film material, etc.
  • transfer mold is liquid material, solid material, granule material
  • laminating film-like sealing materials for example, compression molding (sealing material shape is liquid material, solid material, granule material, film material, etc.), transfer mold (sealing material shape is liquid material, solid material, granule material) , Film material, etc.), and laminating film-like sealing materials.
  • the shape, characteristics, and sealing conditions of the sealing material may be set as appropriate for each sealing method described above. It is necessary to appropriately set the sealing material shape, characteristics, and sealing conditions so that the semiconductor chip on the carrier does not move or peel off at the time of sealing and the semiconductor chip is not damaged.
  • the sealing temperature is preferably 80 ° C. to 220 ° C., more preferably 90 ° C. to 210 ° C., and still more preferably 100 ° C. to 200 ° C.
  • the sealing temperature is 80 ° C. or higher, insufficient filling around the semiconductor chip can be sufficiently suppressed.
  • the sealing temperature is 220 ° C. or lower, it is possible to prevent unfilling due to the curing of the sealing material being too early, an increase in the amount of warping after sealing, and the like.
  • a heat treatment step including post-cure may be added from the viewpoint of adjusting the physical properties of the sealing material.
  • post-cure it is 100 ° C. to 200 ° C., 10 minutes to 5 hours, and is set according to the curing characteristics of the sealing material.
  • the heat treatment may be performed at a temperature lower than the post cure (200 ° C. or lower) for 10 minutes to 3 hours.
  • the manufacturing method of the second semiconductor device of this embodiment is as follows: A method of manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface, A first B step of preparing an expanded tape and a plurality of semiconductor chips each having a circuit surface fixed on the expanded tape; A second B step of extending the interval between the plurality of semiconductor chips fixed on the expanded tape by stretching the expanded tape; Step 3B for maintaining the tension of the stretched expanded tape; A 4B step of transferring the carrier so that the surface opposite to the circuit surface of the plurality of semiconductor chips is fixed; A 5B step of peeling the expanded tape from the plurality of semiconductor chips; A 6B step of sealing a plurality of semiconductor chips on the carrier with a sealing material; A 7B step of polishing the sealing material to expose the pad; An 8B step of peeling the carrier from the plurality of semiconductor chips sealed by the sealing material; A redistribution layer having a redistribution pattern is formed from pads in a plurality of semiconductor chips sealed with a
  • the second semiconductor device manufacturing method of the present embodiment it is possible to manufacture a semiconductor package (FO-WLP) in which the package area is larger than the semiconductor chip area and the terminals can be extended to the outside of the chip. Clearly, according to the second semiconductor device manufacturing method of the present embodiment, the problem in the conventional FO-WLP manufacturing method can be solved in the same manner as the first semiconductor device manufacturing method of the present embodiment.
  • FO-WLP semiconductor package
  • FIG. 4 is a schematic cross-sectional view for explaining one embodiment of the first to fourth steps
  • FIG. 5 is a schematic cross-sectional view for explaining one embodiment of the fifth to eighth step
  • FIG. 6 is a schematic cross-sectional view for explaining another embodiment of the 7B step and the 8B step
  • FIG. 7 is a schematic view for explaining one embodiment of the 9B step and the 10B step. It is sectional drawing.
  • an expanded tape 1 and a plurality of semiconductor chips 2 fixed on the expanded tape 1 are prepared.
  • the expanded tape 1 has an adhesive layer 1 a and a base film 1 b, and the adhesive layer 1 a is in contact with the semiconductor chip 2.
  • the semiconductor chip 2 has a circuit surface provided with pads (circuits) 3, and the circuit surface is fixed to the expanded tape 1 (FIG. 4A).
  • the plurality of semiconductor chips 2 are arranged at intervals. Further, the pad 3 may be embedded in the expanded tape 1 at the time of fixing.
  • the expanded tape 1 is stretched to widen the intervals between the plurality of semiconductor chips 2 fixed on the expanded tape 1 (FIG. 4B).
  • the expanded tape 1 is fixed by using the fixing jig 4 to maintain the tension of the expanded tape 1 (FIG. 4C).
  • transfer is performed to the carrier 5 so that the surface opposite to the circuit surface of the plurality of semiconductor chips 2 is fixed (FIG. 4D).
  • the expanded tape 1 is peeled from the plurality of semiconductor chips 2 (FIG. 5A).
  • the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6 (FIG. 5B). At this time, since the surface opposite to the circuit surface of the semiconductor chip 2 is in contact with the carrier 5, this surface is not sealed, and the circuit surface and the four side surfaces of the semiconductor chip 2 are sealed in total. .
  • the sealing material 6 is polished to expose the pad 3.
  • the carrier 5 is peeled from the plurality of semiconductor chips 2 sealed with the sealing material 6.
  • the order of the 7B process and the 8B process can be switched. That is, after polishing the sealing material 6 to expose the pad 3 (FIG. 5C), the carrier 5 may be peeled from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 5). 5 (d)), after the carrier 5 is peeled from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 6A), the sealing material 6 may be polished to expose the pad 3. Good (FIG. 6B).
  • Fig.7 (a) is an enlarged view of FIG.5 (d) or FIG.6 (b).
  • the rewiring layer 8 having the rewiring pattern 7 is formed from the pads 3 in the plurality of semiconductor chips 2 sealed with the sealing material 6, and the rewiring pattern is outside the region of the semiconductor chip 2.
  • 7 is provided with a connection terminal pad 9 connected to the semiconductor chip 2 (FIG. 7B).
  • the semiconductor chip 2 and the connection terminal pads 9 connected to the semiconductor chip 2 are separated into a group to form a plurality of semiconductor packages 10 (FIG. 7C).
  • step 7B the sealing material is polished to expose the pad. Polishing can be performed using a conventionally known polishing apparatus or the like. Note that the 7B step is not necessarily provided when the sealing can be performed with the pads on the circuit surface exposed in the 6B step.
  • the same material as that in the first semiconductor device manufacturing method can be used.
  • the carrier 5 the surface opposite to the circuit surface of the semiconductor chip is protected.
  • a carrier having a layer formed by laminating a material capable of protecting the sealing material and the chip by coating, spin coating, laminating, etc. on the above-mentioned layer bearing heat resistance and handleability may be used as a carrier. Good.
  • the third method for manufacturing a semiconductor device of this embodiment is as follows: A method of manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface, A first C step of preparing an expanded tape and a plurality of semiconductor chips each having a surface opposite to the circuit surface fixed on the expanded tape; A second C step of extending the interval between the plurality of semiconductor chips fixed on the expanded tape by stretching the expanded tape; Step 3C for maintaining the tension of the stretched expanded tape, A 4C step of transferring the carrier so that the circuit surfaces of the plurality of semiconductor chips are fixed to the carrier; 5C step of peeling the expanded tape from a plurality of semiconductor chips, A 6C step of sealing a plurality of semiconductor chips on the carrier with a sealing material; A 7C step of peeling the carrier from the plurality of semiconductor chips sealed by the sealing material; A plurality of semiconductor chips sealed with a sealing material are divided into pieces for each semiconductor chip to form a plurality of semiconductor packages; and Is provided.
  • FIG. 8 is a schematic cross-sectional view for explaining an embodiment of the 1C to 4C steps
  • FIG. 9 is a schematic cross-sectional view for explaining an embodiment of the 5C to 8C steps
  • FIG. 10 is a schematic cross-sectional view for explaining another embodiment of Steps 4C to 8C.
  • an expanded tape 1 and a plurality of semiconductor chips 2 fixed on the expanded tape 1 are prepared.
  • the expanded tape 1 has an adhesive layer 1 a and a base film 1 b, and the adhesive layer 1 a is in contact with the semiconductor chip 2.
  • the semiconductor chip 2 has a circuit surface on which pads (circuits) 3 are provided, and the surface opposite to the circuit surface is fixed to the expanded tape 1 (FIG. 8A).
  • the plurality of semiconductor chips 2 are arranged at intervals.
  • the expanded tape 1 is stretched to widen the intervals between the plurality of semiconductor chips 2 fixed on the expanded tape 1 (FIG. 8B).
  • the expanded tape 1 is fixed by using the fixing jig 4 to maintain the tension of the expanded tape 1 (FIG. 8C).
  • transfer is performed on the carrier 5 so that the circuit surfaces of the plurality of semiconductor chips 2 are fixed.
  • the pad 3 may be completely embedded in the carrier 5 and the circuit surface of the semiconductor chip 2 may be in contact with the carrier 5 (FIG. 8D). It may be embedded in the carrier 5 or only the end surface of the pad 3 may be in contact with the carrier 5, and a gap may exist between the circuit surface of the semiconductor chip 2 and the carrier 5 (FIG. 10A).
  • the expanded tape 1 is peeled from the plurality of semiconductor chips 2 (FIG. 9A or FIG. 10B).
  • the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6.
  • the circuit surface of the semiconductor chip 2 is in contact with the carrier 5 after the 5C step (FIG. 9A)
  • the circuit surface is not sealed, and the surface opposite to the circuit surface of the semiconductor chip 2 and 4 A total of five side surfaces are sealed (FIG. 9B).
  • the sealing material 6 is also sealed. All six surfaces of the semiconductor chip 2 are sealed (FIG. 10C).
  • the carrier 5 is peeled from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG.
  • Step 1C There is no particular limitation on the method for preparing the expanded tape and the plurality of semiconductor chips fixed on the expanded tape.
  • the semiconductor wafer can be transferred to an expanding tape. Dicing may be performed by forming a fragile layer with a laser and expanding. Further, from the viewpoint of improving productivity by omitting the above-described transfer, a semiconductor wafer may be directly laminated on an expanded tape, and the semiconductor wafer may be diced by the above-described method.
  • the initial semiconductor chip interval (semiconductor chip interval before the 2C process) is preferably narrower, preferably 100 ⁇ m or less, more preferably 80 ⁇ m or less, and even more preferably 60 ⁇ m or less. .
  • the semiconductor wafer is wasted as the above-mentioned chip interval is wide. Therefore, the narrower one as described above is preferable from the viewpoint of cost reduction.
  • the initial semiconductor chip interval is preferably 10 ⁇ m or more. If it is smaller than 10 ⁇ m, the expanded tape area between a plurality of semiconductor chips is small, so that it is difficult to spread.
  • the type of pad on the circuit surface of the semiconductor chip is not particularly limited as long as it can be formed on the circuit surface of the semiconductor chip. Even if it is a bump (projection electrode) such as a copper bump or a solder bump, Ni / Au It may be a relatively flat metal pad such as a plating pad.
  • Examples of expanding tape stretching methods include a push-up method and a pulling method.
  • the push-up method after the expanded tape is fixed, the expanded tape is stretched by raising the stage having a predetermined shape.
  • the tension method is a method in which the expanded tape is stretched by fixing the expanded tape and then pulling the expanded tape in a predetermined direction in parallel with the installed expanded tape surface.
  • the push-up method is preferable because the distance between the semiconductor chips can be extended uniformly and the required (occupied) device area is small and compact.
  • the stretching conditions may be appropriately set according to the characteristics of the expanded tape.
  • the push-up amount tensile amount
  • the push-up amount is preferably 10 mm to 500 mm, and more preferably 10 mm to 300 mm.
  • the temperature may be appropriately set according to the properties of the expanded tape, but may be, for example, 10 ° C to 200 ° C, 10 ° C to 150 ° C, or 20 ° C to 100 ° C. When the temperature is 10 ° C.
  • the push-up speed may be set as appropriate according to the properties of the expanded tape. For example, it may be 0.1 mm / second to 500 mm / second, such as 0.1 mm / second to 300 mm / second, 0.1 mm / second to 200 mm / second. It may be seconds. Productivity improves that it is 0.1 mm / second or more. When it is 500 mm / second or less, peeling between the semiconductor chip and the expanded tape is difficult to occur.
  • the interval between the plurality of semiconductor chips after the 2C step is preferably 300 ⁇ m or more from the viewpoint of more reliably protecting the side surfaces of the semiconductor chip with the sealing material in the sealing step (6C step). From the viewpoint of handleability, the interval between the plurality of semiconductor chips after the second C step is more preferably 500 ⁇ m or more, and further preferably 1 mm or more.
  • the upper limit is not particularly limited, but can be 5 mm or less.
  • the method of holding the expanded tape tension is not particularly limited as long as the tension is held and the distance between the semiconductor chips is not restored.
  • a method of fixing using a fixing jig such as a grip ring (manufactured by Technovision Co., Ltd.), a method of heating and contracting the outer peripheral portion of the expanded tape (heat shrink), and the like can be mentioned.
  • Step 4C The carrier is transferred (laminated) so that the circuit surfaces of the plurality of semiconductor chips are fixed.
  • the laminating method is not particularly limited, and a roll laminator, a diaphragm laminator, a vacuum roll laminator, a vacuum diaphragm laminator, and the like can be employed.
  • Lamination conditions may be set as appropriate according to the physical properties and characteristics of the expanded tape, semiconductor chip, and carrier.
  • a roll laminator it may be room temperature (25 ° C.) to 200 ° C., preferably room temperature (25 ° C.) to 150 ° C., more preferably room temperature (25 ° C.) to 100 ° C.
  • the semiconductor chip is easily transferred (laminated) to the carrier, and when the temperature is lower than 200 ° C., the semiconductor chip is displaced due to distortion or sag due to thermal expansion or low elasticity of the expanded tape (between the expanded tape and the semiconductor chip). ) And semiconductor chips are less likely to scatter.
  • the pressing time may be 5 seconds to 300 seconds, preferably 5 seconds to 200 seconds, and more preferably 5 seconds to 100 seconds. If it is 5 seconds or more, the semiconductor chip is easily transferred (laminated) to the carrier, and if it is 300 seconds or less, the productivity is improved.
  • the pressure may be 0.1 MPa to 3 MPa, preferably 0.1 MPa to 2 MPa, more preferably 0.1 MPa to 1 MPa. When it is 0.1 MPa or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when it is 2 MPa or less, damage to the semiconductor chip is reduced.
  • the adhesive force between the expanded tape and the carrier, the expanded tape and the semiconductor chip, and the semiconductor chip and the carrier should be such that the semiconductor chip transferred onto the carrier does not shift or peel off from the carrier. It is necessary to set appropriately.
  • the adhesive force between the expanded tape and the semiconductor chip is preferably the same as or smaller than the adhesive force between the semiconductor chip and the carrier.
  • the adhesive force is increased or decreased by applying a UV curing function to the expanded tape or the carrier surface and irradiating UV.
  • the expanded tape is removed after UV irradiation (adding UV irradiation process).
  • UV is irradiated to lower the adhesive force (adhesive force) of the expanded tape, and then the laminate is laminated on a carrier, and the expanded tape can be peeled off from the semiconductor chip.
  • the stress on the semiconductor chip is reduced, and the transfer can be performed smoothly without misalignment.
  • Step 6C A plurality of semiconductor chips on the carrier are sealed with a sealing material.
  • the sealing method is not particularly limited.
  • compression molding is liquid material, solid material, granule material, film material, etc.
  • transfer mold is liquid material, solid material, granule material
  • laminating film-like sealing materials for example, compression molding (sealing material shape is liquid material, solid material, granule material, film material, etc.), transfer mold (sealing material shape is liquid material, solid material, granule material) , Film material, etc.), and laminating film-like sealing materials.
  • a heat treatment step including post-cure may be added from the viewpoint of adjusting the physical properties of the sealing material. It is necessary to peel off the carrier after Step 6C or after the additional heat treatment step. Also when peeling off, a heat treatment, a UV treatment step or the like may be added. It is necessary to set the adhesion of the carrier (carrier + adhesive layer, carrier + temporary fixing material, etc.) so that the carrier can be peeled off without damaging the semiconductor chip and the sealing material after the above-described steps.
  • a carrier is peeled from a plurality of semiconductor chips sealed with a sealing material. Before the carrier is peeled off, a process of making the carrier easy to peel off by applying a chemical or mechanical change to the carrier surface layer in contact with the sealing material surface by heat treatment or UV irradiation may be introduced.
  • step 4C to step 7C by transferring the semiconductor chip from the expanded tape to the carrier, the risk of heat resistance in the heating step such as the sealing step can be reduced.
  • the semiconductor chip may be displaced or scattered due to distortion of the expandable expandable tape or deformation due to thermal expansion. May occur.
  • misalignment or chip scattering occurs, the productivity is reduced and the cost is increased. Therefore, it is necessary to transfer the semiconductor chip to the carrier.
  • Step 8C A plurality of semiconductor chips sealed with a sealing material are separated into individual semiconductor chips to form a plurality of semiconductor packages. This step can be performed by a conventionally known method.
  • the interval between the semiconductor chips in the 2C step is set in consideration of the blade width (the portion that is not cut). For example, when it is desired to leave a sealing material having a thickness of 50 ⁇ m on the side surface of the semiconductor chip and the dicing blade width is 250 ⁇ m, the expanded tape is formed so that the interval between the plurality of semiconductor chips after the second C step is 350 ⁇ m. What is necessary is just to set a characteristic and pushing-up conditions (expanding conditions).
  • the size of the semiconductor chip is not particularly limited, but is preferably ⁇ 20 mm or less, more preferably ⁇ 15 mm or less, and even more preferably ⁇ 10 mm or less from the viewpoint of the size that needs to be protected with a sealing material.
  • a back grinding process (a process of thinning the sealing material on the back side of the circuit surface of the semiconductor chip) may be introduced.
  • the back grinding process can be introduced, for example, after the sixth C process or after the seventh C process.
  • a back-grinding step (scraping the sealing material on the circuit surface side) for exposing the pad by back-grinding is performed. It may be introduced.
  • the same material as the material in the manufacturing method of the first semiconductor device can be used.
  • the fourth method for manufacturing a semiconductor device of this embodiment is as follows: A method of manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface, A first D step of preparing an expanded tape and a plurality of semiconductor chips each having a circuit surface fixed on the expanded tape; A second step of extending the interval between the plurality of semiconductor chips fixed on the expanded tape by stretching the expanded tape; A 3D step for maintaining the tension of the stretched expanded tape; A 4D step of transferring the carrier so that the surface opposite to the circuit surface of the plurality of semiconductor chips is fixed; A 5D step of peeling the expanded tape from a plurality of semiconductor chips; A 6D step of sealing a plurality of semiconductor chips on the carrier with a sealing material; A 7D step of polishing the sealing material to expose the pad; An 8D step of peeling the carrier from the plurality of semiconductor chips sealed by the sealing material; A ninth step of forming a plurality of semiconductor packages by dividing the plurality of semiconductor chips sealed by the sealing material into pieces
  • FIG. 11 is a schematic cross-sectional view for explaining an embodiment of the first to fourth steps
  • FIG. 12 is a schematic cross-sectional view for explaining an embodiment of the fifth to ninth steps
  • FIG. 13 is a schematic cross-sectional view for explaining another embodiment of the 7D process and the 8D process.
  • an expanded tape 1 and a plurality of semiconductor chips 2 fixed on the expanded tape 1 are prepared.
  • the expanded tape 1 has an adhesive layer 1 a and a base film 1 b, and the adhesive layer 1 a is in contact with the semiconductor chip 2.
  • the semiconductor chip 2 has a circuit surface provided with pads (circuits) 3, and the circuit surface is fixed to the expanded tape 1 (FIG. 11A).
  • the plurality of semiconductor chips 2 are arranged at intervals. Further, the pad 3 may be embedded in the expanded tape 1 at the time of fixing.
  • the expanded tape 1 is stretched to widen the intervals between the plurality of semiconductor chips 2 fixed on the expanded tape 1 (FIG. 11B).
  • the expanded tape 1 is fixed by using the fixing jig 4 to maintain the tension of the expanded tape 1 (FIG. 11C).
  • transfer is performed on the carrier 5 so that the surface opposite to the circuit surface of the plurality of semiconductor chips 2 is fixed (FIG. 11D).
  • the expanded tape 1 is peeled from the plurality of semiconductor chips 2 (FIG. 12A).
  • the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6 (FIG. 12B). At this time, since the surface opposite to the circuit surface of the semiconductor chip 2 is in contact with the carrier 5, this surface is not sealed, and the circuit surface and the four side surfaces of the semiconductor chip 2 are sealed in total. .
  • the sealing material 6 is polished to expose the pad 3.
  • the carrier 5 is peeled from the plurality of semiconductor chips 2 sealed with the sealing material 6.
  • the order of the 7D process and the 8D process can be switched. That is, after polishing the sealing material 6 to expose the pad 3 (FIG. 12C), the carrier 5 may be peeled from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 12 (d)), after the carrier 5 is peeled from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 13A), the pad 3 may be exposed by polishing the sealing material 6 Good (FIG. 13B).
  • the plurality of semiconductor chips 2 sealed with the sealing material 6 are separated into pieces for each semiconductor chip 2 to form a plurality of semiconductor packages 10 (FIG. 12E).
  • the above-described first to sixth steps can be carried out in the same manner as the above-described first to sixth steps, and the eighth and ninth steps are respectively the seventh and sixth steps. It can be carried out by the same method as in Step 8C.
  • the sealing material is polished to expose the pad. Polishing can be performed using a conventionally known polishing apparatus or the like. Note that the 7D step is not necessarily provided when the sealing can be performed with the circuit surface pads exposed in the 6D step.
  • the same material as that in the first semiconductor device manufacturing method can be used.
  • the carrier 5 the surface opposite to the circuit surface of the semiconductor chip is protected.
  • a carrier having a layer formed by laminating a material capable of protecting the sealing material and the chip by coating, spin coating, laminating, etc. on the above-mentioned layer bearing heat resistance and handleability may be used as a carrier. Good.
  • the distance between the separated semiconductor chips fixed on the expanded tape is increased from 100 ⁇ m or less to 300 ⁇ m or more by stretching the expanded tape while heating.
  • a tape expanding process is provided.
  • the manufacturing method of the semiconductor device of the present embodiment includes a tension holding step for holding the tension of the stretched expanded tape, a transfer step for transferring the semiconductor chip on the expanded tape holding the tension to the carrier, and a transfer to the carrier. And a peeling step of peeling the expanded tape from the semiconductor chip.
  • FIG. 14 is a schematic cross-sectional view for explaining an embodiment of a method for manufacturing a fifth semiconductor device
  • FIG. 15 is a schematic view for explaining another embodiment of a method for manufacturing the fifth semiconductor device. It is sectional drawing.
  • the expanded tape 1 to which the separated semiconductor chip 2 is fixed is prepared (hereinafter also referred to as “preparation step”).
  • the expanded tape 1 has an adhesive layer 1 a and a base film 1 b, and the adhesive layer 1 a is in contact with the semiconductor chip 2.
  • the semiconductor chip 2 has a circuit surface on which pads (circuits) 3 are provided.
  • the surface opposite to the circuit surface of the semiconductor chip 2 may be fixed to the expanded tape 1 (FIG. 14A), or the circuit surface may be fixed to the expanded tape 1 (FIG. 15A).
  • the expanded tape 1 is stretched while being heated, thereby widening the interval between the semiconductor chips 2 fixed on the expanded tape 1 (FIG. 14B or FIG. 15B).
  • the expanded tape 1 is fixed by using the fixing jig 4 to hold the tension of the expanded tape 1 (FIG. 14C or FIG. 15C).
  • the semiconductor chip 2 is transferred to the carrier 5.
  • the preparation step when the surface opposite to the circuit surface of the semiconductor chip 2 is fixed to the expanded tape 1, the circuit surface is fixed to the carrier 5 by the transfer (FIG. 14D), and the semiconductor chip 2 When the circuit surface is fixed to the expanded tape 1, the surface opposite to the circuit surface is fixed to the carrier 5 by the transfer (FIG. 15D).
  • the peeling step the expanded tape 1 is peeled from the semiconductor chip 2 (FIG. 14 (e) or FIG. 15 (e)).
  • ⁇ Preparation process> There is no particular limitation on the method for preparing the expanded tape on which the separated semiconductor chips are fixed. For example, after laminating a semiconductor wafer on a dicing tape or the like and dicing with a blade or a laser to obtain a plurality of individual semiconductor chips, the semiconductor wafer can be transferred to an expanding tape. Dicing may be performed by forming a fragile layer with a laser and expanding. Further, from the viewpoint of improving productivity by omitting the above-described transfer, a semiconductor wafer may be directly laminated on an expanded tape, and the semiconductor wafer may be diced by the above-described method.
  • the initial semiconductor chip interval (semiconductor chip interval before the tape expanding step) is preferably narrow, preferably 100 ⁇ m or less, preferably 80 ⁇ m or less, and more preferably 60 ⁇ m or less.
  • the semiconductor wafer is wasted as the above-mentioned chip interval is wide. Therefore, the narrower one as described above is preferable from the viewpoint of cost reduction.
  • the initial semiconductor chip interval is preferably 10 ⁇ m or more. If it is smaller than 10 ⁇ m, the expanded tape area between a plurality of semiconductor chips is small, so that it is difficult to spread.
  • the type of pad on the circuit surface of the semiconductor chip is not particularly limited as long as it can be formed on the circuit surface of the semiconductor chip. Even if it is a bump (projection electrode) such as a copper bump or a solder bump, Ni / Au It may be a relatively flat metal pad such as a plating pad.
  • ⁇ Tape expanding process By stretching the expanded tape while heating, the interval between the separated semiconductor chips fixed on the expanded tape is increased.
  • Examples of expanding tape stretching methods include a push-up method and a pulling method.
  • the push-up method after the expanded tape is fixed, the expanded tape is stretched by raising the stage having a predetermined shape.
  • the tension method is a method in which the expanded tape is stretched by fixing the expanded tape and then pulling the expanded tape in a predetermined direction in parallel with the installed expanded tape surface.
  • the push-up method is preferable because the distance between the semiconductor chips can be extended uniformly and the required (occupied) device area is small and compact.
  • the stretching conditions may be appropriately set according to the characteristics of the expanded tape.
  • the push-up amount tensile amount
  • the push-up amount is preferably 10 mm to 500 mm, and more preferably 10 mm to 300 mm.
  • the heating temperature may be appropriately set according to the expanded tape characteristics, but is preferably 25 ° C. to 200 ° C., for example. More preferably, it is 25 ° C to 150 ° C, and further preferably 30 ° C to 100 ° C. When the temperature is 25 ° C.
  • the push-up speed may be set as appropriate according to the properties of the expanded tape. For example, it may be 0.1 mm / second to 500 mm / second, such as 0.1 mm / second to 300 mm / second, 0.1 mm / second to 200 mm / second. It may be seconds. Productivity improves that it is 0.1 mm / second or more. When it is 500 mm / second or less, peeling between the semiconductor chip and the expanded tape is difficult to occur.
  • the interval between the semiconductor chips after the tape expanding step may be 300 ⁇ m or more, but an appropriate interval can be selected according to the application.
  • 500 ⁇ m or more is preferable in order to secure a space necessary for providing the rewiring pattern and the connection terminal pad outside the region of the semiconductor chip.
  • the semiconductor chip interval is wide. From the above viewpoint, the interval between the plurality of semiconductor chips after the tape expanding step is preferably 1 mm or more, and more preferably 2 mm or more.
  • the interval between the semiconductor chips after the tape expanding process is 300 ⁇ m or more from the viewpoint of more reliably protecting the side surface of the semiconductor chip with the sealing material in the sealing process.
  • the interval between the plurality of semiconductor chips after the tape expanding step is preferably 500 ⁇ m or more, and more preferably 1 mm.
  • the upper limit of the interval between the semiconductor chips after the tape expanding process is not particularly limited, but can be 5 mm or less.
  • the method of holding the expanded tape tension is not particularly limited as long as the tension is held and the distance between the semiconductor chips is not restored.
  • a method of fixing using a fixing jig such as a grip ring (manufactured by Technovision Co., Ltd.), a method of heating and contracting the outer peripheral portion of the expanded tape (heat shrink), and the like can be mentioned.
  • Transfer is performed so that the semiconductor chip is fixed to the carrier.
  • the laminating method is not particularly limited, and a roll laminator, a diaphragm laminator, a vacuum roll laminator, a vacuum diaphragm laminator, and the like can be employed.
  • Lamination conditions may be set as appropriate according to the physical properties and characteristics of the expanded tape, semiconductor chip, and carrier.
  • a roll laminator it may be room temperature (25 ° C.) to 200 ° C., preferably room temperature (25 ° C.) to 150 ° C., more preferably room temperature (25 ° C.) to 100 ° C.
  • the semiconductor chip is easily transferred (laminated) to the carrier, and when the temperature is lower than 200 ° C., the semiconductor chip is displaced due to distortion or slack due to thermal expansion or low elasticity of the expanded tape (between the expanded tape and the semiconductor chip). ) And semiconductor chips are less likely to scatter.
  • the pressing time may be 5 seconds to 300 seconds, preferably 5 seconds to 200 seconds, and more preferably 5 seconds to 100 seconds. If it is 5 seconds or more, the semiconductor chip is easily transferred (laminated) to the carrier, and if it is 300 seconds or less, the productivity is improved.
  • the pressure may be 0.1 MPa to 3 MPa, preferably 0.1 MPa to 2 MPa, more preferably 0.1 MPa to 1 MPa. When it is 0.1 MPa or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when it is 2 MPa or less, damage to the semiconductor chip is reduced.
  • the adhesive force between the expanded tape and the carrier, the expanded tape and the semiconductor chip, and the semiconductor chip and the carrier should be such that the semiconductor chip transferred onto the carrier does not shift or peel off from the carrier. It is necessary to set appropriately.
  • the adhesive force between the expanded tape and the semiconductor chip is preferably the same as or smaller than the adhesive force between the semiconductor chip and the carrier.
  • the adhesive force is increased or decreased by applying UV (ultraviolet) curing function to the expanded tape or the carrier surface and irradiating with UV.
  • the expanded tape is removed after UV irradiation (adding UV irradiation process).
  • UV is irradiated to lower the adhesive force (adhesive force) of the expanded tape, and then the expanded tape is peeled off from the semiconductor chip by laminating on the carrier.
  • the stress on the semiconductor chip is reduced, and the transfer can be performed smoothly without misalignment.
  • the method for manufacturing a semiconductor device may further include a sealing step of sealing the semiconductor chip fixed on the carrier with a sealing material after the peeling step (not shown).
  • a sealing step of sealing the semiconductor chip fixed on the carrier with a sealing material after the peeling step (not shown).
  • the manufacturing method of the semiconductor device of this embodiment since there is a sufficient space between the semiconductor chips, there are a total of five surfaces including the four side surfaces of the semiconductor chip and the surface opposite to the surface not fixed to the carrier. At least sealed.
  • the interval between the semiconductor chips can be sufficiently widened in the tape expanding process. Can be applied to.
  • the sealing process may be a sealing process in which the semiconductor chip fixed on the expanded tape is sealed with a sealing material after the tension holding process.
  • the sealing method is not particularly limited.
  • compression molding is liquid material, solid material, granule material, film material, etc.
  • transfer mold is liquid material, solid material, granule material
  • laminating film-like sealing materials for example, compression molding (sealing material shape is liquid material, solid material, granule material, film material, etc.), transfer mold (sealing material shape is liquid material, solid material, granule material) , Film material, etc.), and laminating film-like sealing materials.
  • a heat treatment step including post-cure may be added from the viewpoint of adjusting the physical properties of the sealing material. It is necessary to peel off the carrier after the sealing step or after the additional heat treatment step. Also when peeling off, a heat treatment, a UV treatment step or the like may be added. It is necessary to set the adhesion of the carrier (carrier + adhesive layer, carrier + temporary fixing material, etc.) so that the carrier can be peeled off without damaging the semiconductor chip and the sealing material after the above-described steps.
  • a back grinding process (a process of reducing the thickness of the sealing material on the back side of the circuit surface of the semiconductor chip) after the sealing process is introduced. Good.
  • the same material as that used in the method for manufacturing the first semiconductor device described above can be used, but the expanded tape of the present embodiment shown below is used. It can be particularly preferably used. Note that the expanded tape of the present embodiment can be manufactured by the same method as the expanded tape manufacturing method in the above-described first semiconductor device manufacturing method.
  • the expanded tape of the present embodiment has a tensile stress of 10 MPa or less at a heating temperature (for example, 50 ° C.) in the above tape expanding step, and a tensile stress at room temperature (25 ° C.) of 5 MPa or more than the tensile stress at the heating temperature. high.
  • a heating temperature for example, 50 ° C.
  • a tensile stress at room temperature 25 ° C.
  • the tape expanding process it is the expansion of the expanded tape in the area where the semiconductor chip is fixed that contributes to increasing the distance between the semiconductor chips, and the expansion at the end of the expanded tape increases the distance between the semiconductor chips. Does not contribute.
  • the expanded tape in the region where the semiconductor chip is fixed stage region
  • the end portion of the expanded tape is not heated and reaches room temperature.
  • the expanded tape is heated, the tensile stress is reduced, and the expanded tape is more easily stretched when the tensile stress is smaller.
  • the tensile stress of the expanded tape at the heating temperature in the tape expanding step is set to be small in the predetermined range, and the tensile stress at room temperature of the expanded tape is set higher than the predetermined value by the tensile stress at the heating temperature.
  • the expansion of the expanded tape in the region where the semiconductor chip is fixed becomes sufficiently larger than the expansion of the end portion of the expanded tape, and the interval between the semiconductor chips can be further widened.
  • the tensile stress at the heating temperature of the expanded tape is preferably 9 MPa or less, and more preferably 8 MPa or less in order to further widen the interval between the semiconductor chips after expansion.
  • the tensile stress at the heating temperature of the expanded tape is not particularly limited, but is preferably 0.1 MPa or more. If it is less than 0.1 MPa, chip distortion or tape deflection tends to occur.
  • the tensile stress at room temperature (25 ° C.) of the expanded tape is preferably 6 MPa or higher, more preferably 7 MPa or higher than the tensile stress at the heating temperature in order to further widen the interval between the semiconductor chips after expansion. .
  • the tensile stress is a value at a tensile strain of 1 (mm / mm) when measured with a micro force tester (manufactured by INSTRON, INSTRON 5948). The tensile speed was 5 mm / second.
  • the chip interval between the MD and TD after the tape expanding process is uniform.
  • the semiconductor chip and the connection terminal pads connected thereto are separated into a group after sealing, damage to the semiconductor chip is caused. If dicing is possible in a state where there is no damage (if the blade does not damage the semiconductor chip), the MD and TD widths may not be uniform. At the time of dicing, the dicing interval width of MD and TD may not be the same. However, MD lines and TD lines are preferably uniform.
  • the expanded tape preferably has a multi-layer structure such as a base film (base layer) that greatly contributes to stretchability and an adhesive layer that controls adhesive strength.
  • the base film has stretchability and stability for maintaining the distance between the semiconductor chips after the tension holding step.
  • the base film is a polyester film such as a polyethylene terephthalate film; a polytetrafluoroethylene film, a polyethylene film, a polypropylene film, a polymethylpentene film, a polyvinyl acetate film, and an ⁇ -olefin such as poly-4-methylpentene-1.
  • the base film is not limited to a single layer film, and may be a multilayer film obtained by combining two or more plastic films or two or more plastic films of the same type.
  • the base film is preferably a polyolefin film or a urethane resin film from the viewpoint of stretchability.
  • the base film may contain various additives such as an anti-blocking agent as necessary.
  • the thickness of the base film may be appropriately set as necessary, but is preferably 50 ⁇ m to 500 ⁇ m. If the thickness is less than 50 ⁇ m, the stretchability is deteriorated, and if it is more than 500 ⁇ m, problems such as distortion is likely to occur and handling properties are deteriorated.
  • the thickness of the base film is appropriately selected within a range that does not impair workability.
  • a high energy ray (in particular, ultraviolet ray) curable pressure sensitive adhesive is used as the pressure sensitive adhesive constituting the pressure sensitive adhesive layer, it is necessary to have a thickness that does not inhibit the transmission of the high energy ray.
  • the thickness of the base film may be usually 10 to 500 ⁇ m, preferably 50 to 400 ⁇ m, and more preferably 70 to 300 ⁇ m.
  • the substrate layer is composed of a plurality of substrate films, it is preferable to adjust so that the thickness of the entire substrate layer is within the above range.
  • the base film may be subjected to a chemical or physical surface treatment as necessary in order to improve the adhesion with the adhesive layer. Examples of the surface treatment include corona treatment, chromic acid treatment, ozone exposure, flame exposure, high piezoelectric impact exposure, and ionizing radiation treatment.
  • the adhesive layer is not particularly limited as long as the adhesive force can be controlled (setting so that the semiconductor chip is not displaced or scattered for each process).
  • the pressure-sensitive adhesive layer is preferably composed of a pressure-sensitive adhesive component that has adhesive strength at room temperature and has adhesion to the semiconductor chip.
  • the base resin of the pressure-sensitive adhesive component that constitutes the pressure-sensitive adhesive layer include acrylic resin, synthetic rubber, natural rubber, and polyimide resin.
  • the base resin preferably has a functional group (such as a hydroxyl group or a carboxyl group) that can react with other additives.
  • a resin curable by high energy rays such as ultraviolet rays and radiation (particularly an ultraviolet curable resin) or a resin curable by heat (thermosetting resin) may be used.
  • an ultraviolet curable pressure-sensitive adhesive containing an ultraviolet curable resin is preferably used.
  • the pressure-sensitive adhesive component may include a cross-linking agent capable of performing a cross-linking reaction with the functional group of the base resin.
  • the crosslinking agent preferably has at least one functional group selected from the group consisting of an epoxy group, an isocyanate group, an aziridine group, and a melanin group. These crosslinking agents may be used alone or in combination of two or more.
  • catalysts such as an amine and tin, as needed.
  • the adhesive may appropriately contain rosin-based, tackifiers such as terpene resins, and optional components such as various surfactants.
  • the thickness of the adhesive layer is usually 1 to 100 ⁇ m, preferably 2 to 50 ⁇ m, more preferably 5 to 40 ⁇ m.
  • the thickness of the adhesive layer is usually 1 to 100 ⁇ m, preferably 2 to 50 ⁇ m, more preferably 5 to 40 ⁇ m.
  • the adhesive layer is 10 ⁇ m or more, even if the semiconductor wafer is diced on the expanded tape without using the dicing tape, the substrate film will not be damaged (notched, etc.). The process of dicing the wafer and transferring (attaching) it to the expanded tape can be omitted.
  • ethyl acetate was added to adjust the non-volatile content in the acrylic resin solution to 35% by mass to obtain an acrylic resin solution having a functional group capable of chain polymerization.
  • the acid value and hydroxyl value of this resin were measured according to JIS K0070, the acid value was not detected and the hydroxyl value was 121 mgKOH / g.
  • the obtained acrylic resin solution was vacuum-dried at 60 degreeC overnight, and the obtained solid content was elementally analyzed with the fully automatic elemental-analysis apparatus (The Elemental Co., Ltd. product, varioEL). From the measured nitrogen content, the content of 2-methacryloxyethyl isocyanate introduced into the acrylic resin was calculated to be 0.59 mmol / g.
  • the obtained solution was applied and dried on a protective film (surface release-treated polyethylene terephthalate, thickness 25 ⁇ m) to form an adhesive layer.
  • a protective film surface release-treated polyethylene terephthalate, thickness 25 ⁇ m
  • two types having an adhesive layer thickness of 10 ⁇ m or 30 ⁇ m at the time of drying were prepared.
  • the adhesive layer surface was laminated on a base film (thickness: 100 ⁇ m).
  • the obtained two kinds of tapes were aged at 40 ° C. for 4 days.
  • the tape with an adhesive layer of 10 ⁇ m was designated as expanded tape A
  • the tape with 30 ⁇ m was designated as expanded tape B.
  • the base film examples include HiMilan 1706 (Mitsui DuPont Polychemical Co., Ltd., ionomer resin), ethylene / 1-hexene copolymer and butene / ⁇ -olefin copolymer, and HiMilan 1706 in this order.
  • HiMilan 1706 Mitsubishi DuPont Polychemical Co., Ltd., ionomer resin
  • ethylene / 1-hexene copolymer and butene / ⁇ -olefin copolymer examples of the base film.
  • HiMilan 1706 HiMilan 1706
  • a laminated three-layer resin film was used.
  • the adhesive layer, the protective film, and the base film were laminated with a roll laminator at 40 ° C., and the protective film / adhesive layer / base film was in this order.
  • the protective film was peeled off.
  • step 1 ⁇ Preparation of semiconductor chip separated on expanded tape (step 1)> (Evaluation sample A) An 8-inch silicon wafer (thickness: 250 ⁇ m) is laminated on a dicing tape at 40 ° C. using a wafer mount device (DM-300-H, manufactured by JCM Co., Ltd.), and a dicing device (DFD6361) with a blade to a size of 5 mm ⁇ 5 mm. , Manufactured by DISCO Corporation).
  • DM-300-H manufactured by JCM Co., Ltd.
  • Evaluation sample B An 8-inch silicon wafer (thickness 250 ⁇ m) is laminated on the expanded tape B at 40 ° C. using a wafer mount device (DM-300-H, manufactured by JMC Corporation), and a dicing device (5 mm ⁇ 5 mm) with a blade ( Dicing was performed using DFD 6361 (manufactured by DISCO Corporation) to prepare an evaluation sample B. Evaluation sample B was fixed to a 12-inch dicing ring. At this time, the initial semiconductor chip interval was about 50 ⁇ m.
  • Evaluation sample C An 8-inch silicon wafer (thickness: 250 ⁇ m) is laminated on a dicing tape at 40 ° C. using a wafer mount device (DM-300-H, manufactured by JCM Co., Ltd.), and a dicing device (DFD6361) with a blade to a size of 5 mm ⁇ 5 mm. And an evaluation sample C was manufactured by dicing using a disco). At this time, the initial semiconductor chip interval was about 50 ⁇ m.
  • a temporary fixing material was laminated on a 12-inch silicon wafer (original thickness: 775 ⁇ m) with a vacuum laminator (V130, manufactured by Nikko Materials Co., Ltd.), and the outer shape was processed into a wafer shape to prepare a carrier.
  • Lamination conditions were a diaphragm temperature of 80 ° C., a stage of 40 ° C., a time of 60 s, and a pressure of 0.5 MPa.
  • Evaluation samples A and B are set in a 12-inch expander device (MX-5154FN, manufactured by Omiya Kogyo Co., Ltd.), pushed up at a speed of 100 mm / second, pushed up at a temperature (stage temperature) of 50 ° C. for 1 second (push-up amount: 100 mm), and expanded. I stretched the tape. At this time, the semiconductor chip interval for both the evaluation samples A and B increased from about 50 ⁇ m in the initial stage to about 1 mm.
  • MX-5154FN manufactured by Omiya Kogyo Co., Ltd.
  • Step 3> Evaluation samples A and B obtained by stretching the expanded tape were fixed with a grip ring for 12-inch expander (manufactured by Technovision Co., Ltd., GR-12) to maintain the tension. Since Step 2 and Step 3 occur in conjunction with each other (an apparatus that is fixed with a grip ring at the same time that the thrust reaches 100 mm), Step 2 and Step 3 were completed in 1 second.
  • Step 4> After irradiating the evaluation samples A and B holding the tension with UV (UV exposure machine ML-320FSAT, manufactured by Mikasa Co., Ltd.), a semiconductor chip is used as a carrier using a vacuum laminator (V130, manufactured by Nikko Materials Co., Ltd.). Laminated surfaces.
  • Lamination conditions were a diaphragm temperature of 60 ° C., a stage temperature of 60 ° C., a pressure of 0.5 MPa, and 60 seconds.
  • ⁇ Step 5> Only the expanded tape was peeled off from the evaluation samples A and B after lamination to prepare evaluation samples A ′ and B ′ in which semiconductor chips were arranged on the carrier (temporary fixing material).
  • the evaluation samples A ′ and B ′ prepared from the evaluation samples A and B were both good with no semiconductor chip scattering or misalignment.
  • the peeling operation of the expanded tape was performed at room temperature (25 ° C.) / 10 seconds.
  • Evaluation samples A ′ and B ′ were sealed with a sealing device (CPM1180, manufactured by TOWA Corporation) using the sealing material.
  • the sealing was performed with a 12-inch wafer size and a thickness of 350 ⁇ m. Granules were used as the shape of the sealing material.
  • the method was a compression mold.
  • the sealing conditions were 150 ° C./10 minutes / 37 ton. Thereafter, curing at 150 ° C./1 h was performed. After curing, heat treatment was performed at 180 ° C. for 5 minutes to peel off the carrier, and the carrier was peeled off.
  • the evaluation sample C was picked up from the dicing tape with a flip chip bonder (LFB2301, manufactured by Shinkawa Co., Ltd.) and rearranged on the carrier.
  • the crimping time (rearrangement time) around one semiconductor chip having a size of 5 mm ⁇ 5 mm was 2 seconds including the pickup. Since the evaluation sample C has about 1250 semiconductor chips having a size of 5 mm ⁇ 5 mm (calculated to be about 1256, but excluding peripheral chips that are 5 mm ⁇ 5 mm or less during dicing) Placement took 2500 seconds.
  • the interval between the semiconductor chips was set to 1 mm as in the evaluation samples A and B.
  • the sample rearranged on the carrier was designated as an evaluation sample C ′.
  • Evaluation sample C ′ was sealed with a sealing device (CPM1180, manufactured by TOWA Corporation) using the sealing material.
  • the sealing was performed with a 12-inch wafer size and a thickness of 350 ⁇ m. Granules were used as the shape of the sealing material.
  • the method was a compression mold.
  • the sealing conditions were 150 ° C./10 minutes / 37 ton. Thereafter, curing at 150 ° C./1 h was performed. After curing, heat treatment was performed at 180 ° C. for 5 minutes to peel off the carrier, and the carrier was peeled off.
  • (I) Measuring method of semiconductor chip interval The interval between the semiconductor chips was measured with a microscope capable of measuring length (ECLIPSE-L, manufactured by Nikon Corporation). The measurement was performed at a total of 5 points, 1 point at the center and 4 points at the periphery (one point at the top, bottom, left and right of the center). The semiconductor chip interval was an average value of 5 points.
  • Examples 1 and 2 The manufacturing method of the present invention (Examples 1 and 2) has the same accuracy (positional deviation evaluation) as compared with the conventional method (comparative example), and the productivity is remarkably improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

La présente invention concerne une bande d'expansion (1) destinée à être utilisée dans un procédé de fabrication de dispositif à semi-conducteurs comprenant une étape d'expansion de bande dans laquelle la bande d'expansion (1) est chauffée et étendue pour augmenter l'intervalle de puces semi-conductrices individualisées (2), fixées sur la bande d'expansion (1), d'un maximum de 100 µm et d'un minimum de 300 µm. La bande d'expansion (1) présente une contrainte de traction supérieure ne dépassant pas 10 MPa à la température de chauffage de l'étape d'expansion de bande, et une contrainte de traction à température ambiante qui est égale à 5 MPa ou plus élevée que la contrainte de traction à la température de chauffage.
PCT/JP2018/019325 2017-05-22 2018-05-18 Procédé de fabrication de dispositif à semi-conducteurs et bande d'expansion WO2018216621A1 (fr)

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CN201880033282.1A CN110637355B (zh) 2017-05-22 2018-05-18 半导体装置的制造方法及扩展带
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KR102203639B1 (ko) * 2019-08-26 2021-01-15 (주)라이타이저 디스플레이 장치의 제조 방법 및 디스플레이 장치
WO2021102877A1 (fr) * 2019-11-29 2021-06-03 重庆康佳光电技术研究院有限公司 Plaque de support de transfert de masse, dispositif de transfert de masse, et procédé associé
KR20210071919A (ko) * 2019-08-12 2021-06-16 (주)라이타이저 디스플레이 장치의 제조 방법 및 디스플레이 장치
JP2021093452A (ja) * 2019-12-10 2021-06-17 Jsr株式会社 表示装置の製造方法、チップ部品の移設方法、および感放射線性組成物
WO2021192341A1 (fr) * 2020-03-27 2021-09-30 昭和電工マテリアルズ株式会社 Procédé de production de boîtiers de semi-conducteur
JP7188658B1 (ja) * 2021-09-27 2022-12-13 昭和電工マテリアルズ株式会社 半導体装置の製造方法
WO2023033161A1 (fr) * 2021-09-03 2023-03-09 株式会社レゾナック Procédé de fabrication de dispositif à semi-conducteurs, matériau de fixation temporaire, et application pour fabriquer un dispositif à semi-conducteurs de matériau de fixation temporaire
JP7389331B2 (ja) 2019-10-31 2023-11-30 日亜化学工業株式会社 発光デバイスの製造方法
JP7415735B2 (ja) 2020-03-27 2024-01-17 株式会社レゾナック 半導体パッケージの製造方法
JP7459576B2 (ja) 2020-03-12 2024-04-02 株式会社レゾナック パネル及びその製造方法、パネル製造用部材及びその製造方法、並びに半導体チップ

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WO2020170366A1 (fr) * 2019-02-20 2020-08-27 日立化成株式会社 Procédé de fabrication de dispositif à semi-conducteur et bande d'expansion
WO2020171084A1 (fr) * 2019-02-20 2020-08-27 日立化成株式会社 Procédé de fabrication de dispositif à semi-conducteur et bande d'expansion
KR20210071919A (ko) * 2019-08-12 2021-06-16 (주)라이타이저 디스플레이 장치의 제조 방법 및 디스플레이 장치
KR102626606B1 (ko) * 2019-08-12 2024-01-19 (주)라이타이저 디스플레이 장치의 제조 방법 및 디스플레이 장치
KR102203639B1 (ko) * 2019-08-26 2021-01-15 (주)라이타이저 디스플레이 장치의 제조 방법 및 디스플레이 장치
JP7389331B2 (ja) 2019-10-31 2023-11-30 日亜化学工業株式会社 発光デバイスの製造方法
WO2021102877A1 (fr) * 2019-11-29 2021-06-03 重庆康佳光电技术研究院有限公司 Plaque de support de transfert de masse, dispositif de transfert de masse, et procédé associé
JP2021093452A (ja) * 2019-12-10 2021-06-17 Jsr株式会社 表示装置の製造方法、チップ部品の移設方法、および感放射線性組成物
JP7243606B2 (ja) 2019-12-10 2023-03-22 Jsr株式会社 表示装置の製造方法、チップ部品の移設方法、および感放射線性組成物
JP7459576B2 (ja) 2020-03-12 2024-04-02 株式会社レゾナック パネル及びその製造方法、パネル製造用部材及びその製造方法、並びに半導体チップ
WO2021192341A1 (fr) * 2020-03-27 2021-09-30 昭和電工マテリアルズ株式会社 Procédé de production de boîtiers de semi-conducteur
JP7415735B2 (ja) 2020-03-27 2024-01-17 株式会社レゾナック 半導体パッケージの製造方法
WO2023033161A1 (fr) * 2021-09-03 2023-03-09 株式会社レゾナック Procédé de fabrication de dispositif à semi-conducteurs, matériau de fixation temporaire, et application pour fabriquer un dispositif à semi-conducteurs de matériau de fixation temporaire
JP7343080B2 (ja) 2021-09-03 2023-09-12 株式会社レゾナック 半導体装置を製造する方法、仮固定材、及び、仮固定材の半導体装置を製造するための応用
WO2023032163A1 (fr) * 2021-09-03 2023-03-09 株式会社レゾナック Procédé de production d'un dispositif à semi-conducteurs, matériau de fixation provisoire, et application d'un matériau de fixation provisoire pour la production d'un dispositif à semi-conducteurs
WO2023047592A1 (fr) * 2021-09-27 2023-03-30 株式会社レゾナック Procédé de fabrication de dispositif à semi-conducteur
JP7188658B1 (ja) * 2021-09-27 2022-12-13 昭和電工マテリアルズ株式会社 半導体装置の製造方法

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