WO2018205774A1 - 静电防护装置及其制作方法、阵列基板 - Google Patents

静电防护装置及其制作方法、阵列基板 Download PDF

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Publication number
WO2018205774A1
WO2018205774A1 PCT/CN2018/081731 CN2018081731W WO2018205774A1 WO 2018205774 A1 WO2018205774 A1 WO 2018205774A1 CN 2018081731 W CN2018081731 W CN 2018081731W WO 2018205774 A1 WO2018205774 A1 WO 2018205774A1
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layer
conductive
conductive layer
film layer
polarizing film
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PCT/CN2018/081731
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English (en)
French (fr)
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张东徽
倪欢
马小叶
马睿
王锡平
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/092,720 priority Critical patent/US11158625B2/en
Publication of WO2018205774A1 publication Critical patent/WO2018205774A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H59/00—Electrostatic relays; Electro-adhesion relays
    • H01H59/0009—Electrostatic relays; Electro-adhesion relays making use of micromechanics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H71/00—Details of the protective switches or relays covered by groups H01H73/00 - H01H83/00
    • H01H71/10—Operating or release mechanisms
    • H01H71/12—Automatic release mechanisms with or without manual release
    • H01H71/127—Automatic release mechanisms with or without manual release using piezoelectric, electrostrictive or magnetostrictive trip units
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/04—Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
    • H10N30/045—Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/20—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
    • H10N30/204—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators using bending displacement, e.g. unimorph, bimorph or multimorph cantilever or membrane benders
    • H10N30/2041—Beam type
    • H10N30/2042—Cantilevers, i.e. having one fixed end
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H59/00—Electrostatic relays; Electro-adhesion relays
    • H01H2059/009—Electrostatic relays; Electro-adhesion relays using permanently polarised dielectric layers

Definitions

  • Embodiments of the present disclosure relate to an electrostatic protection device, a method of fabricating the same, and an array substrate.
  • the function of the electrostatic protection device is to prevent the semiconductor device on the display panel from being damaged or failed due to electrostatic discharge, thereby preventing damage or failure of the entire display panel, for example, on the data pad (DP) side of the display panel and
  • the ESD (Electro-Static discharge) protection design between the data line opposite (DPO) data line and the common electrode line is more important.
  • the existing ESD (Electro-Static discharge) protection device consists of 2-4 parallel or series triodes, that is, a reinforced diode is formed. When the voltage difference between the data line and the common electrode line on the DP side and the DPO side reaches a certain level, discharge of static electricity in the data line and the common electrode line in the display panel is achieved. A similar situation exists on the gate pad (GP) side and the gate pad opposite (GPO).
  • the ESD protection device still has a current under a normal voltage.
  • An embodiment of the present disclosure provides an electrostatic protection device including: a first conductive layer, a second conductive layer, and a polarizing film layer disposed between the first conductive layer and the second conductive layer, the polarizing film layer Forming a piezoelectric material capable of deforming after being energized; a conductive cantilever beam disposed on the second conductive layer, the free end of the conductive cantilever arm; a conductive evacuation layer, the conductive evacuation layer Located on a side of the conductive suspension beam arm away from the polarizing film layer, the conductive evacuation layer is electrically connected to the first conductive layer and spaced apart from the conductive suspension beam arm; when the first conductive layer is When the voltage difference between the second conductive layers reaches a preset value, the polarization film layer is deformed such that the conductive suspension beam arms are connected to the conductive evacuation layer.
  • the static electricity protection device further includes an alignment film layer formed over the first insulating layer.
  • the alignment film layer material is polysilicon.
  • the deformation direction of the polarizing film layer is the direction of the voltage between the first conductive layer and the second conductive layer.
  • the conductive evacuation layer and the free end of the electrically conductive cantilever arm at least partially coincide with the projection of the first electrically conductive layer.
  • the polarizing film layer is a chromium-doped zinc oxide layer.
  • the embodiment of the present disclosure further provides a method for fabricating the above-mentioned electrostatic protection device, comprising: sequentially forming a first conductive layer, a polarizing film layer, and a second conductive layer, wherein the polarizing film layer includes a piezoelectric material capable of deforming after being energized Forming a conductive cantilever beam on the second conductive layer, the conductive cantilever beam including a free end; forming a conductive evacuation layer, the conductive evacuation layer being electrically connected to the first conductive layer, located at the conductive cantilever arm away from One side of the polarizing film layer is spaced apart from the conductive suspension beam arm; when the voltage difference between the first conductive layer and the second conductive layer reaches a preset value, the polarizing film Deformation of the layer causes the free end of the electrically conductive cantilever beam to be coupled to the electrically conductive evacuation layer.
  • forming the polarizing film layer includes: forming a piezoelectric film layer on the first conductive layer; a voltage difference between the first conductive layer and the second conductive layer satisfies the preset voltage The piezoelectric film layer is subjected to polarization treatment under poor conditions.
  • the manufacturing method further includes forming an alignment film layer over the first conductive layer before forming the piezoelectric film layer.
  • the material of the alignment film layer is polysilicon.
  • forming the piezoelectric film layer includes: depositing a piezoelectric material on the first conductive layer by using a metal oxide chemical vapor deposition method to form a weakly oriented film layer; and forming a weakly oriented film layer in the first The annealing process is performed at a predetermined temperature to form a first piezoelectric film layer having a polycrystalline structure; wherein the first predetermined temperature is greater than or equal to 250 degrees Celsius and less than or equal to 350 degrees Celsius.
  • performing polarization treatment on the piezoelectric film layer to form a polarizing film layer includes: bringing the first piezoelectric film layer to a second preset temperature, and adjusting the first conductive layer and the second a voltage between the conductive layers, wherein the second preset temperature is greater than or equal to 50 degrees Celsius and less than or equal to 150 degrees Celsius; after the adjusted voltage difference reaches a preset voltage difference, the temperature is lowered until the third preset is reached.
  • a polarizing film layer is formed, wherein the third preset temperature is greater than or equal to 10 degrees Celsius and less than or equal to 40 degrees Celsius.
  • forming the conductive suspension beam arm includes: forming an insulation layer after forming the second conductive layer, having a gap between the insulation layer and the second conductive layer; forming a first photoresist in the gap Depositing the first photoresist with the second conductive layer and having the same height as the second conductive layer; depositing on the second conductive layer and the first photoresist
  • the first nano-indium tin metal oxide layer is formed by an annealing process to form a conductive cantilever beam.
  • the height of the surface of the insulating layer is higher than the height of the surface of the cantilever beam
  • forming the conductive evacuation layer comprises: forming a second photoresist in the gap, the second photoresist and the a surface of the insulating layer and having the same height as the insulating layer; a second nano-indium tin metal oxide layer is deposited on the insulating layer and the second photoresist, and conductive is formed by an annealing process Evacuation layer.
  • Embodiments of the present disclosure also provide an array substrate including the above-described static electricity protection device.
  • the array substrate includes a display area and a peripheral area, and the static electricity protection device is disposed in the peripheral area.
  • the array substrate further includes a gate line and a common electrode line, a first conductive layer of the static electricity protection device is connected to the gate line, and a second conductive layer of the static electricity protection device is connected to the common electrode line.
  • the first conductive layer is disposed in the same layer as the gate line, and the second conductive layer is disposed in the same layer as the common electrode line.
  • the array substrate further includes a data line and a common electrode line, a first conductive layer of the static electricity protection device is connected to the data line, and a second conductive layer of the static electricity protection device is connected to the common electrode line.
  • the first conductive layer is disposed in the same layer as the data line
  • the second conductive layer is disposed in the same layer as the common electrode line.
  • 1 is a schematic diagram showing the relationship between voltage and current of an ESD protection device
  • FIG. 2a is a schematic structural diagram of an electrostatic protection device according to an embodiment of the present disclosure
  • Figure 2b is a schematic cross-sectional view along line A-A of Figure 2a;
  • 2c is a schematic structural diagram of an electrostatic protection device according to an embodiment of the present disclosure.
  • 2d is a schematic structural view of an electrostatic protection device according to an embodiment of the present disclosure during discharge
  • 2 e is a schematic structural diagram of an electrostatic protection device according to an embodiment of the present disclosure.
  • 3a-3c are schematic structural views of an electrostatic protection device according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an electrostatic protection device according to another embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a method for fabricating an electrostatic protection device according to an embodiment of the present disclosure
  • FIGS. 6a-6j are schematic structural views of an electrostatic protection device according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • an electrostatic protection device 10 including: a first conductive layer 110; a polarizing film layer partially formed on the first insulating layer 120 130.
  • the polarizing film layer is formed of a piezoelectric material capable of deforming after being energized; a second conductive layer 140 at least partially formed on the polarizing film layer 130; and formed on the second conductive layer 140 a conductive cantilever arm 150; a second insulating layer 160 formed over the first insulating layer 120; formed over the second insulating layer 160 and connected to the first conductive layer 110 through a via 161 in the second insulating layer 160 Conductive evacuation layer 170; conductive cantilever arm 150 is located between conductive evacuation layer 170 and first conductive layer 110.
  • the material of the first conductive layer 110 and the second conductive layer 140 is a metal material.
  • the static electricity protection device 10 may further include a first insulating layer 120 disposed between the first conductive layer 110 and the polarizing film layer 130.
  • the conductive suspension beam arm 150 includes a fixed end 151 and a free end 152.
  • the fixed end 151 is connected to the second conductive layer 140.
  • the conductive evacuation layer 170 includes a first end 171 and a second end 172.
  • the first end 171 passes through the second insulating layer 160.
  • the via 161 is connected to the first conductive layer 110 (see Figure 2a for the location of the via in the second insulating layer 160).
  • Conductive cantilever arms 150 are spaced from conductive evacuation layer 170. For example, as shown in Figure 2c, there is a gap between the free end 152 of the conductive cantilever arm 150 and the second end 172 of the electrically conductive evacuation layer, and the projections of the two on the first conductive layer 110 at least partially coincide.
  • the electrostatic protection device 10 operates as follows.
  • the polarizing film layer 130 is deformed such that the free end 152 of the conductive cantilever arm is connected to the second end 172 of the conductive evacuation layer.
  • the free end 152 of the conductive cantilever beam moves upwardly in the gap due to deformation of the polarizing film layer 130 to couple with the second end 172 of the electrically conductive evacuation layer.
  • the polarizing film layer 130 returns to the initial state, so that the free end 152 of the conductive cantilever arm is disconnected from the conductive evacuation layer 170. connection.
  • the static electricity protection device can be configured to connect the data line to the common electrode line for electrostatic protection between the data line and the common electrode line.
  • the first conductive layer 110 is connected to the data line of the display panel, and the second conductive layer 140 is connected to the common electrode line.
  • the static electricity protection device may be further configured to connect the gate line and the common electrode line for implementing electrostatic protection between the gate line and the common electrode line.
  • the first conductive layer 110 is connected to the gate line
  • the second conductive layer 140 is connected to the common electrode line.
  • the ESD device can also connect a gate line or a data line to a shorting bar to evacuate excess static electricity generated in the line to the shorting bar.
  • Piezoelectric materials are existing materials commonly used for mechanics and electricity, but in order to better understand the technical solutions of the embodiments of the present disclosure, a brief introduction will be made to the piezoelectric materials: the polarized piezoelectric materials have two One of the characteristics is that a voltage is applied to the polarization direction of the piezoelectric material, the piezoelectric material will be deformed in the direction of the electric field or in the tangential direction, and the second is to act on the external force when the piezoelectric material is deformed by an external force.
  • the tangential direction of the direction or external force produces a voltage.
  • the piezoelectric material can achieve a reversible transition between mechanics and electricity according to the above two characteristics.
  • the amount of voltage applied to the piezoelectric material is positively correlated with the shape variable (growth amount) of the piezoelectric material.
  • the amount of voltage applied to the piezoelectric material in the embodiment of the present disclosure is a voltage difference between the first conductive layer and the second conductive layer; in the embodiment of the present disclosure, the shape variable of the piezoelectric material may be the first state in the initial state.
  • the first distance difference ⁇ m between the vertical distance m of the insulating layer and the conductive cantilever arm and the vertical distance m′ of the first insulating layer to the conductive suspension beam arm after deformation may also be the first insulation of the second conductive layer in the initial state
  • the vertical distance n of the layer is a second distance difference ⁇ n from the vertical distance n' from the first insulating layer after deformation, see Figures 3a and 3b.
  • ⁇ m is the first distance difference, that is, the distance between the free end of the conductive cantilever arm and the free end of the conductive evacuation layer
  • ⁇ n is the second distance difference, that is, the shape variable of the polarizing film layer
  • a is the polarization film layer
  • b is the length of the projection of the conductive cantilever arms on the first conductive layer along the direction in which the conductive cantilever arms extend.
  • the preferred value of b/a is 40.
  • the polarized film layer is deformed to cause the conductive cantilever arm and the conductive evacuation layer.
  • the common electrode line and the data line are turned on, and the excess electric charge generated by the static electricity is unimpededly introduced into the common electrode line via the conductive cantilever arm.
  • the direction of deformation of the polarizing film layer is the direction of the voltage between the first conductive layer and the second conductive layer.
  • the electrostatic protection device further includes an alignment layer 180 formed on the first insulating layer, and the alignment layer 180 is configured to buffer the first conductive layer 110 and the polarizing film layer 130.
  • the lattice mismatch between them is to facilitate the orderly arrangement of atoms in the polarized film layer.
  • the atomic spacing in the oriented film layer is larger than the spacing of the general metal atoms, and is closer to the spacing of the atoms in the polarizing film layer, thereby facilitating the orderly arrangement of atoms in the polarizing film layer.
  • the material of the alignment layer 180 is Polysilicon.
  • the difference between the atomic spacing in the polycrystalline silicon and the atomic spacing in the polarizing film layer is less than or equal to 10 picometers.
  • the polarizing film layer may be formed using zinc oxide, for example, a film formed of zinc oxide doped with chromium atoms. Since the atomic directions in the unpolarized zinc oxide thin film are spontaneous and disorderly arranged, when a voltage is applied to the polarizing film layer, atoms in the zinc oxide thin film are arranged in the direction of the electric field of the applied voltage. That is, the polarization direction of the polarizing film layer is the direction of the electric field.
  • the oxidized film has the characteristics of easy preparation, good electrical performance and stability, and is non-toxic and non-polluting.
  • the polarizing film layer has a thickness of 4000 angstroms.
  • both the conductive cantilever arms and the electrically conductive evacuation layer can be formed using nano-indium tin metal oxide.
  • the electrostatic protection device provided by the embodiments of the present disclosure can be applied to a Micro-Electro-Mechanical System (MEMS).
  • MEMS Micro-Electro-Mechanical System
  • an electrostatic protection device including: a gate metal layer 410, a gate insulating layer 420, a polarizing film layer 430, a common electrode layer 440, a conductive cantilever arm 450, and a second An insulating layer 460, a conductive evacuation layer 470, and an active layer 480.
  • the specific working mode of the electrostatic device is as follows:
  • the polarizing film layer 430 is deformed such that the free end of the conductive cantilever arm is connected to the free end of the conductive evacuation layer to achieve the static electricity protection. Discharge operation of the device;
  • An embodiment of the present disclosure further provides an array substrate, which includes the above-described static electricity protection device 10.
  • FIG. 7 is a schematic plan view of an array substrate 20 according to an embodiment of the present disclosure.
  • the array substrate 20 includes a display area 201 and a peripheral area 202, and the electrostatic protection device 10 is disposed on the peripheral area 202 of the array substrate 20.
  • the array substrate 20 includes a plurality of gate lines 210 and a plurality of data lines 220.
  • the plurality of gate lines 210 and the plurality of data lines 220 cross each other, and a plurality of pixel regions are defined in the display region 201, and each pixel region is provided with one pixel.
  • Unit 200 The array substrate 20 also includes a common electrode line 230, of which only a portion of the common electrode line 230 is shown for clarity.
  • a thin film transistor array (not shown) is disposed in the display area 201.
  • the array substrate 20 is applied to a liquid crystal display, and the thin film transistor array is distributed in each of the pixel units 100 and configured as a switching element of the pixel unit 100.
  • the electrostatic protection device 10 is disposed in the peripheral region 202 on the upper and lower sides of the display region 201, that is, on the DP side and the DPO side of the array substrate 20, and connects the data line 220 and the common electrode line 230 for implementing the data line. Electrostatic protection between 220 and common electrode line 230.
  • the first conductive layer 110 is connected to the data line 220
  • the second conductive layer 140 is connected to the common electrode line 230.
  • the first conductive layer 110 is disposed in the same layer as the data line 220 and is formed in a patterning process
  • the second conductive layer 140 is disposed in the same layer as the common electrode line 230 and formed in one process.
  • the common electrode line 230 may be disposed in the same layer as the source/drain electrode layer in the thin film transistor array and formed in a patterning process.
  • “same layer setting” as used in the present disclosure means that two (or two or more) material layer structures are formed by the same deposition process and patterned by the same patterning process, so both (multiple The materials are the same.
  • the static electricity protection device 10 can also be disposed in the peripheral region 202 on the left and right sides of the display region 201, that is, the GP side and the GPO side of the array substrate 2, and the connection gate line 210 and the common electrode line 230 are used for Electrostatic protection between the gate line 210 and the common electrode line 230 is achieved.
  • the first conductive layer 110 is connected to the data line 220
  • the second conductive layer 140 is connected to the common electrode line 230.
  • the first conductive layer 110 is disposed in the same layer as the data line 220 and is formed in a patterning process
  • the second conductive layer 140 is disposed in the same layer as the common electrode line 230 and formed in a patterning process.
  • the ESD device 10 can also be configured to connect the gate line 210 or the data line 220 to a shorting bar to evacuate excess static electricity in the line to the shorting bar for electrostatic protection.
  • the first conductive layer 110 or the second conductive layer 140 is connected to the shorting bar.
  • the alignment film layer 180 may be disposed in the same layer as the active layer in the thin film transistor array and formed in a patterning process.
  • the array substrate 20 further includes a GOA (gate driver on array) gate driving circuit 240 disposed in the peripheral region 202 on the left and right sides of the display region 201.
  • the gate drive circuit 240 is configured to be coupled to the plurality of gate lines 210 and to provide a gate scan signal.
  • the common electrode line 230 may be disposed in the same layer as the source/drain electrode layer in the thin film transistor array and formed in one process.
  • the static electricity protection device 10 is configured to evacuate excess static electricity in the line to the common electrode line or the shorting bar to achieve electrostatic protection when the voltage in the line (eg, the gate line or the data line) reaches a predetermined voltage.
  • the working principle of the electrostatic protection device 10 has been described above and will not be described here.
  • the embodiment of the present disclosure further provides a method for fabricating the above electrostatic protection device, comprising: sequentially forming a first conductive layer, a polarizing film layer, and a second conductive layer, wherein the polarizing film layer includes a piezoelectric material capable of being deformed after being energized Forming a conductive cantilever beam on the second conductive layer, the conductive cantilever beam comprising a free end; forming a conductive evacuation layer, the conductive evacuation layer being electrically connected to the first conductive layer, located at the conductive cantilever arm away from One side of the polarizing film layer is spaced apart from the conductive suspension beam arm; when the voltage difference between the first conductive layer and the second conductive layer reaches a preset value, the polarizing film Deformation of the layer causes the free end of the electrically conductive cantilever beam to be coupled to the electrically conductive evacuation layer.
  • the material of the first conductive layer and the second conductive layer is a metal material.
  • an alignment layer may be formed between the first conductive layer and the polarizing film layer to facilitate orderly arrangement of atoms in the polarizing film layer.
  • a first insulating layer may be formed between the first conductive layer and the polarizing film layer.
  • FIG. 5 is a schematic flow chart of a method for fabricating an electrostatic protection device according to an embodiment of the present disclosure. As shown in the figure, the production method includes:
  • the piezoelectric film layer 610 is polarized to form a polarizing film layer 130. See Figure 6d;
  • the difference between the atomic pitch in the alignment film layer and the atomic pitch in the polarizing film layer is less than or equal to 10 picometers; for example, the alignment film layer is an active layer.
  • step S502 includes the following steps:
  • a piezoelectric material is deposited over the first insulating layer to form a weakly oriented thin film layer at least partially over the first insulating layer; the resulting weakly oriented thin film layer is at a first preset
  • the annealing process is performed at a temperature to form a piezoelectric film layer having a polycrystalline structure; the first preset temperature is greater than or equal to 250 degrees Celsius and less than or equal to 350 degrees Celsius.
  • forming a polarizing film layer in step S504 includes:
  • the temperature is lowered until reaching a third preset temperature to form a polarizing film layer, wherein the third preset temperature is greater than or equal to 10 degrees Celsius and less than or equal to 40 degrees Celsius .
  • the step S505 forming the conductive cantilever beam includes:
  • first photoresist 620 Forming a first photoresist 620 over the second conductive layer, that is, filling the gap 121 between the second conductive layer 140 and the second insulating layer with a photoresist, and the first photoresist 620 is connected to the second conductive layer 140. And having the same height surface as the second conductive layer 140, as shown in FIG. 6g;
  • ITO nano-indium tin metal oxide
  • the first photoresist 620 at the lower portion of the conductive suspension beam arm is removed by an exposure process to obtain a conductive cantilever beam corresponding to the first conductive layer.
  • step S506 forms a conductive evacuation layer, including:
  • the second photoresist 640 is connected to the second insulating layer 160, and has a surface of the same height as the second insulating layer 160;
  • ITO nano-indium tin metal oxide
  • the third insulating layer may be a film layer formed of an organic material.
  • Embodiments of the present disclosure provide an electrostatic protection device, a method for fabricating the same, and an array substrate.
  • the present disclosure does not employ a series or parallel triode, but adds a conductive cantilever arm that is freely movable at one end and gradually increases with an applied voltage.
  • the combination of the gradually growing polarizing film layers realizes a normal voltage difference between the first conductive layer and the second conductive layer, and the conductive cantilever beam is in a floating state, so that the first conductive layer and the second conductive layer are not connected.
  • the conductive cantilever arm is connected to the conductive evacuation layer due to
  • the fixed end of the conductive cantilever beam is connected to the second conductive layer, and the fixed end of the conductive evacuation layer is connected to the first conductive layer, that is, the first conductive layer is connected to the second conductive layer to achieve a discharge effect on static electricity.

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Abstract

一种静电防护装置(10)包括：第一导电层(110)、第二导电层(140)以及设置于第一导电层(110)和第二导电层(140)之间的极化膜层(130)，极化膜层(130)为由通电后能产生形变的压电材料形成；设置于第二导电层(140)之上的导电悬梁臂(150)，导电悬梁臂(150)包括自由端(152)；位于所述导电悬梁臂(150)远离极化膜层(130)的一侧的导电疏散层(170)，导电疏散层(170)与第一导电层(110)电连接，并与导电悬梁臂(150)间隔设置；当第一导电层(110)与第二导电层(140)之间的电压差达到预设值时，极化膜层(130)发生形变致使导电悬梁臂(150)与所述导电疏散层相连。该装置通过设计导电悬梁臂在第一导电层(110)和第二导电层(140)之间的电压差未达到预设值时处于悬空状态，使得第一导电层(110)和第二导电层(140)不相连，从而避免了对第一导电层(110)及第二导电层(140)上负载的影响。

Description

静电防护装置及其制作方法、阵列基板 技术领域
本公开的实施例涉及一种静电防护装置及其制作方法、阵列基板。
背景技术
静电防护装置的作用是防止显示面板上的半导体器件因受到静电放电的影响而损坏或者失效，从而防止整个显示面板的损坏或失效，例如，在显示面板的数据端(data pad,DP)侧和数据端对侧(data pad opposite,DPO)的数据线和公共电极线间的ESD(Electro-Static discharge，静电释放)防护设计则显得更为重要。现有的ESD(Electro-Static discharge，静电释放)防护装置由2-4个并联或者串联的三极管组成，即形成一个加强型的二极管。当DP侧和DPO侧的数据线和公共电极线之间的电压差达到一定程度后，实现对显示面板中的数据线和公共电极线中的静电的放电。在栅信号端(gate pad,GP)侧和栅信号端对侧(gate pad opposite,GPO)也存在类似的情况。
然而，该ESD防护装置在正常电压下仍然存在着电流，具体可参见图1所示的输入电压与输入电流的关系示意图，即在正常电压下仍然保持数据线和公共电极线为连接状态，这种情况必然会对数据线上负载的信号产生干扰。
发明内容
本公开实施例提供一种静电防护装置，包括：第一导电层、第二导电层以及设置于所述第一导电层和第二导电层之间的极化膜层，所述极化膜层为由通电后能产生形变的压电材料形成；导电悬梁臂，所述导电悬臂梁设置于所述第二导电层之上，所述导电悬梁臂自由端；导电疏散层，所述导电疏散层位于所述导电悬梁臂远离所述极化膜层的一侧，所述导电疏散层与所述第一导电层电连接，并与所述导电悬梁臂间隔设置；当所述第一导电层与所述第二导电层之间的电压差达到预设值时，所述极化膜层发生形变致使所述导电悬梁臂与所述导电疏散层相连。
例如，所述静电防护装置还包括：形成在所述第一绝缘层之上的取向膜层。
例如，所述取向膜层材料为多晶硅。
例如，所述极化膜层的形变方向为所述第一导电层与所述第二导电层之间的电压的方向。
例如，所述导电疏散层与所述导电悬梁臂的自由端在所述第一导电层的投影至少部分重合。
例如，所述极化膜层为掺铬氧化锌层。
本公开实施例还提供上述的静电防护装置的制作方法，包括：依次形成第一导电层、极化膜层、第二导电层，所述极化膜层包括通电后能产生形变的压电材料；在所述第二导电层上形成导电悬臂梁，所述导电悬梁臂包括自由端；形成导电疏散层，所述导电疏散层与所述第一导电层电连接，位于所述导电悬梁臂远离所述极化膜层的一侧，并与所述导电悬梁臂间隔设置；当所述第一导电层与所述第二导电层之间的电压差达到预设值时，所述极化膜层发生形变致使所述导电悬梁臂的自由端与所述导电疏散层相连。
例如，形成所述极化膜层包括：在所述第一导电层上形成压电膜层；在所述第一导电层与所述第二导电层之间的电压差满足所述预设电压差的条件下，将所述压电膜层进行极化处理。
例如，该制作方法还包括：在形成所述压电膜层之前，在所述第一导电层之上形成取向膜层。
例如，所述取向膜层的材料为多晶硅。
例如，形成所述压电膜层包括：在所述第一导电层之上，采用金属氧化物化学气相沉积法，沉积压电材料，生成弱取向薄膜层；对生成的弱取向薄膜层在第一预设温度下进行退火工艺，形成多晶结构的第一压电膜层；其中，所述第一预设温度为大于或等于250摄氏度，且小于或等于350摄氏度。
例如，将所述压电膜层进行极化处理，形成极化膜层，包括：使所述第一压电膜层达到第二预设温度，调节所述第一导电层与所述第二导电层之间的电压，其中，所述第二预设温度为大于或等于50摄氏度， 且小于或等于150摄氏度；在调节得到的电压差达到预设电压差后，降温直至达到第三预设温度，形成极化膜层，其中，所述第三预设温度为大于或等于10摄氏度，且小于或等于40摄氏度。
例如，形成所述导电悬梁臂包括：在形成所述第二导电层之后形成绝缘层，所述绝缘层与所述第二导电层之间具有空隙；在所述空隙中形成第一光刻胶，所述第一光刻胶与所述第二导电层连接，且与所述第二导电层具有相同高度的表面；在所述第二导电层和所述第一光刻胶之上，沉积第一纳米铟锡金属氧化物层，并通过退火工艺形成导电悬梁臂。
例如，所述绝缘层表面的高度高于所述悬臂梁表面的高度，其中，形成所述导电疏散层包括：在所述空隙中形成第二光刻胶，所述第二光刻胶与所述绝缘层连接，且与所述绝缘层具有相同高度的表面；在所述绝缘层、所述第二光刻胶之上，沉积第二纳米铟锡金属氧化物层，并通过退火工艺形成导电疏散层。
本公开实施例还提供一种阵列基板，包括上述的静电防护装置。
例如，所述阵列基板包括显示区域和周边区域，所述静电防护装置设置于所述周边区域。
例如，所述阵列基板还包括栅线和公共电极线，所述静电防护装置的第一导电层与所述栅线连接，所述静电防护装置的第二导电层与所述公共电极线连接。
例如，所述第一导电层与所述栅线同层设置，所述第二导电层与所述公共电极线同层设置。
例如，所述阵列基板还包括数据线和公共电极线，所述静电防护装置的第一导电层与所述数据线连接，所述静电防护装置的第二导电层与所述公共电极线连接。
例如，所述第一导电层与所述数据线同层设置，所述第二导电层与所述公共电极线同层设置。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一 些实施例，而非对本发明的限制。
图1为一种ESD防护装置的电压和电流的关系的示意图；
图2a为本公开实施例提供的一种静电防护装置的结构示意图；
图2b为图2a沿剖面线A-A的剖面示意图；
图2c为本公开实施例提供的静电防护装置的结构示意图；
图2d为本公开实施例提供的静电防护装置在放电时的结构示意图；
图2e为本公开实施例提供的静电防护装置的结构示意图；
图3a-图3c为本公开实施例提供的静电防护装置的结构示意图；
图4为本发明另一实施例提供的静电防护装置的结构示意图；
图5为本公开实施例提供的一种静电防护装置的制作方法的流程示意图；
图6a-图6j为本公开实施例提供的静电防护装置的结构示意图；以及
图7为本公开实施例提供的阵列基板的平面示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右” 等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
参见俯视图2a以及沿A-A’的剖面图2b，本公开实施例提供了一种静电防护装置10，包括：第一导电层110；部分形成在第一绝缘层120之上的极化膜层130，所述极化膜层由通电后能产生形变的压电材料形成；至少部分形成在所述极化膜层130之上的第二导电层140；形成在第二导电层140之上的导电悬梁臂150；形成在第一绝缘层120之上的第二绝缘层160；形成在第二绝缘层160之上且通过第二绝缘层160中的过孔161与第一导电层110相连的导电疏散层170；导电悬梁臂150位于导电疏散层170与第一导电层110之间。
例如，第一导电层110和第二导电层140的材料为金属材料。
例如，静电防护装置10还可以包括设置于第一导电层110和极化膜层130之间的第一绝缘层120。
导电悬梁臂150包括固定端151和自由端152，固定端151与第二导电层140相连；导电疏散层170包括第一端171和第二端172，第一端171通过第二绝缘层160中的过孔161与第一导电层110相连(第二绝缘层160中过孔的位置可参见图2a)。导电悬梁臂150与导电疏散层170间隔设置。例如，如图2c所示，导电悬梁臂150的自由端152与导电疏散层的第二端172之间存在空隙，并且二者在第一导电层110上的投影至少部分重合。
静电防护装置10的工作方式如下。
当第一导电层110与第二导电层140之间的电压差达到预设值时，极化膜层130发生形变，使得导电悬梁臂的自由端152与导电疏散层的第二端172相连，实现静电防护装置的放电操作。例如，如图2d所示，导电悬梁臂的自由端152由于极化膜层130发生形变而在该空隙中向上移动从而与导电疏散层的第二端172发生连接。
当第一导电层110与第二导电层140之间的电压差低于所述预设值时，极化膜层130恢复初始状态，从而导电悬梁臂的自由端152与导电疏散层170断开连接。
所述静电防护装置应用于显示面板时，可以有多种用途。例如，静 电防护装置可以配置为连接数据线与公共电极线，用来实现数据线与公共电极线之间的静电防护。例如，第一导电层110与所述显示面板的数据线连接，第二导电层140与公共电极线连接。例如，静电防护装置还可配置为连接栅线与公共电极线，用来实现栅线与公共电极线之间的静电防护。例如，第一导电层110与栅线连接，第二导电层140与公共电极线连接。例如，所述静电防护装置还可以将栅线或者数据线连接至一个短路棒(shorting bar)而将线路中产生的多余的静电疏散至该短路棒中。
压电材料为现有的常用于力学与电学的材料，但为了更好的理解本公开实施例的技术方案，下面将对压电材料进行简单的介绍：经极化处理的压电材料具有两种特性，其一为向压电材料的极化方向施加电压，该压电材料将沿电场的方向或切线方向产生形变，其二为当压电材料受到外力作用产生形变时，在外力作用的方向或外力作用的切线方向产生电压。压电材料根据上述两种特性即可实现力学和电学之间的可逆转变。
根据压电材料的形变量公式可知，向压电材料施加的电压量与压电材料的形变量(生长量)呈正相关。例如，压电材料的形变量公式为S＝d33Ud，其中，S为压电材料的形变量；d33为压电常数，通常可达到140pC/N；Ud为向压电材料施加的电压量。其中，本公开实施例中向压电材料施加的电压量为第一导电层与第二导电层之间的电压差；本公开实施例中压电材料的形变量既可以为初始状态下第一绝缘层到导电悬梁臂的垂直距离m与发生形变后第一绝缘层到导电悬梁臂的垂直距离m’的第一距离差△m，也可以为第二导电层在初始状态下与第一绝缘层的垂直距离n与在发生形变后与第一绝缘层的垂直距离n’的第二距离差△n，参见图3a和图3b。
此外，参见图3c，根据三角形平行线定理可得，
△m/△n＝a/b
其中，△m为第一距离差即导电悬梁臂的自由端与导电疏散层的自由端之间的距离，△n为第二距离差即极化膜层的形变量，a为极化膜层在第一导电层上的投影沿导电悬梁臂的延伸方向的长度，b为导电悬 梁臂在第一导电层上的投影沿导电悬梁臂的延伸方向的长度。
综上可知，当向压电材料施加的电压量一定的情况下，△n为固定值，a与b的比值与△m为线性正相关的关系。
为更具体的理解极化膜层的形变量的大小，将列举具体的实验数据进行说明。当第一导电层与第二导电层之间的电压差为100伏时，即极化膜层接收到的竖直向上的外电压为100伏时，由逆压电效应可知，极化膜层将在竖直方向上产生14纳米的伸长量，以增大第一导电层与第二导电层之间的距离，从而削弱外电场。
例如，为防止击穿，b/a的优选值为40，当第一导电层与第二导电层之间的电压差达到50伏时，极化膜层发生形变致使导电悬梁臂与导电疏散层相连，实现公共电极线与数据线导通，静电产生的多余的电荷经由导电悬梁臂畅通无阻的导入到公共电极线内。
综上可知，所述极化膜层的形变方向为所述第一导电层与所述第二导电层之间的电压的方向。
例如，参见图2e，本公开实施例提供的静电防护装置还包括形成在所述第一绝缘层之上的取向层180，取向层180配置为缓冲第一导电层110与极化膜层130之间的晶格失配，以利于极化膜层中原子有序的排列。取向膜层中的原子间距比一般的金属原子的间距大，更接近极化膜层中原子的间距，从而更有利于极化膜层中原子有序的排列，例如，取向层180的材料为多晶硅。例如，多晶硅中的原子间距与所述极化膜层中的原子间距的差值小于或等于10皮米。
例如，极化膜层可使用氧化锌形成薄膜，例如可使用掺杂铬原子的氧化锌形成的薄膜。由于未经极化处理的氧化锌薄膜中的原子方向为自发且无序排列的，当将对极化膜层施加电压后，氧化锌薄膜中的原子按照施加的电压的电场方向排列。即所述极化膜层的极化方向为电场方向。氧化性薄膜具有易于制备，电学性能好且稳定，无毒无污染等特点。
例如，该极化膜层的厚度为4000埃。
例如，导电悬梁臂和导电疏散层均可使用纳米铟锡金属氧化物形成。
本公开实施例提供的静电防护装置可应用于微机电系统(MEMS, Micro-Electro-Mechanical System)中。
参见图4，本公开另一实施例提供了一种静电防护装置，包括：栅极金属层410、栅极绝缘层420、极化膜层430、公共电极层440、导电悬梁臂450、第二绝缘层460、导电疏散层470以及有源层480。
该静电方式装置的具体工作方式为：
当栅极金属层410与公共电极层440之间的电压差达到预设值时，极化膜层430发生形变，使得导电悬梁臂的自由端与导电疏散层的自由端相连，实现该静电防护装置的放电操作；
当栅极金属层410与公共电极层440之间的电压差低于所述预设值时，极化膜层430恢复初始状态，从而导电悬梁臂的自由端与导电疏散层的自由端断开连接。本公开实施例还提供一种阵列基板，所述阵列基板包括上述静电防护装置10。
图7为本公开实施例提供的阵列基板20的平面示意图。如图所示，阵列基板20包括显示区域201和周边区域202，静电防护装置10设置于阵列基板20的周边区域202。阵列基板20包括多条栅线210和多条数据线220，多条栅线210和多条数据线220彼此交叉，在显示区域201中定义出多个像素区，每个像素区设置有一个像素单元200。阵列基板20还包括公共电极线230，为了清楚起见，图中仅示出了公共电极线230的一部分。显示区域201中设置有薄膜晶体管阵列(未示出)。例如，阵列基板20应用于液晶显示，薄膜晶体管阵列分布于各像素单元100中，配置为像素单元100的开关元件。
在本实施例中，静电防护装置10设置于显示区域201上下两侧的周边区域202中，即阵列基板20的DP侧和DPO侧，连接数据线220和公共电极线230，用于实现数据线220与公共电极线230之间的静电防护。例如，第一导电层110与数据线220连接，第二导电层140与公共电极线230连接。例如，第一导电层110与数据线220同层设置且在一道构图工艺中形成，第二导电层140与公共电极线230同层设置且在一道工艺中形成。例如，公共电极线230可以与薄膜晶体管阵列中的源漏电极层同层设置并在一道构图工艺中形成。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以 上)材料层结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化，因此二者(多者)的材料相同。
在另一实施例中，静电防护装置10还可设置于显示区域201左右两侧的周边区域202中，即阵列基板2的GP侧和GPO侧，连接栅线210和公共电极线230，用于实现栅线210与公共电极线230之间的静电防护。例如，第一导电层110与数据线220连接，第二导电层140与公共电极线230连接。例如，第一导电层110与数据线220同层设置且在一道构图工艺中形成，第二导电层140与公共电极线230同层设置且在一道构图工艺中形成。
在另一实施例中，静电防护装置10还可配置为将栅线210或数据线220连接至一个短路棒(shorting bar)，从而将线路中多余的静电疏散至该短路棒中来实现静电防护。在这种情形下，第一导电层110或者第二导电层140与该短路棒连接。
例如，在静电防护装置10包括取向膜层180的情形，取向膜层180可与薄膜晶体管阵列中的有源层同层设置并在一道构图工艺中形成。
例如，阵列基板20还包括GOA(gate driver on array)栅极驱动电路240，设置于显示区域201左右两侧的周边区域202中。栅极驱动电路240配置为与多条栅线210连接并提供栅极扫描信号。
例如，公共电极线230可以与薄膜晶体管阵列中的源漏电极层同层设置并在一道工艺中形成。
静电防护装置10配置为在线路(例如栅线或者数据线)中的电压达到预定电压时，将线路中多余的静电疏散至公共电极线或者短路棒中从而实现静电防护。静电防护装置10的工作原理已在前文描述，这里不再赘述。
本公开实施例还提供上述静电防护装置的制作方法，包括：依次形成第一导电层、极化膜层、第二导电层，所述极化膜层包括由通电后能产生形变的压电材料；在所述第二导电层上形成导电悬臂梁，所述导电悬梁臂包括自由端；成导电疏散层，所述导电疏散层与所述第一导电层电连接，位于所述导电悬梁臂远离所述极化膜层的一侧，并与所述导电悬梁臂间隔设置；当所述第一导电层与所述第二导电层之间的电压差达 到预设值时，所述极化膜层发生形变致使所述导电悬梁臂的自由端与所述导电疏散层相连。
例如，所述第一导电层和所述第二导电层的材料为金属材料。
例如，在所述第一导电层和所述极化膜层之间还可以形成取向层，以利于所述极化膜层中原子有序的排列。
例如，在所述第一导电层和所述极化膜层之间还可以形成第一绝缘层。
图5为本公开实施例提供的一种静电防护装置的制作方法的流程示意图。如图所示，该制作方法包括：
S501、形成第一导电层110，并在第一导电层110之上形成第一绝缘层120，在第一绝缘层之上形成取向膜层180，取向层180配置为缓冲第一导电层与极化膜层之间的晶格失配，此时该装置的结构可参见图6a所示；
S502、至少部分在取向膜层之上形成由通电后能产生形变的压电材料得到的压电膜层610，此时该装置的结构可参见图6b所示；
S503、至少部分在所述压电膜层之上形成第二导电层140；在第一绝缘层之后，在第一绝缘层上形成第二绝缘层160，第二绝缘层160与第二导电层140之间具有空隙121，此时具体结构可参见图6c所示；
S504、在第一导电层与第二导电层之间的电压差满足预设电压差的条件下，将压电膜层610进行极化处理，形成极化膜层130，此时装置的结构可参见图6d所示；
S505、在第二导电层之上形成导电悬梁臂150，其中，导电悬梁臂的自由端与第一导电层相对应，此时装置的结构可参见图6e所示；
S506、在第二绝缘层之上形成导电疏散层170，其中，导电疏散层通过第二绝缘层的过孔与第一导电层相连(图6f中未显示)；导电悬梁臂位于导电疏散层与第一导电层之间，且导电疏散层的第二端与导电悬梁臂的自由端在第一导电层的投影重合，此时装置的结构可参见图6f所示。
例如，取向膜层中的原子间距与所述极化膜层中的原子间距的差值小于或等于10皮米；例如，取向膜层为有源层。
例如，步骤S502包括如下步骤：
采用金属氧化物化学气相沉积法MOCVD，在第一绝缘层之上沉积压电材料，生成至少部分在第一绝缘层之上的弱取向薄膜层；对生成的弱取向薄膜层在第一预设温度下进行退火工艺，形成多晶结构的压电膜层；第一预设温度为大于或等于250摄氏度，且小于或等于350摄氏度。
例如，步骤S504中形成极化膜层，包括：
当多晶结构的压电膜层610达到第二预设温度时，调节第一导电层与第二导电层之间的电压，其中，所述第二预设温度为大于或等于50摄氏度，且小于或等于150摄氏度；
在调节得到的电压差达到预设电压差后，降温直至达到第三预设温度，形成极化膜层，其中，所述第三预设温度为大于或等于10摄氏度，且小于或等于40摄氏度。
例如，步骤S505形成导电悬梁臂包括：
在第二导电层之上形成第一光刻胶620，即用光刻胶填充第二导电层140与第二绝缘层之间的空隙121，第一光刻胶620与第二导电层140连接，且与第二导电层140具有相同高度的表面，如图6g所示；
在第二导电层、第一光刻胶之上沉积第一纳米铟锡金属氧化物(ITO)层，并通过退火工艺形成导电悬梁臂，如图6h所示；
通过曝光工艺，除去导电悬梁臂下部的第一光刻胶620，得到与第一导电层相对应的导电悬梁臂。
例如，步骤S506形成导电疏散层，包括：
在第二导电层之上形成第三绝缘层630，如图6i所示；
在第二绝缘层160与第三绝缘层之间沉积第二光刻胶640，第二光刻胶640与第二绝缘层160连接，且与第二绝缘层160具有相同高度的表面；
在第二绝缘层、第二光刻胶之上，沉积第二纳米铟锡金属氧化物(ITO)层，并通过退火工艺形成导电疏散层，如图6j所示；
通过曝光工艺，除去第二绝缘层与第三绝缘层之间的第二光刻胶640，得到导电疏散层，其中，导电悬梁臂位于导电疏散层与第一导电层之间，且导电疏散层的自由端与导电悬梁臂的自由端在第一导电层的 投影重合。
例如，所述第三绝缘层可为有机材料生成的膜层。
本公开实施例提供了一种静电防护装置及其制作方法、阵列基板，本公开未采用串联或并联的三极管的方式，而是通过增设一端自由活动的导电悬梁臂以及随着外加电压逐渐增大而逐渐生长的极化膜层的组合，实现第一导电层和第二导电层之间为正常电压差的情况下，导电悬梁臂处于悬空状态，使得第一导电层和第二导电层不相连，从而避免了对第一导电层或第二导电层上负载的信号的影响；而当第一导电层和第二导电层之间超过正常电压差时，导电悬梁臂与导电疏散层相连，由于导电悬梁臂的固定端与第二导电层相连，导电疏散层的固定端与第一导电层相连，也即第一导电层与第二导电层相连，实现对静电的放电效果。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2017年5月11日递交的中国专利申请第201710330412.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种静电防护装置，包括：
    第一导电层、第二导电层以及设置于所述第一导电层和第二导电层之间的极化膜层，所述极化膜层为由通电后能产生形变的压电材料形成；
    导电悬梁臂，所述导电悬臂梁设置于所述第二导电层之上且包括自由端；
    导电疏散层，所述导电疏散层位于所述导电悬梁臂远离所述极化膜层的一侧，与所述第一导电层电连接，并与所述导电悬梁臂间隔设置；
    其中，当所述第一导电层与所述第二导电层之间的电压差达到预设值时，所述极化膜层发生形变致使所述导电悬梁臂的自由端与所述导电疏散层相连。
  2. 根据权利要求1所述的静电防护装置，还包括：设置于所述第一导电层和所述极化膜层之间的取向层，其中，所述取向层配置为缓冲所述第一导电层与所述极化膜层之间的晶格失配。
  3. 根据权利要求1所述的静电防护装置，其中，所述极化膜层的形变方向为所述第一导电层与所述第二导电层之间的电压的方向。
  4. 根据权利要求1所述的静电防护装置，其中，所述导电疏散层与所述导电悬梁臂的自由端在所述第一导电层上的投影至少部分重合。
  5. 根据权利要求1-4任意一项所述的静电防护装置，其中，所述极化膜层为掺铬氧化锌层。
  6. 一种静电防护装置的制作方法，包括：
    依次形成第一导电层、极化膜层、第二导电层，所述极化膜层包括通电后能产生形变的压电材料；
    在所述第二导电层上形成导电悬臂梁，所述导电悬梁臂包括自由端；
    形成导电疏散层，所述导电疏散层与所述第一导电层电连接，位于所述导电悬梁臂远离所述极化膜层的一侧，并与所述导电悬梁臂间隔设置；
    其中，当所述第一导电层与所述第二导电层之间的电压差达到预设值时，所述极化膜层发生形变致使所述导电悬梁臂的自由端与所述导电疏散层相连。
  7. 根据权利要求6所述的制作方法，其中，形成所述极化膜层包括：
    在所述第一导电层上形成压电膜层；
    在所述第一导电层与所述第二导电层之间的电压差满足所述预设电压差的条件下，将所述压电膜层进行极化处理。
  8. 根据权利要求7所述的制作方法，其中，形成所述压电膜层包括：
    在所述第一导电层之上，沉积压电材料，生成弱取向薄膜层；
    对所述弱取向薄膜层在第一预设温度下进行退火工艺，形成多晶结构的第一压电膜层；所述第一预设温度为大于或等于250摄氏度，且小于或等于350摄氏度。
  9. 根据权利要求8所述的制作方法，其中，将所述压电膜层进行极化处理包括：
    使所述第一压电膜层达到第二预设温度，调节所述第一导电层与所述第二导电层之间的电压，其中，所述第二预设温度为大于或等于50摄氏度，且小于或等于150摄氏度；
    在调节得到的电压差达到预设电压差后，降温直至达到第三预设温度，形成所述极化膜层，其中，所述第三预设温度为大于或等于10摄氏度，且小于或等于40摄氏度。
  10. 根据权利要求6所述的制作方法，其中，形成所述导电悬梁臂包括：
    在形成所述第二导电层之后形成绝缘层，所述绝缘层与所述第二导电层之间具有空隙；
    在所述空隙中形成第一光刻胶，所述第一光刻胶与所述第二导电层连接，且与所述第二导电层具有相同高度的表面；
    在所述第二导电层和所述第一光刻胶之上，沉积第一纳米铟锡金属氧化物层，并通过退火工艺形成所述导电悬梁臂。
  11. 根据权利要求10所述的制作方法，所述绝缘层表面的高度高于所述悬臂梁表面的高度，其中，形成所述导电疏散层包括：
    在所述空隙中形成第二光刻胶，所述第二光刻胶与所述绝缘层连接，且与所述绝缘层具有相同高度的表面；
    在所述绝缘层、所述第二光刻胶之上，沉积第二纳米铟锡金属氧化物层，并通过退火工艺形成导电疏散层。
  12. 根据权利要求6-11任意一项所述的制作方法，还包括：
    在形成所述压电膜层之前，在所述第一导电层之上形成取向层，其中，所述取向层配置为缓冲第一导电层与极化膜层之间的晶格失配。
  13. 根据权利要求12所述的制作方法，其中，所述取向膜层的材料为多晶硅。
  14. 根据权利要求2所述的静电防护装置，其中，所述取向层的材料为多晶硅。
  15. 一种阵列基板，包括如权利要求1-5任意一项所述的静电防护装置。
  16. 根据权利要求15所述的阵列基板，包括显示区域和周边区域，其中，所述静电防护装置设置于所述周边区域。
  17. 根据权利要求15所述的阵列基板，包括栅线和公共电极线，其中，所述静电防护装置的第一导电层与所述栅线连接，所述静电防护装置的第二导电层与所述公共电极线连接。
  18. 根据权利要求17所述的阵列基板，所述第一导电层与所述栅线同层设置，所述第二导电层与所述公共电极线同层设置。
  19. 根据权利要求15所述的阵列基板，包括数据线和公共电极线，其中，所述静电防护装置的第一导电层与所述数据线连接，所述静电防护装置的第二导电层与所述公共电极线连接。
  20. 根据权利要求19所述的阵列基板，其中，所述第一导电层与所述数据线同层设置，所述第二导电层与所述公共电极线同层设置。
PCT/CN2018/081731 2017-05-11 2018-04-03 静电防护装置及其制作方法、阵列基板 WO2018205774A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102802333A (zh) * 2011-05-25 2012-11-28 Tdk株式会社 静电保护部件
CN205944083U (zh) * 2016-08-29 2017-02-08 Aem科技(苏州)股份有限公司 一种静电保护器
CN107146792A (zh) * 2017-05-11 2017-09-08 京东方科技集团股份有限公司 一种静电防护装置及其制作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
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KR100683149B1 (ko) * 2003-03-31 2007-02-15 비오이 하이디스 테크놀로지 주식회사 액정표시소자용 어레이기판의 스트레스 제거방법
JP4492677B2 (ja) * 2007-11-09 2010-06-30 セイコーエプソン株式会社 アクティブマトリクス装置、電気光学表示装置、および電子機器
JP2009300948A (ja) * 2008-06-17 2009-12-24 Fdk Corp 磁気光学空間光変調器
CN102856495B (zh) * 2011-06-30 2014-12-31 清华大学 压力调控薄膜晶体管及其应用
CN103926755B (zh) * 2013-12-30 2017-08-25 厦门天马微电子有限公司 一种显示器及其制作方法
US9748048B2 (en) * 2014-04-25 2017-08-29 Analog Devices Global MEMS switch
KR102256719B1 (ko) * 2014-05-12 2021-05-28 삼성전자주식회사 반도체 패키지 및 그 제조 방법
CN105870133A (zh) * 2016-04-29 2016-08-17 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板和显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102802333A (zh) * 2011-05-25 2012-11-28 Tdk株式会社 静电保护部件
CN205944083U (zh) * 2016-08-29 2017-02-08 Aem科技(苏州)股份有限公司 一种静电保护器
CN107146792A (zh) * 2017-05-11 2017-09-08 京东方科技集团股份有限公司 一种静电防护装置及其制作方法

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