TWI301671B - Thin film transistors and displays including the same - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor structure, and more particularly to a thin film transistor and a display including the same. [Previous technology #?] In the panel manufacturing process, it is easy to have an electrostatic discharge (ESD) situation, which will cause great damage to components and circuits. When the panel is designed, it is often installed with electrostatic discharge protection at the outermost periphery of the panel. Components and circuits to reduce the effects of electrostatic discharge during low-profile processes. A "robust" electrostatic discharge component is necessary. However, electrostatic discharge protection components damaged by electrostatic discharge are still seen from time to time during production. Once the electrostatic discharge protection component is damaged, the effective energy cannot be achieved. Protect the internal pixel circuit. Secondly, a good ESD protection component must have "transparency" characteristics, meaning that under normal operating conditions, the ESD protection component must be turned off and not working. If the shutdown characteristics are poor, there will be additional leakage. Current and power loss, especially in portable electronic products such as cell phones or PDAs. In view of the "transparency" characteristics of the ESD protection device, a thin film transistor structure of a floating gate is proposed in U.S. Patent No. 6, ,81, 307 and 6,175,394, which is incorporated herein by reference. Compared to the (diode-type) thin film transistor structure, the initial voltage of the electrostatic discharge protection element is large, and the leakage current and the occupied area are small. Currently, both types of thin film transistor connections are widely used. [Summary of the Invention]

Clients Docket No. : AU0511067 TT^ Docket No: 0632-A50689TW/final/david 5 • 1301671 The present invention provides a thin film transistor comprising a gate formed on a substrate; an insulating layer formed on the substrate Covering the gate; a semiconductor layer formed on the insulating layer; and a source and a drain formed on the semiconductor layer, the source and the drain having a space between the source and the source At least one of the bungee poles does not extend into the area directly above the gate. The present invention provides a thin film transistor comprising a gate formed on a substrate; an insulating layer formed on the substrate and covering the gate; a semiconductor layer formed on the insulating layer; and a source and A drain is formed on the semiconductor layer, the source has a space between the drain and the drain, and at least one of the source and the drain extends into a region directly above the gate. The present invention further provides a display comprising a substrate defining a display area; a plurality of gate lines disposed on the substrate; a plurality of data lines disposed on the substrate, the gates The polar line and the data lines intersect each other to define a plurality of pixel regions, and each pixel region has at least one switch device; at least one shorting bar is disposed around the display region And a plurality of thin film transistors extending from at least one of the source and the drain to the region directly above the gate, disposed outside the display region, wherein each of the thin film electro-crystal systems is electrically connected to the first One of the gate lines and one of the shorting bars and/or one of the data lines and the shorting bar. The present invention further provides a display comprising a substrate defining a display area; a plurality of gate lines disposed on the substrate; a plurality of data lines disposed on the substrate, the gates The polar line and the data lines intersect each other to define a plurality of pixel regions, and each pixel

Client's Docket No: AU0511〇67 ΤΤΛ s Docket No : 0632-A50689TW/final/david 6 M301671 • The zone has at least one switch device; at least one shorting bar is set around the display zone And a plurality of source and drain electrodes extending to the region directly above the gate are disposed outside the display region, wherein each of the thin film electro-crystal systems is electrically connected to the gates One of the pole lines and one of the shorting bars and/or one of the data lines and the shorting bar. The above described objects, features and advantages of the present invention will become more apparent and understood.

[Embodiment] The present invention provides a thin film transistor [including a gate formed on a substrate; an insulating layer formed on the substrate and covering the gate; a semiconductor layer formed on the insulating layer; and a source And a drain formed on the semiconductor layer, the source has a space between the pole and the pole, and at least one of the source and the drain is not extended to a region directly above the gate. The semiconductor layer may include a channel layer and an ohmic contact layer respectively contacting the source and the drain. The channel layer between the source and the drain can be defined as a channel region having a length of approximately 4 to 12 microns. A ballast resistor having a resistance 値 greater than 5 Μ ω is formed between the source/drain and the gate. The source or drain, which does not extend to the region directly above the gate, has a horizontal distance from the gate of about 〇2 μm. The material of the gate and source/drain can be the same or different, including transparent material or reflective material. Suitable transparent materials such as indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide tin

Client, s Docket No.: AU0511067 TTfs Docket No: 0632-A50689TW/final/david 7 1301671 (cadmium tin oxide, CTO), other materials having similar properties or combinations thereof. Suitable reflective materials are, for example, silver, gold, copper, aluminum, titanium, knobs, tungsten, molybdenum, niobium, titanium nitride, tantalum nitride, aluminum oxide, aluminum nitride or alloys or combinations of the foregoing. The gate and source/drain can be single or multi-layer structures. " The material of the insulating layer includes tantalum nitride, tantalum oxide, niobium oxynitride or a combination thereof, and may be a single layer or a multilayer structure. The material of the channel layer and the ohmic contact layer may include amorphous germanium, polycrystalline germanium, microcrystalline germanium, single crystal germanium or a combination thereof, wherein the doped state of the ohmic contact layer may be n-type or p-type doped. Moreover, in order to make the resistance of the ohmic contact layer and the channel layer lower or to make the electron flow smoother, the channel layer can be doped to a lower doping type than the ohmic contact layer, and the doping of the channel layer is doped. The heteromorphic state may be a single layer or multiple layers, while possibly retaining an additional layer of undoped layers. Referring to Fig. 1, a sectional structure of a thin film transistor of the present invention will be described. The thin film transistor 10 includes a gate 14, an insulating layer 16, a half conductor layer 24, and a source 26 and a drain 28. The gate 14 is formed on a substrate 12, the insulating layer 16 is formed on the substrate 12 and covers the gate 14, the semiconductor layer 24 is formed on the insulating layer 16, and the source 26 and the drain 28 are formed on the semiconductor layer 24. The semiconductor layer 24 is composed of a channel layer 20 and an ohmic contact layer 22, wherein the ohmic contact layer 22 is in contact with the source electrode 26 and the drain electrode 28. A space 30 is formed between the source 26 and the drain 28, and the channel layer 20 in the space 30 is defined as a channel region 32. The thin film transistor is characterized in that at least one of the source 26 and the gate 28 does not extend into the region 34 directly above the gate 14, and the horizontal distance between the source 26 or the drain 28 and the gate 14 is zero. . In other words, source 26 or drain 28 is not present in a region of overlap with gate 14.

Clientf s Docket No.: AU0511067 TT s Docket No: 0632-A50689TW/final/david 8 1301671 Please refer to FIGS. 1B and 1C for a cross-sectional structure of another thin film transistor of the present invention. The thin film transistor 50 includes a gate 54, an insulating layer 56, a semiconductor layer 64, and a source 66 and a gate 68. The gate 54 is formed on a substrate 52. The insulating layer 56 is formed on the substrate 52 and covers the gate. The semiconductor layer 64 is formed on the insulating layer 56, and the source 66 and the drain 68 are formed on the semiconductor layer 64. The semiconductor layer 64 is composed of a channel layer 60 and an ohmic contact layer 62, wherein the ohmic contact layer 62 is in contact with the source 66 and the drain 68. A gap 70 is formed between the source 66 and the drain 68, and the channel layer 60 in the space 70 is defined as a channel region 72. The thin film transistor is characterized by at least one of the source 66 and the drain 68 (Fig. 1B) or both (Fig. 1C), not extending into the region 74 directly above the gate 54, the source 66 Or the drain 68 has a horizontal distance W1 from the gate 54. It should be noted that the two horizontal distances W1 shown in Fig. 1C are equal in the embodiment, however, the two horizontal distances W1 may not be equal. The difference between the structures of Figs. 1A and 1B is that in Fig. 1A, the horizontal distance between the source 26 or the drain 28 and the gate 14 is zero, and the source 66 or the drain 68 of the Fig. 1B has a horizontal distance from the gate 54. W1. The same is true for at least one of the source or drain in the structure that does not extend into the area directly above the gate. The invention provides a thin film transistor, comprising a gate formed on a substrate; an insulating layer formed on the substrate and covering the gate; a semiconductor layer formed on the insulating layer; and a source and a drain Formed on the semiconductor layer, having a spacing between the source and the drain, and at least one of the source and the drain extending into a region directly above the gate. The semiconductor layer may include a channel layer and an ohmic contact layer respectively contacting the source and the drain. The channel layer between the source and the drain can be defined as

Clients Docket No. :AU0511067 TTf s Docket No: 0632-A50689TW/final/david 9 •1301671

Client, s Docket No.: AU0511〇67 A channel area with a length of approximately 4 to 12 microns. A ballast resistor having a resistance 値 greater than 5 Μ ω is formed between the source/drain and the gate. The source or the drain extending to the region directly above the gate has a width overlapping with the gate of not more than 0.5 μm. The material of the gate and source/drain can be the same or different, including transparent or reflective materials. Suitable transparent materials such as indium tin oxide (ITO), indium zinc 〇xide (IZ〇), cadmium tin oxide (CTO), aluminum zinc (AZ0) or Other materials with similar properties. Suitable reflective materials are, for example, silver, gold, copper, aluminum, titanium, tantalum, knobs, tungsten, molybdenum, niobium, titanium nitride, tantalum nitride, aluminum oxide, aluminum nitride or alloys or compositions of the above materials. The gate and source/drain can be single or multi-layer structures. The material of the insulating layer includes nitride rock, oxidized stone, oxynitride or a combination thereof, and may be a single layer or a multilayer structure. The material of the channel layer and the ohmic contact layer may include amorphous germanium, polycrystalline germanium, microcrystalline germanium, single crystal germanium or a combination thereof, wherein the doped state of the ohmic contact layer may be n-type or p-type doped. Moreover, in order to make the resistance of the ohmic contact layer and the channel layer low or to make the electron flow j smooth, the channel layer can be doped to a lower doping type than the ohmic contact layer, and the channel layer is doped. The doped form may be a single layer or multiple layers, while possibly retaining an additional layer of undoped layers. Referring to Figure 2, the cross-sectional structure of the thin film transistor of the present invention will be described. The thin film transistor 100 includes a gate 14A, an insulating layer 16A, an etch stop layer 180, a semiconductor layer 24A, and a source 26 and a drain 280. The gate 140 is formed on a substrate 12, and the insulating layer 16 is formed on the substrate 120 and covers the gate 14A. The semiconductor layer 24 is formed on the insulating layer 160. The source 260 and the drain 28 are formed on the semiconductor layer. 24 〇. Half TT^s Docket No: 0632-A50689TW/final/david 10 • 1301671 The beta conductor layer 240 is composed of a channel layer 200 and an ohmic contact layer 220, wherein the ohmic contact layer 220 is in contact with the source 260 and the drain 280. A gap 300 is formed between the source 260 and the "> and the pole 280, and the channel layer 2 间隔 in the space 300 is defined as a channel region 320. The thin film transistor is characterized in that at least one of the source 260 and the drain 280 extends into the region 340 directly above the gate 140, and the source 260 or the drain 280 and the gate 140 have an overlapping width W2. The electrostatic discharge (ESD) protection element designed by the present invention has a large ballast resistor, which can effectively reduce the direct damage caused by electrostatic discharge without adding additional layout area. The baiiast resistor changes its value by controlling the area of overlap between the source/drain and the gate. In addition, due to the design of the parasitic series resistance, the leakage current and power loss of the ESD protection element are extremely low, providing an effective voltage drop to enhance the "robustness" of the ESD protection component. The present invention can be applied to an element having an I-stopper (ion-stopper) structure in addition to the BCE (back channel etched) elements as shown in Figs. 1, 1B, and 2 . Hereinafter, the I-stopper thin film transistor of the present invention will be described with reference to Figs. 3a, 3b and φ. Referring to Fig. 3A, a sectional structure of the (i_st〇pper) thin film transistor of the present invention will be described. The thin film transistor 101 includes a gate 141, an insulating layer 161, a semiconductor layer 241, and a source 261 and a gate 281. The gate electrode 141 is formed on a substrate 121. The insulating layer 161 is formed on the substrate 121 and covers the gate electrode 141. The semiconductor layer 241 is formed on the insulating layer, and the source electrode 261 and the drain electrode 281 are formed on the semiconductor layer 241. The semiconductor layer 241 is composed of a channel layer 201 and an ohmic contact layer 221, wherein the channel layer 201 is in contact with the gate stop layer 181, and the ohmic contact layer 221 and the source are

Clients Docket No. : AU0511067 TT,s Docket No: 0632-A50689TW/final/david Π \ 1301671 \ 261, bungee 281 contact. The channel layer 201 between the source 261 and the drain 281 further includes an etch stop layer 211 to prevent leakage current between the source 261 and the drain 281 when the transistor is turned off. The etch stop layer 211 may be composed of an insulating material such as tantalum nitride, hafnium oxide, or hafnium oxynitride. A gap 301 is formed between the source 261 and the drain 281, and the channel layer 201 in the space 301 is defined as a channel region 321 . At least one of the source 261 and the drain 281 does not extend into the region 341 directly above the gate 141, and the horizontal distance between the source 261 or the drain 281 and the gate 141 is zero. In other words, the source 26 φ or the drain 28 does not exist in an overlapping region with the gate 14. Referring to Figures 3B and 3C, a cross-sectional structure of another I-stopper film transistor of the present invention is illustrated. The thin film transistor 501 includes a gate 541, an insulating layer 561, a semiconductor layer 641, and a source 661 and a drain 681. The gate electrode 541 is formed on a substrate 521. The insulating layer 561 is formed on the substrate 521 and covers the gate electrode 541. The semiconductor layer 641 is formed on the insulating layer 561, and the source electrode 661 and the drain electrode 681 are formed on the semiconductor layer 641. The semiconductor layer 641 is composed of a channel layer 601 and an ohmic contact layer 621, wherein the ohmic contact layer 621 is in contact with the source electrode 661 and the gate electrode 681*. The channel layer 601 between the source 661 and the gate 681 further includes an etch stop layer 611 to prevent leakage current between the source 661 and the gate 681 when the transistor is turned off. The surname termination layer 611 may be composed of an insulating material such as tantalum nitride, hafnium oxide or hafnium oxynitride. A gap 701 is formed between the source 661 and the drain 681, and the channel layer 601 in the gap 701 is defined as a channel region 721. At least one of the source 661 and the drain 681 (Fig. 3B) or both (Fig. 3C) does not extend to the area directly above the gate 541.

Clientrs Docket No.: AU0511067 TT, s Docket No : 0632-A50689TW/final/david 12 1301671 741, the source 661 or the drain 681 has a horizontal distance from the gate 541. It should be noted that the 3C figure The two horizontal distances W1 shown are equal in the embodiment, however, the two horizontal distances W1 may not be equal. The difference between the structures of the 3A and 3B is that in the 3A, the horizontal distance between the source 261 or the drain 281 and the gate 141 is zero, and the source 661 or the drain 681 of the 3B has a horizontal distance from the gate 541. W1. The same is true for at least one of the source or drain in the structure that does not extend into the region directly above the gate. Referring to Figure 4, there is illustrated a cross-sectional structure of an I-stopper film of the present invention. The thin film transistor 1001 includes a gate 1401, an insulating layer 1601, a semiconductor layer 2401, and a source 2601 and a drain 2801. The gate 1401 is formed on a substrate 1201. The insulating layer 1601 is formed on the substrate 1201 and covers the gate 1401. The semiconductor layer 2401 is formed on the insulating layer 1601. The source 2601 and the drain 2801 are formed on the semiconductor layer 2401. The semiconductor layer 2401 is composed of a channel layer 2001 and an ohmic contact layer 2201, wherein the ohmic contact layer 2201 is in contact with the source 26 (Π, the drain 2801). | The channel layer 2001 between the source 2601 and the drain 2801 is further An etch stop layer 2101 is formed to avoid leakage current between the source 2601 and the drain 2801 when the transistor is turned off. The etch stop layer 2101 may be formed of an insulating material such as tantalum nitride, hafnium oxynitride or tantalum oxide. A gap 3001 is formed between the source 2601 and the drain 2801, and the channel layer 2001 in the interval 3001 is defined as a channel region 3201. At least one of the source 2601 and the drain 2801 extends to a region 3401 directly above the gate 1401. The source 2601 or the drain 2801 and the gate 1401 have an overlapping width W2 〇

Client1 s Docket No.: AU0511067 TTf s Docket No: 0 632-A5068 9TW/final/david 13 1301671 • The present invention further provides a display comprising a substrate defining a display area; a plurality of gate lines, Provided on the substrate; a plurality of data lines are disposed on the substrate, the gate lines and the data lines intersect each other to define a plurality of pixel regions, and each pixel region has at least one switching element (switch device); at least one shorting bar disposed at a periphery of the display area; and a plurality of thin film transistors having at least a source and a drain not extending to a region directly above the gate, disposed outside the display area Each of the thin film transistors is electrically connected to one of the above-mentioned gate lines and one of the shorting bars and/or one of the above data lines and the shorting bar. The display includes a common line disposed around the display area and electrically connected to the shorting bar. The invention further provides a display comprising a substrate defining a display area; a plurality of gate lines disposed on the substrate; a plurality of data lines disposed on the substrate, the gate lines and The data lines intersect each other to define a plurality of pixel regions, and each of the pixel regions has at least one switch device; at least one shorting bar is disposed at a periphery of the display region; and a plurality of sources a thin film transistor extending from at least φ of the pole and the drain to a region directly above the gate is disposed outside the display region, wherein each of the thin film transistors is electrically connected to one of the gate, the wire and the shorting bar And / or one of the above data lines and the shorting bar. The display further includes a common line disposed around the display area and electrically connected to the shorting bar. The display of the present invention may include an electroluminescence display, a light-emitting diode display, a field-emission display, and a carbon nanotube display (nano-carbon 14).

Clientf s Docket No.: AU0511067 TTVs Docket No: 0632-A50689TW/final/david

• 1301671 • tube display), liquid crystal display or plasma display. 0 The thin film transistor of the present invention can be connected to a diode-type thin film transistor or can be connected to be floating. A thin film transistor of a floating gate. The following is a description of each of the fifth and sixth figures. Referring to Figure 5, there is shown a schematic diagram of a display circuit design comprising a diode thin film transistor of the present invention. The plurality of gate lines 4 and the data lines 5 are perpendicularly intersected with each other on the substrate 9 to define a plurality of pixel regions 11 and are respectively coupled to the driving circuits 6 and 7 located around the periphery of the display region. The switching element 2 is disposed in the pixel region 11 and coupled to the gate line and the data line constituting the pixel region. The pixel region 11 further includes a capacitor element 3 coupled to the switching element 2. a plurality of thin film transistors 1 and shorting bars 13 which are not extended or extended to a region directly above the gate, and are disposed at a periphery of the display region, wherein each of the thin film transistors 1 is electrically connected to each other One of the plurality of gate lines 4, the other thin film transistor 1 and the shorting bar 13 and/or one of the plurality of data lines 5, the other thin film transistor 1 and the shorting bar 13. The above-mentioned diode-type thin film transistor has an initial voltage of about 20 to 40 volts, a leakage current of less than 1E-6 amps, and a power consumption of less than 2E-5 watts. Referring to Figure 6, there is shown a schematic diagram of a display circuit design of the present invention comprising a floating gate thin film transistor. The plurality of gate lines 4 and the data lines 5 are perpendicularly arranged on the substrate 9 to define a plurality of pixel regions 11 and are respectively coupled to the driving circuits 6 and 7 located around the periphery of the display region. The switching element 2 is disposed in the halogen region 11 and coupled to the gate lines and the data lines constituting the pixel region. The halogen element 11 further includes a capacitive element 3 coupled to the switching element 2. At least one of the plurality of sources and the drain does not extend or extend to the gate

Client's Docket No.: AU0511067 TTf s Docket No: 0632-A50 68 9TW/final/david 15 1301671 . The thin film transistor 1 and the shorting bar 13 in the upper area are disposed around the display area, and each of the thin film transistors 1 Each of the plurality of gate lines 4 and the shorting bar 13 and/or one of the plurality of data lines 5 and the shorting bar 13 are electrically connected. The floating gate type thin film transistor has an initial voltage of about 60 to 100 volts, a leakage current of less than 1E-7 amps, and a power consumption of less than 6E-6 watts. Although the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and any one skilled in the art can change and refine it without departing from the scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Client1 s Docket No .: AU0511067 TTr s Docket No: 0632-A50 68 9TW/final/david 16 1301671 [Simplified Schematic] Figs. 1A to 1C and Fig. 2 are schematic cross-sectional views showing the structure of a BCE thin film transistor of the present invention. 3A to 3C and Fig. 4 are schematic cross-sectional views showing the structure of an etch-stop (I_st〇pper) thin film transistor of the present invention. Fig. 5 is a schematic view showing the circuit design of the display including the diode type thin film transistor of the present invention. Figure 6 is a schematic diagram showing the design of the display circuit of the present invention comprising a floating gate thin film transistor. [Description of main component symbols] 10, 50, 100, 101, 501, 1〇〇1 ~ thin film transistor; 12, 52, 120, 121, 521, 1201 ~ substrate; 14, 54, 140, 141, 541, 1401 ~ gate; 16, 56, 160, 161, 561, 1601 ~ insulating layer; 20, 60, 200, 201, 601, 2001 ~ channel layer; 22, 62, 220, 221, 621, 2201 ~ ohmic contact layer; 10 24, 64, 240, 241, 641, 2401 ~ semiconductor layer; 26, 66, 260, 261, 661, 2601 ~ source; 28, 68, 280, 281, 681, 2801 ~ no pole; 30, 70, 300, 3 (Η, 7 (Π, 3001 ~ interval; 32, 72, 320, 321, 721, 3201 ~ channel area; 34, 74, 340, 341, 741, 3401 ~ directly above the gate; 211, 61 Bu 2101 ~ residual stop layer; W1 ~ source /;: and the horizontal distance between the pole and the gate;

Clients Docket No. :AU0511067 TT^s Docket No: 0632-A50689TW/final/david 1301671 • W2 ~ source/drain and gate overlap width; 1, 15~ thin film transistor; 2~ switching element; 3~ capacitor 4; gate line; 5~ data line, 6, 7~ drive circuit; 8~ shared line; 9~ substrate; • 11~ 昼 区 area; 13~ shorting rod.

Clientf s Docket No·: AU0511067 TTf s Docket No : 0632-A50689TW/final/david

Claims (1)

: 1301671 X. Patent application scope: 1. A thin film transistor comprising: a gate formed on a substrate; an insulating layer formed on the substrate and covering the gate; a semiconductor layer formed on the insulating layer And a source and a drain are formed on the semiconductor layer, a gap is formed between the source and the drain, and at least one of the source and the drain is Does not extend into the area directly above the gate. 2. The thin film transistor of claim 1, wherein the singular semiconductor layer comprises a channel layer and an ohmic contact layer, the ohmic contact layer contacting the source and the drain, respectively. 3. The thin film transistor of claim 2, wherein the channel layer between the source and the gate is defined as a channel region. 4. The thin film transistor of claim 3, wherein the length of the channel region is between about 4 and 12 microns. 5. The thin film transistor of claim 2, further comprising an etch stop layer disposed between the channel layer and the ohmic contact layer. 6. The thin film transistor of claim 1, wherein a ballast resistor is formed between the source/nopole and the gate. 7. The thin film transistor of claim 6, wherein the ballast resistance is greater than 5 Μ ω. 8. The thin film transistor according to claim 1, wherein the source or the drain which is not extended to the region directly above the gate has a horizontal distance from the gate of about 0 to 2 μm. . 9. The thin film transistor according to claim 1, wherein the thin film electromorphic system comprises a diode-type TFT Clientfs Docket No.: AU0511067 TTf s Docket No: 0632-A50689TW /final/david 19 :1301671 \ or floating gate TFT. 10. The thin film transistor according to claim 9, wherein the starting voltage of the diode thin film transistor is about 20 to 40 volts. 11. The thin film transistor of claim 9, wherein the floating gate thin film transistor has an initial voltage of about 60 to 100 volts. 12. A thin film transistor comprising: a gate formed on a substrate; an insulating layer formed on the substrate and covering the gate; • a semiconductor layer formed on the insulating layer; and a a source and a drain are formed on the semiconductor layer, a gap is formed between the source and the drain, and at least one of the source and the drain extends to the gate In the area directly above. 13. The thin film transistor of claim 12, wherein the semiconductor layer comprises a channel layer and an ohmic contact layer. The ohmic contact layer contacts the source and the drain, respectively. 14. The thin film transistor of claim 13, wherein the channel layer between the source and the drain is defined as a channel region. 15. The thin film transistor of claim 14, wherein the channel region has a length of between about 4 and 12 microns. 16. The thin film transistor of claim 13, further comprising an etch stop layer disposed between the channel layer and the ohmic contact layer. 17. The thin film transistor of claim 12, wherein a ballast resistor is formed between the source/drain and the gate. 18. The film of claim 17 Transistor, where Clientf s Docket No .: AU0511067 TT, s Docket No : 0632-A5068 9TW/final/david 20 : 1301671 - The ballast resistance is greater than 5 Μ ω. 19. The thin film transistor of claim 2, wherein the source or drain extending into the region directly above the gate has a overlap width with the gate of no more than 0.5 micron. The thin film transistor according to claim 12, wherein the thin film electromorphic system is a diode-type TFT or a floating gate TFT. The thin film transistor according to claim 20, wherein the starting voltage of the diode thin film transistor is about 20 to 40 volts. The thin film transistor according to claim 20, wherein the floating gate thin film transistor has an initial voltage of about 60 to 100 volts, and includes: a substrate, a definition a display area; a plurality of gate lines disposed on the substrate; a plurality of data lines disposed on the substrate, the gate lines and the data lines intersecting each other to define a plurality of pixel regions, each of the pixel regions having at least one switch device; at least one shorting bar disposed at the periphery of the display area; and a plurality of the first item as claimed in the patent application The thin film transistor is disposed outside the display area, wherein each of the thin film electro-crystal systems is electrically connected to one of the gate lines and one of the shorting bars and/or the data lines and the shorting bar. The display of claim 23, further comprising a common line disposed around the display area and electrically connected to the shorting bar. Client's Docket No.: AU0511067 TTfs Docket No: 0632-A50689TW/final/david 21 :1301671 - 25. A type of display comprising: a substrate defining a display area; a plurality of gate lines disposed at the a plurality of data lines disposed on the substrate, the gate lines and the data lines intersecting each other to define a plurality of pixel regions, and each of the pixel regions has at least one switch a switch device; at least one shorting bar disposed at a periphery of the display area; and a plurality of thin film transistors as described in claim 12, • disposed outside the display area, each of which The thin film electro-crystal system is electrically connected to one of the gate lines and one of the shorting bars and/or the data lines and the shorting bar. 26. The display of claim 25, further comprising a common line disposed around the display area and electrically connected to the shorting bar. Clientrs Docket No·:AU0511067 22 TTf s Docket No : 0632-A5068 9TW/final/david